®
EL4581
Data Sheet August 16, 2002
Sync Separator , 50% Slice, S-H, Filter
The EL4581 extracts timing information from standard negative going
video sync found in NTSC, PAL, and
SECAM broadcast systems. It can also be used in non standard formats and with computer graphics systems at higher
scan rates, by adjusting a single external resistor. When the
input does not have correct serration pulses in the vertical
interval, a default vertical output is produced.
Outputs are composite sync, vertical sync, burst/back porch
output, and odd/even output. The later operates only in interlaced scan formats.
The EL4581 provides a reliable method of determining correct sync slide level by setting it to the mid-point between
sync tip and blanking level at the back porch. This 50% level
is determined by two internal self timing sample and hold circuits that track sync tip and back porch levels. This also
provides a degree of hum and noise rejection to the input signal, and compensates for varying input levels of 0.5
2.0V
P-P
.
A built in linear phase, third order, low pass filter attenuates
the chroma signal in color systems to prevent incorrectly set
color burst from disturbing the 50% sync slide.
This device may be used to replace the industry standard
LM1881, offering improved performance and reduced power
consumption.
P-P
to
FN7172
Features
• NTSC, PAL and SECAM sync separation
• Single supply, +5V
• Precision 50% slicing, internal caps
• Built-in color burst filter
• Decodes non-standard verticals
• Pin compatible with LM1881
•Low power
• Typically 1.5mA supply current
• Resistor programmable scan rate
• Few external components
• Available in 8-pin PDIP and SO packages
Applications
• Video special effects
• Video test equipment
• Video distribution
• Displays
•Imaging
• Video data capture
• Video triggers
The EL4581 video sync separator is manufactured using
Elantec’s high performance analog CMOS process.
Pinout
EL4581
(8-Pin SO, DIP)
TOP VIEW
COMPOSITE
SYNC OUT
COMPOSITE
VIDEO IN
VERTICAL
SYNC OUT
All other trademarks mentioned are the property of their respective owners. Manufactured under U.S. Patent 5,528,303. Manufactured under License, U .S . Patents 5,486,869; 5,754,250.
GND
1
2
3
4
1
8
VDD 5V
7
ODD/EVEN OUTPUT
RSET
6
BURST/BACK
5
PORCH OUTPUT
CAUTION: These devices are sensitiv e to electrostatic discharge; follow proper IC Handling Procedures.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
1-888-INTERSIL or 321-724-7143
Ordering Information
PART
NUMBER
EL4581CN -40°C to +85°C 8-Pin PDIP MDP0031
EL4581CS -40°C to +85°C 8-Pin SO MDP0027
TEMP.
RANGE PACKAGE PKG. NO.
Demo Board
A dedicated demo board is not available. However, this
device can be placed on the EL4584/5 Demo Board.
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
EL4581
Absolute Maximum Ratings (T
Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
V
CC
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests , therefore: T
DC Electrical Specifications Unless otherwise state V
= 25 °C)
A
+0.5V
CC
= TC = T
J
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
A
= 5V, TA = 25°C, R
DD
SET
= 680kΩ.
PARAMETER DESCRIPTION TEMP MIN TYP MAX UNIT
I
DD
VDD = 5V (Note 1) 25°C 0.75 1.7 3 mA
Clamp Voltage Pin 2, Unloaded 25°C 1.3 1.5 1.9 V
Discharge Current Pin 2 = 2V 25°C 6 10 20 µA
Clamp Charge Current Pin 2, V
Ref Voltage Pin 6, V
= 1V 25°C 2 3 mA
IN
= 5V (Note 2) 25°C 1.5 1.8 2.1 V
DD
VOL Output Low Voltage IOL = 1.6mA 25°C 800 mV
V
Output High Voltage IOH = -40µA 25°C 4 V
OH
I
= -1.6mA 25°C 2.4 V
OH
NOTES:
1. No video signal, outputs unloaded.
2. Tested for V
5V ±5% which guarantees timing of output pulses over this range.
DD
Dynamic Specifications V
= 5V, IVpk-pk video, TA = 25°C, CL = 15pF, IOH = -1.6mA, IOL = 1.6mA. Signal voltages are peak to peak.
DD
PARAMETER DESCRIPTION TEMP MIN TYP MAX UNIT
Vertical Sync Width, t
Burst/Back Porch Width, t
VS
B
Vertical Sync Default Delay t
Filter Attenuation F
Composite Sync Prop Delay V
(Note 1) 25°C 190 230 300 µs
(Note 1) 25°C 2.5 3.5 4.5 µs
VSD
= 3.4MHz (Note 2) 25°C 24 dB
IN
- Composite Sync (Note 1) 25°C 260 400 ns
IN
25°C405570µs
Input Dynamic Range p-p NTSC Signal (Note 3) 25°C 0.5 2 V
Slice Level Input Voltage = 1V
P-P
25°C 40% 50% 60%
(Note 4) Full 40% 50% 60%
NOTES:
1. C/S, Vertical and Burst outputs are all active low - V
2. Attenuation is a function of R
3. Typical min. is 0.3V
4. Refers to threshold level of sync. tip to back porch amplitude.
P-P
.
SET
(PIN6).
= 2.4V, VOL = 0.8V.
OH
2
EL4581
Pin Descriptions
PIN NUMBER PIN NAME FUNCTION
1 Composite Sync Out Composite sync pulse output. Sync pulses start on a falling edge and end on a rising edge.
2 Composite Video in AC coupled composite video input. Sync tip must be at the lowest potential (Positive picture phase).
3 Vertical Sync Out Vertical sync pulse output. The falling edge of Vert Sync is the start of the vertical period.
4 GND Supply ground.
5 Burst/Back Porch Output Burst/Back porch output. Low during burst portion of composite video.
6R
7 Odd/Even Output Odd/Even field output. Low during odd fields, high during even fields. Transitions occur at start of
8V
NOTE 1. R
SET
(Note 1) An external resistor to ground sets all internal timing. 681k, 1% resistor will provide correct timing
SET
5V Positive supply. (5V)
DD
must be a 1% resistor.
for NTSC signals.
Vert Sync pulse.
3