intersil EL4511 DATA SHEET

®

EL4511

Data Sheet July 21, 2005

Super Sync Separator

The EL4511 sync separator IC is designed for operation in

the next generation of DTV, HDTV, and projector

applications, as well as broadcast equipment and other

applications where video signals need to be processed.

The EL4511 accept s sync on green, separate sync, and H/V

sync inputs, automatically selecting the relevant format. It is

also capable of detecting and decoding tri-level syncs used

with the latest HD systems. Unlike standard sync separators,

the EL4511 can automatically detect the line rate and locks

to it, without the use of an external R

SET

resistor.

The EL4511 is available in a 24-pin QSOP package and

operates over the full 0°C to 70°C temperature range.

Ordering Information

PAR T

NUMBER PACKAGE

EL4511CU 24-Pin QSOP - MDP0040

EL4511CU-T7 24-Pin QSOP 7” MDP0040

EL4511CU-T13 24-Pin QSOP 13” MDP0040

EL4511CUZ

(See Note)

EL4511CUZ-T7

(See Note)

EL4511CUZ-T13

(See Note)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

24-Pin QSOP

(Pb-Free)

24-Pin QSOP

(Pb-Free)

24-Pin QSOP

(Pb-Free)

TAPE &

REEL PKG. DWG. #

- MDP0040

7” MDP0040

13” MDP0040

FN7009.7

Features

• Composite, component, HDTV, and PC signal-compatible

• Tri-level & bi-level sync-compatible

• Auto sync detection

• 150kHz max line rate

• Low power

• Small package outline

• 3.3V and 5V operation

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• HDTV/DTV analog inputs

• Video projectors

• Computer monitors

• Set top boxes

• Security video

• Broadcast video equipment

Pinout

EL4511

(24-PIN QSOP)

TOP VIEW

XTAL

VBLANK

SYNCLOCK

PDWN

SDENB

SCL

1

2

3

4

5

6

XTALN

24

ODD/EVEN

23

VERTOUT

22

HOUT

21

BACKPORCH

20

SYNCOUT

19

SDA

7

GNDD1

8

HIN

9

SYNCIN

10

VERTIN

11

LEVEL

12

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Manufactured under License, U.S. Patents 5,486,869; 5,754,250

Manufactured under U.S. Patent 5,528,303

18

17

16

15

14

13

VCCD

GNDD2

GNDA2

VCCA2

VCCA1

GNDA1

2

EL4511

Electrical Specifications V

= V

S

CCA1

= V

CCA2

= V

= +5V, TA = 25°C, NTSC input signal on SYNCIN, no output loads, unless

CCD

otherwise specified. (Continued)

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

REFERENCE OSCILLATOR

F

IN

F

XTAL

CONTROL INTERFACE SIGNALS PDWN, SDENB

V

HIGH

V

LOW

O/PV

HI

O/PV

LOW

F

SCL

T

Setup Time 30 ns

CLS

Hold Time 30 ns

T

CLH

T

Load to Clock Time 30 ns

LC

T

DC

Clock to Data Out Time 30 ns

T

CD

Reference Input Frequency Refer to description of operation 50 kHz

Crystal Frequency Watch crystal (optional) 32.768 kHz

, SCL AND SDA

Input Logic High Threshold V

Input Logic Low Threshold V

SDA O/P Logic High State @ 1mA V

+1V

GNDD

-0.4 V

CCD

-1V

SDA O/P Logic Low State @ 1mA GNDD+0.4 V

Serial Control Clock Frequency 5 MHz

Hold to Clock Time 30 ns

NOTES:

1. NTSC signal; see curves for other rates.

2. XTAL pin must be low, otherwise 70µA.

3. I/P range reduces if V

of 3.3V - 4.5V (see Timing Diagram 1).

S

3

FN7009.7

July 21, 2005

EL4511

Pin Descriptions

PIN NUMBER PIN NAME PIN TYPE PIN DESCRIPTION

1 XTAL Input Crystal input (see Table 2 for details)

2 VBLANK Logic Output Vertical blank output

3 SYNCLOCK Logic Output Indicates that the EL4511 has locked to the line rate and has found three consecutive

“good H lines”

4 PWDN Logic Input Power-down = hi

5 SDENB

6 SCL Logic Input Serial clock

7 SDA Logic BIDIR Serial data (input for chip setup, output for diagnostic information)

8 GNDD1 Power Digital ground 1

9 HIN Input Horizontal sync

10 SYNCIN Input Video input, which may incorporate sync signal; connect to Y or G

11 VERTIN Input Vertical sync input

12 LEVEL Output Indicates 2x amplitude of sync tip vs. back porch; referred to ground

13 GNDA1 Power Analog ground 1

14 VCCA1 Power Analog power supply 1

15 VCCA2 Power Analog power supply 2

16 GNDA2 Power Analog ground 2

17 GNDD2 Power Digital ground 2

18 VCCD1 Power Digital power supply 1

19 SYNCOUT Logic Output Composite sync output

20 BACKPORCH Logic Output Back porch output

21 HOUT Logic Output Horizontal sync output

22 VERTOUT Logic Output Vertical sync output

23 ODD/EVEN Logic Output Odd-Even field indicator output

24 XTALN Output Crystal output (see Table 2 for details)

Logic Input Serial interface enable = low

Typical Performance Curves

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD

1.4

1.136W

1.2

1

0.8

0.6

0.4

0.2

POWER DISSIPATION (W)

0

0 255075100 150

FIGURE 1. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

Q

S

θ

O

J

A

P

=

2

8

4

8

°

C

/

W

12585

AMBIENT TEMPERATURE (°C)

4

JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD

1.2

1

870mW

0.8

0.6

0.4

0.2

POWER DISSIPATION (W)

0

0 255075100 150

Q

θ

S

O

J

A

P

=

2

1

4

1

5

°

C

/

W

12585

AMBIENT TEMPERATURE (°C)

FIGURE 2. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FN7009.7

July 21, 2005

EL4511

VCCDVCCA1

VERTICAL SYNC

COMPOSITE SYNC

HORIZONTAL SYNC

POWER DOWN

LOW ACTIVE SERIAL

DATA ENABLE

SERIAL CLOCK

SERIAL DATA

VERTIN

SYNCIN

HIN

PDWN

SDENB

SCL

SDA

SLICING

&

ANALOG

PROCESSING

RESET

SERIAL I/F

GNDA1

DIGITAL PROCESSING

RATE ACQUISITION OSCILLATOR

REFERENCE

OSCILLATOR

MODE CONTROL PINS

FIGURE 3. BLOCK DIAGRAM

LEVEL

HOUT

SYNCOUT

VERTOUT

VBLANK

BACKPORCH

ODD/EVEN

SYNCLOCK

GNDD1

GNDD2

XTALXTALINGNDA2VCCA2

SYNC LEVEL

HORIZONTAL O/P

COMP SYNC O/P

VERTICAL O/P

VERTICAL BLANKING O/P

BACK PORCH O/P

ODD/EVEN O/P

SYNC LOCK O/P

5

FN7009.7

July 21, 2005

3H 3H 3H

2 3

1

4 5

6 7

8 9

10 19 20

21

Start of Field One

9 Line Vertical Interval

Notes:

b. The composite sync output reproduces all the video input sync pulses, with a propagation delay. c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay. d. Odd-even output is low for even field, and high for odd field. e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay).

Post-Equalizing

Pulse Interval

.5H

FIGURE 4. EXAMPLE OF VERTICAL INTERVAL (525)

6

FN7009.7

July 21, 2005

SYNCOUT OUTPUT

OUTPUT

V

OUT

ODD/EVEN OUTPUT

BACKPORCH OUTPUT

EL4511

COMPOSITE VIDEO INPUT, BEGINNING OF FIELD ONE

START OF FIELD ONE

622 623 624 625 1 2 3 4 5 6 7 23 24

T

VS

H

OUTPUT

OUT

V BLANK OUTPUT

Notes:

b. The composite sync output reproduces all the video input sync pulses, with a propagation delay. c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay. d. Odd-even output is low for even field, and high for odd field. e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay).

FIGURE 5. EXAMPLE OF VERTICAL INTERVAL (625)

7

FN7009.7

July 21, 2005

SYNCIN

SYNCOUT

H

OUT

BACKPORCH

V

OUT

V

BLANK

EL4511

8 ... 211125 723 45 61124 11123

DEFAULT 20 LINES

ODD/EVEN

SYNCIN

SYNCOUT

H

OUT

BACKPORCH

V

OUT

V

BLANK

ODD/EVEN

DEFAULT 20 LINES

ODD FIELD

EVEN FIELD

FIGURE 6. EXAMPLE OF HDTV 1080I/30 LINE COMPOSITE VIDEO: INTERLACED, ODD & EVEN FIELD

570 ... 583562 569564 565 566 567 568561 563560

8

FN7009.7

July 21, 2005