®
EL4511
Data Sheet July 21, 2005
Super Sync Separator
The EL4511 sync separator IC is designed for operation in
the next generation of DTV, HDTV, and projector
applications, as well as broadcast equipment and other
applications where video signals need to be processed.
The EL4511 accept s sync on green, separate sync, and H/V
sync inputs, automatically selecting the relevant format. It is
also capable of detecting and decoding tri-level syncs used
with the latest HD systems. Unlike standard sync separators,
the EL4511 can automatically detect the line rate and locks
to it, without the use of an external R
SET
resistor.
The EL4511 is available in a 24-pin QSOP package and
operates over the full 0°C to 70°C temperature range.
Ordering Information
PAR T
NUMBER PACKAGE
EL4511CU 24-Pin QSOP - MDP0040
EL4511CU-T7 24-Pin QSOP 7” MDP0040
EL4511CU-T13 24-Pin QSOP 13” MDP0040
EL4511CUZ
(See Note)
EL4511CUZ-T7
(See Note)
EL4511CUZ-T13
(See Note)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
24-Pin QSOP
(Pb-Free)
24-Pin QSOP
(Pb-Free)
24-Pin QSOP
(Pb-Free)
TAPE &
REEL PKG. DWG. #
- MDP0040
7” MDP0040
13” MDP0040
FN7009.7
Features
• Composite, component, HDTV, and PC signal-compatible
• Tri-level & bi-level sync-compatible
• Auto sync detection
• 150kHz max line rate
• Low power
• Small package outline
• 3.3V and 5V operation
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• HDTV/DTV analog inputs
• Video projectors
• Computer monitors
• Set top boxes
• Security video
• Broadcast video equipment
Pinout
EL4511
(24-PIN QSOP)
TOP VIEW
XTAL
VBLANK
SYNCLOCK
PDWN
SDENB
SCL
1
2
3
4
5
6
XTALN
24
ODD/EVEN
23
VERTOUT
22
HOUT
21
BACKPORCH
20
SYNCOUT
19
SDA
7
GNDD1
8
HIN
9
SYNCIN
10
VERTIN
11
LEVEL
12
1
Copyright © Intersil Americas Inc. 2002-2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Manufactured under License, U.S. Patents 5,486,869; 5,754,250
Manufactured under U.S. Patent 5,528,303
18
17
16
15
14
13
VCCD
GNDD2
GNDA2
VCCA2
VCCA1
GNDA1
2
EL4511
Electrical Specifications V
= V
S
CCA1
= V
CCA2
= V
= +5V, TA = 25°C, NTSC input signal on SYNCIN, no output loads, unless
CCD
otherwise specified. (Continued)
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
REFERENCE OSCILLATOR
F
IN
F
XTAL
CONTROL INTERFACE SIGNALS PDWN, SDENB
V
HIGH
V
LOW
O/PV
HI
O/PV
LOW
F
SCL
T
Setup Time 30 ns
CLS
Hold Time 30 ns
T
CLH
T
Load to Clock Time 30 ns
LC
T
DC
Clock to Data Out Time 30 ns
T
CD
Reference Input Frequency Refer to description of operation 50 kHz
Crystal Frequency Watch crystal (optional) 32.768 kHz
, SCL AND SDA
Input Logic High Threshold V
Input Logic Low Threshold V
SDA O/P Logic High State @ 1mA V
+1V
GNDD
-0.4 V
CCD
CCD
-1V
SDA O/P Logic Low State @ 1mA GNDD+0.4 V
Serial Control Clock Frequency 5 MHz
Hold to Clock Time 30 ns
NOTES:
1. NTSC signal; see curves for other rates.
2. XTAL pin must be low, otherwise 70µA.
3. I/P range reduces if V
of 3.3V - 4.5V (see Timing Diagram 1).
S
3
FN7009.7
July 21, 2005
EL4511
Pin Descriptions
PIN NUMBER PIN NAME PIN TYPE PIN DESCRIPTION
1 XTAL Input Crystal input (see Table 2 for details)
2 VBLANK Logic Output Vertical blank output
3 SYNCLOCK Logic Output Indicates that the EL4511 has locked to the line rate and has found three consecutive
“good H lines”
4 PWDN Logic Input Power-down = hi
5 SDENB
6 SCL Logic Input Serial clock
7 SDA Logic BIDIR Serial data (input for chip setup, output for diagnostic information)
8 GNDD1 Power Digital ground 1
9 HIN Input Horizontal sync
10 SYNCIN Input Video input, which may incorporate sync signal; connect to Y or G
11 VERTIN Input Vertical sync input
12 LEVEL Output Indicates 2x amplitude of sync tip vs. back porch; referred to ground
13 GNDA1 Power Analog ground 1
14 VCCA1 Power Analog power supply 1
15 VCCA2 Power Analog power supply 2
16 GNDA2 Power Analog ground 2
17 GNDD2 Power Digital ground 2
18 VCCD1 Power Digital power supply 1
19 SYNCOUT Logic Output Composite sync output
20 BACKPORCH Logic Output Back porch output
21 HOUT Logic Output Horizontal sync output
22 VERTOUT Logic Output Vertical sync output
23 ODD/EVEN Logic Output Odd-Even field indicator output
24 XTALN Output Crystal output (see Table 2 for details)
Logic Input Serial interface enable = low
Typical Performance Curves
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
1.4
1.136W
1.2
1
0.8
0.6
0.4
0.2
POWER DISSIPATION (W)
0
0 255075100 150
FIGURE 1. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Q
S
θ
O
J
A
P
=
2
8
4
8
°
C
/
W
12585
AMBIENT TEMPERATURE (°C)
4
JEDEC JESD51-3 LOW EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
1.2
1
870mW
0.8
0.6
0.4
0.2
POWER DISSIPATION (W)
0
0 255075100 150
Q
θ
S
O
J
A
P
=
2
1
4
1
5
°
C
/
W
12585
AMBIENT TEMPERATURE (°C)
FIGURE 2. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7009.7
July 21, 2005
EL4511
VCCDVCCA1
VERTICAL SYNC
COMPOSITE SYNC
HORIZONTAL SYNC
POWER DOWN
LOW ACTIVE SERIAL
DATA ENABLE
SERIAL CLOCK
SERIAL DATA
VERTIN
SYNCIN
HIN
PDWN
SDENB
SCL
SDA
SLICING
&
ANALOG
PROCESSING
RESET
SERIAL I/F
GNDA1
DIGITAL PROCESSING
RATE
ACQUISITION
OSCILLATOR
REFERENCE
OSCILLATOR
MODE CONTROL PINS
FIGURE 3. BLOCK DIAGRAM
LEVEL
HOUT
SYNCOUT
VERTOUT
VBLANK
BACKPORCH
ODD/EVEN
SYNCLOCK
GNDD1
GNDD2
XTALXTALINGNDA2VCCA2
SYNC LEVEL
HORIZONTAL O/P
COMP SYNC O/P
VERTICAL O/P
VERTICAL BLANKING O/P
BACK PORCH O/P
ODD/EVEN O/P
SYNC LOCK O/P
5
FN7009.7
July 21, 2005
3H 3H 3H
2 3
1
4 5
6 7
8 9
10 19 20
21
Start of
Field One
9 Line
Vertical
Interval
Notes:
b. The composite sync output reproduces all the video input sync pulses, with a propagation delay.
c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay.
d. Odd-even output is low for even field, and high for odd field.
e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses
during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay).
Post-Equalizing
Pulse Interval
.5H
FIGURE 4. EXAMPLE OF VERTICAL INTERVAL (525)
6
FN7009.7
July 21, 2005
SYNCOUT OUTPUT
OUTPUT
V
OUT
ODD/EVEN OUTPUT
BACKPORCH OUTPUT
EL4511
COMPOSITE VIDEO INPUT, BEGINNING OF FIELD ONE
START OF FIELD ONE
622 623 624 625 1 2 3 4 5 6 7 23 24
T
VS
H
OUTPUT
OUT
V BLANK OUTPUT
Notes:
b. The composite sync output reproduces all the video input sync pulses, with a propagation delay.
c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay.
d. Odd-even output is low for even field, and high for odd field.
e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses
during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay).
FIGURE 5. EXAMPLE OF VERTICAL INTERVAL (625)
7
FN7009.7
July 21, 2005
SYNCIN
SYNCOUT
H
OUT
BACKPORCH
V
OUT
V
BLANK
EL4511
8 ... 211125 723 45 61124 11123
DEFAULT 20 LINES
ODD/EVEN
SYNCIN
SYNCOUT
H
OUT
BACKPORCH
V
OUT
V
BLANK
ODD/EVEN
DEFAULT 20 LINES
ODD FIELD
EVEN FIELD
FIGURE 6. EXAMPLE OF HDTV 1080I/30 LINE COMPOSITE VIDEO: INTERLACED, ODD & EVEN FIELD
570 ... 583562 569564 565 566 567 568561 563560
8
FN7009.7
July 21, 2005
EL4511
Default 20 Lines
Default 20 Lines
FIGURE 7. HDTV 1080I/25 LINE COMPOSITE VIDEO: INTERLACED ODD & EVEN FIELD (1250 LINES)
9
FN7009.7
July 21, 2005
EL4511
Timing Diagram 1 - Example of Horizontal Interval 525/625 Line Composite
CONDITIONS: V
INPUT
DYNAMIC
RANGE
0.5V-2V
CCA1
CCA1
=5V)
0.5V-1V
=3.3V)
(@V
(@V
= V
CCA1
SYNC IN
SYNC OUT
H
OUT
= V
CCA2
SYNC LEVEL
50%
td
SYNCOUT
td
HOUT
= +5V, TA = 25°C, NO FILTER (REGISTER 2 BIT 4 = 0)
CCD
COLOR BURST
V
SLICE
V
SYNC
SYNC
TIP
(SYNC TIP
VOLTAGE)
DEPENDS ON WIDTH OF INPUT SYNC AT 50% LEVEL
WHITE LEVEL
V
BLANK
(BLANKING LEVEL
VOLTAGE)
VIDEO
SYNC
T
HOUT
T
BACKPORCH
BACKPORCH
td
BACKPORCH
No Filter
PARAMETER DESCRIPTION CONDITIONS
td
SYNCOUT
td
HOUT
td
BACKPORCH
T
HOUT
T
BACKPORCH
NOTE:
1. Delay variation is less than 2.5ns over temperature range.
SYNCOUT Timing Relative to Input See Timing Diagram 1 65 ns
HOUT Timing Relative to Input See Timing Diagram 1 470 ns
BACKPORCH Timing Relative to Input See Timing Diagram 1 525 ns
Horizontal Output Width See Timing Diagram 1 1545 ns
BACKPORCH (Clamp) Width See Timing Diagram 1 3345 ns
TYP
(Note 1) UNIT
10
FN7009.7
July 21, 2005
EL4511
Timing Diagram 2 - Example of Horizontal Interval 525/625 Line Composite
CONDITIONS: V
INPUT
DYNAMIC
RANGE
0.5V-2V
CCA1
CCA1
=5V)
0.5V-1V
=3.3V)
(@V
(@V
= VC
CCA1
SYNC IN
SYNC OUT
H
OUT
= V
CA2
CCD
SYNC LEVEL
50%
td
SYNCOUT
td
HOUT
= +5V, TA = 25°C, FILTER IN (REGISTER 2 BIT 4 = 1)
COLOR BURST
SYNC
TIP
DEPENDS ON WIDTH OF INPUT SYNC AT 50% LEVEL
V
SYNC
(SYNC TIP
VOLTAGE)
V
SLICE
WHITE LEVEL
V
BLANK
(BLANKING LEVEL
VOLTAGE)
VIDEO
SYNC
T
HOUT
T
BACKPORCH
BACKPORCH
td
BACKPORCH
Filter In
PARAMETER DESCRIPTION CONDITIONS
td
SYNCOUT
td
HOUT
td
BACKPORCH
T
HOUT
T
BACKPORCH
NOTE:
1. Delay variation is less than 2.5ns over temperature range.
SYNCOUT Timing Relative to Input See Timing Diagram 2 220 ns
HOUT Timing Relative to Input See Timing Diagram 2 470 ns
BACKPORCH Timing Relative to Input See Timing Diagram 2 525 ns
Horizontal Output Width See Timing Diagram 2 1545 ns
BACKPORCH (Clamp) Width See Timing Diagram 2 3345 ns
TYP
(Note 1) UNIT
11
FN7009.7
July 21, 2005
12
EL4511
Timing Diagram 4 - Example of Horizontal Interval (HDTV)
CONDITIONS: V
SYNCIN
SYNC OUT
CCA1
H
OUT
= V
CCA2
td
SYNCOUT
= V
= +3.3V/+5V, TA = 25°C, FILTER (REGISTER 2 BIT 4 = 1)
CCD
td
HOUT
T
HOUT
T
BACKPORCH
BACKPORCH
td
BACKPORCH
H Timing for HDTV, With Filter (using 720p input)
PARAMETER DESCRIPTION CONDITIONS
td
SYNCOUT
td
HOUT
td
BACKPORCH
T
HOUT
T
BACKPORCH
NOTE:
1. Delay variation is less than 2.5ns over temperature range.
SYNCOUT Timing Relative to Input See Timing Diagram 4 120 110 ns
HOUT Timing Relative to Input See Timing Diagram 4 112 100 ns
BACKPORCH Timing Relative to Input See Timing Diagram 4 155 140 ns
Horizontal Output Width See Timing Diagram 4 300 300 ns
BACKPORCH (Clamp) Width See Timing Diagram 4 300 300 ns
TYP
@ 3.3V
(Note 1)
TYP
@ 5V
(Note 1) UNIT
13
FN7009.7
July 21, 2005
Operation Summarized Table
Default register settings. All with no external analog filter. No Mode setting. 525/625
PINS 1 &
OPERATING
STANDARD DEFAULT
SDTV (Clean signals)
525 NTSC Yes 00 default Cor rect Correct Correct Correct Correct Correct Correct
14
SDTV (VHS tape signals)
SDTV (525 only)
Macrovision VHS O/P Yes 00 default See Note See Note See Note See Note See Note See Note See Note This operation works on most machines, but
Macrovision DVD O/P Ye s 00 default Bad See N ote See Note See Note See Note See Note See Note Short drop out on one field, likely some
EDTV Bi-Level Sync
No O/E output for some of these standards, because no serrations during vertical
625 PAL Ye s 00 default Correct Correct Correct Correct Correct Correct Correct
625 SECAM Yes 00 default Correct Corr ect Correct Correct Correct Correct Correct
525 NTSC Yes 00 default Correct Correct Correct Correct Correct Correct Will break up with Fast Forward and Fast
625 PAL Ye s 00 default Correct Correct Correct Correct Correct Correct Will break up with Fast Forward and Fast
625 SECAM Yes 00 default Correct Correct Correct Correct Correct Correct Will break up with Fast Forward and Fast
480 I / (29/30) Yes 00 default Correct Corr ect Always H Correct Correct Correct Correct
24 XTAL,
XTALN
DIGITAL
FILTER
ENABLED
SYNC
LOCKV BLANK O/E V
OUT
H
OUT
BACK
PORCH
SYNC
OUT COMMENTS
Reverse modes.
Reverse modes.
Reverse modes.
some combinations will fail
machines will fail.
EL4511
480 I / (59/60) Yes 00 default Correct Corr ect Always H Correct Correct Correct Correct
480 P / (59/60) Yes 00 default Correct Corr ect Always H Correct Correct Correct Correct
576 P / (50) Yes 00 default Correct Corr ect Always H Correct Correct Correct Correct
HDTV Tri-Level Sync
720 P / (59/60) Yes 00 default Correct Corr ect Always H
(correct)
July 21, 2005
FN7009.7
1080 I /24 Yes 00 default Correct Corr ect Correct Correct Correct Correct Correct
1080 I / 25 Yes 00 default Correct Corr ect Correct Correct Correct Correct Correct
Correct Correct Correct Correct
Operation Summarized Table
Default register settings. All with no external analog filter. No Mode setting. 525/625 (Continued)
PINS 1 &
OPERATING
STANDARD DEFAULT
1080 I / (29/30) Yes 00 default Correct Corr ect Correct Correct Correct Correct Correct
1080 I / (48/50) Yes 00 default Correct Corr ect Correct Correct Correct Correct Correct
15
VGA
All standards generated by the Quantum are supported except 1024@42Hz and work OK
1024/X (4 of 5 standards) Yes 11 default Correct Corr ect Always H Correct Correct Correct Correct 1024@42 not supported
1080 I / (59/60) Yes 00 default Correct Corr ect Correct Correct Correct Correct Correct
1035 I / (29/30) Yes 00 default Correct Corr ect Correct Correct Correct Correct Correct
1080 P /
(24/35/30/50/59/60)
640 /X (6 standards) Yes 11 default Correct Corr ect Always H Correct Correct Correct Correct
720 Yes 11 default Correct Corr ect Always H Correct Correct Correct Correct
800/X (5 standards) Yes 11 default Correct Corr ect Always H Correct Correct Correct Correct
1152 Ye s 11 default Correct Correct Always H Correct Correct Correct Correct
1280/X (5 standards) Yes 11 default Correct Corr ect Always H Correct Correct Correct Correct
1600/X (5 standards) Yes 11 default Correct Corr ect Always H Correct Correct Correct Correct
Yes 00 default Correct Correct Always H
24 XTAL,
XTALN
DIGITAL
FILTER
ENABLED
SYNC
LOCKV BLANK O/E V
(correct)
BACK
OUT
PORCH
OUT
Correct Correct Correct Correct
H
SYNC
OUT COMMENTS
EL4511
1792/X (2 standards) Yes 11 default Correct Corr ect Always H Correct Correct Correct Correct
1836/X (2 standards) Yes 11 default Correct Corr ect Alw ays H Correct Correct Correct Correct Max Line rate 112.5kHz
1920/X (2 standards) Yes 11 default Correct Corr ect Alw ays H Correct Correct Correct Correct Max Line rate 112.5kHz
July 21, 2005
FN7009.7
Timing Diagram 5 - 720p Standard with Filter in Circuit
Description of Operation
The EL4511 has 3 modes of operation. The first is default
mode with pins 1 and 24 connected to ground with 10K.
Second is using pins 1 and 24 to provide simple mode
control. The third is using the serial port to use a crystal or a
clock into XTALN pin 24 to determine the vide o syn c rate
and/or more extensive mode control.
The EL4511 incorporates the following functional blocks:
• Analog I/Ps, processing, and slicing
• Signal source and polarity detector
• Signal & H rate acquisition block
• Advanced sync separator which will detect both
conventional and tri-level sync signals
• Video lock and level indicators
• Reference counter
• Computer and control interface
Analog I/Ps, Processing, and Slicing
The EL4511 has three I/P pins which may be connected to a
source of external sync signals.
For YPrPb or RGB applications, Y or G should be connected
to SYNCIN. For applications with separate horizontal and
vertical sync inputs, these should be connected to HIN and
VERTIN, respectively. (HIN may also be used for composite
sync without video.)
Hi. Setting bit 1 to high will disconnect the input bias
network.
Once the acquisition process is complete (see below for
description), the slice level will be adaptive. The sync signal
is measured from sync tip to blanking level; (Tri-level is
measured between negative and positive sync tips). The
slice level is then set to 50% of these levels.
(Serial Mode) It is possible to force the slicing level to
remain at the fixed level of 78mV above the sync tip;
Register 2, bit 5 is set High to do this. This can help when
dealing with signal that have bursts of noise, or formats that
have signals that will modify the sync amplitude
measurement process.
VGA type of signals will be connected to the HIN and
VERTIN pins (use HIN for combined H & V). These are DC
coupled signals; they will be sliced at a fixed le vel of
approximately 1.4V. These inputs may be any combination
of positive and negative polarities; the EL4511 will inverss (u wTJT*-0.0013 Tc0.0035 Tw[4.0019 Tc016 Tc0.0038 Tw[(is measured)-5.requ
Composite video input signals should be connected to
SYNCIN. This should be AC coupled from a low impedance
source. The input resistance is in the order of 100kΩ. Af ter H
lock is obtained, this signal will be “soft clamped” (5kΩ) to
approximately 20% of the V
In the default mode, the clamping action ensures that the
correct slicing levels will be used throughout the field.
(Serial Mode) This operation can be modified through
Register 9. The soft clamp can be disabled by setting bit 3 to
CCA1
16
voltage.
FN7009.7
July 21, 2005
Video Format Switching
The part should be powered down for at least 500µs to re set
the internal registers when the input video signal is switched
from one video format to another video format. It is possible
the part will generate wrong outputs if it is not powered down
between two different input video signals.
USE OF THE POWER DOWN FUNCTION
The Power down pin (pin 4) can be used to hard reset the
internal circuit of the EL4511. To disable the internal circuit,
just apply a 5V to the power down pin. To enable the internal
circuit, just apply a 0V to the power down pin.
The SYNCLOCK pin 3 minus edge can be used to generate
a 5V 500µs pulse to the PDWN pin 4 to reset the internal
digital registers automatically when the video input has a
changed video format.
(Serial Mode) The oscillator frequency is adjusted at the
beginning of the line. At the time of frequency adjustment the
clock O/P may have a phase discontinuity.
Advanced Sync Separator
Once the line rate has been determined, the signal can be
analyzed by the advanced sync separator. This has been
designed to be compatible with a wide range of video
standards, operating with horizontal line rates up to 150kHz.
PAL/NTSC/SECAM; HDTV, including bi-l evel and tri-level
sync Standards and computer display syncs. The EL4511
can be programmed to disable the detection of either bi-level
or tri-level sync signals or to prioritize the detection of one
sync signal type over the other.
If the vertical sync input pin, VERTIN, is enabled, the EL4511
will automatically detect whether a valid signal is present on
that pin, and incorporate that signal into the algorithm.
Otherwise, the input signal on which the horizontal sync was
detected will be treated as a composite sync. The sync
separator also includes a qualification scheme which rejects
high frequency noise and other video artifacts, such as color
burst. The horizontal line rate is automatically acquired from
the signal (see above.) A digital filter is included in the signal
path to remove noise and glitches; this may be removed if
the extra delay it incurs needs to be removed. (Serial Mode)
Setting register 2, bit 4 to Low will remove the filter.
Horizontal Rate Acquisition Oscillator
This oscillator is frequency locked to 512 times the horizontal
rate. This clock signal generates the timing and gating
signals that are employed internally by the EL4511. This
operation is entirely automatic and requires no input from the
external circuitry or microprocessor.
(Serial Mode) It is possible to gain access to this oscillator
O/P by changing the assignment of pin 2 (V
(ODD/EVEN).
Register 6, bits 7:6 make this selection; see Table 1 for
allocations.
TABLE 1. ACQUISITION CLOCK MULTIPLEXER
CmuxCtrl ACTION
Reg6
b7 b6
0 0 Normal Operation
0 1 Clock multiplexed onto Odd/Even (pin 23)
1 0 Clock multiplexed onto V
1 1 Reserved
BLANK
BLANK
(pin 2)
) or pin 23
After the signal has been identified and the qualification
process is complete, the SYNCLOCK pin will go high and
the output waveforms will be enabled. (Serial Mode) These
may be enabled all the time by setting register 1, bit 6 to a
high state. This can help noisy and varying signals as the
revalidation does not have to take place before the signals
are available at the outputs, See Figures 4 through 7 for
examples of various types of input signal.
Part of the signal recognition algorithm uses the number of
horizontal lines between vertical pulses. A counter is clocked
by the Hclock, this counter is also used to generate vertical
timing pulses. (Serial Mode) This count information is
available via the serial I/F; this is a 12 bit number.
(Serial Mode) The lines per frame count is available at
register 8, bits 7:4 for the MSBs; the LSBs are available at
register 7, bits 7:0. Register 8, bit 2 indicates that the
lines/frame counter has been updated when it is high.
This counter also generates the V
waveform. Using a
BLANK
look up table, the default blanking is based on number of
lines in the field. (Serial Mode) This operation may be
disabled by setting register 3, bit 7 to a low. As this is
dependent on application and product usage, this may be
modified. Register 3, bits 6:0 will set the number of
horizontal lines after VERTOUT leading edge. Register 4,
bits 7:4 sets the number of lines before the VERTOUT
leading edge.
17
FN7009.7
July 21, 2005
Video Lock and Level Indicators
Loss of video signal can be detected by monitoring the
SYNCLOCK pin 3. This pin goes high once the sync
separator has detected a valid sync signal and goes low if
this signal is lost for more than 20 successive lines. (Serial
Mode) This signal is also available at register 14 pin 5. Other
lock acquisition signals available from the system are listed
in Table 4.
The sync tip amplitude is buffered with a nominal gain of
2.15 to produce a positive, ground-referenced signal on the
LEVEL pin. This output can be used for AGC applications.
Decode Mode
In order to allow more flexibility when operating without a
serial interface, the XTAL and XTALN pins are decoded by
default to enable four control modes. These modes could be
used to over-ride sync type used. See Table 2 for details.
(Serial Mode) The all-signal type allowed mode is the same
as the default mode when the crystal oscillator is enabled
(set bit 6 of Reg9 to 1) except the countsPerField function is
disabled in Reg13 and Reg14.
The bi-level mode is for bi-level sync only, such as NTSC
and PAL. The tri-level mode is for tri-level sync only, such as
HDTV signals. The VGA only mode is for computer digital
types of signals signal only.
TABLE 2. MODE CONTROL USING PINS 1 & 24
ENXTAL
Register9
b 6
0 0 0 0 0 0 All signals
0 0 1 0 1 1 Tri-Level Only
0 1 0 1 0 1 Bi-Level Only
0 1 1 1 1 1 VGA only
1 X X Set by
PIN 1
XTAL
PIN 24
XTALN
MODE
CONTROL DESCRIPTION
Register1
b5 b4 b3
enabled
Serial I/F
Crystal Oscillator
is operational
Applications Examples
The following examples show how a system may be
configured to operate the EL4511.
Application 1 (minimum circuitry application)
In this example, the requirement is for vertical and horizontal
timing to be generated from either an NTSC/PAL composite
video waveform, or a computer generated image with
separate TTL level syncs.
The EL4511 has the advantage that the sync separation is
carried out over a wide frequency range without the need to
adjust "R
separators.
As there is no Microcontroller connected in this example,
there is no need for a XTAL at pins 1 & 24. These pins are
tied low, this enables the EL4511 to check for either type of
input signal (See Table 2 for details.)
The internal pull-up resistors on XTAL & XTALN are very
high, these pins should use 10kΩ pull-up/down to operate
when not using a crystal.
By default, the EL4511 will wake up with Register 9, bit 6 set
to Low. This will allow the use of logic levels on pins 1 & 24
to drive register1, bits 5:3 and register 2 bit 0 into the
combinations shown in Table 2.
(Serial Mode) To define the mode through the serial
interface, the register 9, bit 6 must be set to High, the logic
levels on pins 1 & 24 are no longer valid; (most likely now
being an AC signal for the reference clock).
" as required by earlier generations of sync
SET
18
FIGURE 8. APPLICATIONS DRAWING 1
FN7009.7
July 21, 2005
EL4511
Application 2 (application using mode setting
logic signals)
In this example, the require m en t is to provide the
synchronizing information in a small display device. In this
example the incoming sync signals may come from one of
three sources. Computer, HDTV Set-top Box or an
NTSC/PAL tuner.
The EL4511 has the advantage that the sync separation is
carried out over a wide frequency range without the need to
H SYNC
V SYNC
HDTV
SYNCS
75Ω
75Ω
75Ω
620Ω
adjust "R
SET
separators.
As there is no Microcontroller connected in this example,
there is no need for a XTAL at pins 1 & 24. These pins can
be used to force the EL4511 to select the correct operation
(and speed up acquisition).
Note that a Low Pas Filter is in the NTSC/PAL signal path to
reduce noise, glitches and subcarrier. (In signals with bad
Croma/Luma gain balance, the subcarrier can extend into
the sync slicing level) (See Table 2 for details.)
VIDEO SIGNALS (RGB)
VIDEO SIGNALS (HDTV)
COMPONENT
510pF
COMPOSITE
" as required by earlier generations of sync
V
CC
CVBS
75Ω
COMPUTER
HDTV
NTSC/PAL
VIDEO SIGNAL (CVBS)
+
4.7µF 0.1µF
10kΩ
10kΩ
100nF
9
11
10
4
1
24
14
HIN
VERTIN
SYNCIN
PDWN
XTAL
XTALN
8
FIGURE 9. APPLICATIONS DRAWING 2
V
CC
VCCA1
18
VCCD
15
VCCA2
GNDA2
VERTOUT
EL4511
HOUT
GNDD113GNDA217GNDD26SCL7SDA
0.1µF
16
22
VERTICAL
TIMING
21
HORIZONTAL
TIMING
V
CC
19
FN7009.7
July 21, 2005
EL4511
Serial Mode Operation
See “Description of Operation” for more details of (Serial
Mode).
Using the Reference Oscillator and Counter
A counter is provided for measuring the vertical time inte rval;
this counts the clocks at the XTAL pin 1 between vertical
pulses.
This information is not necessary for the operation of the
chip; only for information to the system micro-control. The
count value is read from register 14 at bits 7:6 for the MSBs,
the LSBs are available in register 13, bits 7:0. Register 14,
bit 4 should be a high to indicate that the read operation did
not collide with the up-date timing.
If the crystal oscillator is enabled through the serial interface
(Register 9, bit 6, ENXTAL), the XTAL and XTALN pins will
become the crystal input and crystal output pins for the
32.7kHz crystal. It is also possible to drive the XTAL pin with
a logic level clock up to a maximum of 50kHz; this signal is
only used to measure the vertical rate.
Example:
Using a 32.768kHz crystal, the count period is 30.52µs. With
a 20ms vertical rate, there will be approximately 656 cycles
(290 Hex) in the "counts per field" registers 13 and 14. With
a 16.666'ms vertical rate, the count of 546 (222 Hex) will be
seen.
Computer & Control Interface
In addition to the mode control pins, the chips default
operating mode may be changed by way of a serial
interface. This is of the three-wire type, Data, clock and
/enable. After the /ENABLE line (pin 5) is taken low, the 16
bits of data on the SDA pin 7 will be clocked into the chip by
the clock signal SCL pin 6. See Figure 10.
The first bit of the data determines whether it will be a read
or write operation. When set to a "0", a write operation will
take place. The following 7 bits, select the register to be
written to. Finally, the last 8 bits are the data to be written or
read. For a read operation, the first bit is a "1".
In general, when registers entries are changed, the
unchanged register bits must have the “Reset Values”
entered as defined by Table 5.
XTAL
(PIN 1)
XTALN
(PIN 24)
VERTOUT
TIMING
‘1’
‘0’
REGISTER 9
BIT 6
8
Q0 Q7
REGISTER 13 REGISTER 14
LD LD
8
Q0 Q7
R
CLK
(SEE TABLE 3)
10 BIT COUNTER
MODE
DECODE
Q6 Q7
Q8 Q9
3
REGISTER 1, BITS 5:3
REGISTER 2, BIT 0
TO SERIAL I/F
FIGURE 10. BLOCK DIAGRAM OF REFERENCE OSCILLATOR
20
FN7009.7
July 21, 2005
EL4511
TABLE 3. MODE CONTROL TRUTH TABLE
(see also Table 2 for hardware over-ride)
MODE
CTRL
Reg 1
b5 b4 b3
0 0 0 1 1 1 0 0 0
0 0 1 1 1 1 0 1 0
0 1 0 1 1 1 1 0 0
0 1 1 1 0 0 1 0 0
1 0 0 0 1 1 0 0 0
1 0 1 0 1 0 0 0 0
1 1 0 0 1 1 0 1 0
1 1 1 0 1 1 0 1 1
EnTriLevel, EnBiLevel and EnHinVin; these enable tri-level sync
detection, two-level sync detection and separate H/V (VGA) sync
detection, respectively.
Other signals used to prioritize tri-level syncs (TriLevPriority),
separate H/V (Hin Priority), or to only allow signals from
HIN/VERTIN (HinVinOnly).
EnTri
Level
EnBi
Level
EnHin
Vin
TriLevel
Priority
Hin
Priority
HinVin
Only
TABLE 4. ACQUISITION CONTROL SIGNALS
REGISTER BIT
8 3 En50Slice 1 = Sample and Hold front
8 1 Pro gressive 1 = Progressive scan
8 0 Tri-Level
9 5 ENLEVEL
9 4 ENLEVEL
9 2 ENALOS
14 5 SYNCLOCK Same information as
16 4 RateLocked Line rate is locked
16 3 ALOS Sync Amplitude is below
SIGNAL
NAME DESCRIPTION
end is in use
detected
Detected
BLANKING
1 = Tri-Level syncs detected
1 = V
when system is not locked
1 = Disable V
1 = Analog loss of signal not
used in lock indication.
SYNCLOCK pin 3
minimum
LEVEL
is available
LEVEL
Output
21
FN7009.7
July 21, 2005
EL4511
TABLE 5. SERIAL INTERFACE REGISTER BIT ALLOCATIONS
REGISTER
NUMBER
13 Absolute Timing Ref 1 R
14 Absolute Timing Ref 2 & Misc R
REGISTER
BIT SIGNAL NAME TYPE
1 General Control Reg 1 R/W 00h
7 General Reset 0 Software reset. Does not affect serial interface.
6 AlwaysEnOutputs 0 Overrides internal qualification of outputs.
5:3 ModeCtrl 0 Sync acquisition. Selects input signal. See Table 3.
2 General Control Reg 2 R/W 10h
5 Select Fixed Slicing (no S/H) 0 Necessary for SECAM. May be useful for VCRs.
4 FILTER_ENABLED 1 Set Hi to include digital filter on horizontal input.
1 OE_MODE 0 Set Hi for Odd/Even changes on rising edge of vertical.
3V
Control Reg 1 R/W 90h
BLANK
7 EnVBlank 1 Enables vertical blank interval detection algorithm.
6:0 VSTPlusBP 10h Number of lines after vertical sync time.
4V
& Polarity Ctrl R/W 4Fh
BLANK
7:4 VFrontPorch 4h N umber of lines before vertical sync time.
3 DefaultHPolarity 1 HIN polarity on reset if EnHpolarityDet = Lo.
2 DefaultVPolarity 1 VERTIN polarity on reset and if EnVpolarityDet = Lo.
1 EnHPolarityDet 1 Allows EL4511 to detect and set polarity on HIN.
0 EnVPolarityDet 1 Allows EL4511 to detect and set polarity on VERTIN.
6 Oscillator Control 2 R/W 22h
7:6 CMuxCtrl <1:0> 0 Multiplexes clock onto V
7V
O/P Reg 1 R Only valid if V
BLANK
7:0 LinesPerFrame <7:0> - Least significant byte of lines per frame count.
8V
O/P Reg 2 & Misc R 80h
BLANK
7:4 LinesPerFrame <11:8> - Most significant 4 bits of lines per frame count.
3 En50Slice - Indicates sample and hold front end is being used.
2 LPFValid - Indicates lines per frame has been updated.
1 progressive - N ot valid for certain types of composite sync.
0 tri-level detect - Only valid if tri-level sync detected.
9 Analog Control Reg 1 R/W
6 ENXTAL 0 Set Hi to enable cr ystal oscillator.
5 ENLEVELBLANKING 0 Set Hi to enable V
4 ENLEVEL
3 ENSYCLAMP
2ENALOS
1ENRVIDEO
0 PWRSAVE 0 Set Hi to put the analog circuit into powersave mode.
7:0 CountsPerField <7:0> - Crystal clock periods per field: L.S. Byte. (see description)
RESET
VALUE DESCRIPTION AND COMMENTS
or Odd/Even. See Table 1.
BLANK
circuit is enabled
BLANK
when not locked.
LEVEL
0 Set Hi to disable V
LEVEL
output.
0 Set Hi to disable “soft” sync tip clamping in SYNCIN.
0 Set Hi to disable analog loss of signal feature.
0 Set Hi to disable internal biasing on SYNCIN (passive resistor
or soft clamp.)
22
FN7009.7
July 21, 2005
TABLE 5. SERIAL INTERFACE REGISTER BIT ALLOCATIONS (Continued)
REGISTER
NUMBER
REGISTER
BIT SIGNAL NAME TYPE
7:6 CountsPerField <9:8> - Crystal clock periods per field: Bits 9:8. (see description)
5 SyncLock As sync lock pin.
4 CPFValid - Counts per field valid. Set L if read occurs during a n update.
3 SetBiLevel - Lo: Tri-level mode; Hi: Bi-level mode.
2 VinSyncDet - Indicates vertical sync on VERTIN successfully acquired.
1 VinPolarity - VERTIN polarity setting: Observe.
0 HPolarity - HIN polarity setting: Observe.
16 Oscillator Settings Observe 2 R
4 RateLocked - Indicates line rate successfully acquired.
3 ALOS - Analog loss of signal, measured via S/H. H indicates analog
RESET
VALUE DESCRIPTION AND COMMENTS
signal amplitude is below threshold.
23
FIGURE 11. SERIAL INTERFACE TIMING DIAGRAM
FN7009.7
July 21, 2005
EL4511
Application 3 (application using a microcontroller
interface)
In this example, the require m en t is to provide the
synchronizing information in a video digitizing interface. This
example is very similar to the example in application 2. In
this example the incoming sync signals may come from one
of three sources. Computer, HDTV source or an NTSC/PAL
device.
As there is a Microcontroller connected in this example, a
32.768kHz XTAL is connected to pins 1 & 24; this will all ow
the system microcontroller to gather timing information for
H SYNC
V SYNC
HDTV
SYNCS
75Ω
75Ω
VIDEO SIGNALS (RGB)
75Ω
VIDEO SIGNALS (HDTV)
620Ω
the vertical rate. To enable the crystal oscillator, register 9,
bit 6 must be set to a high.
Note that a Low Pass Filter is in the NTSC/P AL signal path to
reduce noise, glitches and subcarrier. (In signals with bad
Croma/Luma gain balance, the subcarrier can extend into
the sync slicing level).
As some of the signals in this application were non standard
formats, the fixed slice mode is used by setting register 2,
bit 5 to a high. Register 1, bit 6 is also set to a high. Th is
forced the EL4511 to provide outputs even when the input
signals are not recognized by the internal algorithms.
COMPONENT
CVBS
75Ω
100nF
COMPOSITE
9
HIN
11
VERTIN
10
SYNCIN
4
PDWN
1
XTAL
24
XTALN
14
18
VCCD
VCCA1
EL4511
GNDD113GNDA217GNDD26SCL7SDA
8
510pF
VIDEO SIGNAL (CVBS)
+
4.7µF 0.1µF
32.768kHz
CRYSTAL
FIGURE 12. APPLICATIONS DRAWING 3
V
CC
15
VCCA2
GNDA2
VERTOUT
HOUT
BACKPORCH
VBLANK
SDENB
5
V
CC
0.1µF
16
22
VERTICAL
TIMING
21
HORIZONTAL
TIMING
20
VIDEO
CLAMP
2
PLL
COAST
TO MICROCONTROLLER
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24
FN7009.7
July 21, 2005
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