The EL4332 is a triple very high speed 2:1 MultiplexerAmplifier. It is intended primarily for component video
multiplexing and is especially suited for pixel switching. The
amplifiers have their gain set to 2 internally, which reduces
the need for many external components. The gain-of-2
facilitates driving back terminated cables. All three amplifiers
are switched simultaneously from their A to B inputs by the
TTL/CMOS compatible, common A/B control pin.
A -3dB bandwidth of 300MHz together with 3ns multiplexing
time enable the full performance of the fastest component
video systems to be realized.
The EL4332 runs from standard ±5V supplies, and is
available in the narrow 16-pin small outline package.
Pinout
EL4332
[16-PIN SO (0.150”)]
TOP VIEW
FN7163.2
Features
• 3ns A-B switching
• 300MHz bandwidth
• Fixed gain of 2, for cable driving
• > 650V/µs slew rate
• TTL/CMOS compatible switch
• Pb-free available
Applications
• RGB multiplexing
• Picture-in-picture
• Cable driving
• HDTV processing
• Switched gain amplifiers
• ADC input multiplexer
Ordering Information
PART NUMBERPACKAGE
EL4332CS16-Pin SO (0.150”)-MDP0027
EL4332CS-T716-Pin SO (0.150”)7”MDP0027
EL4332CS-T1316-Pin SO (0.150”)13”MDP0027
EL4332CSZ
(Note)
EL4332CSZ-T7
(Note)
EL4332CSZ-T13
(Note)
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T
Input Referred Offset Voltage820mV
Input Referred Offset Voltage Delta (Note 1)28mV
Input Resistance30kΩ
Input Bias Current-7-30µA
Input Bias Current Delta (Note 1)0.54.0µA
Gain1.942.002.06V/V
Gain Delta (Note 1)0.52.5%
Input Capacitance3.3pF
PSRRPower Supply Rejection Ratio5070dB
V
O
Output Voltage Swing into 500Ω load±2.7±3.6V
Output Voltage Swing into 150Ω load+3/-2.7V
I
OUT
Xtalk
Xtalk
V
IH
V
IL
I
IL
I
IH
I
S
AB
CH-CH
Current Output, Measured with 75Ω Load (Note 2)3040mA
Crosstalk from Non-selected Input (at DC)-70-100dB
Crosstalk from one Amplifier to another Amplifier-70-100dB
Input Logic High Level2.0V
Input Logic Low Level0.8V
Logic Low Input Current (VIN = 0V)-0.3-40-80µA
Logic High Input Current (VIN = 0V)-303µA
Total Supply Current384860mA
NOTES:
1. Each channel’s A-input to its B-input.
2. There is no short circuit protection on any output.
AC Electrical SpecificationsV
= +5V, VEE = -5V, Temperature = 25°C, RL = 150Ω, CL = 3pF.
CC
PARAMETERDESCRIPTIONMINTYPMAXUNITS
BW-3dB Bandwidth300MHz
BW 0.1dB±0.1dB Bandwidth105MHz
DGDifferential Gain at 3.58MHz0.04%
DPDifferential Phase at 3.58MHz0.08°
PkgPeaking with Nominal Load0.2dB
SRSlew Rate (4V Square Wave, Measured 25%–75%)650V/µs
2
EL4332
AC Electrical SpecificationsV
PARAMETERDESCRIPTIONMINTYPMAXUNITS
t
S
T
SW
OSOvershoot, V
ab10MInput to Input Isolation at 10MHz60dB
I
SO
100MInput to Input Isolation at 100MHz40dB
I
ch-ch10MChannel to Channel Isolation at 10MHz61dB
SO
100MChannel to Channel Isolation at 100MHz50dB
Settling Time to 0.1% of Final Value13ns
Time to Switch Inputs3ns
= +5V, VEE = -5V, Temperature = 25°C, RL = 150Ω, CL = 3pF. (Continued)
CC
= 4V
OUT
P-P
8%
Pin Descriptions
PIN NAMEFUNCTION
A1, A2, A3“A” inputs to amplifiers 1, 2 and 3 respectively.
B1, B2, B3“B” inputs to amplifiers 1, 2 and 3 respectively.
GND1, GND2, GND3These are the individual ground pins for each channel.
Out1, Out2, Out3Amplifier outputs. Note: there is no short circuit protection on any output.
V
CC
V
EE
A/BCommon input select pin, a logic high selects the “A” inputs, logic low selects the “B” inputs. CMOS/TTL
Positive power supply. Typically +5V.
Negative power supply. Typically -5V.
compatible.
Burn In Schematic
3
Typical Performance Curves
EL4332
FIGURE 1. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 3. SWITCHING TO GROUND FROM A LARGE
SIGNAL UNCORRELATED SINE WAVE
FIGURE 2. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 4. SWITCHING FROM GROUND TO A LARGE
SIGNAL UNCORRELATED SINE WAVE
FIGURE 5. SWITCHING TO GROUND FROM A SMALL
SIGNAL UNCORRELATED SINE WAVE
FIGURE 7. SWITCHING GLITCH (INPUTS AT GROUND)
4
FIGURE 6. SWITCHING FROM GROUND TO A SMALL
SIGNAL UNCORRELATED SINE WAVE
FIGURE 8. SWITCHING FROM A FAMILY OF DC LEVELS TO
GROUND
Typical Performance Curves (Continued)
EL4332
FIGURE 9. SWITCHING FROM GROUND TO A FAMILY OF DC
LEVELS
FIGURE 11. GAIN vs FREQUENCYFIGURE 12. GAIN vs FREQUENCY
FIGURE 10. CHANNEL A/B SWITCHING DELAY
FIGURE 13. -3dB BW vs SUPPLY VOLTAGE
5
FIGURE 14. BANDWIDTH vs DIE TEMPERATURE
Typical Performance Curves (Continued)
EL4332
FIGURE 15. FREQUENCY RESPONSE WITH CAPACITIVE
LOADS
FIGURE 17. A-INPUT TO B–INPUT ISOLATIONFIGURE 18. CHANNEL-CHANNEL ISOLATION
FIGURE 16. INPUT VOLTAGE NOISE OVER FREQUENCY
FIGURE 19. OUTPUT SWING vs SUPPLY VOLTAGE
6
FIGURE 20. OUTPUT SWING vs FREQUENCY
Typical Performance Curves (Continued)
EL4332
FIGURE 21. SLEW RATE vs SUPPLY VOLTAGE
FIGURE 23. SUPPLY CURRENT vs SUPPLY VOLTAGE
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
1.8
1.6
1.563W
1.4
1.2
1
0.8
0.6
0.4
POWER DISSIPATION (W)
0.2
0
0 255075100150
FIGURE 25. POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 22. SLEW RATE vs DIE TEMPERATURE
FIGURE 24. POWER DISSIPATION vs AMBIENT
S
O
16
θ
(
0.
J
A
150”
=
80°
)
C
/
W
12585
AMBIENT TEMPERATURE (°C)
JEDEC JESD51-3 LOW EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
1.2
1.136W
1
0.8
0.6
0.4
0.2
POWER DISSIPATION (W)
0
0 255075100150
S
O
1
6
θ
(
J
0
A
=
.
1
1
5
1
0
0
”
°
)
C
/
W
12585
AMBIENT TEMPERATURE (°C)
TEMPERATURE
7
EL4332
FIGURE 26. TYPICAL CONNECTION FOR A 2:1 COMPONENT VIDEO MULTIPLEXER
Applications Information
Figure 26 shows a typical use for the EL4332. The circuit is a
component video (R,G, B or Y,U,V) multiplexer. Since the
gain of the internal amplifiers has been set to 2, the only
extra components needed are the supply decoupling
capacitors and the back terminating resistors, if transmission
lines are to be driven. The EL4332 can drive backmatched
50Ω or 75Ω loads.
Grounds
It will be noticed that each mux-amp channel has its own
separate ground pin. These g ro und pins have been kept
separate to keep the channel separation inside the chip as
large as possible. The feedback resistors use these ground
pins as their reference. The resistors total 400Ω, so there is
a significant signal current flowing from these pins to ground.
The ground pins should all be connected together, to a
ground plane underneath the chip. 1 oz. copper for the
ground plane is highly recommended.
Further notes and recommended practices for high speed
printed circuit board layout can be found in the tutorials in
the Elantec databooks.
Supplies
Supply bypassing should be as physically near the power
pins as possible. Chip capacitors should be used to
minimize lead inductance. Note that larger values of
capacitor tend to have larger internal inductances. So when
designing for 3 transmission lines or similar moderate loads,
a 0.1µF ceramic capacitor right next to the power pin in
parallel with a 22µF tantalum capacitor placed as close to
the 0.1µF is recommended. For lighter loadings, or if not all
the channels are being used, a single 4.7µF capacitor has
been found quite adequate.
Note that component video signals do tend to have a high
level of signal correlation. This is especially true if the video
signal has been derived from 3 synchronously clocked
DACs. This corresponds to all three channels drawing large
slew currents simultaneously from the supplies. Thus, proper
bypassing is critical.
8
Logic Inputs
The A/B select, logic input, is internally referenced to
ground. It is set at 2 diode drops above ground, to give a
threshold of about 1.4V (see Figure 27). The PNP input
transistor requires that the driving gate be able to sink
current, typically < 30µA, for a logic “low”. If left to float, it will
be a logic “high”.
FIGURE 27. SIMPLIFIED LOGIC INPUT STAGE
EL4332
The input PNP transistors have sufficient gain that a simple
level shift circuit (see Figure 28) can be used to provide a
simple interface with Emitter Coupled Logic. Typically,
200mV is enough to switch from a solid logic “low” to a
“high.”
FIGURE 28. ADAPTING THE SELECT PIN
The capacitor C
FOR ECL LOGIC LEVELS
is only in the network to prevent the A/B
FF
pin’s capacitance from slowing the control signal. The
network shown level shifts the ECL levels, -0.7V to -1.5V to
+1.6V and +1.1V respectively. The terminating resistor, R
TT
is required since the open emitter of the ECL gate can not
sink current. If a -2V rail is not being used, a 220Ω to 330Ω
resistor to the -5.2V rail would have the same effect.
,
9
EL4332
Expanding the Multiplexer
In Figure 29, a 3:1 multiplexer circuit is shown. The
expansion to more inputs is very straight forward. Since the
EL4332 has a fixed gain of 2, interstage attenuators may be
required as shown in Figure 28. The truth table for the 3:1
multiplexer select lines is:
TABLE 1.
XY MUX OUTPUT
00R3, G3, B3
01R2, G2, B2
1XR1, G1, B1
When interstage attenuators are used, the values should be
kept down in the region of 50Ω–300Ω. This is to prevent a
combination of circuit board stray capacitance and the
EL4332’s input capacitance forming a significant pole. For
example, if instead of 100Ω as shown, resistors of 1kΩ had
been used, and assuming 3pF of stray and 3pF of input
capacitance, a pole would be formed at about 53MHz.
FIGURE 29. TYPICAL CONNECTION FOR A 3:1 COMPONENT VIDEO MULTIPLEXER
10
EL4332
A Bandwidth Selectable Circuit
In Figure 30, a circuit is shown that allows three signals to be
either low pass filtered or full bandwidth.
This could be useful where an input signal is frequently
noisy. The component values shown give a Butterworth LPF
response, with a -3dB frequency of 50MHz. Note again, the
resistor values are low, so that stray capacitance does not
affect the desired cut-off frequency.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data she ets are current before placin g orders. Information furn ished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or othe rwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
15
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