Page 1
®
DG401, DG403
Data Sheet June 15, 2006
Monolithic CMOS Analog Switches
The DG401 and DG403 monolithic CMOS analog switches
have TTL and CMOS compatible digital inputs.
These switches feature low analog ON resistance (<45Ω)
and fast switch time (t
< 150ns). Low charge injection
ON
simplifies sample and hold applications.
The improvements in the DG401, DG403 series are made
possible by using a high voltage silicon-gate process. An
epitaxial layer prevents the latch-up associated with older
CMOS technologies. The 44V maximum voltage range
permits controlling 30V
signals. Power supplies may be
P-P
single-ended from +5V to +34V, or split from ±5V to ±17V.
The analog switches are bilateral, equally matched for AC or
bidirectional signals. The ON resistance variation with analog
signals is quite low over a ±15V analog input range. The three
different devices provide the equivalent of two SPST (DG401)
or two SPDT (DG403) relay switch contacts with CMOS or
TTL level activation. The pinout is similar, permitting a
standard layout to be used, choosing the switch function as
needed.
Pinouts
DG401 (SOIC, TSSOP)
TOP VIEW
S
D
1
1
NC
2
NC
3
NC
4
NC
5
NC
6
NC
7
D
8
2
DG403 (SOIC, TSSOP)
TOP VIEW
1
D
1
2
NC
3
D
3
4
S
3
5
S
4
6
D
4
7
NC
8
D
2
16
1
15
IN
1
14
V-
13
GND
V
12
L
11
V+
IN
10
2
S
9
2
S
16
1
IN
15
1
14
V-
13
GND
12
V
L
V+
11
IN
10
2
S
9
2
FN3284.10
Features
• ON Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . . 45Ω
• Low Power Consumption (PD). . . . . . . . . . . . . . . . . . .<35µW
• Fast Switching Action
-t
(Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150ns
ON
-t
(Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100ns
OFF
• Low Charge Injection
• DG401 Dual SPST; Same Pinout as HI-5041
• DG403 Dual SPDT; DG190, IH5043, IH5151, HI-5051
• TTL, CMOS Compatible
• Single or Split Supply Operation
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Audio Switching
• Battery Operated Systems
• Data Acquisition
• Hi-Rel Systems
• Sample and Hold Circuits
• Communication Systems
• Automatic Test Equipment
Ordering Information
PART
NUMBER*
DG401DY DG401DY -40 to 85 16 Ld SOIC M16.15
DG401DYZ-T
(Note)
DG401DVZ
(Note)
DG403DY DG403DY -40 to 85 16 Ld SOIC M16.15
DG403DYZ
(Note)
DG403DVZ
(Note)
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
PART
MARKING
TEMP.
RANGE (°C) PACKAGE
DG401DYZ -40 to 85 16 Ld SOIC
Tape and Reel
(Pb-free)
DG401DVZ -40 to 85 16 Ld TSSOP
(Pb-free)
DG403DYZ -40 to 85 16 Ld SOIC
(Pb-free)
DG403DVZ -40 to 85 16 Ld TSSOP
(Pb-free)
PKG.
DWG. #
M16.15
M16.173
M16.15
M16.173
NOTE: (NC) No Connection.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 1999, 2002-2004, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Page 2
TRUTH TABLE
DG401 DG403
LOGIC
SWITCH SWITCH 1, 2 SWITCH 3, 4
0OFF OFF ON
1ON ON OFF
NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V.
Functional Diagrams
DG401 DG403
V
L
12 11
16
S
1
V+
1
D
1
V
L
12 11
16
S
1
V+
1
D
1
15
IN
1
10
IN
2
9
S
2
13 14
GND V-
Schematic Diagram
V+
V
L
8
D
2
SWITCHES SHOWN FOR LOGIC “1” INPUT
4
S
3
15
IN
1
10
IN
2
9
S
2
5
S
4
13 14
GND V-
3
D
3
8
D
2
6
D
4
SOURCE
V-
V
GND
IN
V+
DRAIN
V-
2
FN3284.10
June 15, 2006
Page 3
Absolute Maximum Ratings Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V
GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to (V+) +0.3V
L
Digital Inputs V
, VD (Note 1) . . . . . (V-) -2V to (V+) + 2V or 30mA,
S
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle, Max). . 100mA
Thermal Resistance (Typical, Note 2) θ
(°C/W)
JA
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Maximum Junction Temperature (Plastic Package). . . . . . . . . 150°C
Maximum Stor age Tem perat ure Ra nge. . . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 30 0°C
(SOIC and TSSOP- Lead Tips Only)
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20V (Max)
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max)
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min)
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20ns
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Signals on S
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θ
JA
, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
X
Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, V
Unless Otherwise Specified
PARAMETER TEST CONDITIONS
= 2.4V, 0.8V (Note 3), VL = 5V,
IN
TEMP
(NOTE 4)
(°C)
MIN
(NOTE 5)
TYP
(NOTE 4)
MAX UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
Turn-OFF Time, t
ON
OFF
Break-Before-Make Time De la y (DG4 03), t
Charge Injection, Q (Figure 3) C
OFF Isolation (Figure 4) R
RL = 300Ω, CL = 35pF 25 - 100 150 ns
25 - 60 100 ns
RL = 300Ω, CL = 35pF 25 5 12 - ns
D
= 10nF, VG = 0V, RG = 0Ω 25 - 60 - pC
L
= 100Ω, CL = 5pF, f = 1MHz 25 - 72 - dB
L
Crosstalk (Channel-to-Channel) (Figure 6) 25 - -90 - dB
Source OFF Capacitance, C
Drain OFF Capacitance, C
Channel ON Capacitance, C
S(OFF)
D(OFF)
D(ON)
+ C
S(ON)
f = 1MHz, VS = VD = 0V (Figure 7) 25 - 12 - pF
25 - 12 - pF
25 - 39 - pF
DIGITAL INPUT CHARACTERISTICS
Input Current with V
Input Current with V
Low, I
IN
High, I
IN
IL
IH
VIN Under T est = 0.8V, All Others = 2.4V Full -1 0.005 1 µA
VIN Under T est = 2.4V, All Others = 0.8V Full -1 0.005 1 µA
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Drain-Source ON Resistance, r
Matching Between Channels, ∆r
r
DS(ON)
Source OFF Leakage Current, I
Drain OFF Leakage Current, I
DS(ON)
S(OFF)
D(OFF)
DS(ON)
V+ = 13.5V, V- = -13.5V,
I
= 10mA, VD = ±10V
S
V+ = 16.5V, V- = -16.5V,
I
= -10mA, VD = 5, 0, -5V
S
V+ = 16.5V, V- = -16.5
V
= ±15.5V, VS = 15.5V
D
Full -15 - 15 V
25 - 20 45 Ω
Full - - 55 Ω
25 - 3 3 Ω
Full - - 5 Ω
25 -0.5 -0.01 0.5 nA
Full -5 - 5 nA
25 -0.5 -0.01 0.5 nA
Full -5 - 5 nA
Channel ON Leakage Current, I
D(ON)+IS(ON)
V± = ±16.5V, VD = VS = ±15.5V 25 -1 -0.04 1 nA
Full -10 - 10 nA
3
FN3284.10
June 15, 2006
Page 4
Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, V
= 2.4V, 0.8V (Note 3), VL = 5V,
IN
Unless Otherwise Specified (Continued)
TEMP
PARAMETER TEST CONDITIONS
(°C)
(NOTE 4)
MIN
(NOTE 5)
TYP
(NOTE 4)
MAX UNITS
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ V+ = 16.5V, V- = -16.5V,
V
= 0V or 5V
IN
25 - 0.01 1 µA
Full - - 5 µA
Negative Supply Current, I- 25 -1 -0.01 - µA
Full -5 - - µA
Logic Supply Current, I
L
25 - 0.01 1 µA
Full - - 5 µA
Ground Current, I
GND
25 -1 -0.01 - µA
Full -5 - - µA
NOTES:
= input voltage to perform proper function.
3. V
IN
4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Test Circuits and Waveforms
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
SWITCH
INPUT
(NOTE 7)
3V
50%
0V
t
OFF
V
S
V
O
90%
0V
-V
S
t
ON
tr < 20ns
t
< 20ns
f
90%
10%
NOTES:
6. Logic input waveform is inverted for switches that have the
opposite logic sense.
= 10V for tON, VS = -10V for t
7. V
S
OFF
.
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
5V +15V
V
L
SWITCH
INPUT
LOGIC
INPUT
Repeat test for IN
For load conditions, see Specifications. C
S
IN
1
1
2
GND
0V -15V
and S2.
capacitance.
VOV
=
V+
R
------------------------------------
S
RLr
+
DS ON()
L
FIGURE 1B. TEST CIRCUIT
= 300Ω
R
L
C
= 35pF
L
V
D
1
V-
includes fixture and stray
L
O
R
L
C
L
4
FN3284.10
June 15, 2006
Page 5
Test Circuits and Waveforms (Continued)
LOGIC
INPUT
SWITCH
OUTPUT
(V
O1
SWITCH
OUTPUT
(V
O2
SWITCH
OUTPUT
3V
0V
V
S1
90%
)
0V
V
S2
)
0V
t
D
FIGURE 2A. MEASUREMENT POINTS
∆V
O
V
O
ON
IN
X
OFF
V
= 10V
S1
VS2 = 10V
IN
1
LOGIC
INPUT
90%
t
D
includes fixture and stray capacitance.
C
L
FIGURE 2. BREAK-BEFORE-MAKE TIME
R
G
V
ON
G
5V +15V
V
L
GND
V+
D
1
D
2
R
L2
V-
0V -15V
FIGURE 2B. TEST CIRCUIT
5V +15V
V
L
V+
RL = 300Ω
C
= 35pF
L
V
O2
D
1
V
O1
R
L1
C
L2
C
L1
V
O
C
L
SIGNAL
GENERATOR
ANALYZER
FIGURE 4. OFF ISOLATION TEST CIRCUIT
V-
Q = ∆V
GND
x C
O
L
0V -15V
FIGURE 3A. MEASUREMENT POINTS FIGURE 3B. TEST CIRCUIT
FIGURE 3. CHARGE INJECTION
+15V
GND
+5V
IN
V-
-15V
+15V
+5V
V+
C
V
S
V
D
R
L
GND
V
C
L
SIGNAL
GENERATOR
IN
X
0V, 2.4V
ANALYZER
V-
C
R
L
V+
C
V
S
V
D
-15V
FIGURE 5. INSERTION LOSS TEST CIRCUIT
V
C
L
X
0V, 2.4V
C
5
FN3284.10
June 15, 2006
Page 6
Test Circuits and Waveforms (Continued)
+5V
SIGNAL
GENERATOR
ANALYZER
0V, 2.4V
R
L
+15V
V+
C
V
S1
IN
1
V
D2
GND
-15V
V
C
L
V
D1
IN
2
V
S2
V-
50Ω
0V, 2.4V
C
NC
IMPEDANCE
ANALYZER
+15V
V+
C
V
S
V
D
GND
+5V
IN
V-
-15V
V
L
0V, 2.4V
AS REQUIRED
X
C
C
FIGURE 6. CROSSTALK TEST CIRCUIT
Application Information
Dual Slope Integrators
The DG403 is well suited to configure a selectable slope
integrator. One control signal selects the timing capacitor C
or C
. Another one selects eIN or discharges the capacitor in
2
preparation for the next integration cycle.
+15V+5V
TTL
e
IN
INTEGRATE/
RESET
SCOPE
SELECT
V
L
S
1
S
3
IN
1
S
2
S
4
IN
2
GND
D
D
D
D
DG403
-15V
V+
1
2
C
1
3
4
C
2
V-
e
OUT
FIGURE 7. CAPACITANCES TEST CIRCUIT
Peak Detector
A3 acting as a comparator provides the logic drive for
1
operating SW
compared to the analog input e
A
is high keeping SW1 closed. This allows C1 to charge up
3
to the analog input voltage. When e
goes negative, turning SW
. The output of A2 is fed back to A3 and
1
. If eIN > e
IN
goes below e
off. The system will therefore
1
IN
the output of
OUT
OUT
store the most positive analog input experienced.
RESET
SW
2
A
1
-
+
e
IN
+
A
3
SW
DG401
R
1
1
C
1
A
2
+
-
e
, A3
OUT
FIGURE 8. DUAL SLOPE INTEGRATOR
6
FIGURE 9. POSITIVE PEAK DETECTOR
FN3284.10
June 15, 2006
Page 7
Typical Performance Curves
10
V+ = 15V
V- = -15V
8
6
(V)
T
V
4
T
A
= 20°C
DG403
SW3, 4
(V)
T
V
4
VL = 5V
T
= 25°C
A
3
2
2
0
0 2 4 6 8101214161820
VL (V)
FIGURE 10. INPUT SWITCHING THRESHOLD vs LOGIC
SUPPLY VOLTAGE
40
35
30
(Ω)
25
DS(ON)
r
20
15
10
-15 -10 -5 0 5 10 15
VD (V)
FIGURE 12. r
vs VD AND TEMPERATURE
DS(ON)
V+ = 15V
V- = -15V
V
L
125°C
25°C
-40°C
= 5V
85°C
0°C
-55°C
1
0
02468101214161820
SUPPLY VOLTAGE (±V)
FIGURE 11. INPUT SWITCHING THRESHOLD vs
POWER SUPPLY VOLTAGE
60
TA = 25°C
50
40
V+ = 12V, V- = -12V
(Ω)
V+ = 15V, V- = -15V
V+ = 20V, V- = -20V
DS(ON)
r
30
20
10
FIGURE 13. r
-15-25 -5 5 2515
vs VD AND POWER SUPPLY VOLTAGE
DS(ON)
VD (V)
V+ = 6V, V- = -6V
V+ = 10V, V- = -10V
V+ = 22V, V- = -22V
70
60
50
(Ω)
40
DS(ON)
r
30
20
10
FIGURE 14. r
V- = 0V
TA = 25°C
V+ = 7.5V
V+ = 10V
V+ = 12V
V+ = 15V
V+ = 20V
V+ = 22V
5010152520
VD (V)
vs VD AND SINGLE SUPPLY VOLTAGE FIGURE 15. CHARGE INJECTION vs SOURCE VOLTAGE
DS(ON)
200
180
160
140
120
100
Q (pC)
V+ = 15V
V- = -15V
= 5V
V
L
80
60
40
20
0
-15 -10 -5 5 10 15
0
VS (V)
CL = 100pF
7
CL = 10nF
CL = 1nF
June 15, 2006
FN3284.10
Page 8
Typical Performance Curves (Continued)
0.0
-0.5
-1.0
-1.5
LOSS (dB)
V+ = 15V, V- = -15V
= 5V, VS = 1V
V
L
-2.0
SEE INSERTION LOSS TEST SETUP
(FIGURE 5)
RMS
10K 100K 1M 10M
FREQUENCY (Hz)
FIGURE 16. INSERTION LOSS vs FREQUENCY
(nA)
D(OFF)
I
100.0
10.0
1.0
0.1
0.01
V+ = 15V
V- = -15V
V
= 5V
L
= ±14V
V
D
TYPICAL
RL = 600Ω
R
= 75Ω
L
R
= 50Ω
L
100.0
(nA)
S(OFF)
I
0.001
0.0001
100.0
(nA)
S(ON)
+ I
D(ON)
I
V+ = 15V
V- = -15V
10.0
L
V
D
= ±14V
= 5V
V
1.0
0.1
TYPICAL
0.01
-55 -35 -15 5 25 45 65
TEMPERATURE (°C)
FIGURE 17. I
vs TEMPERATURE
S(OFF)
V+ = 15V
V- = -15V
V
10.0
L
V
D
= 5V
= ±14V
1.0
TYPICAL
0.1
0.01
85 105 125
0.001
0.0001
-55 -35 -15 5 25 45 65
TEMPERATURE (°C)
FIGURE 18. I
90
WHEN V
SUPPLY, SWITCH SUBSTRATE
60
D(OFF)
EXCEEDS POWER
ANALOG
DIODES BEGIN TO CONDUCT
85 105 125
vs TEMPERATURE FIGURE 19. I
0.001
0.0001
-55 -35 -15 5 25 45 65
TEMPERATURE (°C)
+ I
D(ON)
10.0
V+ = 15V
V- = -15V
V
= 5V
L
1.0
vs TEMPERATURE
S(ON)
85 105 125
30
I-
(pA)
D
, I
S
I
-120
-150
-30
-60
-90
0
I
, I
D(OFF)
S(OFF)
I
D(ON)
-15 -10 -5 0 5 10 15
-20
V
S
, VD (V)
+ I
S(ON)
V+ = 15V, V- = -15V
V
= 5V, TA = 25°C
L
, VS = 0V
I
D(OFF)
I
, VD = 0V
S(OFF)
0.1
, (µA)
L
I
0.01
I+, I -,
I
0.001
L
I-
0.0001
20
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE (°C)
FIGURE 20. LEAKAGE CURRENTS vs ANALOG VOLTAGE FIGURE 21. SUPPLY CURRENT vs TEMPERATURE
I+
I
L
8
FN3284.10
June 15, 2006
Page 9
Typical Performance Curves (Continued)
20
15
10
V+ = 15V
V- = -15V
= 5V
V
L
5
(V)
0
S
V
-5
NOT MEASURABLE DUE TO
CAPACITIVE FEEDTHROUGH
-10
-20
SEE BBM TEST SETUP
-15
05040302010
(FIGURE 2)
BREAK-BEFORE-MAKE TIME (ns)
FIGURE 22. BREAK-BEFORE-MAKE vs ANALOG VOLTAGE
(ns)
OFF
, t
ON
t
600
540
480
420
360
300
240
180
120
tON, VS = -10V
60
0
054321
t
OFF
, VS = 10V
t
OFF
tON, VS = 10V
, VS = -10V
(V)
V
IN
V+ = 15V
V- = -15V
VL = 5V
40
= 5V
V
L
35
30
= 10V
V
S
(ns)
OFF
, t
ON
t
25
20
V
S
= -10V
15
10
5
0
SEE BBM TEST SETUP (FIGURE 2)
0252015105
SUPPLY VOLTAGE (±V)
FIGURE 23. BREAK-BEFORE-MAKE vs POWER
SUPPLY VOLTAGE
240
V+ = 15V
210
V- = -15V
VL = 5V
180
150
(ns)
120
OFF
, t
90
ON
t
tON, VS = -10V
60
30
0
6
-55 -35 -15 5 25 45 65 85 105 125
tON, VS = 10V
TEMPERATURE (°C)
t
t
OFF
OFF
, VS = -10V
, VS = 10V
FIGURE 24. SWITCHING TIME vs INPUT LOGIC VOLTAGE
(NOTE 8)
200
V
= 5V
S
t
180
160
140
120
(ns)
100
OFF
, t
ON
t
80
ON
VS = -5V
t
ON
V
= 5V
S
t
OFF
V
= -5V
S
t
OFF
VL = 5V
60
40
20
0
0252015105
SUPPLY VOLTAGE (±V)
FIGURE 26. SWITCHING TIME vs POWER SUPPL Y VOL TAGE
(NOTE 8)
9
FIGURE 25. SWITCHING TIME vs TEMPERATURE (NOTE 8)
300
(ns)
OFF
, t
ON
t
270
240
210
180
150
120
90
60
30
V- = 0V
V- = -5V
V+ = -15V
V- = -15
V- = -15V
V- = -5V
V- = 0V
t
OFF
t
ON
t
ON
t
ON
V- = 0V
VS = 5V
0
0252015105
POSITIVE SUPPLY (V)
FIGURE 27. SWITCHING TIME vs POSITIVE SUPPL Y
VOLTAGE (NOTE 8)
FN3284.10
June 15, 2006
Page 10
Typical Performance Curves (Continued)
FIGURE 28. SWITCHING TIME vs POSITIVE SUPPLY VOLTAGE (NOTE 8)
NOTE:
8. Refer to Figure 1 for test conditions.
(ns)
OFF
, t
ON
t
300
270
240
210
180
150
120
90
60
30
0
V- = -5V
V- = -15V
V- = -15V
V- = -5V
0252015105
t
ON
t
ON
t
OFF
t
OFF
POSITIVE SUPPLY (V)
VS = -5V
10
FN3284.10
June 15, 2006
Page 11
Thin Shrink Small Outline Plastic Packages (TSSOP)
N
INDEX
AREA
123
-A-
0.05(0.002)
D
SEATING PLANE
e
b
0.10(0.004) C AM BS
M
E1
-B-
A
-C-
0.25(0.010) BM M
E
α
A1
0.10(0.004)
GAUGE
PLANE
0.25
0.010
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A-0.043 - 1.10 -
A1 0.002 0.006 0.05 0.15 -
L
A2 0.033 0.037 0.85 0.95 -
b 0.0075 0.012 0.19 0.30 9
c 0.0035 0.008 0.09 0.20 -
D 0.193 0.201 4.90 5.10 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
c
E 0.246 0.256 6.25 6.50 L 0.020 0.028 0.50 0.70 6
N16 167
o
α
0
o
8
o
0
o
8
NOTESMIN MAX MIN MAX
-
Rev. 1 2/02
11
FN3284.10
June 15, 2006
Page 12
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) BM M
H
L
h x 45°
α
e
B
0.25(0.010) C AM BS
M
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
A1
C
0.10(0.004)
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 D 0.3859 0.3937 9.80 10.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N16 167
α
0° 8° 0° 8° -
NOTESMIN MAX MIN MAX
Rev. 1 6/05
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12
FN3284.10
June 15, 2006
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