intersil CA3420 DATA SHEET

®

CA3420

Data Sheet October 4, 2005

0.5MHz, Low Supply Voltage, Low Input
Current BiMOS Operational Amplifier

The CA3420 is an integrated circuit operational amplifier that
combines PMOS transistors and bipolar transistors on a
single monolithic chip. The CA3420 BiMOS operational
amplifier features gate protected PMOS transistors in the
input circuit to provide very high input impedance, very low
input currents (less than 1pA). The internal bootstrapping
network features a unique guardbanding technique for
reducing the doubling of leakage current for every 10°C
increase in temperature. The CA3420 operates at total
supply voltages from 2V to 20V either single or dual supply.
This operational amplifier is internally phase compensated to
achieve stable operation in the unity gain follower
configuration. Additionally, it has access terminals for a
supplementary external capacitor if additional frequency roll­off is desired. Terminals are also provided for use in
applications requiring input offset voltage nulling. The use of
PMOS in the input stage results in common mode input
voltage capability down to 0.45V below the negative supply
terminal, an important attribute for single supply application.
The output stage uses a feedback OTA type amplifier that
can swing essentially from rail-to-rail. The output driving
current of 1.5mA (Min) is provided by using nonlinear current
mirrors.

FN1320.9

Features

• 2V Supply at 300µA Supply Current

• 1pA Input Current (Typ) (Essentially Constant to 85°C)

• Rail-to-Rail Output Swing (Drive ±2mA into 1kΩ Load)

• Pin Compatible with 741 Operational Amplifiers

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• pH Probe Amplifiers

• Picoammeters

• Electrometer (High Z) Instruments

• Portable Equipment

• Inaccessible Field Equipment

• Battery-Dependent Equipment (Medical and Military)

Functional Diagram

X1

Ordering Information

PART

NUMBER

CA3420E CA3420E -55 to 125 8 Ld PDIP E8.3

CA3420EZ
(Note)

*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.

NOTE: Intersil Pb-free plus anneal products employ special
Pb-free material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS compliant
and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

PAR T

MARKING

CA3420EZ -55 to 125 8 Ld PDIP*

TEMP.

RANGE (°C) PACKAGE

(Pb-free)

PKG.

DWG. #

E8.3

X1

BUFFER AMPS;

BOOTSTRAPPED

INPUT PROTECTION

NETWORK

Pinout

OFFSET NULL

INPUT

NON-INV.

INPUT

INV.

V-

-

BIPOLAR

+

1

2

3

4

MOS

HIGH GAIN

(50K)

CA3420 (PDIP)

TOP VIEW

-

+

MOS

BIPOLAR

OTA BUFFER

8

STROBE

7

V+

6

OUTPUT

5

OFFSET NULL

(X2)

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2002, 2005. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

CA3420

Absolute Maximum Ratings Thermal Information

Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ + 8V) to (V- -0.5V)

Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA

Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Thermal Resistance (Typical, Note 2) θ

PDIP Package* . . . . . . . . . . . . . . . . . . 105 N/A

Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C

*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.

NOTES:

1. Short circuit may be applied to ground or to either supply.

is measured with the component mounted on an evaluation PC board in free air.

2. θ

JA

(°C/W) θJC (°C/W)

JA

Electrical Specifications Typical Values Intended Only for Design Guidance, V

= ±10V, TA = 25°C

SUPPLY

PARAMETER SYMBOL TEST CONDITIONS TYP UNITS

Input Resistance R

Input Capacitance C

Output Resistance R

Equivalent Input Noise Voltage e

I

I

O

N

f = 1kHz RS = 100Ω 62 nV/√Hz

150 TΩ

4.9 pF

300 Ω

f = 10kHz 38 nV/√Hz

Short-Circuit Current Source IOM+2.6mA

To Opposite Supply Sink I

Gain Bandwidth Product f

-2.4mA

OM

T

0.5 MHz

Slew Rate SR 0.5 V/µs

Transient Response Rise Time t

R

RL = 2kΩ, CL = 100pF 0.7 µs

Overshoot OS 15 %

Current from Terminal 8 To V- I

To V + I

Electrical Specifications For Equipment Design, At V

+20µA

8

-2mA

8

= ±1V, TA = 25°C, Unless Otherwise Specified

SUPPLY

TEST

PARAMETER SYMBOL

Input Offset Voltage |V

Input Offset Current (Note 3) |I

Input Current (Note 3) |I

Large Signal Voltage Gain A

IO

IO

I

OL

CONDITIONS MIN TYP MAX UNITS

| - 5 10 mV

| - 0.01 4 pA

|-15pA

RL = 10kΩ 10 100 - kV/V

80 100 - dB

Common Mode Rejection Ratio CMRR - 560 1800 µV/V

55 65 - dB

Common Mode Input Voltage Range V

Power Supply Rejection Ratio PSRR ∆V

+0.20.5- V

lCR

---1.3- V

V

lCR

/∆V - 100 1000 µV/V

IO

60 80 - dB

+R

Max Output Voltage V

OM

- -0.85 -0.91 - V

V

OM

= ∞ 0.90 0.95 - V

L

Supply Current I+ - 350 650 µA

Device Dissipation P
Input Offset Voltage Temperature Drift ∆V

D

/∆T- 4-µV/°C

lO

-0.71.1 mW

NOTE:

3. The maximum limit represents the levels obtainable on high speed automatic test equipment. Typical values are obtained under laboratory conditions.

2

FN1320.9

October 4, 2005