intersil CA3338, CA3338A DATA SHEET

CA3338, CA3338A

Data Sheet July 2004

CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters

The CA3338 family are CMOS/SOS high speed R2R voltage output digital-to-analog converters. They can operate from a single +5V supply, at video speeds, and can produce “rail-to-rail” output swings. Internal level shifters and a pin for an optional second supply provide for an output range below digital ground. The data complement control allows the inversion of input data while the latch enable control provides either feedthrough or latched operation. Both ends of the R2R ladder network are available externally and may be modulated for gain or offset adjustments. In addition, “glitch” energy has been kept very low by segmenting and thermometer encoding of the upper 3 bits.

The CA3338 is manufactured on a sapphire substrate to give low dynamic power dissipation, low output capacitance, and inherent latch-up resistance.

Ordering Information

PART

NUMBER

CA3338E ±1.0 LSB -40 to 85 16 Ld PDIP E16.3

CA3338EZ (Note)

LINEARITY

(INL, DNL)

±1.0 LSB -40 to 85 16 Ld PDIP

TEMP.

RANGE ( ° C ) PACKAGE

(Pb-free)

PKG.

DWG. #

E16.3

FN1850.4

Features

• CMOS/SOS Low Power

• R2R Output, Segmented for Low “Glitch”

• CMOS/TTL Compatible Inputs

• Fast Settling: (Typ) to

/2 LSB . . . . . . . . . . . . . . . . . . 20ns

• Feedthrough Latch for Clocked or Unclocked Use

• Accuracy (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB

• Data Complement Control

• High Update Rate (Typ) . . . . . . . . . . . . . . . . . . . . . 50MHz

• Unipolar or Bipolar Operation

• Pb-free Available

Applications

• TV/Video Display

• High Speed Oscilloscope Display

• Digital Waveform Generator

• Direct Digital Synthesis

Pinout

CA3338, CA3338A

(PDIP, SOIC)

TOP VIEW

CA3338AE ±0.75 LSB -40 to 85 16 Ld PDIP E16.3

CA3338AEZ (Note)

CA3338M ±1.0 LSB -40 to 85 16 Ld SOIC M16.3

CA3338MZ (Note)

CA3338AM ±0.75 LSB -40 to 85 16 Ld SOIC M16.3

CA3338AMZ (Note)

Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.

±0.75 LSB -40 to 85 16 Ld PDIP

(Pb-free)

±1.0 LSB -40 to 85 16 Ld SOIC

(Pb-free)

±0.75 LSB -40 to 85 16 Ld SOIC

(Pb-free)

E16.3

M16.3

D3 D2

6 7

16 15 14 13 12 11 10

LE COMP V

REF

OUT

REF

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Functional Diagram

CA3338, CA3338ACA3338, CA3338A

COMP

3-BIT

LEVEL

SHIFTERS

TO 7-LINE

THERMOMETER

ENCODER

FEEDTHROUGH

LATCHES

R ≅ 160Ω

REF

OUT

REF

CA3338, CA3338A

Absolute Maximum Ratings Thermal Information

DC Supply-Voltage Range. . . . . . . . . . . . . . . . . . . . . . .-0.5V to +8V

- VSS or VDD - VEE, Whichever is Greater)

Input Voltage Range

Digital Inputs (LE, COMP D0 - D7). . . . V

Analog Pins (V

DC Input Current

REF

+, V

REF

-, V

OUT

) . . . .VDD - 8V to VDD + 0.5V

- 0.5V to VDD + 0.5V

Digital Inputs (LE, COMP, D0 - D7) . . . . . . . . . . . . . . . . . . ±20mA

Recommended Supply Voltage Range . . . . . . . . . . . . .4.5V to 7.5V

Thermal Resistance (Typical, Note 1) θ

PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A

SOIC Package . . . . . . . . . . . . . . . . . . . 100 N/A

Maximum Junction Temperature

Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Maximum Storage Temperature Range, T

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range (TA)

Plastic Package, E suffix, M suffix . . . . . . . . . . . . . . -40

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

1. θ

C to 85oC

(oC/W) θJC (oC/W)

. . . . -65oC to 150oC

STG

Electrical Specifications T

= 25oC, VDD = 5V, V

Unless Otherwise Specified

REF

+ = 4.608V, VSS = VEE = V

- = GND, LE Clocked at 20MHz, RL ≥ 1 MΩ,

REF

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ACCURACY

Resolution 8 - - Bits Integral Linearity Error See Figure 4

CA3338 - - ±1LSB CA3338A - - ±0.75 LSB

Differential Linearity Error See Figure 4

CA3338 - - ±0.75 LSB CA3338A - - ±0.5 LSB

Gain Error Input Code = FF

, See Figure 3

HEX

CA3338 - - ±0.75 LSB CA3338A - - ±0.5 LSB

Offset Error Input Code = 00

; See Figure 3 - - ±0.25 LSB

HEX

DIGITAL INPUT TIMING

Update Rate To Maintain Update Rate V Set Up Time t Set Up Time t Hold Time t Latch Pulse Width t Latch Pulse Width t

SU1 SU2

W W

OUTPUT PARAMETERS R Output Delay t Output Delay t Rise Time t Settling Time t

D1 D2

Output Impedance V

REF

For Low Glitch - -2 - ns For Data Store - 8 - ns For Data Store - 5 - ns For Data Store - 5 - ns V

REF

Adjusted for 1V

From LE Edge - 25 - ns From Data Changing - 22 - ns 10% to 90% of Output - 4 - ns 10% to Settling to 1/2 LSB - 20 - ns

REF

/2 LSB Settling DC 50 - MHz

- = VEE = -2.5V, V

- = VEE = -2.5V, V Output

P-P

+ = +2.5V DC 20 - MHz

REF

+ = +2.5V - 25 - ns

REF

+ = 6V, VDD = 6V 120 160 200 Ω Glitch Area - 150 - pV/s Glitch Area V

- = VEE = -2.5V,V

REF

+ = +2.5V - 250 - pV/s

REF

CA3338, CA3338A

Electrical Specifications T

= 25oC, VDD = 5V, V

+ = 4.608V, VSS = VEE = V

REF

- = GND, LE Clocked at 20MHz, RL ≥ 1 MΩ,

REF

Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

REFERENCE VOLTAGE

+ Range (+) Full Scale, Note 2 V

REF

- Range (-) Full Scale, Note 2 V

REF

+ Input Current V

REF

+ = 6V, VDD = 6V - 40 50 mA

REF

- + 3 - V

REF

-V

+ - 3 V

REF

SUPPLY VOLTAGE

Static I

or I

LE = Low, D0 - D7 = High - 100 220 µA

LE = Low, D0 - D7 = Low - - 100 µA Dynamic I Dynamic I V

Rejection 50kHz Sine Wave Applied - 3 - mV/V

Rejection 50kHz Sine Wave Applied - 1 - mV/V

DD DD

or I or I

EE EE

= 10MHz, 0V to 5V Square Wave - 20 - mA

OUT

= 10MHz, ±2.5V Square Wave - 25 - mA

OUT

DIGITAL INPUTS D0 - D7, LE, COMP High Level Input Voltage Note 2 2 - - V Low Level Input Voltage Note 2 - - 0.8 V Leakage Current - ±1 ±5 µA Capacitance - 5 - pF

TEMPERATURE COEFFICIENTS

Output Impedance - 200 - ppm/×

NOTE:

2. Parameter not tested. but guaranteed by design or characterization.

Pin Descriptions

CA3338, CA3338A

PIN NAME DESCRIPTION

1 D7 Most Significant Bit 2 D6 Input 3D5 Data 4D4 Bits 5 D3 (High = True) 6D2 7D1 8V

9D0Least Significant Bit. Input Data Bit 10 V 11

12 V 13

14 COMP Data Complement Control input. Active High 15 LE Latch Enable Input. Active Low 16 V

Digital Ground

Analog Ground

Reference Voltage Negative Input

REF

Analog Output

OUT

Reference Voltage Positive Input

REF

Digital Power Supply, +5V

Digital Signal Path

The digital inputs (LE, COMP, and D0 - D7) are of TTL compatible HCT High Speed CMOS design: the loading is essentially capacitive and the logic threshold is typically

1.5V. The 8 data bits, D0 (weighted 2

are applied to Exclusive OR gates (see Functional Diagram). The COMP (data complement) control provides the second input to the gates: if COMP is high, the data bits will be inverted as they pass through.

) through D7 (weighted 27),

INPUT

DAT A

LATCH

ENABLE

OUTPUT

VOLTAGE

FIGURE 2. DATA AND LATCH ENABLE TO OUTPUT TIMING

90%

10%

/2 LSB

Latch Operation

Data is fed from input to output while LE is low: LE should be tied low for non-clocked operation.

Non-clocked operation or changing data while LE is low is not recommended for applications requiring low output “glitch” energy: there is no guarantee of the simultaneous changing of input data or the equal propagation delay of all bits through the converter. Several parameters are given if the converter is to be used in either of these modes: t gives the delay from the input changing to the output changing (10%), while t

and tH give the set up and hold

SU2

times (referred to LE rising edge) needed to latch data. See Figures 1 and 2.

Clocked operation is needed for low “glitch” energy use. Data must meet the given t

set up time to the LE falling edge,

SU1

and the tH hold time from the LE rising edge. The delay to the output changing, t

, is now referred to the LE falling

edge.

The input data and the LE (latch enable) signals are next applied to a level shifter. The inputs, operating between the levels of V

and VSS, are shifted to operate between V

and VEE. VEE optionally at ground or at a negative voltage, will be discussed under bipolar operation. All further logic elements except the output drivers operate from the V and V

supplies.

The upper 3 bits of data, D5 through D7, are input to a 3-to-7 line bar graph encoder. The encoder outputs and D0 through D4 are applied to a feedthrough latch, which is controlled by LE (latch enable).

INPUT DATA

SU1

LATCHED LATCHED

LATCH

ENABLE

FIGURE 1. DATA TO LATCH ENABLE TIMING

DAT A

FEEDTHROUGH

SU2

There is no need for a square wave LE clock; LE must only meet the minimum t

pulse width for successful latch

operation. Generally, output timing (desired accuracy of settling) sets the upper limit of usable clock frequency.

Output Structure

The latches feed data to a row of high current CMOS drivers, which in turn feed a modified R2R ladder network.

The “N” channel (pull down) transistor of each driver plus the bottom “2R” resistor are returned to V scale reference. The “P” channel (pull up) transistor of each driver is returned to V

In unipolar operation, V

+, the (+) full-scale reference.

REF

- would typically be returned to

REF

analog ground, but may be raised above ground (see specifications). There is substantial code dependent current that flows from V specifications), so V

REF

+ to V

REF

- (see V

REF

- should have a low impedance path

to ground.

- this is the (-) full-

REF

+ input current in

REF

CA3338, CA3338A

In bipolar operation, V voltage (the maximum voltage rating to V observed). V

, which supplies the gate potential for the

- would be returned to a negative

REF

must be

output drivers, must be returned to a point at least as negative as V

-. Note that the maximum clocking speed

REF

decreases when the bipolar mode is used.

Static Characteristics

The ideal 8-bit D/A would hav e an output eq ual to V an input code of 00 equal to 255/256 of V code of FF

HEX

(zero scale output), and an output

HEX

+ (referred to V

REF

-) with an input

REF

(full scale output). The difference between the ideal and actual values of these two par ameters are the OFFSET and GAIN errors, respectively; see Figure 3.

If the code into an 8-bit D/A is changed by 1 count, the output should change by 1/255 (full scale output - zero scale output). A deviation from this step size is a diff erential linearity error, see Figure 4. Note that the error is expressed in fractions of the ideal step size (usually called an LSB). Also note that if the (-) differential linearity error is less (in absolute numbers) than 1 LSB, the device is monotonic. (The output will always increase for increasing code or decrease for decreasing code).

If the code into an 8-bit D/A is at any value, say “N”, the output voltage should be N/255 of the full scale output (referred to the zero scale output). Any deviation from that output is an integral linearity error, usually expressed in LSBs. See Figure 4.

Note that OFFSET and GAIN errors do not affect integral linearity, as the linearity is referenced to actual zero and full scale outputs, not ideal. Absolute accuracy would have to also take these errors into account.

255/256

REF

+ - V

254/256

REF

253/256

3/256

2/256

1/256

OUTPUT VOLTAGE AS A FRACTION OF V

00 01 02 03 FD FE FF

FIGURE 3. D/A OFFSET AND GAIN ERROR

= IDEAL TRANSFER CURVE = ACTUAL TRANSFER CURVE

OFFSET

ERROR

(SHOWN +)

INPUT CODE IN HEXADECIMAL (COMP = LOW)

GAIN ERROR

(SHOWN -)

REF

- with

STRAIGHT LINE FROM “0” SCALE TO FULL SCALE

= IDEAL TRANSFER CURVE = ACTUAL TRANSFER CURVE

OUTPUT VOLTAGE

FIGURE 4. D/A INTEGRAL AND DIFFERENTIAL LINEARITY

ERROR

VOLTAGE

INTEGRAL LINEARITY

ERROR (SHOWN -)

A = IDEAL STEP SIZE (1/255 OF FULL

SCALE -“0” SCALE VOLTAGE) B - A = +DIFFERENTIAL LINEARITY ERROR C - A = -DIFFERENTIAL LINEARITY ERROR

INPUT CODE

Dynamic Characteristics

Keeping the full-scale range (V possible gives the best linearity and lowest “glitch” energy (referred to 1V). This provides the best “P” and “N” channel gate drives (hence saturation resistance) and propagation delays. The V

REF

+ (and V

REF

well bypassed as near the chip as possible. “Glitch” energy is defined as a spu rious voltage that occu rs as

the output is changed from one voltage to another. In a binary input converter, it is usually highe st at the most significa nt bit transition (7F

HEX

to 80

for an 8 bit device), and can be

HEX

measured by displaying the output as the input co de alternates around that point. The “glitch” energy is the area between the actual output display and an ideal one L SB step voltage (subtracting negative area from positi ve), at either the positive or negative-going step. It is usually expressed in pV/s .

The CA3338 uses a modified R2R ladder, whe re the 3 mo st significant bits drive a bar graph decoder and 7 equally weighted resistors. This makes the “glitch” energy at each scale transition (1F

HEX

to 20 essentially equal, and far less than the MSB transition would otherwise display.

For the purpose of comparison to other converters, the output should be resistively divided to 1V full scale. Figure 5 shows a typical hook-up for checking “glitch” energy or settling time .

The settling time of the A/D is mainly a function of the output resistance (approxi ma tely 160 Ω i n par allel w ith the load resistance) and the load plus internal chip capacitance. Both “glitch” energy and settling time measurements require v e ry good circuit and probe grounding: a probe tip connector such as Tektronix part number 131-0258-00 is recommended.

REF

+ - V

-) as high as

REF

- if bipolar) terminal should be

HEX

, 3F

HEX

to 40

HEX

, etc.)

CLOCK

8 DATA BITS

+5V

1-7, 9

CA3338, CA3338A

CA3338

+5V +2.5V

-2.5V

PROBE TIP OR BNC CONNECTOR

REMOTE V

OUT

D0 - D7

COMP

OUT

REF

DIGITAL

GROUND

FUNCTION CONNECTOR R1 R2 R3 V

ANALOG GROUND

OUT (P-P)

Oscilloscope Display Probe Tip 82Ω 62Ω N/C 1V Match 93Ω Cable BNC 75 160 93 1V Match 75Ω Cable BNC 18 130 75 1V Match 50Ω Cable BNC Short 75 50 0 79V

NOTES:

3. V

OUT(P-P)

4. All drawn capacitors are 0.1µF multilayer ceramic/4.7µF tantalum.

is approximate, and will vary as R

of D/A varies.

OUT

5. Dashed connections are for unipolar operation. Solid connection are for bipolar operation.

FIGURE 5. CA3338 DYNAMIC TEST CIRCUIT

+6V

4.7µF TAN +

5pF

0.1µF CER.

4.7µF TAN

UP TO 5 OUTPUT LINES FOR R = 75Ω, 3 LINES FOR R = 50Ω

= ±1.5V

OUT

PEAK

CA3338

D0 - D7

COMP V

OUT

REF

CLOCK

8 DATA

BITS

+5V

1-7, 9

4.7µF

TAN

0.1µF CER.

NOTES:

1. Both V bypassed within

+ pin and 392Ω resistor should be

REF

/4 inch.

2. Keep nodal capacitance at CA3450 pin 3 as

+3.00V AT 25mA

1kΩ

4.7µF TAN

0.1µF CER.

392Ω

10kΩ

ADJUST OFFSET

7, 8

392Ω

CA3450

4, 5, 12, 13

-6V

low as possible.

3. V

Range = ±3V at CA3450.

OUT

FIGURE 6. CA3338 AND CA3450 FOR DRIVING MULTIPLE COAXIAL LINES

OUT

CA3338, CA3338A

TABLE 1. OUTPUT VOLTAGE vs INPUT CODE AND V

REF

STEP SIZE

Input Code 11111111 111111102=FE

10000001 100000002=80 011111112=7F

00000001 000000002=00

•

=FF

=81

=01

HEX HEX

HEX

HEX HEX

5.12V 0

0.0200V

5.1000V

5.0800

2.5800

2.5600

2.5400

0.0200

0.0000

5.00V

0.0195V

4.9805V

4.9610

2.5195

2.5000

2.4805

0.0195

0.0000

4.608V 0

0.0180V

4.5900V

4.5720

2.3220

2.3040

2.2860

0.0180

0.0000

-2.56V

0.0200V

2.5400V

2.5200

0.0200

0.0000

- 0.0200

-2.5400

-2.5600

2.56V

REF

2.50V

-2.50V

0.0195V

2.4805V

2.4610

0.0195

0.0000

-0.0195

-2.4805

-2.5000

Applications

The output of the CA3338 can be resistively divided to match a doubly terminated 50Ω or 75Ω line, although peak-to-peak swings of less than 1V may result. The output magnitude will also vary with the converter’s output impedance. Figure 5 shows such an application. Note that because of the HCT input structure, the CA3338 could be operated up to +7.5V V V

+ supplies and still accept 0V to 5V CMOS input voltages.

REF

If larger voltage swings or better accuracy is desired, a high speed output buffer, such as the HA-5033, HA-2542, or CA3450, can be employed. Figure 6 shows a typical application, with the output capable of driving ±2V into multiple 50Ω terminated lines.

and

Operating and Handling Considerations

HANDLING

All inputs and outputs of CMOS devices have a network for electrostatic protection during handling. Recommended handling practices for CMOS devices are described in AN6525. “Guide to Better Handling and Operation of CMOS Integrated Circuits.”

OPERATING

OPERATING VOLTAGE

During operation near the maximum supply voltage limit, care should be taken to avoid or suppress power supply turn-on and turn-off transients, power supply ripple, or ground noise; any of these conditions must not cause the absolute maximum ratings to be exceeded.

INPUT SIGNALS

To prevent damage to the input protection circuit, input signals should never be greater than V Input currents must not exceed 20mA even when the power supply is off.

UNUSED INPUTS

A connection must be provided at every input terminal. All unused input terminals must be connected to either V GND, whichever is appropriate.

nor less than VSS.

Dual-In-Line Plastic Packages (PDIP)

CA3338, CA3338A

-C-

-B-

INDEX

AREA

BASE

PLANE

SEATING

PLANE

12 3 N/2

-AD

0.010 (0.25) C AM BS

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpendic-

7. e

ular to datum .

and eC are measured at the lead tips with the leads unconstrained.

must be zero or greater.

-C-

8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

E16.3 (JEDEC MS-001-BB ISSUE D)

16 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 B1 0.045 0.070 1.15 1.77 8, 10

C 0.008 0.014 0.204 0.355 -

D 0.735 0.775 18.66 19.68 5

D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

0.300 BSC 7.62 BSC 6

- 0.430 - 10.92 7

L 0.115 0.150 2.93 3.81 4

N16 169

NOTESMIN MAX MIN MAX

Rev. 0 12/93

CA3338, CA3338A

Small Outline Plastic Packages (SOIC)

INDEX AREA

123

-AD

0.25(0.010) C AM BS

-B-

SEA TING PLANE

-C-

0.25(0.010) BM M

0.10(0.004)

h x 45

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

M16.3 (JEDEC MS-013-AA ISSUE C)

16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 D 0.3977 0.4133 10.10 10.50 3 E 0.2914 0.2992 7.40 7.60 4 e 0.050 BSC 1.27 BSC H 0.394 0.419 10.00 10.65 h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N16 167

Rev. 0 12/93

NOTESMIN MAX MIN MAX

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intersil CA3338, CA3338A DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual