intersil CA3338, CA3338A DATA SHEET

CA3338, CA3338A

Data Sheet July 2004

CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters

The CA3338 family are CMOS/SOS high speed R2R voltage output digital-to-analog converters. They can operate from a single +5V supply, at video speeds, and can produce “rail-to-rail” output swings. Internal level shifters and a pin for an optional second supply provide for an output range below digital ground. The data complement control allows the inversion of input data while the latch enable control provides either feedthrough or latched operation. Both ends of the R2R ladder network are available externally and may be modulated for gain or offset adjustments. In addition, “glitch” energy has been kept very low by segmenting and thermometer encoding of the upper 3 bits.

The CA3338 is manufactured on a sapphire substrate to give low dynamic power dissipation, low output capacitance, and inherent latch-up resistance.

Ordering Information

PART

NUMBER

CA3338E ±1.0 LSB -40 to 85 16 Ld PDIP E16.3

CA3338EZ (Note)

LINEARITY

(INL, DNL)

±1.0 LSB -40 to 85 16 Ld PDIP

TEMP.

RANGE ( ° C ) PACKAGE

(Pb-free)

PKG.

DWG. #

E16.3

FN1850.4

Features

• CMOS/SOS Low Power

• R2R Output, Segmented for Low “Glitch”

• CMOS/TTL Compatible Inputs

• Fast Settling: (Typ) to

/2 LSB . . . . . . . . . . . . . . . . . . 20ns

• Feedthrough Latch for Clocked or Unclocked Use

• Accuracy (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB

• Data Complement Control

• High Update Rate (Typ) . . . . . . . . . . . . . . . . . . . . . 50MHz

• Unipolar or Bipolar Operation

• Pb-free Available

Applications

• TV/Video Display

• High Speed Oscilloscope Display

• Digital Waveform Generator

• Direct Digital Synthesis

Pinout

CA3338, CA3338A

(PDIP, SOIC)

TOP VIEW

CA3338AE ±0.75 LSB -40 to 85 16 Ld PDIP E16.3

CA3338AEZ (Note)

CA3338M ±1.0 LSB -40 to 85 16 Ld SOIC M16.3

CA3338MZ (Note)

CA3338AM ±0.75 LSB -40 to 85 16 Ld SOIC M16.3

CA3338AMZ (Note)

Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.

±0.75 LSB -40 to 85 16 Ld PDIP

(Pb-free)

±1.0 LSB -40 to 85 16 Ld SOIC

(Pb-free)

±0.75 LSB -40 to 85 16 Ld SOIC

(Pb-free)

E16.3

M16.3

D3 D2

6 7

16 15 14 13 12 11 10

LE COMP V

REF

OUT

REF

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Functional Diagram

CA3338, CA3338ACA3338, CA3338A

COMP

3-BIT

LEVEL

SHIFTERS

TO 7-LINE

THERMOMETER

ENCODER

FEEDTHROUGH

LATCHES

R ≅ 160Ω

REF

OUT

REF

CA3338, CA3338A

Absolute Maximum Ratings Thermal Information

DC Supply-Voltage Range. . . . . . . . . . . . . . . . . . . . . . .-0.5V to +8V

- VSS or VDD - VEE, Whichever is Greater)

Input Voltage Range

Digital Inputs (LE, COMP D0 - D7). . . . V

Analog Pins (V

DC Input Current

REF

+, V

REF

-, V

OUT

) . . . .VDD - 8V to VDD + 0.5V

- 0.5V to VDD + 0.5V

Digital Inputs (LE, COMP, D0 - D7) . . . . . . . . . . . . . . . . . . ±20mA

Recommended Supply Voltage Range . . . . . . . . . . . . .4.5V to 7.5V

Thermal Resistance (Typical, Note 1) θ

PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A

SOIC Package . . . . . . . . . . . . . . . . . . . 100 N/A

Maximum Junction Temperature

Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Maximum Storage Temperature Range, T

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range (TA)

Plastic Package, E suffix, M suffix . . . . . . . . . . . . . . -40

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

1. θ

C to 85oC

(oC/W) θJC (oC/W)

. . . . -65oC to 150oC

STG

Electrical Specifications T

= 25oC, VDD = 5V, V

Unless Otherwise Specified

REF

+ = 4.608V, VSS = VEE = V

- = GND, LE Clocked at 20MHz, RL ≥ 1 MΩ,

REF

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ACCURACY

Resolution 8 - - Bits Integral Linearity Error See Figure 4

CA3338 - - ±1LSB CA3338A - - ±0.75 LSB

Differential Linearity Error See Figure 4

CA3338 - - ±0.75 LSB CA3338A - - ±0.5 LSB

Gain Error Input Code = FF

, See Figure 3

HEX

CA3338 - - ±0.75 LSB CA3338A - - ±0.5 LSB

Offset Error Input Code = 00

; See Figure 3 - - ±0.25 LSB

HEX

DIGITAL INPUT TIMING

Update Rate To Maintain Update Rate V Set Up Time t Set Up Time t Hold Time t Latch Pulse Width t Latch Pulse Width t

SU1 SU2

W W

OUTPUT PARAMETERS R Output Delay t Output Delay t Rise Time t Settling Time t

D1 D2

Output Impedance V

REF

For Low Glitch - -2 - ns For Data Store - 8 - ns For Data Store - 5 - ns For Data Store - 5 - ns V

REF

Adjusted for 1V

From LE Edge - 25 - ns From Data Changing - 22 - ns 10% to 90% of Output - 4 - ns 10% to Settling to 1/2 LSB - 20 - ns

REF

/2 LSB Settling DC 50 - MHz

- = VEE = -2.5V, V

- = VEE = -2.5V, V Output

P-P

+ = +2.5V DC 20 - MHz

REF

+ = +2.5V - 25 - ns

REF

+ = 6V, VDD = 6V 120 160 200 Ω Glitch Area - 150 - pV/s Glitch Area V

- = VEE = -2.5V,V

REF

+ = +2.5V - 250 - pV/s

REF

+ 7 hidden pages