intersil 82C89 User Manual

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82C89

Data Sheet February 27, 2006

CMOS Bus Arbiter

The Intersil 82C89 Bus Arbiter is manufactured using a selfaligned silicon gate CMOS process (Scaled SAJI IV). This circuit, along with the 82C88 bus controller, provides full bus arbitration and control for multi-processor systems. The 82C89 is typically used in medium to large 80C86 or 80C88 systems where access to the bus by several processors must be coordinated. The 82C89 also provides high output current and capacitive drive to eliminate the need for additional bus buffering.

Static CMOS circuit design insures low operating power. The advanced Intersil SAJI CMOS process results in performance equal to or greater than existing equivalent products at a significant power savings.

Ordering Information

PAR T

NUMBER

CP82C89 CP82C89 0 to +70 20 Ld PDIP E20.3

CP82C89Z* (Note)

MD82C89/B MD82C89/B -55 to +125 20 Ld CERDIP F20.3

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

PART

MARKING

CP82C89Z 0 to +70 20 Ld PDIP

TEMP.

RANGE (°C) PACKAGE

(Pb-free)

PKG.

DWG. #

E20.3

FN2980.2

Features

• Pin Compatible with Bipolar 8289

• Performance Compatible with:

- 80C86/80C88 . . . . . . . . . . . . . . . . . . . . . . . . . (5/8MHz)

• Provides Multi-Master System Bus Control and Arbitration

• Provides Simple Interface with 82C88/8288 Bus Controller

• Synchronizes 80C86/8086, 80C88/8088 Processors with Multi-Master Bus

• Bipolar Drive Capability

• Four Operating Modes for Flexible System Configuration

• Low Power Operation

- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10µA (Max)

- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 1mA/MHz (Max)

• Operating Temperature Ranges

- C82C89 . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

- M82C89 . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

• Pb-Free Plus Anneal Available (RoHS Compliant)

Pinout

82C89 (PDIP, CERDIP)

TOP VIEW

IOB

SYSB/RESB

RESB

BCLK

INIT

BREQ

BPRO

BPRN

GND

CLK

LOCK

CRQLCK

ANYRQST

AEN

CBRQ

BUSY

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Functional Diagram

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82C89

INIT BCLK BREQ BPRN BPRO

BUSY

CBRQ

AEN

SYSB/ RESB

MULTIBUS™ COMMAND SIGNALS

SYSTEM SIGNALS

MULTIBUS™ is an Intel Corp. trademark.

80C86/

80C88

STATUS

CONTROL/

STRAPPING

OPTIONS

LOCK

CLK

CRQLCK

RESB

ANYRQST

IOB

ARBITRATION

MULTIBUS

STATUS

DECODER

CONTROL

+5V GND

INTERFACE

LOCAL

BUS

INTERFACE

Pin Description

SYMBOL NUMBER TYPE DESCRIPTION

GND 10 GROUND.

, S1, S2 1, 18-19 I STATUS INPUT PINS: The status input pins from an 80C86, 80C88 or 8089 processor. The 82C89 decodes

CLK 17 I CLOCK: From the 82C84A or 82C85 clock chip and serves to establish when bus arbiter actions are initiated.

LOCK

CRQLCK

RESB 4 I RESIDENT BUS: A strapping option to configure the arbiter to operate in systems having both a multi-master

ANYRQST 14 I ANY REQUEST: A strapping option which permits the multi-master system bus to be surrendered to a lower

IOB

AEN

INIT

20 VCC: The +5V Power supply pin. A 0.1µF capacitor between pins 10 and 20 is recommended for decoupling.

these pins to initiate bus request and surrender actions. (See Table 1).

16 I LOCK: A processor generated signal which when activated (low) prevents the arbiter from surrendering the multi-

master system bus to any other bus arbiter, regardless of its priority.

15 I COMMON REQUEST LOCK: An active low signal which prevents the arbiter from surrendering the multi-master

system bus to any other bus arbiter requesting the bus through the CBRQ

input pin.

system bus and a Resident Bus. Strapped high, the multi-master system bus is requested or surrendered as a function of the SYSB/RESB

input pin. Strapped low, the SYSB/RESB input is ignored.

priority arbiter as if it were an arbiter of higher priority (i.e., when a lower priority arbiter requests the use of the multi-master system bus, the bus is surrendered as soon as it is possible). When ANYRQST is strapped low, the bus is surrendered according to Table A in Design Information. If ANYRQST is strapped high and CBRQ activated, the bus is surrendered at the end of the present bus cycle. Strapping CBRQ

low and ANYRQST high forces the 82C89 arbiter to surrender the multi-master system bus after each transfer cycle. Note that when surrender occurs BREQ

is driven false (high).

2 I IO BUS: A strapping option which configures the 82C89 Arbiter to operate in systems having both an IO Bus

(Peripheral Bus) and a multi-master system bus. The arbiter requests and surrenders the use of the multi-master system bus as a function of the status line, S2

. The multi-master system bus is permitted to be surrendered while the processor is performing IO commands and is requested whenever the processor performs a memory command. Interrupt cycles are assumed as coming from the peripheral bus and are treated as an IO command.

13 O ADDRESS ENABLE: The output of the 82C89 Arbiter to the processor’s address latches, to the 82C88 Bus

Controller and 82C84A or 82C85 Clock Generator. AEN

serves to instruct the Bus Controller and address latches

when to three-state their output drivers.

6 I INITIALIZE: An active low multi-master system bus input signal used to reset all the bus arbiters on the multi-

master system bus. After initialization, no arbiters have the use of the multi-master system bus.

FN2980.2

February 27, 2006

82C89

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Pin Description (Continued)

SYMBOL NUMBER TYPE DESCRIPTION

SYSB/RESB 3 I SYSTEM BUS/RESIDENT BUS: An input signal when the arbiter is configured in the System/Resident Mode

is strapped high) which determines when the multi-master system bus is requested and multi-master

(RESB system bus surrendering is permitted. The signal is intended to originate from a form of address-mapping circuitry, such as a decoder or PROM attached to the resident address bus. Signal transitions and glitches are permitted on this pin from θ1 of T4 to θ1 of T2 of the processor cycle. During the period from θ1 of T2 to θ1 of T4, only clean transitions are permitted on this pin (no glitches). If a glitch occurs, the arbiter may capture or miss it, and the multi-master system bus may be requested or surrendered, depending upon the state of the glitch. The arbiter requests the multi-master system bus in the System/Resident Mode when the state of the SYSB/RESB pin is high and permits the bus to be surrendered when this pin is low.

CBRQ

BCLK

BREQ

BPRN

BPRO

BUSY 11 I/O BUSY: An active low open-drain multi-master system bus interface signal used to instruct all the arbiters on the

12 I/O COMMON BUS REQUEST: An input signal which instructs the arbiter if there are any other arbiters of lower

priority requesting the use of the multi-master system bus. The CBRQ bus upon request are connected together. The Bus Arbiter running the current transfer cycle will not itself pull the CBRQ connected to the CDRQ transfer cycle drops its BREQ Strapping CBRQ transfer cycle. See the pin definition of ANYRQST.

5 I BUS CLOCK: The multi-master system bus clock to which all multi-master system bus interface signals are

synchronized.

7 O BUS REQUEST: An active low output signal in the Parallel Priority Resolving Scheme which the arbiter activates

to request the use of the multi-master system bus.

9 I BUS PRIORITY IN: The active low signal returned to the arbiter to instruct it that it may acquire the multi-master

system bus on the next falling edge of BCLK requesting arbiter presently on the bus. The loss of BPRN priority arbiter.

8 O BUS PRIORITY OUT: An active low output signal used in the serial priority resolving scheme where BPRO is

daisy-chained to BPRN

bus when the multi-master system bus is available. When the multi-master system bus is available the highest requesting arbiter (determined by BPRN When the arbiter is done with the bus, it releases the BUSY another arbiter to acquire the multi-master system bus.

pins (open-drain output) of all the 82C89 Bus Arbiters which surrender to the multi-master system

line low. Any other arbiter

line can request the multi-master system bus. The arbiter presently running the current

signal and surrenders the bus whenever the proper surrender conditions exist.

low and ANYRQST high allows the multi-master system bus to be surrendered after each

. BPRN active indicates to the arbiter that it is the highest priority

instructs the arbiter that it has lost priority to a higher

of the next lower priority arbiter.

) seizes the bus and pulls BUSY low to keep other arbiters off of the bus.

signal, permitting it to go high and thereby allowing

Functional Description

The 82C89 Bus Arbiter operates in conjunction with the 82C88 Bus Controller to interface 80C86, 80C88 processors to a multi-master system bus (both the 80C86 and 80C88 are configured in their max mode). The processor is unaware of the arbiter’s existence and issues commands as though it has exclusive use of the system bus. If the processor does not have the use of the multi-master system bus, the arbiter prevents the Bus Controller (82C88), the data transceivers and the address latches from accessing the system bus (e.g. all bus driver outputs are forced into the high impedance state). Since the command sequence was not issued by the 82C88, the system bus will appear as “Not Ready” and the processor will enter wait states. The processor will remain in Wait until the Bus Arbiter acquires the use of the multi-master system bus whereupon the arbiter will allow the bus controller, the data transceivers, and the address latches to access the system. Typically, once the command has been issued and a data transfer has taken place, a transfer acknowledge (XACK) is returned to the processor to indicate “READY” from the

accessed slave device. The processor then completes its transfer cycle. Thus the arbiter serves to multiplex a processor (or bus master) onto a multi-master system bus and avoid contention problems between bus masters.

Arbitration Between Bus Masters

In general, higher priority masters obtain the bus when a lower priority master completes its present transfer cycle. Lower priority bus masters obtain the bus when a higher priority master is not accessing the system bus. A strapping option (ANYRQST) is provided to allow the arbiter to surrender the bus to a lower priority master as though it were a master of higher priority. If there are no other bus masters requesting the bus, the arbiter maintains the bus so long as its processor has not entered the HALT State. The arbiter will not voluntarily surrender the system bus and has to be forced off by another master’s bus request, the HALT State being the only exception. Additional strapping options permit other modes of operation wherein the multi-master system bus is surrendered or requested under different sets of conditions.

FN2980.2

February 27, 2006

Priority Resolving Techniques

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Since there can be many bus masters on a multi-master system bus, some means of resolving priority between bus masters simultaneously requesting the bus must be provided. The 82C89 Bus Arbiter provides several resolving techniques. All the techniques are based on a priority concept that at a given time one bus master will have priority above all the rest. There are provisions for using parallel priority resolving techniques, serial priority resolving techniques, and rotating priority techniques.

Parallel Priority Resolving

The parallel priority resolving technique uses a separate bus request line BREQ system bus, see Figure 1. Each BREQ priority encoder which generates the binary address of the highest priority BREQ is decoded by a decoder to select the corresponding BPRN (Bus Priority In) line to be returned to the highest priority requesting arbiter. The arbiter receiving priority (BPRN then allows its associated bus master onto the multi-master system bus as soon as it becomes available (i.e., the bus is no longer busy). When one bus arbiter gains priority over another arbiter it cannot immediately seize the bus, it must wait until the present bus transaction is complete. Upon completing its transaction the present bus occupant recognizes that it no longer has priority and surrenders the bus by releasing BUSY signal line which goes to every bus arbiter on the system bus. When BUSY presently has bus priority (BPRN and pulls BUSY waveform timing diagram, Figure 2. Note that all multimaster system bus transactions are synchronized to the bus clock (BCLK

). This allows the parallel priority resolving circuitry or

any other priority resolving scheme employed to settle.

•••

•

BUSY

CBRQ

FIGURE 1. PARALLEL PRIORITY RESOLVING TECHNIQUE

for each arbiter on the multi-master

line enters into a

line which is active. The binary address

. BUSY is an active low “OR” tied

goes inactive (high), the arbiter which

true) then seizes the bus

low to keep other arbiters off of the bus. See

BREQ

BUS

ARBITER

BUS

ARBITER

BREQ

BUS

ARBITER

BUS

ARBITER

BREQ

BREQ BPRN

BPRN

74HC148

PRIORITY

ENCODER

••

74HC138

3 TO 8

ENCODER

true)

••

82C89

BCLK

BREQ

BPRN

BUSY

FIGURE 2. HIGHER PRIORITY ARBITER OBTAINING THE

NOTES:

1. Higher priority bus arbiter releases BUSY

2. Higher priority bus arbiter then acquires the bus and pulls BUSY down.

3. Lower priority bus arbiter releases BUSY

4. Higher priority bus arbiter then acquires the bus and pulls BUSY down.

BUS FROM A LOWER PRIORITY ARBITER

Serial Priority Resolving

The serial priority resolving technique eliminates the need for the priority encoder-decoder arrangement by daisychaining the bus arbiters together, connecting the higher priority bus arbiter’s BPRO to the BPRN

NOTE: The number of arbiters that may be daisy-chained together in the serial priority resolving scheme is a function of BCLK propagation delay from arbiter to arbiter. Normally, at 10MHz only 3 arbiters may be daisychained.

of the next lower priority. See Figure 3.

•

BUSYCBRQ

FIGURE 3. SERIAL PRIORITY RESOLVING

(Bus Priority Out) output

BUS

ARBITER

BUS

ARBITER

BUS

ARBITER

BUS

ARBITER

BPRN

BPRO

BPRN

BPRO

BPRN

BPRO

BPRN

BPRO

•

and the

Rotating Priority Resolving

The rotating priority resolving technique is similar to that of the parallel priority resolving technique except that priority is dynamically re-assigned. The priority encoder is replaced by a more complex circuit which rotates priority between requesting arbiters thus allowing each arbiter an equal chance to use the multi-master system bus, over time.

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February 27, 2006

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