intersil 82C59A User Manual

®

www.BDTIC.com/Intersil

82C59A

Data Sheet FN2784.5March 17, 2006

CMOS Priority Interrupt Controller

The Intersil 82C59A is a high performance CMOS Priority
Interrupt Controller manufactured using an advanced 2µm
CMOS process. The 82C59A is designed to relieve the
system CPU from the task of polling in a multilevel
priority system. The high speed and industry standard
configuration of the 82C59A make it compatible with
microprocessors such as 80C286, 80286, 80C86/88,
8086/88, 8080/85 and NSC800.

The 82C59A can handle up to eight vectored priority
interrupting sources and is cascadable to 64 without
additional circuitry. Individual interrupting sources can be
masked or prioritized to allow custom system configuration.
Two modes of operation make the 82C59A compatible with
both 8080/85 and 80C86/88/286 formats.

Static CMOS circuit design ensures low operating power.
The Intersil advanced CMOS process results in performance
equal to or greater than existing equivalent products at a
fraction of the power.

Features

• Pb-Free Plus Anneal Available (RoHS Compliant)

• 12.5MHz, 8MHz and 5MHz Versions Available

• High Speed, “No Wait-State” Operation with 12.5MHz
80C286 and 8MHz 80C86/88

• Pin Compatible with NMOS 8259A

• 80C86/88/286 and 8080/85/86/88/286 Compatible

• Eight-Level Priority Controller, Expandable to
64 Levels

• Programmable Interrupt Modes

• Individual Request Mask Capability

• Fully Static Design

• Fully TTL Compatible

• Low Power Operation

- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . 10µA Maximum

- ICCOP . . . . . . . . . . . . . . . . . . . . . .1mA/MHz Maximum

• Single 5V Power Supply

• Commercial, Industrial and Military Operating
Temperature Ranges Available

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. 2002, 2005, 2006. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

82C59A82C59A

www.BDTIC.com/Intersil

Ordering Information

PART NUMBER

PAR T

MARKING 8MHz

CP82C59A CP82C59A CP82C59A-12 CP82C59A-12 28 Ld PDIP 0 to +70 E28.6

CP82C59AZ
(Note)

CS82C59A CS82C59A CS82C59A-12 CS82C59A-12 28 Ld PLCC 0 to +70 N28.45

CS82C59A96 CS82C59A CS82C59A-1296 CS82C59A-12 28 Ld PLCC

CS82C59AZ
(Note)

CS82C59AZ96
(Note)

IS82C59A IS82C59A IS82C59A-12 IS82C59A-12 28 Ld PLCC -40 to +85 N28.45

IS82C59AX96 IS82C59A IS82C59A-12X96 IS82C59A-12 28 Ld PLCC

IS82C59AZ
(Note)

IS82C59AZX96
(Note)

ID82C59A ID82C59A 28 Ld CERDIP -40 to +85 F28.6

MD82C59A/B MD82C59A/B -55 to +125 F28.6

5962-8501601YA 5962-

8501601YA

*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

5962-8501602YA 5962-

5962-85016023A 5962-

PART

MARKING 12.5MHz

CP82C59AZ CP82C59A-12Z

(Note)

CS82C59AZ CS82C59A-12Z

(Note)

CS82C59AZ CS82C59A-12Z96

(Note)

IS82C59AZ IS82C59A-12Z

(Note)

IS82C59AZ IS82C59A-12Z96

(Note)

8501602YA

85016023A

PAR T

MARKING

CP82C59A-12Z 28 Ld PDIP*

CS82C59A-12Z 28 Ld PLCC

CS82C59A-12Z 28 Ld PLCC

IS82C59A-12Z 28 Ld PLCC

IS82C59A-12Z 28 Ld PLCC

PACKAGE

(Pb-Free)

(Tape & Reel)

(Pb-Free)

(Pb-Free, Tape
& Reel)

(Tape & Reel)

(Pb-Free)

(Pb-Free, Tape
& Reel)

SMD# -55 to +125 F28.6

28 Pad CLCC ­SMD#

TEMP

RANGE (°C)

0 to +70 E28.6

0 to +70 N28.45

0 to +70 N28.45

0 to +70 N28.45

-40 to +85 N28.45

-40 to +85 N28.45

-40 to +85 N28.45

-55 to +125 J28.A

PKG.

DWG. #5MHz

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2

FN2784.5

March 17, 2006

Pinouts

www.BDTIC.com/Intersil

82C59A (PDIP, CERDIP)

TOP VIEW

82C59A82C59A

82C59A (PLCC, CLCC)

TOP VIEW

CS

WR

RD

D7
D6
D5
D4
D3
D2
D1

D0
CAS 0
CAS 1

GND

1
2
3
4
5

6
7
8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

V

CC

A0
INTA
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0
INT
SP

/EN

CAS 2

D6
D5
D4
D3
D2
D1
D0

D7

RD

WR

3 2

4

5
6

7
8

9
10
11

12

14 15 16 17 18

13

CAS 1

GND

CAS 0

CS

1

28 27 26

CAS 2

CC

V

/ EN
SP

A0

INT

INTA

IR0

25

IR7

24

IR6

23

IR5

22

IR4
IR3

21
20

IR2

19

IR1

PIN DESCRIPTION

D7 - D0 Data Bus (Bidirectional)

RD

WR

Read Input

Write Input

A0 Command Select Address

CS

Chip Select

CAS 2 - CAS 0 Cascade Lines

SP

/EN Slave Program Input Enable

INT Interrupt Output

INTA

Interrupt Acknowledge Input

IR0 - IR7 Interrupt Request Inputs

Functional Diagram

D7-D

0

RD

WR

A

0

CS

CAS 0
CAS 1
CAS 2

SP/EN

DATA

BUS

BUFFER

READ/
WRITE
LOGIC

CASCADE

BUFFER

COMPARATOR

3

INTERNAL BUS

INTA

IN -

SERVICE

REG
(ISR)

FIGURE 1.

CONTROL LOGIC

PRIORITY

RESOLVER

INTERRUPT MASK REG

(IMR)

INT

INTERRUPT

REQUEST

REG

(IRR)

IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7

March 17, 2006

FN2784.5

82C59A82C59A

www.BDTIC.com/Intersil

Pin Description

SYMBOL TYPE DESCRIPTION

V

CC

GND I GROUND

CS

WR I WRITE: A low on this pin when CS is low enables the 82C59A to accept command words from the CPU.

RD

D7 - D0 I/O BIDIRECTIONAL DATA BUS: Control, status, and interrupt-vector information is transferred via this bus.

CAS0 - CAS2 I/O CASCADE LINES: The CAS lines form a private 82C59A bus to control a multiple 82C59A structure. These

/EN I/O SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin. When in the Buffered Mode it can be used

SP

INT O INTERRUPT: This pin goes high whenever a valid interrupt request is asserted. It is used to interrupt the CPU,

IR0 - IR7 I INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request is executed by raising an IR input (low to

INTA

A0 I ADDRESS LINE: This pin acts in conjunction with the CS

I VCC: The +5V power supply pin. A 0.1µF capacitor between pins 28 and 14 is recommended for decoupling.

I CHIP SELECT: A low on this pin enables RD and WR communications between the CPU and the 82C59A. INTA

functions are independent of CS

I READ: A low on this pin when CS is low enables the 82C59A to release status onto the data bus for the CPU.

pins are outputs for a master 82C59A and inputs for a slave 82C59A.

as an output to control buffer transceivers (EN
designate a master (SP

thus, it is connected to the CPU's interrupt pin.

high), and holding it high until it is acknowledged (Edge Triggered Mode), or just by a high level on an IR input
(Level Triggered Mode). Internal pull-up resistors are implemented on IR0 - 7.

I INTERRUPT ACKNOWLEDGE: This pin is used to enable 82C59A interrupt-vector data onto the data bus by

a sequence of interrupt acknowledge pulses issued by the CPU.

decipher various Command Words the CPU writes and status the CPU wishes to read. It is typically connected
to the CPU A0 address line (A1 for 80C86/88/286).

= 1) or slave (SP = 0).

.

). When not in the Buffered Mode it is used as an input to

, WR, and RD pins. It is used by the 82C59A to

Functional Description

Interrupts in Microcomputer Systems

Microcomputer system design requires that I/O devices such
as keyboards, displays, sensors and other components
receive servicing in an efficient manner so that large
amounts of the total system tasks can be assumed by the
microcomputer with little or no effect on throughput.

The most common method of servicing such devices is the
Polled approach. This is where the processor must test each
device in sequence and in effect “ask” each one if it needs
servicing. It is easy to see that a large portion of the main
program is looping through this continuous polling cycle and
that such a method would have a serious, detrimental effect
on system throughput, thus, limiting the tasks that could be
assumed by the microcomputer and reducing the cost
effectiveness of using such devices.

CPU

ROM

FIGURE 2. POLLED METHOD

CPU - DRIVEN
MULTIPLEXER

I/O (1)RAM

I/O (2)

I/O (N)

4

FN2784.5

March 17, 2006

82C59A82C59A

www.BDTIC.com/Intersil

A more desirable method would be one that would allow the
microprocessor to be executing its main program and only
stop to service peripheral devices when it is told to do so by
the device itself. In effect, the method would provide an
external asynchronous input that would inform the processor
that it should complete whatever instruction that is currently
being executed and fetch a new routine that will service the
requesting device. Once this servicing is complete, however,
the processor would resume exactly where it left off.

This is the Interrupt-driven method. It is easy to see that
system throughput would drastically increase, and thus,
more tasks could be assumed by the microcomputer to
further enhance its cost effectiveness.

INT

CPU

PIC

RAM

ROM

I/O (1)

I/O (2)

The Programmable Interrupt Controller (PlC) functions as an
overall manager in an Interrupt-Driven system. It accepts
requests from the peripheral equipment, determines which of
the incoming requests is of the highest importance (priority),
ascertains whether the incoming request has a higher
priority value than the level currently being serviced, and
issues an interrupt to the CPU based on this determination.

Each peripheral device or structure usually has a special
program or “routine” that is associated with its specific
functional or operational requirements; this is referred to as a
“service routine”. The PlC, after issuing an interrupt to the
CPU, must somehow input information into the CPU that can
“point” the Program Counter to the service routine
associated with the requesting device. This “pointer” is an
address in a vectoring table and will often be referred to, in
this document, as vectoring data.

82C59A Functional Description

The 82C59A is a device specifically designed for use in real
time, interrupt driven microcomputer systems. It manages
eight levels of requests and has built-in features for
expandability to other 82C59As (up to 64 levels). It is
programmed by system software as an I/O peripheral. A
selection of priority modes is available to the programmer so
that the manner in which the requests are processed by the
82C59A can be configured to match system requirements.
The priority modes can be changed or reconfigured
dynamically at any time during main program operation. This
means that the complete interrupt structure can be defined
as required, based on the total system environment.

I/O (N)

FIGURE 3. INTERRUPT METHOD

DATA

D7 - D

0

RD

WR

A

CS

CAS 0
CAS 1
CAS 2

SP/EN

0

BUS

BUFFER

READ/
WRITE
LOGIC

CASCADE

BUFFER

COMPARATOR

FIGURE 4. 82C59A FUNCTIONAL DIAGRAM

INTERNAL BUS

IN

SERVICE

REG
(ISR)

CONTROL LOGIC

PRIORITY

RESOLVER

INTERRUPT MASK REG

(IMR)

INTINTA

INTERRUPT

REQUEST

REG

(IRR)

IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7

5

FN2784.5

March 17, 2006

82C59A82C59A

www.BDTIC.com/Intersil

Interrupt Request Register (IRR) and In-Service Register
(ISR)

The interrupts at the IR input lines are handled by two registers
in cascade, the Interrupt Request Register (lRR) and the In­Service Register (lSR). The IRR is used to indicate all the
interrupt levels which are requesting service, and the ISR is
used to store all the interrupt levels which are currently being
serviced.

Priority Resolver

This logic block determines the priorities of the bits set in the
lRR. The highest priority is selected and strobed into the
corresponding bit of the lSR during the INTA

Interrupt Mask Register (IMR)

The lMR stores the bits which disable the interrupt lines to be
masked. The IMR operates on the output of the IRR.
Masking of a higher priority input will not affect the interrupt
request lines of lower priority.

Interrupt (INT)

This output goes directly to the CPU interrupt input. The
VOH level on this line is designed to be fully compatible with
the 8080, 8085, 8086/88, 80C86/88, 80286, and 80C286
input levels.

Interrupt Acknowledge (INTA

INTA

pulses will cause the 82C59A to release vectoring
information onto the data bus. The format of this data
depends on the system mode (µPM) of the 82C59A.

Data Bus Buffer

This 3-state, bidirectional 8-bit buffer is used to interface the
82C59A to the System Data Bus. Control words and status
information are transferred through the Data Bus Buffer.

)

sequence.

Read (RD

A LOW on this input enables the 82C59A to send the status
of the Interrupt Request Register (lRR), In-Service Register
(lSR), the Interrupt Mask Register (lMR), or the interrupt
level (in the poll mode) onto the Data Bus.

A0

This input signal is used in conjunction with WR
signals to write commands into the various command
registers, as well as to read the various status registers of
the chip. This line can be tied directly to one of the system
address lines.

The Cascade Buffer/Comparator

This function block stores and compares the IDs of all
82C59As used in the system. The associated three I/O pins
(CAS0 - 2) are outputs when the 82C59A is used as a
master and are inputs when the 82C59A is used as a slave.
As a master, the 82C59A sends the ID of the interrupting
slave device onto the CAS0 - 2 lines. The slave, thus
selected will send its preprogrammed subroutine address
onto the Data Bus during the next one or two consecutive
INTA

Interrupt Sequence

The powerful features of the 82C59A in a microcomputer
system are its programmability and the interrupt routine
addressing capability. The latter allows direct or indirect
jumping to the specified interrupt routine requested without
any polling of the interrupting devices. The normal sequence
of events during an interrupt depends on the type of CPU
being used.

)

and RD

pulses. (See section “Cascading the 82C59A”.)

Read/Write Control Logic

The function of this block is to accept output commands from
the CPU. It contains the Initialization Command Word (lCW)
registers and Operation Command Word (OCW) registers
which store the various control formats for device operation.
This function block also allows the status of the 82C59A to
be transferred onto the Data Bus.

Chip Select (CS

A LOW on this input enables the 82C59A. No reading or
writing of the device will occur unless the device is selected.

Write (WR

A LOW on this input enables the CPU to write control words
(lCWs and OCWs) to the 82C59A.

)

)

6

FN2784.5

March 17, 2006

ADDRESS BUS (16)

www.BDTIC.com/Intersil

CONTROL BUS

DATA BUS (8)

82C59A82C59A

I/OR I/OW INT INTA

CASCADE

LINES

CS RD WR INTAINTD7 - D

CAS 0
CAS 1
CAS 2

SP

SLAVE PROGRAM/

ENABLE BUFFER

FIGURE 5. 82C59A STANDARD SYSTEM BUS INTERFACE

A

IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ

/EN

7

These events occur in an 8080/8085 system:

1. One or more of the INTERRUPT REQUEST lines

(IR0 - IR7) are raised high, setting the corresponding IRR
bit(s).

2. The 82C59A evaluates those requests in the priority

resolver and sends an interrupt (INT) to the CPU, if
appropriate.

3. The CPU acknowledges the lNT and responds with an

pulse.

INTA

4. Upon receiving an lNTA

from the CPU group, the highest
priority lSR bit is set, and the corresponding lRR bit is
reset. The 82C59A will also release a CALL instruction
code (11001101) onto the 8-bit data bus through D0 - D7.

5. This CALL instruction will initiate two additional INTA
pulses to be sent to 82C59A from the CPU group.

6. These two INTA

pulses allow the 82C59A to release its
preprogrammed subroutine address onto the data bus.
The lower 8-bit address is released at the first INTA

pulse

and the higher 8-bit address is released at the second

pulse.

INTA

7. This completes the 3-byte CALL instruction released by
the 82C59A. In the AEOI mode, the lSR bit is reset at the
end of the third INTA

pulse. Otherwise, the lSR bit
remains set until an appropriate EOI command is issued
at the end of the interrupt sequence.

The events occurring in an 80C86/88/286 system are the
same until step 4.

0

6

0

82C59A

5

3

4

INTERRUPT

REQUESTS

2

1

0

4. The 82C59A does not drive the data bus during the first
INTA

pulse.

5. The 80C86/88/286 CPU will initiate a second INTA

pulse.
During this INTA pulse, the appropriate ISR bit is set and
the corresponding bit in the IRR is reset. The 82C59A
outputs the 8-bit pointer onto the d ata bus to be read by
the CPU.

6. This completes the interrupt cycle. In the AEOI mode, the
ISR bit is reset at the end of the second INTA pulse. Oth­erwise, the ISR bit remains set until an appropriate EOI
command is issued at the end of the interrupt subroutine.

If no interrupt request is present at step 4 of either sequence
(i.e., the request was too short in duration), the 82C59A will
issue an interrupt level 7. If a slave is programmed on IR bit
7, the CAS lines remain inactive and vector addresses are
output from the master 82C59A.

Interrupt Sequence Outputs

8080, 8085 Interrupt Response Mode

This sequence is timed by three INTA
lNTA

pulse, the CALL opcode is enabled onto the data bus.

First Interrupt Vector Byte Data: Hex CD

D7 D6 D5 D4 D3 D2 D1 D0

Call Code11001101

During the second INTA

pulse, the lower address of the

appropriate service routine is enabled onto the data bus.

pulses. During the first

7

FN2784.5

March 17, 2006

82C59A82C59A

www.BDTIC.com/Intersil

When interval = 4 bits, A5 - A7 are programmed, while
A0 - A4 are automatically inserted by the 82C59A. When
interval = 8, only A6 and A7 are programmed, while A0 - A5
are automatically inserted.

CONTENT OF SECOND INTERRUPT VECTOR BYTE

IR INTERVAL = 4

D7 D6 D5 D4 D3 D2 D1 D0

7A7A6A511100

6A7A6A511000

5A7A6A510100

4A7A6A510000

3A7A6A501100

2A7A6A501000

1A7A6A500100

0A7A6A500000

IR INTERVAL = 8

D7 D6 DS D4 D3 D2 D1 D0

7A7A6111000

6A7A6110000

5A7A6101000

4A7A6100000

3A7A6011000

2A7A6010000

1A7A6001000

0A7A6000000

slave if so programmed) will send a byte of data to the
processor with the acknowledged interrupt code composed
as follows (note the state of the ADI mode control is ignored
and A5 - A11 are unused in the 86/88/286 mode).

CONTENT OF INTERRUPT VECTOR BYTE FOR

80C86/88/286 SYSTEM MODE

D7 D6 D5 D4 D3 D2 D1 D0

lR7T7T6T5T4T3 1 1 1

lR6T7T6T5T4T3 1 1 0

IR5T7T6T5T4T3 1 0 1

IR4T7T6T5T4T3 1 0 0

IR3T7T6T5T4T3 0 1 1

IR2T7T6T5T4T3 0 1 0

IR1T7T6T5T4T3 0 0 1

IR0T7T6T5T4T3 0 0 0

Programming the 82C59A

The 82C59A accepts two types of command words
generated by the CPU:

1. Initialization Command Words (ICWs): Before normal
operation can begin, each 82C59A in the system must be
brought to a starting point - by a sequence of 2 to 4 bytes
timed by WR

pulses.

2. Operation Command Words (OCWs): These are the
command words which command the 82C59A to operate
in various interrupt modes. Among these modes are:

a. Fully nested mode.
b. Rotating priority mode.
c. Special mask mode.

During the third INTA

pulse, the higher address of the
appropriate service routine, which was programmed as byte 2
of the initialization sequence (A8 - A15), is enabled onto the
bus.

CONTENT OF THIRD INTERRUPT VECTOR BYTE

D7 D6 D5 D4 D3 D2 D1 D0

A15 A14 A13 A12 A11 A10 A9 A8

80C86, 8OC88, 80C286 Interrupt Response Mode

80C86/88/286 mode is similar to 8080/85 mode except that
only two Interrupt Acknowledge cycles are issued by the
processor and no CALL opcode is sent to the processor. The
first interrupt acknowledge cycle is similar to that of 8080/85
systems in that the 82C59A uses it to internally freeze the
state of the interrupts for priority resolution and, as a master,
it issues the interrupt code on the cascade lines. On this first
cycle, it does not issue any data to the processor and leaves
its data bus buffers disabled. On the second interrupt
acknowledge cycle in the 86/88/286 mode, the master (or

8

d. Poll e d mode.

The OCWs can be written into the 82C59A anytime after
initialization.

Initialization Command Words (lCWs)

General

Whenever a command is issued with A0 = 0 and D4 = 1, this
is interpreted as Initialization Command Word 1 (lCW1).
lCW1 starts the initialization sequence during which the
following automatically occur:

a. The edge sense circuit is reset, which means that follow-

ing initialization, an interrupt request (IR) input must make

a low-to-high transition to generate an interrupt.
b. The Interrupt Mask Register is cleared.
c. lR7 input is assigned priority 7.
d. Special Mask Mode is cleared and Status Read is set to

lRR.

FN2784.5

March 17, 2006

82C59A82C59A

www.BDTIC.com/Intersil

e. If lC4 = 0, then all functions selected in lCW4 are set to

zero. (Non-Buffered mode (see note), no Auto-EOI,
8080/85 system).

NOTE: Master/Slave in ICW4 is only used in the buffered mode.

ICW1

ICW2

NO (SNGL = 1)

NO (IC4 = 0)

INTERRUPT REQUESTS

FIGURE 6. 82C59A INITIALIZATION SEQUENCE

IN

CASCADE

MODE

YES (SNGL = 0))

ICW3

IS ICW4

NEEDED

YES (IC4 = 1)

ICW4

READY TO ACCEPT

Initialization Command Words 1 and 2 (ICW1, lCW2)

A5 - A15: Page starting address of service routines. In an
8080/85 system the 8 request levels will generate CALLS to
8 locations equally spaced in memory. These can be
programmed to be spaced at intervals of 4 or 8 memory
locations, thus, the 8 routines will occupy a page of 32 or 64
bytes, respectively.

The address format is 2 bytes long (A0 - A15). When the
routine interval is 4, A0 - A4 are automatically inserted by the
82C59A, while A5 - A15 are programmed externally. When
the routine interval is 8, A0 - A5 are automatically inserted by
the 82C59A while A6 - A15 are programmed externally.

The 8-byte interval will maintain compatibility with current
software, while the 4-byte interval is best for a compact jump
table.

In an 80C86/88/286 system, A15 - A11 are inserted in the
five most significant bits of the vectoring byte and the
82C59A sets the three least significant bits according to the
interrupt level. A10 - A5 are ignored and ADI (Address
interval) has no effect.

LTlM: If LTlM = 1, then the 82C59A will operate in the level

interrupt mode. Edge detect logic on the interrupt
inputs will be disabled.

ADI: ALL address inter val. ADI = 1 then interval = 4; ADI

= 0 then interval = 8.

SNGL: Single. Means that this is the only 82C59A in the

system. If SNGL = 1, no ICW3 will be issued.

IC4: If this bi t is set - lCW4 has to be issued. If lCW4 is

not needed, set lC4 = 0.

Initialization Command Word 3 (ICW3)

This word is read only when there is more than one 82C59A
in the system and cascading is used, in which case
SNGL = 0. It will load the 8-bit slave register. The functions of
this register are:

a. In the master mode (either when SP

= 1, or in buffered
mode when M/S = 1 in lCW4) a “1” is set for each slave in
the bit corresponding to the appropriate IR line for the
slave. The master then will release byte 1 of the call
sequence (for 8080/85 system) and will enable the corre­sponding slave to release bytes 2 and 3 (for 80C86/88/
286, only byte 2) through the cascade lines.

b. In the slave mode (either when SP

= 0, or if BUF = 1 and
M/S = 0 in lCW4), bits 2 - 0 identify the slave. The slave
compares its cascade input with these bits and if they are
equal, bytes 2 and 3 of the call sequence (or just b y te 2 for
80C86/88/286) are released by it on the Data Bus.

NOTE: (The slave address must correspond to the IR line it is
connected to in the master ID).

Initialization Command Word 4 (ICW4)

SFNM: If SFNM = 1, the special fully nested mode is pro-

grammed.

BUF: If BUF = 1, the buffered mode is programmed. In

buffered mode, SP/EN becomes an enable output
and the master/slave determination is by M/S.

M/S: If buffered mode is selected: M/S = 1 means the

82C59A is programmed to be a master, M/S = 0
means the 82C59A is programmed to be a slave. If
BUF = 0, M/S has no function.

AEOI: If AEOI = 1, the automatic end of interrup t mode is

programmed.

µPM: Microprocessor mode: µPM = 0 sets the 82C59A for

8080/85 system operation, µPM = 1 sets the
82C59A for 80C86/88/286 system operation.

9

FN2784.5

March 17, 2006

ICW1

www.BDTIC.com/Intersil

82C59A82C59A

A

0

0

D

7

A

7

D

A

ICW2

A

0

1

D

7

A

15

D

A

14

T

7

ICW3 (MASTER DEVICE)

A

0

D

7

D

1S7S

6

6

D

5

A

5

D

D

4

3

D

2

D

D

1

0

LTIM1ADISNGLIC4

1 = ICW4 needed
0 = No ICW4 needed

1 = Single
0 = Cascade Mode

CALL address interval
1 = Interval of 4
0 = Interval of 8

1 = Level triggered mode
0 = Edge triggered mode

- A5 of Interrupt vector address

A

7

(MCS-80/85 mode only)

6

6

6

D

5

A

13

T

6

D

5

S

5

D

A

12

T

5

D

S

D

4

T

4

4

3

A

11

4

D

3

S

3

D

2

A

10

T

3

D

2

S

2

D

A

9

D

S

1

D

1

1

0

A

8

A

- A8 of interrupt vector address

15

(MCS80/85 mode)

- T3 of interrupt vector address

T

7

(8086/8088 mode)

D

0

S

0

ICW3 (SLAVE DEVICE)

A

0

D

7

1000 0ID2ID

D

6

D

5

D

D

4

0

ICW4

A

0

D

7

D

6

D

5

D

D

4

1000 BUFM/SAEOIµPMSFNM

0
1
11

NOTE: Slave ID is equal to the corresponding master IR input.

1 = IR input has a slave
0 = IR input does not have a slave

3

D

2

D

D

1

1

0

ID

0

SLAVE ID (NOTE)

01 5234 67
01 1010 01
00 0110 11

00 1001 11

3

D

2

X - Non buffered mode
0

D

D

1

0

- Buffered mode slave

1 = 8086/8088 mode
0 = MCS-80/85 mode

1 = Auto EOI
0 = Normal EOI

- Buffered mode master

1 = Special fully nested moded
0 = Not special fully nested mode

FIGURE 7. 82C59A INITIALIZATION COMMAND WORD FORMAT

10

FN2784.5

March 17, 2006

82C59A82C59A

www.BDTIC.com/Intersil

Operation Command Words (OCWs)

After the Initialization Command Words (lCWs) are
programmed into the 82C59A, the device is ready to accept
interrupt requests at its input lines. However, during the
82C59A operation, a selection of algorithms can command
the 82C59A to operate in various modes through the
Operation Command Words (OCWs).

OPERATION COMMAND WORDS (OCWs)

A0 D7 D6 D5 D4 D3 D2 D1 D0

OCW1

1 M7M6 M5M4M3M2M1M0

OCW2

0 R SL EOI 0 0 L2 L1 L0

OCW3

0 0 ESMM SMM 0 1 P RR RIS

Operation Command Word 1 (OCW1)

OCW1 sets and clears the mask bits in the Interrupt Mask
Register (lMR) M7 - M0 represent the eight mask bits. M = 1
indicates the channel is masked (inhibited), M = 0 indicates
the channel is enabled.

trailing edge of the last INTA
further interrupts of the same or lower priority are inhibited,
while higher levels will generate an interrupt (which will be
acknowledged only if the microprocessor internal interrupt
enable flip-flop has been re-enabled through software).

After the initialization sequence, IR0 has the highest priority
and IR7 the lowest. Priorities can be changed, as will be
explained in the rotating priority mode or via the set priority
command.

. While the IS bit is set, all

Operation Command Word 2 (OCW2)

R, SL, EOI - These three bits control the Rotate and End of
Interrupt modes and combinations of the two. A chart of
these combinations can be found on the Operation
Command Word Format.

L2, L1, L0 - These bits determine the interrupt level acted
upon when the SL bit is active.

Operation Command Word 3 (OCW3)

ESMM - Enable Special Mask Mode. When this bit is set to 1
it enables the SMM bit to set or reset the Special Mask
Mode. When ESMM = 0, the SMM bit becomes a “don’t
care”.

SMM - Special Mask Mode. If ESMM = 1 and SMM = 1, the
82C59A will enter Special Mask Mode. If ESMM = 1 and
SMM = 0, the 82C59A will revert to normal mask mode.
When ESMM = 0, SMM has no effect.

Fully Nested Mode

This mode is entered after initialization unless another mode
is programmed. The interrupt requests are ordered in priority
from 0 through 7 (0 highest). When an interrupt is
acknowledged the highest priority request is determined and
its vector placed on the bus. Additionally, a bit of the Interrupt
Service register (IS0 - 7) is set. This bit remains set until the
microprocessor issues an End of Interrupt (EOI) command
immediately before returning from the service routine, or if
the AEOI (Automatic End of Interrupt) bit is set, until the

11

FN2784.5

March 17, 2006

OCW1

www.BDTIC.com/Intersil

A

0

D

7

1M7M

D

D

6

6

5

M

5

D

M

D

4

4

3

M

3

OCW2

A

0

D

7

0 R SL EOI 0 L

001
011

†

101
100
0

0

0

1

1

1

†

1
0

1
10

†

0

D

D

6

5

D

4

0

Non-specific EOI command
Specific EOI command
Rotate on non-specific EOI command

Rotate in automatic EOI mode (set)
Rotate in automatic EOI mode (clear)

Rotate on specific EOI command
Set priority command
No operation

D

3

OCW3

A

0

D

7

D

D

6

5

D

D

4

3

0 0 ESMM SMM 1 P RR RIS0

82C59A82C59A

D

2

M

2

D

2

2

End of interrupt

Automatic rotation

Specific rotation

- L2 are used

† L

0

D

2

D

1

M

1

D

0

M

0

Interrupt Mask
1 = Mask set
0 = Mask reset

D

1

L

1

D

0

L

0

IR LEVEL TO BE

ACTED UPON

01 5234 67
01 1010 01
00 0110 11

00 1001 11

D

1

D

0

READ REGISTER COMMAND

0011

1100

Read IS reg on

pulse

next RD

No Action

Read IR reg on
next RD

pulse

FIGURE 8. 82C59A OPERATION COMMAND WORD FORMAT

12

1 = Poll command
0 = No poll command

SPECIAL MASK MODE

0011

1100

Set special
mask

FN2784.5

March 17, 2006

No Action

Reset special
mask

82C59A

www.BDTIC.com/Intersil

End of Interrupt (EOI)

The In-Service (IS) bit can be reset either automatically
following the trailing edge of the last in sequence INTA pulse
(when AEOI bit in lCW1 is set) or by a command word that
must be issued to the 82C59A before returning from a
service routine (EOI Command). An EOI command must be
issued twice if servicing a slave in the Cascade mode, once
for the master and once for the corresponding slave.

There are two forms of EOl command: Specific and Non­Specific. When the 82C59A is operated in modes which
preserve the fully nested structure, it can determine which IS
bit to reset on EOI. When a Non-Specific command is issued
the 82C59A will automatically reset the highest IS bit of
those that are set, since in the fully nested mode the highest
IS level was necessarily the last level acknowledged and
serviced. A non-specific EOI can be issued with OCW2
(EOl = 1, SL = 0, R = 0).

IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0

“IS” Status01010000

Priority
Status

After Rotate (lR4 was serviced, all other priorities rotated
correspondingly)

IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0

“IS” Status01000000

Priority
Status

76543210

lowest highest

21076543

highest lowest

When a mode is used which may disturb the fully nested
structure, the 82C59A may no longer be able to determine
the last level acknowledged. In this case a Specific End of
Interrupt must be issued which includes as part of the
command the IS level to be reset. A specific EOl can be
issued with OCW2 (EOI = 1, SL = 1, R = 0, and L0 - L2 is the
binary level of the IS bit to be reset).

An lRR bit that is masked by an lMR bit will not be cleared by
a non-specific EOI if the 82C59A is in the Special Mask
Mode.

Automatic End of Interrupt (AEOI) Mode

If AEOI = 1 in lCW4, then the 82C59A will operate in AEOl
mode continuously until reprogrammed by lCW4. In this
mode the 82C59A will automatically perform a non-specific
EOI operation at the trailing edge of the last interrupt
acknowledge pulse (third pulse in 8080/85, second in
80C86/88/286). Note that from a system standpoint, this
mode should be used only when a nested multilevel interrupt
structure is not required within a single 82C59A.

Automatic Rotation (Equal Priority Devices)

In some applications there are a number of interrupting
devices of equal priority. In this mode a device, after being
serviced, receives the lowest priority, so a device requesting
an interrupt will have to wait, in the worst case until each of 7
other devices are serviced at most once. For example, if the
priority and “in service” status is:

Before Rotate (lR4 the highest priority requiring service)

There are two ways to accomplish Automatic Rotation using
OCW2, the Rotation on Non-Specific EOI Command (R = 1,
SL = 0, EOI = 1) and the Rotate in Automatic EOI Mode
which is set by (R = 1, SL = 0, EOI = 0) and cleared by
(R = 0, SL = 0, EOl = 0).

Specific Rotation (Specific Priority)

The programmer can change priorities by programming the
lowest priority and thus, fixing all other priorities; i.e., if IR5 is
programmed as the lowest priority device, then IR6 will have
the highest one.

The Set Priority command is issued in OCW2 where: R = 1,
SL = 1, L0 - L2 is the binary priority level code of the lowest
priority device.

Observe that in this mode internal status is updated by soft­ware control during OCW2. However, it is independent of the
End of Interrupt (EOI) command (also executed by OCW2).
Priority changes can be executed during an EOI command
by using the Rotate on Specific EOl command in OCW2
(R = 1, SL = 1, EOI = 1, and L0 - L2 = IR level to receive
lowest priority).

Interrupt Masks

Each Interrupt Request input can be masked individually by
the Interrupt Mask Register (IMR) programmed through
OCW1. Each bit in the lMR masks one interrupt channel if it
is set (1). Bit 0 masks IR0, Bit 1 masks IR1 and so forth.
Masking an IR channel does not affect the operation of other
channels.

Special Mask Mode

Some applications may require an interrupt service routine
to dynamically alter the system priority structure during its
execution under software control. For example, the routine
may wish to inhibit lower priority requests for a portion of its
execution but enable some of them for another portion.

13

FN2784.5

March 17, 2006

82C59A82C59A

www.BDTIC.com/Intersil

The difficulty here is that if an Interrupt Request is
acknowledged and an End of Interrupt command did not
reset its IS bit (i.e., while executing a service routine), the
82C59A would have inhibited all lower priority requests with
no easy way for the routine to enable them.

That is where the Special Mask Mode comes in. In the
Special Mask Mode, when a mask bit is set in OCW1, it
inhibits further interrupts at that level and enables interrupts
from all other levels (lower as well as higher) that are not
masked.

Thus, any interrupts may be selectively enabled by loading
the mask register.

The Special Mask Mode is set by OCW3 where: ESMM = 1,
SMM = 1, and cleared where ESMM = 1, SMM = 0.

Poll Command

In this mode, the INT output is not used or the
microprocessor internal Interrupt Enable flip flop is reset,

IR

8080/85

MODE

V

CC

FREEZE

INTA

EDGE
SENSE
LATCH

CLR

Q

SET

LTI M B IT

0 = EDGE

1 = LEVEL

TO OTHER PRIORITY CELLS

REQUEST

LATCH

QD

CQ

disabling its interrupt input. Service to devices is achieved by
software using a Poll command.

The Poll command is issued by setting P = 1 in OCW3. The
82C59A treats the next RD
0, CS

= 0) as an interrupt acknowledge, sets the appropriate

pulse to the 82C59A (i.e., RD =

IS bit if there is a request, and reads the priority level.
Interrupt is frozen from WR

to RD.

The word enabled onto the data bus during RD

D7 D6 D5 D4 D3 D2 D1 D0

I----W2W1W0

W0 - W2: Binary code of the highest pr iority level request-

ing service.

I: Equal to a “1” if there is an interrupt.

This mode is useful if there is a routine command common to
several levels so that the INTA

sequence is not needed
(saves ROM space). Another application is to use the poll
mode to expand the number of priority levels to more than 64.

CLR ISR

ISR BIT

SET ISR

NON­MASKED
REQ

PRIORITY
RESOLVER

CONTROL
LOGIC

MASK LATCH

QD

C

CLR

CLR

Q

SET

IN - SERVICE

LATCH

is:

80C86/

88/286
MODE

NOTES:

1. Master clear active only during ICW1.

2. FREEZE

3. Truth Table for D-latch.

C D Q Operation

1D1D1Follow

0XQn-1Hold

INTA

FREEZE

is active during INTA and poll sequence only.

FREEZE READ

IRR

WRITE

MASK

14

READ IMR
READ ISR
MASTER CLEAR

FN2784.5

March 17, 2006

82C59A82C59A

www.BDTIC.com/Intersil

Reading the 82C59A Status

The input status of several internal registers can be read to
update the user information on the system. The following
registers can be read via OCW3 (lRR and ISR) or OCW1
(lMR).

Interrupt Request Register (IRR): 8-bit register which
contains the levels requesting an interrupt to be
acknowledged. The highest request level is reset from the
lRR when an interrupt is acknowledged. lRR is not affected
by lMR.

In-Service Register (ISR): 8-bit register which contains the
priority levels that are being serviced. The ISR is updated
when an End of Interrupt Command is issued.

Interrupt Mask Register: 8-bit register which contains the
interrupt request lines which are masked.

The lRR can be read when, prior to the RD

pulse, a Read

Register Command is issued with OCW3 (RR = 1, RIS = 0).

The ISR can be read when, prior to the RD

pulse, a Read

Register Command is issued with OCW3 (RR = 1, RIS = 1).

There is no need to write an OCW3 before every status read
operation, as long as the status read corresponds with the
previous one: i.e., the 82C59A “remembers” whether the lRR
or ISR has been previously selected by the OCW3. This is
not true when poll is used. In the poll mode, the 82C59A
treats the RD

following a “poll write” operation as an INTA.

After initialization, the 82C59A is set to lRR.

For reading the lMR, no OCW3 is needed. The output data bus
will contain the lMR whenever RD

is active and A0 = 1 (OCW1).

Polling overrides status read when P = 1, RR = 1 in OCW3.

Edge and Level Triggered Modes

This mode is programmed using bit 3 in lCW1.

If LTlM = “0”, an interrupt request will be recognized by a low to
high transition on an IR input. The IR input can remain high
without generating another interrupt.

If LTIM = “1”, an interrupt request will be recognized by a “high”
level on an IR input, and there is no need for an edge detection.
The interrupt request must be removed before the EOI
command is issued or the CPU interrupt is enabled to prevent a
second interrupt from occurring.

The priority cell diagram shows a conceptual circuit of the level
sensitive and edge sensitive input circuitry of the 82C59A. Be
sure to note that the request latch is a transparent D type latch.

In both the edge and level triggered modes the IR inputs
must remain high until after the falling edge of the first INTA
If the IR input goes low before this time a DEFAULT lR7 will
occur when the CPU acknowledges the interrupt. This can
be a useful safeguard for detecting interrupts caused by
spurious noise glitches on the IR inputs. To implement this
feature the lR7 routine is used for “clean up” simply
executing a return instruction, thus, ignoring the interrupt. If
lR7 is needed for other purposes a default lR7 can still be
detected by reading the ISR. A normal lR7 interrupt will set
the corresponding ISR bit, a default IR7 won’t. If a default
IR7 routine occurs during a normal lR7 routine, however, the
ISR will remain set. In this case it is necessary to keep track
of whether or not the IR7 routine was previously entered. If
another lR7 occurs it is a default.

In power sensitive applications, it is advisable to place the
82C59A in the edge-triggered mode with the IR lines
normally high. This will minimize the current through the
internal pull-up resistors on the IR pins.

.

80C86/88/286

IR

INTA

NOTE:

1. Edge triggered mode only.

INT

LATCH

ARM

(NOTE 1)

EARLIEST IR

CAN BE

REMOVED

FIGURE 10. IR TRIGGERING TIMING REQUIREMENTS

LATCH

ARM

(NOTE 1)

8080/85

80C86/88/286

15

8080/85

LATCH

(NOTE 1)

ARM

FN2784.5

March 17, 2006

82C59A82C59A

www.BDTIC.com/Intersil

The Special Fully Nested Mode

This mode will be used in the case of a big system where
cascading is used, and the priority has to be conserved
within each slave. In this case the special fully nested mode
will be programmed to the master (using lCW4). This mode
is similar to the normal nested mode with the following
exceptions:

a. When an interrupt request from a cer tain slave is in ser-

vice, this slave is not locked out from the master’s priority
logic and further interrupt requests from higher priority
IRs within the slave will be recognized by the master and
will initiate interrupts to the processor. (In the normal
nested mode a slave is masked out when its request is in
service and no higher requests from the same slave can
be serviced.

b. When exiting the Interrupt Service routine the software

has to check whether the interrupt serviced was the o nly
one from that slave. This is done by sending a non-spe­cific End of Interrupt (EOI) command to the slave and
then reading its In-Service register a nd checking for zero.
If it is empty, a non-specified EOI can be sent to the mas­ter, too. If not, no EOI should be sent.

Buffered Mode

When the 82C59A is used in a large system where bus
driving buffers are required on the data bus and the
cascading mode is used, there exists the problem of
enabling buffers

The buffered mode will structure the 82C59A to send an
enable signal on SP

/EN to enable the buffers. In this mode,
whenever the 82C59A’s data bus outputs are enabled, the
SP

/EN output becomes active.

This modification forces the use of software programming to
determine whether the 82C59A is a master or a slave. Bit 3
in ICW4 programs the buffered mode, and bit 2 in lCW4
determines whether it is a master or a slave.

Cascade Mode

The 82C59A can be easily interconnected in a system of one
master with up to eight slaves to handle up to 64 priority
levels.

The master controls the slaves through the 3 line cascade
bus (CAS2 - 0). The cascade bus acts like chip selects to the
slaves during the INTA

sequence.

In a cascade configuration, the slave interrupt outputs (INT)
are connected to the master interrupt request inputs. When a
slave request line is activated and afterwards acknowledged,
the master will enable the corresponding slave to release the
device routine address during bytes 2 and 3 of INTA

. (Byte 2

only for 80C86/88/286).

The cascade bus lines are normally low and will contain the
slave address code from the leading edge of the first INTA
pulse to the trailing edge of the last INTA

pulse. Each
82C59A in the system must follow a separate initialization
sequence and can be programmed to work in a different
mode. An EOI command must be issued twice: once for the
master and once for the corresponding slave. Chip select
decoding is required to activate each 82C59A.

NOTE: Auto EOI is supported in the slave mode for the 82C59A.

The cascade lines of the Master 82C59A are activated only
for slave inputs, non-slave inputs leave the cascade line
inactive (low). Therefore, it is necessary to use a slave
address of 0 (zero) only after all other addresses are used.

CS

82C59A
SP/EN 756 43210

GND

- D

0D7

756 43210

INTA

0

SLAVE A

INTA
CAS 0
CAS 1
CAS 2

16

ADDRESS BUS (16)

CONTROL BUS

DATA BUS (8)

CS

82C59A
SP/EN 756 43210

GND

FIGURE 11. CASCADING THE 82C59A

- D

0D7

756 43210

INTERRUPT REQUESTS

0

SLAVE B

INTA

INTA
CAS 0
CAS 1
CAS 2

CS

CAS 0
CAS 1
CAS 2

SP/EN 756 43210

V

CC

- D

0

INTA

0D7

MASTER 82C59A

75421036

INTA

INT REQ

FN2784.5

March 17, 2006

82C59A82C59A

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V

Input, Output or I/O Voltage. . . . . . . . . . . . .GND-0.5V to V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class I

CC

+0.5V

Operating Conditions

Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . .+4.5V to +5.5V

Operating Temperature Range

CX82C59A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0

IX82C59A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40

MX82C59A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55

Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V

o

C to 70oC

o

C to 85oC

o

C to 125oC

Thermal Resistance (Typical)

CERDIP Package. . . . . . . . . . . . . . . . . 55 12

CLCC Package. . . . . . . . . . . . . . . . . . . 65 14

PDIP Package*. . . . . . . . . . . . . . . . . . . 55 N/A

PLCC Package. . . . . . . . . . . . . . . . . . . 65 N/A

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Maximum Junction Temperature Ceramic Package. . . . . . . . +175°C

Maximum Junction Temperature Plastic Package . . . . . . . . .+150°C

Maximum Lead Temperature Package (Soldering 10s). . . . . +300°C

(PLCC - Lead Tips Only)

*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1250 Gates

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

θ

(°C/W) θJC (°C/W)

JA

DC Electrical Specifications V

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

V

V

V

OH

V

OL

II Input Leakage Current -1.0 +1.0 µAV

IO Output Leakage Current -10.0 +10.0 µAV

ILIR IR Input Load Current -

lCCSB Standby Power Supply Current - 10 µAVCC = 5.5V, VIN = VCC or GND Outputs

ICCOP Operating Power Supply Current - 1 mA/MHz V

NOTES:

1. Except for IR0 - lR7 where V

2. ICCOP = 1mA/MHz of peripheral read/write cycle time. (ex: 1.0µs I/O read/write cycle time = 1mA).

Capacitance T

SYMBOL PARAMETER TYP UNITS TEST CONDITIONS

CIN Input Capacitance 15 pF FREQ = 1MHz, all measurements reference to

COUT Output Capacitance 15 pF

CI/O I/O Capacitance 15 pF

Logical One Input Voltage 2.0

lH

Logical Zero Input Voltage - 0.8 V

IL

Output HIGH Voltage 3.0

Output LOW Voltage - 0.4 V lOL = +2.5mA

= V

IN

= +25°C

A

= +5.0V ±10%, TA = Operating Temperature Range

CC

-VVC82C59A, I82C59A

2.2

-VVIOH = -2.5mA

VCC -0.4

CC

or open.

-200

-

10

µA
µA

M82C59A

= -100µA

l

OH

= GND or VCC, Pins 1-3, 26-27

IN

= GND or VCC, Pins 4-13, 15-16

OUT

= 0V

V

IN

= V

V

IN

CC

Open, (Note 1)

= 5.0V, VIN = VCC or GND, Outputs Open,

CC

= 25°C, (Note 2)

T

A

device GND.

AC Electrical Specifications V

SYMBOL PARAMETER

TIMING REQUIREMENTS

(1) TAHRL A0/CS

(2) TRHAX A0/CS

(3) TRLRH RD

Setup to RD/INTA 10 - 10 - 5 - ns

Hold after RD/INTA 5-5-0- ns

/lNTA Pulse Width 235 - 160 - 60 - ns

= +5.0V ±10%, GND = 0V, TA = Operating Temperature Range

CC

5MHz 8MHz 12.5MHz

17

UNITS

TEST

CONDITIONSMIN MAX MIN MAX MIN MAX

March 17, 2006

FN2784.5

82C59A82C59A

www.BDTIC.com/Intersil

AC Electrical Specifications V

SYMBOL PARAMETER

(4) TAHWL A0/CS Setup to WR 0-0-0- ns

(5) TWHAX A0/CS

(6) TWLWH WR

(7) TDVWH Data Setup to WR

(8) TWHDX Data Hold after WR

(9) TJLJH Interrupt Request Width Low 100 - 100 - 40 - ns

(10) TCVlAL Cascade Setup to Second or Third INTA

(11) TRHRL End of RD

(12) TWHWL End of WR

(13) TCHCL

(Note 1)

TIMING RESPONSES

(14) TRLDV Data Valid from RD

(15) TRHDZ Data Float after RD

(16) TJHlH Interrupt Output Delay - 350 - 300 - 90 ns 1

(17) TlALCV Cascade Valid from First INTA

(18) TRLEL Enable Active from RD

(19) TRHEH Enable Inactive from RD

(20) TAHDV Data Valid from Stable Address - 210 - 200 - 60 ns 1

(21) TCVDV Cascade Valid to Valid Data - 300 - 200 - 70 ns 1

NOTE:

1. Worst case timing for TCHCL in an actual microprocessor system is typically greater than the values specified for the 82C59A,
(i.e. 8085A = 1.6µs, 8085A -2 = 1µs, 80C86 = 1µs, 80C286 -10 = 131ns, 80C286 -12 = 98ns).

Hold after WR 5-5-0- ns

Pulse Width 165 - 95 - 60 - ns

Only)

to next RD, End of INTA (within an

sequence only)

INTA

to next WR 190 - 190 - 60 - ns

End of Command to next command (not same
command type), End of INTA
sequence to next INTA sequence

(Master Only)

= +5.0V ±10%, GND = 0V, TA = Operating Temperature Range (Continued)

CC

5MHz 8MHz 12.5MHz

UNITS

240 - 160 - 70 - ns

5-5-0- ns

(Slave

/INTA - 160 - 120 - 40 ns 1

/INTA 5 100 5 85 5 22 ns 2

or INTA - 125 - 100 - 40 ns 1

or INTA -60-50-22 ns 1

55 - 40 - 30 - ns

160 - 160 - 90 - ns

500 - 400 - 90 - ns

- 565 - 360 - 50 ns 1

TEST

CONDITIONSMIN MAX MIN MAX MIN MAX

AC Test Circuit

V

1

R

OUTPUT FROM

DEVICE UNDER

NOTE: Includes stray and jig capacitance.

TEST

TEST CONDITION DEFINITION TABLE

TEST

CONDITION V

1 1.7V 523Ω Open 100pF

2V

1

CC

C

1

(NOTE)

1.8kΩ 1.8kΩ 50pF

1

R

2

R

1

TEST
POINT

R

2

18

C

1

FN2784.5

March 17, 2006

AC Testing Input, Output Waveform

www.BDTIC.com/Intersil

82C59A82C59A

INPUT

V

IH

V

IL

+0.4V

1.5V

- 0.4V

OUTPUT

1.5V

V

OH

V

OL

NOTE: AC Testing: All input signals must switch between VIL - 0.4V and VIH + 0.4V. Input rise and fall times are driven at 1ns/V.

Timing Waveforms

WR

ADDRESS BUS

CS

A

DATA BUS

RD/INTA

(4)

TAH WL

0

(6)

TWLWH

(7)

TDVWH

FIGURE 12. WRITE

(3)

TRLRH

(8)

TWHDX

(5)

TWHAX

EN

ADDRESS BUS

CS

A

DATA BUS

RD

INTA

WR

RD

INTA

WR

RD

INTA

WR

(18)

TRLEL

(1)

TAHRL

0

(14)

TRLDV

(20)

TAHDV

FIGURE 13. READ

(11)

TRHRL

(12)

TWHWL

(13)

TCHCL

/INTA

TRHEH

(15)

TRHDZ

(19)

(2)

TRHAX

FIGURE 14. OTHER TIMING

19

FN2784.5

March 17, 2006

Timing Waveforms (Continued)

www.BDTIC.com/Intersil

IR

(16)

TJHIH

82C59A82C59A

(9)

TJLJH

INT

INTA

DB

CAS 0 - 2

SEE NOTE 1

SEE

NOTE 2

TCVIAL

(17)

TIALCV

NOTES:

1. Interrupt Request (IR) must remain HIGH until leading edge of first INTA

2. During first INTA

the Data Bus is not active in 80C86/88/286 mode.

3. 80C86/88/286 mode.

4. 8080/8085 mode.

FIGURE 15. INTA

Burn-In Circuits

MD82C59A CERDIP

(10)

(21)

TCVDV

.

SEQUENCE

SEE NOTE 3 SEE NOTE 4

(10)

TCVIAL

GND

WR

RD

D7
D6
D5
D4
D3
D2
D1

D0
CAS 0
CAS 1

GND

R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R3
R3

1
2
3
4
5
6
7
8

9
10
11
12
13
14

28

R1

27

R1

26

R2

25

R2

24

R2

23

R2

22

R2

21

R2

20

R2

19

R2

18
17

R3

16

R3

15

A0
INTA
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0
A
SP
CAS 2

/EN

V

CC

C1

V

CC

R3

A

R3

20

FN2784.5

March 17, 2006

Burn-In Circuits

www.BDTIC.com/Intersil

82C59A

5962-850160X3A CLCC

VCCC1

D7 RD WR GND A0 INTA

R1 R1 R1R1 R1 R1

NOTES:

= 5.5V ±0.5V.

1. V

CC

2. V

= 4.5V ±10%.

IH

= -0.2V to 0.4V.

3. V

IL

4. GND = 0V.

5. R1 = 47kΩ ±5%.

6. R2 = 510Ω ±5%.

3 2 14

R1 R1 R1 R1 R4 R2

CAS0

CAS1

D6

D5

D4

D3

D2
D1

D0

R1

R1

R1

R1

R1

R1

R1

5

6

7

8

9

10

11

7. R3 = 10kΩ ±5%.

8. R4 = 1.2kΩ ±5%.

9. C1 = 0.01µF min.

10. F0 = 100kHz ±10%.

11. F1 = F0/2, F2 = F1/2, ...F8 = F7/2.

14 15 16 17 1812 13

GND

28 27 26

/EN

CAS2

SP

25

24

23

22

21

20

19

/2

IR0

CC

V

R2

R2

R2

R2

R2

R2

R2

IR7

IR6

IR5

IR4

IR3
IR2

IR1

21

FN2784.5

March 17, 2006

Die Characteristics

www.BDTIC.com/Intersil

METALLIZATION:

Type: Si-Al-Cu
Thickness: Metal 1: 8k

Å ± 0.75kÅ

Metal 2: 12kÅ ± 1.0kÅ

GLASSIVATION:

Type: Nitrox
Thickness: 10k

Å ± 3.0kÅ

Metallization Mask Layout

82C59A

82C59A

CAS0

CAS1

GND

CAS2

SP

/EN

INT

IR0

D0 D1 D2 D3 D4 D5

D6

D7

RD

WR

CS

V

CC

A0

INTA

IR1 IR2 IR3 IR4 IR5 IR6

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

22

IR7

FN2784.5

March 17, 2006