intersil 82C59A User Manual

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82C59A

Data Sheet FN2784.5March 17, 2006

CMOS Priority Interrupt Controller

The Intersil 82C59A is a high performance CMOS Priority Interrupt Controller manufactured using an advanced 2µm CMOS process. The 82C59A is designed to relieve the system CPU from the task of polling in a multilevel priority system. The high speed and industry standard configuration of the 82C59A make it compatible with microprocessors such as 80C286, 80286, 80C86/88, 8086/88, 8080/85 and NSC800.

The 82C59A can handle up to eight vectored priority interrupting sources and is cascadable to 64 without additional circuitry. Individual interrupting sources can be masked or prioritized to allow custom system configuration. Two modes of operation make the 82C59A compatible with both 8080/85 and 80C86/88/286 formats.

Static CMOS circuit design ensures low operating power. The Intersil advanced CMOS process results in performance equal to or greater than existing equivalent products at a fraction of the power.

Features

• Pb-Free Plus Anneal Available (RoHS Compliant)

• 12.5MHz, 8MHz and 5MHz Versions Available

• High Speed, “No Wait-State” Operation with 12.5MHz 80C286 and 8MHz 80C86/88

• Pin Compatible with NMOS 8259A

• 80C86/88/286 and 8080/85/86/88/286 Compatible

• Eight-Level Priority Controller, Expandable to 64 Levels

• Programmable Interrupt Modes

• Individual Request Mask Capability

• Fully Static Design

• Fully TTL Compatible

• Low Power Operation

- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . 10µA Maximum

- ICCOP . . . . . . . . . . . . . . . . . . . . . .1mA/MHz Maximum

• Single 5V Power Supply

• Commercial, Industrial and Military Operating Temperature Ranges Available

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

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Ordering Information

PART NUMBER

PAR T

MARKING 8MHz

CP82C59A CP82C59A CP82C59A-12 CP82C59A-12 28 Ld PDIP 0 to +70 E28.6

CP82C59AZ (Note)

CS82C59A CS82C59A CS82C59A-12 CS82C59A-12 28 Ld PLCC 0 to +70 N28.45

CS82C59A96 CS82C59A CS82C59A-1296 CS82C59A-12 28 Ld PLCC

CS82C59AZ (Note)

CS82C59AZ96 (Note)

IS82C59A IS82C59A IS82C59A-12 IS82C59A-12 28 Ld PLCC -40 to +85 N28.45

IS82C59AX96 IS82C59A IS82C59A-12X96 IS82C59A-12 28 Ld PLCC

IS82C59AZ (Note)

IS82C59AZX96 (Note)

ID82C59A ID82C59A 28 Ld CERDIP -40 to +85 F28.6

MD82C59A/B MD82C59A/B -55 to +125 F28.6

5962-8501601YA 5962-

8501601YA

*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

5962-8501602YA 5962-

5962-85016023A 5962-

PART

MARKING 12.5MHz

CP82C59AZ CP82C59A-12Z

(Note)

CS82C59AZ CS82C59A-12Z

(Note)

CS82C59AZ CS82C59A-12Z96

(Note)

IS82C59AZ IS82C59A-12Z

(Note)

IS82C59AZ IS82C59A-12Z96

(Note)

8501602YA

85016023A

PAR T

MARKING

CP82C59A-12Z 28 Ld PDIP*

CS82C59A-12Z 28 Ld PLCC

IS82C59A-12Z 28 Ld PLCC

PACKAGE

(Pb-Free)

(Tape & Reel)

(Pb-Free)

(Pb-Free, Tape & Reel)

(Tape & Reel)

(Pb-Free)

(Pb-Free, Tape & Reel)

SMD# -55 to +125 F28.6

28 Pad CLCC SMD#

TEMP

RANGE (°C)

0 to +70 E28.6

0 to +70 N28.45

-40 to +85 N28.45

-55 to +125 J28.A

PKG.

DWG. #5MHz

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

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March 17, 2006

Pinouts

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82C59A (PDIP, CERDIP)

TOP VIEW

82C59A82C59A

82C59A (PLCC, CLCC)

TOP VIEW

D7 D6 D5 D4 D3 D2 D1

D0 CAS 0 CAS 1

GND

1 2 3 4 5

6 7 8

9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

A0 INTA IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0 INT SP

/EN

CAS 2

D6 D5 D4 D3 D2 D1 D0

3 2

5 6

7 8

9 10 11

14 15 16 17 18

CAS 1

GND

CAS 0

28 27 26

CAS 2

/ EN SP

INT

INTA

IR0

IR7

IR6

IR5

IR4 IR3

21 20

IR2

IR1

PIN DESCRIPTION

D7 - D0 Data Bus (Bidirectional)

Read Input

Write Input

A0 Command Select Address

Chip Select

CAS 2 - CAS 0 Cascade Lines

/EN Slave Program Input Enable

INT Interrupt Output

INTA

Interrupt Acknowledge Input

IR0 - IR7 Interrupt Request Inputs

Functional Diagram

D7-D

CAS 0 CAS 1 CAS 2

SP/EN

DATA

BUS

BUFFER

READ/ WRITE LOGIC

CASCADE

BUFFER

COMPARATOR

INTERNAL BUS

INTA

IN -

SERVICE

REG (ISR)

FIGURE 1.

CONTROL LOGIC

PRIORITY

RESOLVER

INTERRUPT MASK REG

(IMR)

INT

INTERRUPT

REQUEST

REG

(IRR)

IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7

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Pin Description

SYMBOL TYPE DESCRIPTION

GND I GROUND

WR I WRITE: A low on this pin when CS is low enables the 82C59A to accept command words from the CPU.

D7 - D0 I/O BIDIRECTIONAL DATA BUS: Control, status, and interrupt-vector information is transferred via this bus.

CAS0 - CAS2 I/O CASCADE LINES: The CAS lines form a private 82C59A bus to control a multiple 82C59A structure. These

/EN I/O SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin. When in the Buffered Mode it can be used

INT O INTERRUPT: This pin goes high whenever a valid interrupt request is asserted. It is used to interrupt the CPU,

IR0 - IR7 I INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request is executed by raising an IR input (low to

INTA

A0 I ADDRESS LINE: This pin acts in conjunction with the CS

I VCC: The +5V power supply pin. A 0.1µF capacitor between pins 28 and 14 is recommended for decoupling.

I CHIP SELECT: A low on this pin enables RD and WR communications between the CPU and the 82C59A. INTA

functions are independent of CS

I READ: A low on this pin when CS is low enables the 82C59A to release status onto the data bus for the CPU.

pins are outputs for a master 82C59A and inputs for a slave 82C59A.

as an output to control buffer transceivers (EN designate a master (SP

thus, it is connected to the CPU's interrupt pin.

high), and holding it high until it is acknowledged (Edge Triggered Mode), or just by a high level on an IR input (Level Triggered Mode). Internal pull-up resistors are implemented on IR0 - 7.

I INTERRUPT ACKNOWLEDGE: This pin is used to enable 82C59A interrupt-vector data onto the data bus by

a sequence of interrupt acknowledge pulses issued by the CPU.

decipher various Command Words the CPU writes and status the CPU wishes to read. It is typically connected to the CPU A0 address line (A1 for 80C86/88/286).

= 1) or slave (SP = 0).

). When not in the Buffered Mode it is used as an input to

, WR, and RD pins. It is used by the 82C59A to

Functional Description

Interrupts in Microcomputer Systems

Microcomputer system design requires that I/O devices such as keyboards, displays, sensors and other components receive servicing in an efficient manner so that large amounts of the total system tasks can be assumed by the microcomputer with little or no effect on throughput.

The most common method of servicing such devices is the Polled approach. This is where the processor must test each device in sequence and in effect “ask” each one if it needs servicing. It is easy to see that a large portion of the main program is looping through this continuous polling cycle and that such a method would have a serious, detrimental effect on system throughput, thus, limiting the tasks that could be assumed by the microcomputer and reducing the cost effectiveness of using such devices.

CPU

ROM

FIGURE 2. POLLED METHOD

CPU - DRIVEN MULTIPLEXER

I/O (1)RAM

I/O (2)

I/O (N)

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A more desirable method would be one that would allow the microprocessor to be executing its main program and only stop to service peripheral devices when it is told to do so by the device itself. In effect, the method would provide an external asynchronous input that would inform the processor that it should complete whatever instruction that is currently being executed and fetch a new routine that will service the requesting device. Once this servicing is complete, however, the processor would resume exactly where it left off.

This is the Interrupt-driven method. It is easy to see that system throughput would drastically increase, and thus, more tasks could be assumed by the microcomputer to further enhance its cost effectiveness.

INT

CPU

PIC

RAM

ROM

I/O (1)

I/O (2)

The Programmable Interrupt Controller (PlC) functions as an overall manager in an Interrupt-Driven system. It accepts requests from the peripheral equipment, determines which of the incoming requests is of the highest importance (priority), ascertains whether the incoming request has a higher priority value than the level currently being serviced, and issues an interrupt to the CPU based on this determination.

Each peripheral device or structure usually has a special program or “routine” that is associated with its specific functional or operational requirements; this is referred to as a “service routine”. The PlC, after issuing an interrupt to the CPU, must somehow input information into the CPU that can “point” the Program Counter to the service routine associated with the requesting device. This “pointer” is an address in a vectoring table and will often be referred to, in this document, as vectoring data.

82C59A Functional Description

The 82C59A is a device specifically designed for use in real time, interrupt driven microcomputer systems. It manages eight levels of requests and has built-in features for expandability to other 82C59As (up to 64 levels). It is programmed by system software as an I/O peripheral. A selection of priority modes is available to the programmer so that the manner in which the requests are processed by the 82C59A can be configured to match system requirements. The priority modes can be changed or reconfigured dynamically at any time during main program operation. This means that the complete interrupt structure can be defined as required, based on the total system environment.

I/O (N)

FIGURE 3. INTERRUPT METHOD

DATA

D7 - D

CAS 0 CAS 1 CAS 2

SP/EN

BUS

BUFFER

READ/ WRITE LOGIC

CASCADE

BUFFER

COMPARATOR

FIGURE 4. 82C59A FUNCTIONAL DIAGRAM

INTERNAL BUS

SERVICE

REG (ISR)

CONTROL LOGIC

PRIORITY

RESOLVER

INTERRUPT MASK REG

(IMR)

INTINTA

INTERRUPT

REQUEST

REG

(IRR)

IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7

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Interrupt Request Register (IRR) and In-Service Register (ISR)

The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt Request Register (lRR) and the InService Register (lSR). The IRR is used to indicate all the interrupt levels which are requesting service, and the ISR is used to store all the interrupt levels which are currently being serviced.

Priority Resolver

This logic block determines the priorities of the bits set in the lRR. The highest priority is selected and strobed into the corresponding bit of the lSR during the INTA

Interrupt Mask Register (IMR)

The lMR stores the bits which disable the interrupt lines to be masked. The IMR operates on the output of the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower priority.

Interrupt (INT)

This output goes directly to the CPU interrupt input. The VOH level on this line is designed to be fully compatible with the 8080, 8085, 8086/88, 80C86/88, 80286, and 80C286 input levels.

Interrupt Acknowledge (INTA

INTA

pulses will cause the 82C59A to release vectoring information onto the data bus. The format of this data depends on the system mode (µPM) of the 82C59A.

Data Bus Buffer

This 3-state, bidirectional 8-bit buffer is used to interface the 82C59A to the System Data Bus. Control words and status information are transferred through the Data Bus Buffer.

)

sequence.

Read (RD

A LOW on this input enables the 82C59A to send the status of the Interrupt Request Register (lRR), In-Service Register (lSR), the Interrupt Mask Register (lMR), or the interrupt level (in the poll mode) onto the Data Bus.

This input signal is used in conjunction with WR signals to write commands into the various command registers, as well as to read the various status registers of the chip. This line can be tied directly to one of the system address lines.

The Cascade Buffer/Comparator

This function block stores and compares the IDs of all 82C59As used in the system. The associated three I/O pins (CAS0 - 2) are outputs when the 82C59A is used as a master and are inputs when the 82C59A is used as a slave. As a master, the 82C59A sends the ID of the interrupting slave device onto the CAS0 - 2 lines. The slave, thus selected will send its preprogrammed subroutine address onto the Data Bus during the next one or two consecutive INTA

Interrupt Sequence

The powerful features of the 82C59A in a microcomputer system are its programmability and the interrupt routine addressing capability. The latter allows direct or indirect jumping to the specified interrupt routine requested without any polling of the interrupting devices. The normal sequence of events during an interrupt depends on the type of CPU being used.

)

and RD

pulses. (See section “Cascading the 82C59A”.)

Read/Write Control Logic

The function of this block is to accept output commands from the CPU. It contains the Initialization Command Word (lCW) registers and Operation Command Word (OCW) registers which store the various control formats for device operation. This function block also allows the status of the 82C59A to be transferred onto the Data Bus.

Chip Select (CS

A LOW on this input enables the 82C59A. No reading or writing of the device will occur unless the device is selected.

Write (WR

A LOW on this input enables the CPU to write control words (lCWs and OCWs) to the 82C59A.

)

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ADDRESS BUS (16)

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CONTROL BUS

DATA BUS (8)

82C59A82C59A

I/OR I/OW INT INTA

CASCADE

LINES

CS RD WR INTAINTD7 - D

CAS 0 CAS 1 CAS 2

SLAVE PROGRAM/

ENABLE BUFFER

FIGURE 5. 82C59A STANDARD SYSTEM BUS INTERFACE

IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ

/EN

These events occur in an 8080/8085 system:

1. One or more of the INTERRUPT REQUEST lines

(IR0 - IR7) are raised high, setting the corresponding IRR bit(s).

2. The 82C59A evaluates those requests in the priority

resolver and sends an interrupt (INT) to the CPU, if appropriate.

3. The CPU acknowledges the lNT and responds with an

pulse.

INTA

4. Upon receiving an lNTA

from the CPU group, the highest priority lSR bit is set, and the corresponding lRR bit is reset. The 82C59A will also release a CALL instruction code (11001101) onto the 8-bit data bus through D0 - D7.

5. This CALL instruction will initiate two additional INTA pulses to be sent to 82C59A from the CPU group.

6. These two INTA

pulses allow the 82C59A to release its preprogrammed subroutine address onto the data bus. The lower 8-bit address is released at the first INTA

pulse

and the higher 8-bit address is released at the second

pulse.

INTA

7. This completes the 3-byte CALL instruction released by the 82C59A. In the AEOI mode, the lSR bit is reset at the end of the third INTA

pulse. Otherwise, the lSR bit remains set until an appropriate EOI command is issued at the end of the interrupt sequence.

The events occurring in an 80C86/88/286 system are the same until step 4.

82C59A

INTERRUPT

REQUESTS

4. The 82C59A does not drive the data bus during the first INTA

pulse.

5. The 80C86/88/286 CPU will initiate a second INTA

pulse. During this INTA pulse, the appropriate ISR bit is set and the corresponding bit in the IRR is reset. The 82C59A outputs the 8-bit pointer onto the d ata bus to be read by the CPU.

6. This completes the interrupt cycle. In the AEOI mode, the ISR bit is reset at the end of the second INTA pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine.

If no interrupt request is present at step 4 of either sequence (i.e., the request was too short in duration), the 82C59A will issue an interrupt level 7. If a slave is programmed on IR bit 7, the CAS lines remain inactive and vector addresses are output from the master 82C59A.

Interrupt Sequence Outputs

8080, 8085 Interrupt Response Mode

This sequence is timed by three INTA lNTA

pulse, the CALL opcode is enabled onto the data bus.

First Interrupt Vector Byte Data: Hex CD

D7 D6 D5 D4 D3 D2 D1 D0

Call Code11001101

During the second INTA

pulse, the lower address of the

appropriate service routine is enabled onto the data bus.

pulses. During the first

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