intersil 82C55A User Manual

82C55A

Data Sheet August 25, 2005

CMOS Programmable Peripheral Interface

The Intersil 82C55A is a high performance CMOS version of the industry standard 8255A and is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). It is a general purpose programmable I/O device which may be used with many different microprocessors. There are 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. The high performance and industry standard configuration of the 82C55A make it compatible with the 80C86, 80C88 and other microprocessors.

Static CMOS circuit design insures low operating power. TTL compatibility over the full military temperature range and bus hold circuitry eliminate the need for pull-up resistors. The Intersil advanced SAJI process results in performance equal to or greater than existing functionally equivalent products at a fraction of the power.

Ordering Information

FN2969.8

Features

• Pb-Free Plus Anneal Available (RoHS Compliant) (See Ordering Info)

• Pin Compatible with NMOS 8255A

• 24 Programmable I/O Pins

• Fully TTL Compatible

• High Speed, No “Wait State” Operation with 5MHz and 8MHz 80C86 and 80C88

• Direct Bit Set/Reset Capability

• Enhanced Control Word Read Capability

• L7 Process

• 2.5mA Drive Capability on All I/O Ports

• Low Standby Power (ICCSB). . . . . . . . . . . . . . . . . . .10µA

PAR T N U MBERS

PAR T

MARKING 8MHz

CP82C55A-5 CP82C55A-5 CP82C55A CP82C55A 0 to 70 40 Ld PDIP E40.6

CP82C55A-5Z (Note) CP82C55A-5Z CP82C55AZ (Note) CP82C55AZ 0 to 70 40 Ld PDIP (Pb-free)

IP82C55A IP82C55A -40 to 85 40 Ld PDIP

IP82C55AZ (Note) IP82C55AZ -40 to 85 40 Ld PDIP (Pb-free)

CS82C55A-5* CS82C55A-5 CS82C55A* CS82C55A* 0 to 70 44 Ld PLCC N44.65

CS82C55AZ* (Note) CS82C55AZ 0 to 70 44 Ld PLCC (Pb-free)

IS82C55A-5 IS82C55A-5 IS82C55A* IS82C55A* -40 to 85 44 Ld PLCC

IS82C55AZ* (Note) IS82C55AZ -40 to 85 44 Ld PLCC (Pb-free)

CQ82C55A* CQ82C55A* 0 to 70 44 Ld MQFP Q44.10x10

CQ82C55AZ (Note) CQ82C55AZ 0 to 70 44 Ld MQFP (Pb-free)

IQ82C55A* IQ82C55A* -40 to 85 44 Ld MQFP

IQ82C55AZ* (Note) IQ82C55AZ -40 to 85 44 Ld MQFP (Pb-free)

ID82C55A ID82C55A -40 to 85 40 Ld CERDIP F40.6

MD82C55A/B MD82C55A/B -55 to 125

8406602QA 8406602QA SMD#

8406602XA 8406602XA SMD# 44 Ld CLCC J44.A

*Add “96” suffix to part number for tape and reel packaging.

PAR T

MARKING

TEMP.

RANGE (°C) PACKAGE PKG. DWG. #5MHz

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Pinouts

82C55A (PDIP, CERDIP)

TOP VIEW

PA3

PA2

PA1

PA0

GND

PC7

PC6

PC5

PC4

PC0

PC1

PC2

PC3

PB0

PB1

PB2

40 39 38 37 36 35 34 33 32

31 30 29 28 27 26 25 24 23 22 21

PA4 PA5 PA6

PA7 WR RESET D0 D1 D2 D3 D4 D5 D6 D7 V

PB7

PB6 PB5 PB4 PB3

82C55A

82C55A (CLCC)

TOP VIEW

PA0

PA1

PA2

GND

PC7

PC6

PC5

PC4

PC0

PC1

PC2

18 19 20 21 22 23 24 25 26 27 28

PC3

PB0

PB3

PB1

PB2

PA3

PA4

PA5

PB4

PB5

PB6

PA6

PA7

4065 3 21444342414

RESET

PB7

GND

A1 A0

PC7

PC6 PC5 PC4 PC0 PC1

82C55A (PLCC)

TOP VIEW

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

262524232221201918

PB4

PB5

PB6

2827

PB7

RESET

D0 D1

GND

PC7

PC6

PC5

PC4

PC0

PC1

PC2

44 43 42 41 40

12 13 14 15 16 17

44 43 42 41 40

123456

7 8 9 10 11 12 13 14 15 16 17

PB0

PB1

PB2

PB3

PC2

PC3

82C55A (MQFP)

PA0

PA1

PA2

PC3

PB0

PB1

TOP VIEW

PA4

PA5

PB3

PB4

PA3

39 38 37 36 35 34

PB2

PA6

PA7

2221201918

PB5

PB6

RESET

PB7

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82C55A

Pin Description

SYMBOL TYPE DESCRIPTION

GND GROUND

D0-D7 I/O DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus.

RESET I RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode with the “Bus

WR I WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A.

A0-A1 I ADDRESS: These input signals, in conjunction with the RD

PA0-PA7 I/O PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are present on this port.

PB0-PB7 I/O PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.

PC0-PC7 I/O PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.

VCC: The +5V power supply pin. A 0.1µF capacitor between VCC and GND is recommended for decoupling.

Hold” circuitry turned on.

I CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU

communications.

I READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus.

and WR inputs, control the selection of one of the three ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus A0, A1.

Functional Diagram

POWER

SUPPLIES

BIDIRECTIONAL

DATA BUS

D7-D0

RESET

+5V

GND

DATA BUS

BUFFER

READ

WRITE

CONTROL

LOGIC

GROUP A

CONTROL

GROUP B

CONTROL

8-BIT INTERNAL DATA BUS

GROUP A

PORT A

(8)

GROUP A

PORT C UPPER

(4)

GROUP B

PORT C

LOWER

(4)

GROUP B

PORT B

(8)

I/O

PA7 -PA0

I/O

PC7-PC4

I/O

PC3-PC0

I/O

PB7-PB0

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Functional Description

Data Bus Buffer

This three-state bidirectional 8-bit buffer is used to interface the 82C55A to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer.

Read/Write and Control Logic

The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups.

(CS

) Chip Select. A “low” on this input pin enables the

communication between the 82C55A and the CPU.

(RD

) Read. A “low” on this input pin enables 82C55A to send

the data or status information to the CPU on the data bus. In essence, it allows the CPU to “read from” the 82C55A.

(WR

) Write. A “low” on this input pin enables the CPU to

write data or control words into the 82C55A.

(A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. They are normally connected to the least significant bits of the address bus (A0 and A1).

82C55A BASIC OPERATION

INPUT OPERATION

A1 A0 RD

00010Port A → Data Bus

01010Port B → Data Bus

10010Port C → Data Bus

11010Control Word → Data Bus

00100Data Bus → Port A

01100Data Bus → Port B

10100Data Bus → Port C

11100Data Bus → Control

XXXX1Data Bus → Three-State

XX110Data Bus → Three-State

WR CS

(RESET) Reset. A “high” on this input initializes the control

register to 9Bh and all ports (A, B, C) are set to the input mode. “Bus hold” devices internal to the 82C55A will hold the I/O port inputs to a logic “1” state with a maximum hold current of 400µA.

(READ)

OUTPUT OPERATION

(WRITE)

DISABLE FUNCTION

I/O

PA7 -

POWER

SUPPLIES

BIDIRECTIONAL

DATA BUS

D7-D0

A1 A0

RESET

FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,

+5V GND

DATA

BUS

BUFFER

READ

WRITE

CONTROL

LOGIC

READ/WRITE, GROUP A & B CONTROL LOGIC FUNCTIONS

GROUP A

CONTROL

8-BIT INTERNAL DATA BUS

GROUP B

CONTROL

GROUP A

PORT A

(8)

GROUP A

PORT C

UPPER

(4)

GROUP B

PORT C LOWER

(4)

GROUP B

PORT B

(8)

PA0

I/O

PC7-

PC4

I/O

PC3-

PC0

I/O

PB7-

PB0

Group A and Group B Controls

The functional configuration of each port is programmed by the systems software. In essence, the CPU “outputs” a control word to the 82C55A. The control word contains information such as “mode”, “bit set”, “bit reset”, etc., that initializes the functional configuration of the 82C55A.

Each of the Control blocks (Group A and Group B) accepts “commands” from the Read/Write Control logic, receives “control words” from the internal data bus and issues the proper commands to its associated ports.

Control Group A - Port A and Port C upper (C7 - C4)

Control Group B - Port B and Port C lower (C3 - C0)

The control word register can be both written and read as shown in the “Basic Operation” table. Figure 4 shows the control word format for both Read and Write operations. When the control word is read, bit D7 will always be a logic “1”, as this implies control word mode information.

Ports A, B, and C

The 82C55A contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or “personality” to further enhance the power and flexibility of the 82C55A.

Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both “pull-up” and “pull-down” bus-hold devices are present on Port A. See Figure 2A.

Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer. See Figure 2B.

Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into

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82C55A

two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports A and B. See Figure 2B.

MASTER

RESET

OR MODE

CHANGE

INTERNAL

DATA IN

INTERNAL DATA OUT

(LATCHED)

FIGURE 2A. PORT A BUS-HOLD CONFIGURATION

RESET

OR MODE

CHANGE

INTERNAL

DATA IN

INTERNAL DATA OUT

(LATCHED)

FIGURE 2B. PORT B AND C BUS-HOLD CONFIGURATION

FIGURE 2. BUS-HOLD CONFIGURATION

INPUT MODE

OUTPUT MODE

EXTERNAL PORT A PIN

EXTERNAL PORT B, C PIN

Operational Description

Mode Selection

There are three basic modes of operation than can be selected by the system software:

Mode 0 - Basic Input/Output Mode 1 - Strobed Input/Output Mode 2 - Bidirectional Bus

When the reset input goes “high”, all ports will be set to the input mode with all 24 port lines held at a logic “one” level by internal bus hold devices. After the reset is removed, the 82C55A can remain in the input mode with no additional initialization required. This eliminates the need to pull-up or pull-down resistors in all-CMOS designs. The control word register will contain 9Bh. During the execution of the system program, any of the other modes may be selected using a single output instruction. This allows a single 82C55A to service a variety of peripheral devices with a simple software maintenance routine. Any port programmed as an output port is initialized to all zeros when the control word is written.

ADDRESS BUS

CONTROL BUS

DATA BUS

MODE 0

MODE 1

MODE 2

RD, WR

8I/O

PB7-PB0

8I/O

PB7-PB0 CONTROL

8I/O

PB7-PB0

D7-D0 A0-A1

82C55A

4I/O

PC3-PC0

OR I/O

PC7-PC4

CONTROL

OR I/O

CONTROL

4I/O

8I/O

PA7 -PA0

8I/O

PA7 -PA0

BIDIRECTIONAL

FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE

CONTROL WORD

D7 D6 D5 D4 D3 D2 D1 D0

GROUP B

PORT C (LOWER) 1 = INPUT 0 = OUTPUT

PORT B 1 = INPUT 0 = OUTPUT

MODE SELECTION 0 = MODE 0 1 = MODE 1

GROUP A

PORT C (UPPER) 1 = INPUT 0 = OUTPUT

PORT A 1 = INPUT 0 = OUTPUT

MODE SELECTION 00 = MODE 0 01 = MODE 1 1X = MODE 2

MODE SET FLAG 1 = ACTIVE

FIGURE 4. MODE DEFINITION FORMAT

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82C55A

The modes for Port A and Port B can be separately defined, while Port C is divided into two portions as required by the Port A and Port B definitions. All of the output registers, including the status flip-flops, will be reset whenever the mode is changed. Modes may be combined so that their functional definition can be “tailored” to almost any I/O structure. For instance: Group B can be programmed in Mode 0 to monitor simple switch closings or display computational results, Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interruptdriven basis.

The mode definitions and possible mode combinations may seem confusing at first, but after a cursory review of the complete device operation a simple, logical I/O approach will surface. The design of the 82C55A has taken into account things such as efficient PC board layout, control signal definition vs. PC layout and complete functional flexibility to support almost any peripheral device with no external logic. Such design represents the maximum use of the available pins.

Single Bit Set/Reset Feature (Figure 5)

Any of the eight bits of Port C can be Set or Reset using a single Output instruction. This feature reduces software requirements in control-based applications.

When Port C is being used as status/control for Port A or B, these bits can be set or reset by using the Bit Set/Reset operation just as if they were output ports.

CONTROL WORD

D7 D6 D5 D4 D3 D2 D1 D0

XXX

DON’T

CARE

FIGURE 5. BIT SET/RESET FORMAT

BIT SET/RESET 1 = SET 0 = RESET

BIT SELECT

1234567 01010101 00110011 00001111

BIT SET/RESET FLAG 0 = ACTIVE

B0 B1 B2

Interrupt Control Functions

When the 82C55A is programmed to operate in mode 1 or mode 2, control signals are provided that can be used as interrupt request inputs to the CPU. The interrupt request signals, generated from port C, can be inhibited or enabled by setting or resetting the associated INTE flip-flop, using the bit set/reset function of port C.

This function allows the programmer to enable or disable a CPU interrupt by a specific I/O device without affecting any other device in the interrupt structure.

INTE Flip-Flop Definition

(BIT-SET)-INTE is SET - Interrupt Enable

(BIT-RESET)-INTE is Reset - Interrupt Disable

NOTE: All Mask flip-flops are automatically reset during mode selection and device Reset.

Operating Modes

Mode 0 (Basic Input/Output). This functional configuration provides simple input and output operations for each of the three ports. No handshaking is required, data is simply written to or read from a specific port.

Mode 0 Basic Functional Definitions:

• Two 8-bit ports and two 4-bit ports

• Any Port can be input or output

• Outputs are latched

• Inputs are not latched

• 16 different Input/Output configurations possible

MODE 0 PORT DEFINITION

A B GROUP A

PORT C

D4 D3 D1 D0 PORT A

0 0 0 0 Output Output 0 Output Output

0 0 0 1 Output Output 1 Output Input

0 0 1 0 Output Output 2 Input Output

0 0 1 1 Output Output 3 Input Input

0 1 0 0 Output Input 4 Output Output

0 1 0 1 Output Input 5 Output Input

0 1 1 0 Output Input 6 Input Output

0 1 1 1 Output Input 7 Input Input

1 0 0 0 Input Output 8 Output Output

1 0 0 1 Input Output 9 Output Input

1 0 1 0 Input Output 10 Input Output

1 0 1 1 Input Output 11 Input Input

1 1 0 0 Input Input 12 Output Output

1 1 0 1 Input Input 13 Output Input

1 1 1 0 Input Input 14 Input Output

1 1 1 1 Input Input 15 Input Input

(Upper) PORT B

GROUP B

PORT C (Lower)

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Mode 0 (Basic Input)

82C55A

tRR

tHR

tRA

tIR

INPUT

tAR

, A1, A0

D7-D0

tRD tDF

Mode 0 (Basic Output)

tWW

tDW

tWD

tWB

, A1, A0

OUTPUT

D7-D0

tAW

Mode 0 Configurations

CONTROL WORD #0 CONTROL WORD #2

0D60D50D40D30D20D10

D7 - D0

82C55A

1D70D60D50D40D30D21D10

PA7 - PA0

PC7 - PC4

D7 - D0

PC3 - PC0

tWA

82C55A

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

CONTROL WORD #1 CONTROL WORD #3

1D70D60D50D40D30D20D11

82C55A

D7 - D0

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

1D70D60D50D40D30D21D11

D7 - D0

82C55A

PB7 - PB0

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

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82C55A

Mode 0 Configurations (Continued)

CONTROL WORD #4 CONTROL WORD #8

1D70D60D50D41D30D20D10

82C55A

D7 - D0

PA7 - PA0

PC7 - PC4

PC3 - PC0

1D70D60D51D40D30D20D10

D7 - D0

82C55A

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

CONTROL WORD #5 CONTROL WORD #9

1D70D60D50D41D30D20D11

82C55A

D7 - D0

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

1D70D60D51D40D30D20D11

D7 - D0

CONTROL WORD #6 CONTROL WORD #10

1D70D60D50D41D30D21D10

82C55A

D7 - D0

PA7 - PA0

PC7 - PC4

PC3 - PC0

1D70D60D51D40D30D21D10

D7 - D0

82C55A

PB7 - PB0

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

CONTROL WORD #7 CONTROL WORD #11

1D70D60D50D41D30D21D11

82C55A

D7 - D0

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

1D70D60D51D40D30D21D11

D7 - D0

82C55A

PB7 - PB0

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

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82C55A

Mode 0 Configurations (Continued)

CONTROL WORD #12 CONTROL WORD #14

1D70D60D51D41D30D20D10

82C55A

D7 - D0

PA7 - PA0

PC7 - PC4

PC3 - PC0

1D70D60D51D41D30D21D10

D7 - D0

82C55A

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

CONTROL WORD #13 CONTROL WORD #15

1D70D60D51D41D30D20D11

82C55A

D7 - D0

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

1D70D60D51D41D30D21D11

D7 - D0

Operating Modes

Mode 1 - (Strobed Input/Output). This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction with strobes or “hand shaking” signals. In mode 1, port A and port B use the lines on port C to generate or accept these “hand shaking” signals.

Mode 1 Basic Function Definitions:

• Two Groups (Group A and Group B)

• Each group contains one 8-bit port and one 4-bit control/data port

• The 8-bit data port can be either input or output. Both inputs and outputs are latched.

• The 4-bit port is used for control and status of the 8-bit port.

Input Control Signal Definition

(Figures 6 and 7)

CONTROL WORD

1D70D61D51D41/0

CONTROL WORD

D6 D5 D4 D3 D2 D1 D0

82C55A

D2 D1 D0

PC6, PC7 1 = INPUT

0 = OUTPUT

MODE 1 (PORT A)

INTE

MODE 1 (PORT B)

INTE

PB7 - PB0

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

PA7 -PA0

PC4

PC3

PC6, PC7

PB7-PB0

PC2

STBA

IBFAPC5

INTRA

I/O

STBB

IBFBPC1

STB (Strobe Input)

A “low” on this input loads data into the input latch.

IBF (Input Buffer Full F/F)

A “high” on this output indicates that the data has been loaded into the input latch: in essence, an acknowledgment. IBF is set by STB edge of the RD

input being low and is reset by the rising

input.

FIGURE 6. MODE 1 INPUT

PC0

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