intersil 82C54 User Manual

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82C54

Data Sheet FN2970.4

CMOS Programmable Intervel Timer

The Intersil 82C54 is a high performance CMOS Programmable Interval Timer manufactured using an advanced 2 micron CMOS process.

The 82C54 has three independently programmable and functional 16-bit counters, each capable of handling clock input frequencies of up to 8MHz (82C54) or 10MHz (82C54-10) or 12MHz (82C54-12).

The high speed and industry standard configuration of the 82C54 make it compatible with the Intersil 80C86, 80C88, and 80C286 CMOS microprocessors along with many other industry standard processors. Six programmable timer modes allow the 82C54 to be used as an event counter, elapsed time indicator, programmable one-shot, and many other applications. Static CMOS circuit design insures low power operation.

The Intersil advanced CMOS process results in a significant reduction in power with performance equal to or greater than existing equivalent products.

July 11, 2005

Features

• 8MHz to 12MHz Clock Input Frequency

• Compatible with NMOS 8254

- Enhanced Version of NMOS 8253

• Three Independent 16-Bit Counters

• Six Programmable Counter Modes

• Status Read Back Command

• Binary or BCD Counting

• Fully TTL Compatible

• Single 5V Power Supply

•Low Power

- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10µA

- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA at 8MHz

• Operating Temperature Ranges

- CX82C54 . . . . . . . . . . . . . . . . . . . . . . . . .0

- IX82C54 . . . . . . . . . . . . . . . . . . . . . . . . -40

- MD82C54 . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC

C to +70oC

C to +85oC

Pinouts

82C54 (PDIP, CERDIP)

TOP VIEW

D7 D6

6 7

CLK 0

OUT 0

GATE 0

GND

24 23 22 21 20 19 18 17 16 15 14 13

VCC WR RD CS A1 A0 CLK 2 OUT 2 GAT E 2 CLK 1 GAT E 1 OUT 1

• Pb-Free Plus Anneal Available (RoHS Compliant)

82C54 (PLCC/CLCC)

TOP VIEW

VCC

CLK 0

1234

10 11

12 13 14 15 16 17 18

GND

OUT 0

GATE 0

262728

25 24

CS A1

CLK2

OUT 2

GATE 2

CLK 1

OUT 1

GATE 1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

82C54

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Ordering Information

PART NUMBERS

CP82C54 CP82C54-10 CP82C54-12 0 CP82C54Z (See Note) CP82C54-10Z (See Note) CP82C54-12Z (See Note) 0 CS82C54* CS82C54-10* CS82C54-12 0 CS82C54Z* (See Note) CS82C54-10Z* (See Note) CS82C54-12Z* (See Note) 0 ID82C54 - - -40 IP82C54 IP82C54-10 - -40 IP82C54Z (See Note) IP82C54-10Z (See Note) - -40 IS82C54* IS82C54-10* - -40 IS82C54Z (See Note) IS82C54-10Z (See Note) - -40 MD82C54/B - - -55 SMD # 8406501JA - - -55 SMD# 84065013A - 84065023A -55 Contact factory for availability.

*Add “96” suffix for tape and reel.

**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

TEMPERATURE

RANGE PACKAGE

C to +70oC 24 Lead PDIP E24.6

C to +70oC 24 Lead PDIP** (Pb-free) E24.6

C to +70oC 28 Lead PLCC N28.45

C to +70oC 28 Lead PLCC (Pb-free) N28.45

C to +85oC 24 Lead CERDIP F24.6

C to +85oC 24 Lead PDIP E24.6

C to +85oC 24 Lead PDIP** (Pb-free) E24.6

C to +85oC 28 Lead PLCC N28.45

C to +85oC 28 Lead PLCC (Pb-free) N28.45

C to +125oC 24 Lead CERDIP F24.6

C to +125oC 28 Lead CLCC J28.A

PKG.

DWG. #8MHz 10MHz 12MHz

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

82C54

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Absolute Maximum Ratings Thermal Information

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V

Input, Output or I/O Voltage. . . . . . . . . . . . GND-0.5V to V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

+0.5V

Operating Conditions

Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . .+4.5V to +5.5V

Operating Temperature Range

CX82C54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0

IX82C54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40

MD82C54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55

C to +70oC

C to +85oC

C to +125oC

Thermal Resistance (Typical)

CERDIP Package. . . . . . . . . . . . . . . . . 55 12

CLCC Package. . . . . . . . . . . . . . . . . . . 65 14

PDIP Package*. . . . . . . . . . . . . . . . . . . 55 N/A

PLCC Package. . . . . . . . . . . . . . . . . . . 60 N/A

Storage Temperature Range . . . . . . . . . . . . . . . . . -65

Maximum Junction Temperature Ceramic Package. . . . . . . .+175

Maximum Junction Temperature Plastic Package. . . . . . . . .+150

Maximum Lead Temperature Package (Soldering 10s). . . . .+300

(PLCC - Lead Tips Only)

*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2250 Gates

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

(oC/W) θJC (oC/W)

C to +150oC

o o o

C C C

DC Electrical Specifications V

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH Logical One Input Voltage 2.0 - V CX82C54, IX82C54

VIL Logical Zero Input Voltage - 0.8 V VOH Output HIGH Voltage 3.0 - V IOH = -2.5mA

VOL Output LOW Voltage - 0.4 V IOL = +2.5mA II Input Leakage Current -1 +1 µA VIN = GND or V

IO Output Leakage Current -10 +10 µA VOUT = GND or V

ICCSB Standby Power Supply Current - 10 µAV

ICCOP Operating Power Supply Current - 10 mA V

Capacitance T

SYMBOL PARAMETER TYP UNITS TEST CONDITIONS

CIN Input Capacitance 20 pF FREQ = 1MHz

COUT Output Capacitance 20 pF FREQ = 1MHz

CI/O I/O Capacitance 20 pF FREQ = 1MHz

NOTE:

1. Not tested, but characterized at initial design and at major process/design changes.

= +25oC; All Measurements Referenced to Device GND, Note 1

= +5.0V ± 10%, Includes all Temperature Ranges

2.2 - V MD82C54

-0.4 - V IOH = -100µA

DIP Pins 9,11,14-16,18-23

DIP Pins 1-8

= 5.5V, VIN = GND or VCC,

Outputs Open, Counters Programmed

= 5.5V,

CLK0 = CLK1 = CLK2 = 8MHz, VIN = GND or V Outputs Open

82C54

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AC Electrical SpecificationsV

SYMBOL PARAMETER

READ CYCLE

(1) TAR Address Stable Before RD (2) TSR CS (3) TRA Address Hold Time After RD 0-0-0-ns 1 (4) TRR RD (5) TRD Data Delay from RD (6) TAD Data Delay from Address - 210 - 185 - 185 ns 1 (7) TDF RD (8) TRV Command Recovery Time 200 - 165 - 165 - ns

WRITE CYCLE

(9) TAW Address Stable Before WR (10) TSW CS (11) TWA Address Hold Time After WR 0-0-0-ns (12) TWW WR (13) TDW Data Setup Time Before WR (14) TWD Data Hold Time After WR (15) TRV Command Recovery Time 200 - 165 - 165 - ns

CLOCK AND GATE

(16) TCLK Clock Period 125 DC 100 DC 80 DC ns 1 (17) TPWH High Pulse Width 60 - 30 - 30 - ns 1 (18) TPWL Low Pulse Width 60 - 40 - 30 - ns 1 (19) TR Clock Rise Time - 25 - 25 - 25 ns (20) TF Clock Fall Time - 25 - 25 - 25 ns (21) TGW Gate Width High 50 - 50 - 50 - ns 1 (22) TGL Gate Width Low 50 - 50 - 50 - ns 1 (23) TGS Gate Setup Time to CLK 50 - 40 - 40 - ns 1 (24) TGH Gate Hold Time After CLK 50 - 50 - 50 - ns 1 (25) TOD Output Delay from CLK - 150 - 100 - 100 ns 1 (26) TODG Output Delay from Gate - 120 - 100 - 100 ns 1 (27) TWO OUT Delay from Mode Write - 260 - 240 - 240 ns 1 (28) TWC CLK Delay for Loading 0 55 0 55 0 55 ns 1 (29) TWG Gate Delay for Sampling -5 40 -5 40 -5 40 ns 1 (30) TCL CLK Setup for Count Latch -40 40 -40 40 -40 40 ns 1

NOTE:

1. Not tested, but characterized at initial design and at major process/design changes.

Stable Before RD 0-0-0-ns 1

Pulse Width 150 - 95 - 95 - ns 1

to Data Floating 5 85 5 65 5 65 ns 2, Note 1

Stable Before WR 0-0-0-ns

Pulse Width 95 - 95 - 95 - ns

= +5.0V ± 10%, Includes all Temperature Ranges

82C54 82C54-10 82C54-12

30 - 25 - 25 - ns 1

- 120 - 85 - 85 ns 1

0-0-0-ns

140 - 95 - 95 - ns

25-0-0-ns

UNITS

TEST

CONDITIONSMIN MAX MIN MAX MIN MAX

Functional Diagram

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82C54

CLK 0 GATE 0 OUT 0

CLK 1 GATE 1 OUT 1

CLK 2 GATE 2 OUT 2

CONTROL

WORD

CONTROL

LOGIC

GATE n

CLK n

OUT n

INTERNAL BUS

STATUS

LATCH

STATUS

COUNTER INTERNAL BLOCK DIAGRAM

D7 - D

A A

0 1

BUFFER

READ/ WRITE LOGIC

CONTROL

WORD

INTERNAL BUS

DAT A/

BUS

COUNTER

Pin Description

SYMBOL

D7 - D0 1 - 8 I/O DATA: Bi-directional three-state data bus lines, connected to system data bus.

CLK 0 9 I CLOCK 0: Clock input of Counter 0.

OUT 0 10 O OUT 0: Output of Counter 0.

GATE 0 11 I GATE 0: Gate input of Counter 0.

GND 12 GROUND: Power supply connection.

OUT 1 13 O OUT 1: Output of Counter 1.

GATE 1 14 I GATE 1: Gate input of Counter 1.

CLK 1 15 I CLOCK 1: Clock input of Counter 1.

GATE 2 16 I GATE 2: Gate input of Counter 2.

OUT 2 17 O OUT 2: Output of Counter 2.

CLK 2 18 I CLOCK 2: Clock input of Counter 2.

A0, A1 19 - 20 I ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write

DIP PIN

NUMBER TYPE DEFINITION

operations. Normally connected to the system address bus.

A1 A0 SELECTS

0 0 Counter 0 0 1 Counter 1 1 0 Counter 2 1 1 Control Word Register

21 I CHIP SELECT: A low on this input enables the 82C54 to respond to RD and WR signals. RD and WR

are ignored otherwise. RD WR

22 I READ: This input is low during CPU read operations. 23 I WRITE: This input is low during CPU write operations. 24 - VCC: The +5V power supply pin. A 0.1µF capacitor between pins VCC and GND is recommended for

decoupling.

82C54

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Functional Description

General

The 82C54 is a programmable interval timer/counter designed for use with microcomputer systems. It is a general purpose, multi-timing element that can be treated as an array of I/O ports in the system software.

The 82C54 solves one of the most common problems in any microcomputer system, the generation of accurate time delays under software control. Instead of setting up timing loops in software, the programmer configures the 82C54 to match his requirements and programs one of the counters for the desired delay. After the desired delay, the 82C54 will interrupt the CPU. Software overhead is minimal and variable length delays can easily be accommodated.

Some of the other computer/timer functions common to microcomputers which can be implemented with the 82C54 are:

• Real time clock

• Event counter

• Digital one-shot

• Programmable rate generator

• Square wave generator

• Binary rate multiplier

• Complex waveform generator

• Complex motor controller

Data Bus Buffer

This three-state, bi-directional, 8-bit buffer is used to interface the 82C54 to the system bus (see Figure 1).

Read/Write Logic

The Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the 82C54. A1 and A0 select one of the three counters or the Control Word Register to be read from/written into. A “low” on the RD

input tells the 82C54 that the CPU is reading one of the counters. A “low” on the WR is writing either a Control Word or an initial count. Both RD WR

are qualified by CS; RD and WR are ignored unless the

82C54 has been selected by holding CS

input tells the 82C54 that the CPU

and

low .

Control Word Register

The Control Word Register (Figure 2) is selected by the Read/Write Logic when A1, A0 = 11. If the CPU then does a write operation to the 82C54, the data is stored in the Control Word Register and is interpreted as a Control Word used to define the Counter operation.

The Control Word Register can only be written to; status information is available with the Read-Back Command.

CLK 0 GAT E 0 OUT 0

CLK 1 GAT E 1 OUT 1

D7 - D

A A

DAT A/

0 1

BUS

BUFFER

READ/ WRITE LOGIC

INTERNAL BUS

COUNTER

D7 - D

FIGURE 1. DATA BUS BUFFER AND READ/WRITE LOGIC

BUFFER

CONTROL

WORD

FUNCTIONS

DAT A/

BUS

READ/ WRITE LOGIC

INTERNAL BUS

COUNTER

CLK 0 GATE 0 OUT 0

CLK 1 GATE 1 OUT 1

CLK 2 GATE 2 OUT 2

CONTROL

WORD

FIGURE 2. CONTROL WORD REGISTER AND COUNTER

FUNCTIONS

COUNTER

CLK 2 GAT E 2 OUT 2

Counter 0, Counter 1, Counter 2

These three functional blocks are identical in operation, so only a single Counter will be described. The internal block diagram of a signal counter is shown in Figure 3. The counters are fully independent. Each Counter may operate in a different Mode.

The Control Word Register is shown in the figure; it is not part of the Counter itself, but its contents determine how the Counter operates.

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The status register, shown in the figure, when latched, contains the current contents of the Control Word Register and status of the output and null count flag. (See detailed explanation of the Read-Back command.)

The actual counter is labeled CE (for Counting Element). It is a 16-bit presettable synchronous down counter.

INTERNAL BUS

CONTROL

WORD

CONTROL

LOGIC

GATE n

CLK n

FIGURE 3. COUNTER INTERNAL BLOCK DIAGRAM

OUT n

STATUS

LATCH

STATUS

OLM and OLL are two 8-bit latches. OL stands for “Output Latch”; the subscripts M and L for “Most significant byte” and “Least significant byte”, respectively. Both are normally referr ed to as one unit and called just OL. These latches normally “follow” the CE, but if a suitable Counter Latch Command is sent to the 82C54, the latches “latch” the present count until read by the CPU and then return to “following” the CE. One latch at a time is enabled by the counter’ s Control Logic to drive the internal bus. This is how the 16-bit Counter communicates over the 8-bit internal bus. Note that the CE itself cannot be read; whenever you read the count, it is the OL that is being read.

Similarly , there are two 8-bit registers called CRM and CRL (for “Count Register”). Both are normally referred to as one unit and called just CR. When a new count is written to the Counter, the count is stored in the CR and later transferred to the CE. The Control Logic allows one register at a time to be loaded from the internal bus. Both bytes are transf e rred to the CE simultaneously . CRM and CRL are cleared when the Counter is programmed for one byte counts (either most significant byte only or least significant byte only) the other byte will be zero. Note that the CE cannot be written into; whenever a count is written, it is written into the CR.

The Control Logic is also shown in the diagram. CLK n, GATE n, and OUT n are all connected to the outside world through the Control Logic.

82C54 System Interface

The 82C54 is treated by the system software as an array of peripheral I/O ports; three are counters and the fourth is a control register for MODE programming.

Basically, the select inputs A0, A1 connect to the A0, A1 address bus signals of the CPU. The CS

can be derived directly from the address bus using a linear select method or it can be connected to the output of a decoder.

Operational Description

General

After power-up, the state of the 82C54 is undefined. The Mode, count value, and output of all Counters are undefined.

How each Counter operates is determined when it is programmed. Each Counter must be programmed before it can be used. Unused counters need not be programmed.

Programming the 82C54

Counters are programmed by writing a Control Word and then an initial count.

All Control Words are written into the Control Word Register, which is selected when A1, A0 = 11. The Control Word specifies which Counter is being programmed.

By contrast, initial counts are written into the Counters, not the Control Word Register. The A1, A0 inputs are used to select the Counter to be written into. The format of the initial count is determined by the Control Word used.

ADDRESS BUS (16)

A1 A0

CONTROL BUS

I/OW

I/OR

DATA BUS (8)

COUNTER

OUT GATE CLK

FIGURE 4. COUNTER INTERNAL BLOCK DIAGRAM

D0 - D7

82C54

COUNTER

OUTGATECLK OUTGATECLK

Write Operations

The programming procedure for the 82C54 is very flexible. Only two conventions need to be remembered:

1. For Each Counter, the Control Word must be written before the initial count is written.

2. The initial count must f ollow the count format specified in the Control Word (least significant byte only, most significant byte only, or least significant byte and then most significant byte).

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