intersil 80C86 User Manual

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80C86

August 22, 2006

Features

• Compatible with NMOS 8086

• Completely Static CMOS Design

- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C86-2)

• Low Power Operation

- lCCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500μA Max

- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 10mA/MHz Typ

• 1MByte of Direct Memory Addressing Capability

• 24 Operand Addressing Modes

• Bit, Byte, Word and Block Move Operations

• 8-Bit and 16-Bit Signed/Unsigned Arithmetic

- Binary, or Decimal

- Multiply and Divide

• Wide Operating Temperature Range

- C80C86 . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

- M80C86 . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

Pinouts

80C86 (DIP)

TOP VIEW

MAX (MIN) V

GND AD14 AD13 AD12 AD11 AD10

AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

NMI

INTR

CLK

GND

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE

/S7 MN/MX RD RQ/GT0 RQ/GT1 LOCK S2 S1 S0 QS0 QS1 TEST READY RESET

(HOLD) (HLDA) (WR) (M/IO) (DT/R)) (DEN) (ALE) (INTA)

Description

The Intersil 80C86 high performance 16-bit CMOS CPU is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). Two modes of operation, minimum for small systems and maximum for larger applications such as multiprocessing, allow user configuration to achieve the highest performance level. Full TTL compatibility (with the exception of CLOCK) and industry standard operation allow use of existing NMOS 8086 hardware and software designs.

Ordering Information

MAX MODE

80C86

MIN MODE

80C86

AD10 AD10

AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1

AD0

AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1

AD0

CMOS 16-Bit Microprocessor

TEMP.

RANGE

PACKAGE

(°C) 8MHz

PDIP 0 to +70 CP80C86-2 CP80C86-2 E40.6

0 to +70 CP80C86-2Z CP80C86-2Z E40.6

CERDIP -55 to +125 MD80C86-2/B MD80C86-2/B F40.6

SMD# -55 to +125 8405202QA 8405202QA F40.6

80C86 (PLCC, CLCC)

TOP VIEW

6 3

7 8

9 10 11 12 13 14 15 16 17

AD13

INTR

AD14

CLK

GND

AD12

AD11 AD11

NMI

AD15

A16/S3

AD15

A16/S3

RESET

TEST

READY

A17/S4

INTA

A18/S5

40414243

2827262524232221201918

ALE

PART

MARKING

NC NC

A19/S6

BHE

/S7

MN/MX

HOLD

HLDA

M/IO

DT/R

DEN

MIN MODE

80C86

MAX MODE

80C86

PKG.

NO.

A19/S6

BHE

/S7

MN/MX

RD RQ/GT0 RQ/GT1

LOCK

S2 S1

NC NC

NMI

INTR

| Intersil (and design) is a trademark of Intersil Americas Inc.

141

CLK

GND

RESET

TEST

READY

QS1

QS0

FN2957.2

Functional Diagram

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80C86

TEST

INTR

NMI

/GT0, 1

HOLD

HLDA

EXECUTION UNIT

DATA POINTER

AND

INDEX REGS

(8 WORDS)

16-BIT ALU

FLAGS

CLK RESET READY

BUS INTERFACE UNIT

SEGMENT REGISTERS

INSTRUCTION POINTER

BUS INTERFACE UNIT

CONTROL AND TIMING

MN/MX

RELOCATION

AND

(5 WORDS)

6-BYTE

INSTRUCTION

QUEUE

GND V

LOCK

QS0, QS1

, S1, S0

/S7

BHE A19/S6 A16/S3

AD15-AD0

, RD, WR

INTA DT/R, DEN, ALE, M/IO

BUS

INTERFACE

UNIT

EXECUTION

UNIT

MEMORY INTERFACE

B-BUS

ES CS SS DS

AH BH CH

AL BL CL DL

SP BP

SI DI

C-BUS

INSTRUCTION

STREAM BYTE

QUEUE

A-BUS

ARITHMETIC/

LOGIC UNIT

FLAGS

EXECUTION UNIT

CONTROL SYSTEM

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Pin Description

The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).

SYMBOL

AD15-AD0 2-16, 39 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed memory/lO address (T1) and

NUMBER TYPE DESCRIPTION

data (T2, T3, TW, T4) bus. A0 is analogous to BHE D0. It is LOW during Ti when a byte is to be transferred on the lower portion of the bus in memory or I/O operations. Eight-bit oriented devices tied to the lower half would normally use A0 to condition chip select functions (See BHE ance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”.

). These lines are active HIGH and are held at high imped-

for the lower byte of the data bus, pins D7-

A19/S6 A18/S5 A17/S4 A16/S3

/S7 34 O BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to

BHE

35-38 O ADDRESS/STA TUS: During T1, these are the four most significant address lines for memory op-

erations. During I/O operations these lines are LOW. During memory and I/O operations, status information is available on these lines during T2, T3, TW, T4. S6 is always LOW. The status of the interrupt enable FLAG bit (S5) is updated at the beginning of each clock cycle. S4 and S3 are encoded as shown.

This information indicates which segment register is presently being used for data accessing. These lines are held at high impedance to the last valid logic level during local bus “hold ac-

knowledge” or “grant sequence”.

S4 S3 CHARACTERISTICS

0 0 Alternate Data 01Stack 1 0 Code or None 11Data

enable data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devices tied to the upper half of the bus would normally use BHE is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus. The S7 status information is available during T2, T3 and T4. The signal is active LOW, and is held at high impedance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”, it is LOW during T1 for the first interrupt acknowledge cycle.

BHE A0 CHARACTERISTICS

0 0 Whole Word 0 1 Upper Byte From/to Odd Address 1 0 Lower Byte From/to Even address 1 1 None

to condition chip select functions. BHE

READY 22 I READY: is the acknowledgment from the addressed memory or I/O device that will complete the

32 O READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, de-

pending on the state of the M/IO the 80C86 local bus. RD teed to remain HIGH in T2 until the 80C86 local bus has floated.

This line is held at a high impedance logic one state during “hold acknowledge” or “grand sequence”.

data transfer. The RDY signal from memory or I/O is synchronized by the 82C84A Clock Generator to form READY. This signal is active HIGH. The 80C86 READY input is not synchronized. Correct operation is not guaranteed if the Setup and Hold Times are not met.

or S2 pin. This signal is used to read devices which reside on

is active LOW during T2, T3 and TW of any read cycle, and is guaran-

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80C86

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Pin Description (Continued)

SYMBOL

INTR 18 I INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle

NUMBER TYPE DESCRIPTION

of each instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by software resetting the interrupt enable bit. lNTR is internally synchronized. This signal is active HIGH.

TEST

NMI 17 I NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A

RESET 21 I RESET: causes the processor to immediately terminate it s present activity . The signal must tran-

CLK 19 I CLOCK: provide s the basic timing for the processor and bus controller. It is asymmetric with a

VCC 40 VCC: +5V power supply pin. A 0.1μF capacitor between pins 20 and 40 is recommended for de-

GND 1, 20 GND: Ground. Note: both must be connected. A 0.1μF capacitor between pins 1 and 20 is rec-

MN/MX

23 I TEST : input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,

otherwise the processor waits in an “Idle” state. This input is synchronized internally during each clock cycle on the leading edge of CLK.

subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the end of the current instruction. This input is internally synchronized.

sition LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execution, as described in the Instruction Set description, when RESET returns LOW. RESET is internally synchronized.

33% duty cycle to provide optimized internal timing.

coupling.

ommended for decoupling.

33 I MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are

discussed in the following sections.

Minimum Mode System

The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = VCC). Only the pin functions which are unique to minimum mode are described; all other pin functions are as described below.

SYMBOL

M/IO

INTA

ALE 25 O ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the

NUMBER TYPE DESCRIPTION

28 O STA TUS LINE: logically equivalent to S2 in the maximum mode. It is used to distinguish a mem-

29 O WRITE: indicates that the processor is performing a write memory or write I/O cycle, depending

24 O INTERRUPT ACKNOWLEDGE: is used as a read strobe for interrupt acknowledge cycles. It is

ory access from an I/O access. M/lO valid until the final T4 of the cycle (M = HIGH, I/O = LOW). M/lO one during local bus “hold acknowledge”.

on the state of the M/IO LOW, and is held to high impedance logic one during local bus “hold acknowledge”.

active LOW during T2, T3 and TW of each interrupt acknowledge cycle. Note that INTA floated.

82C82/82C83 address latch. It is a HIGH pulse active during clock LOW of T1 of any bus cycle. Note that ALE is never floated.

signal. WR is active for T2, T3 and TW of any write cycle. It is active

becomes valid in the T4 preceding a bus cycle and remains

144

is held to a high impedance logic

is never

80C86

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Minimum Mode System (Continued)

The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX minimum mode are described; all other pin functions are as described below.

= VCC). Only the pin functions which are unique to

SYMBOL

DT/R 27 O DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use a data bus

DEN

HOLD HLDA

NUMBER TYPE DESCRIPTION

transceiver. It is used to control the direction of data flow through the transceiver. Logically,

is equivalent to S1 in maximum mode, and its timing is the same as for M/IO (T = HIGH,

DT/R R = LOW). DT/R

26 O DATA ENABLE: provided as an output enable for a bus transceiver in a minimum system which

uses the transceiver. DEN cles. For a read or INTA a write cycle it is active from the beginning of T2 until the middle of T4. DEN impedance logic one during local bus “hold acknowledge”.

31, 30 I

HOLD: indicates that another master is requesting a local bus “hold”. To be an acknowledged, HOLD must be active HIGH. The processor receiving the “hold” will issue a “hold acknowledge” (HLDA) in the middle of a T4 or TI clock cycle. Simultaneously with the issuance of HLDA, the processor will float the local bus and control lines. After HOLD is detected as being LOW, the processor will lower HLDA, and when the processor needs to run another cycle, it will again drive the local bus and control lines.

HOLD is not an asynchronous input. External synchronization should be provided if the system cannot otherwise guarantee the setup time.

is held to a high impedance logic one during local bus “hold acknowledge”.

is active LOW during each memory and I/O access and for INTA cy-

cycle it is active from the middle of T2 u ntil the middle of T4, while for

is held to a high

Maximum Mode System

The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are unique to maximum mode are described below.

SYMBOL

S0 S1 S2

NUMBER TYPE DESCRIPTION

26 27 28

O O O

STATUS: is active during T4, T1 and T2 and is returned to the passive state (1, 1, 1) during T3 or during TW when READY is HIGH. This status is used by the 82C88 Bus Controller to generate all memory and I/O access control signals. Any change by S2 indicate the beginning of a bus cycle, and the return to the passive state in T3 or TW is used to indicate the end of a bus cycle.

These signals are held at a high impedance logic one state during “grant sequence”.

S2 S1 S0 CHARACTERISTICS

0 0 0 Interrupt Acknowledge 0 0 1 Read I/O Port 0 1 0 Write I/O Port 011Halt 1 0 0 Code Access 1 0 1 Read Memory 1 1 0 Write Memory 111Passive

, S1 or S0 during T4 is used to

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80C86

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Maximum Mode System (Continued)

The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX unique to maximum mode are described below.

- GND). Only the pin functions which are

SYMBOL

RQ/GT0 RQ/GT1

NUMBER TYPE DESCRIPTION

31, 30 I/O REQUEST/GRANT: pins are used by other local bus masters to force the processor to release

the local bus at the end of the processor’s current bus cycle. Each pin is bidirectional with

/GTO having higher priority than RQ/GT1. RQ/GT has an internal pull-up bus hold device so

RQ it may be left unconnected. The request/grant sequence is as follows (see RQ Timing)

1. A pulse of 1 CLK wide from another local bus master indicates a local bus request (“hold”) to the 80C86 (pulse 1).

2. During a T4 or TI clock cycle, a pulse 1 CLK wide from the 80C86 to the requesting master (pulse 2) indicates that the 80C86 has allowed the local bus to float and that it will enter the “grant sequence” state at the next CLK. The CPU’s bus interface unit is disconnected logically from the local bus during “grant sequence”.

3. A pulse 1 CLK wide from the requesting master indicates to the 80C86 (pulse 3) that the “hold” request is about to end and that the 80C86 can reclaim the local bus at the next CLK. The CPU then enters T4 (or TI if no bus cycles pending). Each Master-Master exchange of the local bus is a sequence of 3 pulses. There must be one idle CLK cycle after each bus exchange. Pulses are active low. If the request is made while the CPU is performing a memory cycle, it will release the local bus during T4 of the cycle when all the following conditions are met:

1. Request occurs on or before T2.

2. Current cycle is not the low byte of a word (on an odd address).

3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.

4. A locked instruction is not currently executing. If the local bus is idle when the request is made the two possible events will follow:

1. Local bus will be released during the next cycle.

2. A memory cycle will st art within three clocks. Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied.

/GT Sequence

LOCK

QS1, QSO 24, 25 O QUEUE STATUS: The queue status is valid during the CLK cycle after which the queue opera-

29 O LOCK: output indicates that other system bus masters are not to gain control of the system bus

while LOCK remains active until the completion of the next instruction. This signal is active LOW, and is held at a high impedance logic one state during “grant sequence”. In MAX mode, LOCK ically generated during T2 of the first INTA cycle.

tion is performed. QS1 and QS0 provide status to allow external tracking of the internal 80C86 instruction queue. Note that QS1, QS0 never become high impedance.

is active LOW. The LOCK signal is activated by the “LOCK” prefix instruction and

is automat-

cycle and removed during T2 of the second INTA

QSI QSO

0 0 No Operation 0 1 First byte of op code from queue 1 0 Empty the queue 1 1 Subsequent byte from queue

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80C86

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Functional Description

Static Operation

All 80C86 circuitry is of static design. Internal registers, counters and latches are static and require no refresh as with dynamic circuit design. This eliminates the minimum operating frequency restriction placed on other microprocessors. The CMOS 80C86 can operate from DC to the specified upper frequency limit. The processor clock may be stopped in either state (HIGH/LOW) and held there indefinitely. This type of operation is especially useful for system debug or power critical applications.

The 80C86 can be single stepped using only the CPU clock. This state can be maintained as long as is necessary. Single step clock operation allows simple interface circuitry to provide critical information for bringing up your system.

Static design also allows very low frequency operation (down to DC). In a power critical situation, this can provide extremely low power operation since 80C86 power dissipation is directly related to operating frequency. As the system frequency is reduced, so is the operating power until, ultimately, at a DC input frequency, the 80C86 power requirement is the standby current, (500μA maximum).

Internal Architecture

The internal functions of the 80C86 processor are partitioned logically into two processing units. The first is the Bus Interface Unit (BlU) and the second is the Execution Unit (EU) as shown in the CPU functional diagram.

These units can interact directly, but for the most part perform as separate asynchronous operational processors. The bus interface unit provides the functions related to instruction fetching and queuing, operand fetch and store, and address relocation. This unit also provides the basic bus control. The overlap of instruction pre-fetching provided by this unit serves to increase processor performance through improved bus bandwidth utilization. Up to 6 bytes of the instruction stream can be queued while waiting for decoding and execution.

The instruction stream queuing mechanism allows the BIU to keep the memory utilized very efficiently. Whenever there is space for at least 2 bytes in the queue, the BlU will attempt a word fetch memory cycle. This greatly reduces “dead-time” on the memory bus. The queue acts as a First-In-First-Out (FIFO) buffer, from which the EU extracts instruction bytes as required. If the queue is empty (following a branch instruction, for example), the first byte into the queue immediately becomes available to the EU.

The execution unit receives pre-fetched instructions from the BlU queue and provides un-relocated operand addresses to the BlU. Memory operands are passed through the BIU for processing by the EU, which passes results to the BIU for storage.

Memory Organization

The processor provides a 20-bit address to memory, which locates the byte being referenced. The memory is organized as a linear array of up to 1 million bytes, addressed as 00000(H) to FFFFF(H). The memory is logically divided i nto

code, data, extra and stack segments of up to 64K bytes each, with each segment falling on 16-byte boundaries. (See Figure 1).

FFFFFH

64K-BIT

+ OFFSET

SEGMENT

CS SS DS ES

FIGURE 1. 80C86 MEMORY ORGANIZATION

TABLE 1.

TYPE OF

MEMORY

REFERENCE

Instruction Fetch CS None IP Stack Operation SS None SP Variable (except

following) String Source DS CS, ES, SS SI String Destination ES None DI BP Used As Base

DEFAULT SEGMENT

BASE

DS CS, ES, SS Effective

SS CS, DS, ES Effective

ALTERNATE

SEGMENT

CODE SEGMENT

XXXXOH

STACK SEGMENT

DATA SEGMENT

EXTRA SEGMENT

00000H

BASE OFFSET

Address

All memory references are made relative to base addresses contained in high speed segment registers. The segment types were chosen based on the addressing needs of programs. The segment register to be selected is automatica lly chosen according to the specific rules of Table 1. All information in one segment type share the same logical attributes (e.g. code or data). By structuring memory into re-locatable areas of similar characteristics and by automatically selecting segment registers, programs are shorter, faster and more structured. (See Table 1).

Word (16-bit) operands can be located on even or odd address boundaries and are thus, not constrained to even boundaries as is the case in many 16-bit computers. For address and data operands, the least significant byte of the word is stored in the lower valued address location and the most significant byte in the next higher address location. The BIU automatically performs the

proper number of memory

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accesses; one, if the word operand is on an even byte boundary and two, if it is on an odd byte boundary. Except for the performance penalty, this double access is transparent to the software. The performance penalty does not occur for instruction fetches; only word operands.

Physically, the memory is organized as a high bank (D15D8) and a low bank (D7-D0) of 512K bytes addressed in parallel by the processor’s address lines.

Byte data with even addresses is transferred on the D7-D0 bus lines, while odd addressed byte data (A0 HIGH) is transferred on the D15-D8 bus lines. The processor provides two enable signals, BHE and A from or writing into either an odd byte location, even byte location, or both. The instruction stream is fetched from memory as words and is addressed internally by the processor at the byte level as necessary.

In referencing word data, the BlU requires o ne or two memory cycles depending on whether the starting byte of the word is on an even or odd address, respectively. Consequently, in re ferencing word operands performance can be optimized by locating data on even address boundaries. This is an especially useful technique for using the stack, since odd address references to the stack may adversely affect the context switching time for interrupt processing or task multiplexing.

Certain locations in memory are reserved for specific CPU operations (See Figure 2). Locations from address FFFF0H through FFFFFH are reserved for operations including a jump to the initial program loading routine. Following RESET, the CPU will always begin execution at location FFFF0H where the jump must be located. Locations 00000H through 003FFH are reserved for interrupt operations. Each of the 256 possible interrupt service routines is accessed thru its own pair of 16bit pointers (segment address pointer and offset address pointer). The first pointer, used as the offset address, is loaded into the lP and the second pointer, which designates the base address is loaded into the CS. At this point program control is transferred to the interrupt routine. The pointer elements are assumed to have been stored at the respective places in reserved memory prior to occurrence of interrupts.

Minimum and Maximum Operation Modes

The requirements for supporting minimum and maximum 80C86 systems are sufficiently different that they cannot be met efficiently using 40 uniquely defined pins. Consequently, the 80C86 is equipped with a strap pin (MN/MX defines the system configuration. The definition of a certain subset of the pins changes, dependent on the condition of the strap pin. When the MN/MX 80C86 defines pins 24 through 31 and 34 in maximum mode. When the MN/MX ates bus control signals itself on pins 24 through 31 and 34.

The minimum mode 80C86 can be used with either a multiplexed or demultiplexed bus. This architecture provides the 80C86 processing power in a highly integrated form.

The demultiplexed mode requires two 82C82 latches (for 64K addressability) or three 82C82 latches (for a full megabyte of addressing). An 82C86 or 82C87 transceiver can also be used if data bus buffering is required. (See Figure 6A.) The

pin is strapped to VCC, the 80C86 gener-

, to selectively allow reading

) which

pin is strapped to GND, the

80C86 provides DEN ALE to latch the addresses. This configuration of the minimum mode provides the standard demultiplexed bus structure with heavy bus buffering and relaxed bus timing requirement s.

The maximum mode employs the 82C88 bus controller (See Figure 6B). The 82C88 decodes status lines S0 and provides the system with all bus control signals.

Moving the bus control to the 82C88 provides better source and sink current capability to the control lines, and frees the 80C86 pins for extended large system features. Hardware lock, queue status, and two request/grant interfaces are provided by the 80C86 in maximum mode. Thes e feat ures al low coprocessors in local bus and remote bus configurations.

Bus Operation

The 80C86 has a combined address and data bus commonly referred to as a time multiplexed bus. This technique provides the most efficient use of pins on the processor while permitting the use of a standard 40 lead package. This “local bus” can be buffered directly and used throughout the system with address latching provided on memory and I/O modules. In addition, the bus can also be demultiplexed at the processor with a single set of 82C82 address latches if a standard non-multiplexed bus is desired for the system.

Each processor bus cycle consists of at least four CLK cycles. These are referred to as T1, T2, T3 and T4 (see Figure 3). The address is emitted from the proce ssor during T1 and data transfer occurs on the bus during T3 and T4. T2 is used primarily for changing the direction of the bus during read operations. In the event that a “NOT READY” indication is given by the addressed device, “Wait” states (TW) are inserted between T3 and T4 . Each inserted wait state is the same duration as a CLK cycle. Periods can occur between 80C86 driven bus cycles. These are referred to as idle” states (T cycles for internal housekeeping and processing.

During T1 of any bus cycle, the ALE (Address Latch Enable) signal is emitted (by either the processor or the 82C88 bus controller, depending on the MN/MX edge of this pulse, a valid address and certain status information for the cycle may be latched.

Status bits S0 maximum mode, to identify the type of bus transaction according to Table 2.

) or inactive CLK cycles. The processor uses these

0 0 0 Interrupt 0 0 1 Read I/O 010Write I/O 011Halt 1 0 0 Instruction Fetch 1 0 1 Read Data from Memory 1 1 0 Write Data to Memory 1 1 1 Passive (No Bus Cycle)

S1 S0 CHARACTERISTICS

and DT/R to control the transceiver, and

, S1 and S2,

strap). At the trailing

, S1 and S2 are used by the bus controller, in

TABLE 2.

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Status bits S3 through S7 are time multiplexed with high order address bits and the BHE signal, and are therefore valid during T2 through T4. S3 and S4 indicate which segment register (see Instruction Set Description) was used for this bus cycle in forming the address, according to Table 3.

S5 is a reflection of the PSW interrupt enable bit. S3 is always zero and S7 is a spare status bit.

TABLE 3.

S4 S3 CHARACTERISTICS

0 0 Alternate Data (Extra Segment) 01Stack 1 0 Code or None 11Data

FFFFFH

FFFF0H

3FFH 3FCH

RESET BOOTSTRAP

PROGRAM JUMP

TYPE 225 POINTER

(AVAILABLE)

I/O Addressing

In the 80C86, I/O operations can address up to a maximum of 64K I/O byte registers or 32K I/O word registers. The I/O address appears in the same format as the memory address on bus lines A15-A0. The address lines A19-A16 are zero in I/O operations. The variable I/O instructions which use register DX as a pointer have full address capability while the direct I/O instructions directly address one or two of the 256 I/O byte locations in page 0 of the I/O address space.

I/O ports are addressed in the same manner as memory locations. Even addressed bytes are transferred on the D7-D0 bus lines and odd addressed bytes on D15-D8. Care must be taken to ensure that each register within an 8-bit peripheral located on the lower portion of the bus be addressed as even.

AVAILABLE

INTERRUPT

POINTERS

(224)

RESERVED

INTERRUPT

POINTERS

(27)

DEDICATED INTERRUPT

POINTERS

(5)

TYPE 33 POINTER

084H

080H

07FH

014H

010H

00CH

008H

004H

000H

(AVAILABLE)

TYPE 32 POINTER

(AVAILABLE)

TYPE 31 POINTER

(AVAILABLE)

TYPE 5 POINTER

(RESERVED)

TYPE 4 POINTER

OVERFLOW

TYPE 3 POINTER

1 BYTE INT INSTRUCTION

TYPE 2 POINTER NON MASKABLE

TYPE 1 POINTER

SINGLE STEP

TYPE 0 POINTER

DIVIDE ERROR

CS BASE ADDRESS

IP OFFSET

16 BITS

FIGURE 2. RESERVED MEMORY LOCATIONS

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CLK

ALE

2-S0

ADDR/

STATUS

ADDR/DATA

(4 + NWAIT) = TCY

T1 T2 T3 T4TWAIT T1 T2 T3 T4TWAIT

BHE,

A19-A16

A15-A0

BUS RESERVED

FOR DATA IN

S7-S3

D15-D0

VALID

A19-A16

A15-A0 DATA OUT (D15-D0)

(4 + NWAIT) = TCY

GOES INACTIVE IN THE STATE

JUST PRIOR TO T

BHE

S7-S3

, INTA

READY

READYREADY

WAIT WAIT

DT/R

DEN

MEMORY ACCESS TIME

FIGURE 3. BASIC SYSTEM TIMING

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External Interface

Processor RESET and Initialization

Processor initialization or start up is accomplished with activation (HIGH) of the RESET pin. The 80 C86 RESET is require d to be HIGH for greater than 4 CLK cycles. The 80C86 will terminate operations on the high-going edge of RESET and will remain dormant as long as RESET is HIGH. The low-going transition of RESET triggers an internal reset sequence for approximately 7 clock cycles. After this interval, the 80C86 operates normally beginning with the instruction in absolute location FFFF0H. (See Figure 2). The RESET input is internally synchronized to the processor clock. At initialization, the HIGHto-LOW transition of RESET must occur no sooner than 50 μs (or 4 CLK cycles, whichever is greater) after power-up, to allow complete initialization of the 80C86.

NMl will not be recognized prior to the second CLK cycle following the end of RESET. If NMl is asserted sooner than nine clock cycles after the end of RESET, the processor may execute one instruction before responding to the interrupt.

Bus Hold Circuitry

To avoid high current conditions caused by floating inputs to CMOS devices and to eliminate need for pull-up/down resistors, “bus-hold” circuitry has been used on the 80C86 pins 2-16, 2632 and 34-39. (See Figure 4A and Figure 4B). These circuits will maintain the last valid logic state if no driving source is present (i.e., an unconnected pin or a driving sourc e which goes to a high impedance state). To overdrive the “bus hold” circuits, an external driver must be capable of supplying approximately 400μA minimum sink or source current at valid input voltage levels. Since this “bus hold” circuitry is active and not a “res istive” type element, the associated power supply current is negligible and power dissipation is significantly reduced when compared to the use of passive pu ll-up res isto rs.

BOND

PAD

EXTERNAL

OUTPUT

DRIVER

Interrupt Operations

Interrupt operations fall into two classes: software or hard- ware initiated. The software initiated interrupts and software aspects of hardware interrupts are specified in the Instruction Set Description. Hardware interrupts can be classified as non-maskable or maskable.

Interrupts result in a transfer of control to a new program location. A 256-element table containing address pointers to the interrupt service program locations resides in absolute locations 0 through 3FFH, which are reserved for this purpose. Each element in the table is 4 bytes in size and corresponds to an interrupt “type”. An interrupting device supplies an 8-bit type number during the interrupt acknowledge sequence, which is used to “vector” through the appropriate element to the new interrupt service program location. All flags and both the Code Segment and Instruction Pointer register are saved as part of the lNTA

sequence. These are restored upon exe-

cution of an Interrupt Return (IRET) instruction.

Non-Maskable Interrupt (NMI)

The processor provides a single non-maskable interrupt pin (NMI) which has higher priority than the maskable interrupt request pin (INTR). A typical use would be to activate a power failure routine. The NMI is edge-triggered on a LOWto-HIGH transition. The activation of this pin causes a type 2 interrupt.

NMl is required to have a duration in the HIGH state of greater than two CLK cycles, but is not required to be synchronized to the clock. Any positive transition of NMI is latched on-chip and will be serviced at the end of the current instruction or between whole moves of a block-type instruction. Worst case response to NMI would be for multiply, divide, and variable shift instructions. There is no specification on the occurrence of the low-going edge; it may occur before, during or after the servicing of NMI. Another positive edge triggers another response if it occurs after the start of the NMI procedure. The signal must be free of logical spikes in general and be free of bounces on the low-goin g edge to avoid triggering extraneous responses.

INPUT

BUFFER

INPUT

PROTECTION

CIRCUITRY

Maskable Interrupt (INTR)

The 80C86 provides a single interrupt request input (lNTR) which can be masked internally by software with the rese tting of the interrupt enable flag (IF) status bit. The interrupt

FIGURE 4A. BUS HOLD CIRCUITRY PIN 2-16, 34-39

request signal is level triggered. It is internally syn chronized during each clock cycle on the high-going edge of CLK. To be responded to, lNTR must be present (HIGH) during the clock period preceding the end of the current instruction or the end of a whole move for a block type instruction. lNTR may be removed anytime after the falling edge of the first

signal. During the interrupt response sequence further

INTA interrupts are disabled. The enable bit is reset as part of the response to any interrupt (lNTR, NMI, software interrupt or single-step), although the FLAGS register which is automatically pushed onto the stack reflects the state of the processor prior to the interrupt. Until the old FLAGS register is restored, the enable bit will be zero unless specifically set by

OUTPUT

DRIVER

BUFFER

INPUT

PROTECTION

CIRCUITRY

FIGURE 4B. BUS HOLD CIRCUITRY PIN 26-32

BOND

PAD

EXTERNAL PIN

an instruction.

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80C86

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During the response sequence (Figure 5) the processor executes two successive (back-to-back) interrupt acknowledge cycles. The 80C86 emits the LOCK

signal (Max mode only) from T2 of the first bus cycle until T2 of the second. A local bus “hold” request will not be honored until the end of the second bus cycle. In the second bus cycle, a byte is supplied to the 80C86 by the 82C59A Interrupt Controller, which identifies the source (type) of the interrupt. This byte is multiplied by four and used as a pointer into the interrupt vector lookup table. An INTR signal left HIGH will be continually responded to within the limitations of the enable bit and sample period. The INTERRUPT RETURN instruction includes a FLAGS pop which returns the status of the original interrupt enabl e bit when it restores the FLAGS.

T1 T2 T3 T4 TI

ALE

LOCK

INTA

AD0-

AD15

FLOAT

FIGURE 5. INTERRUPT ACKNOWLEDGE SEQUENCE

TYPE

VECTOR

Halt

When a software “HALT” instruction is executed the processor indicates that it is entering the “HALT” state in one of two ways depending upon which mode is strapped. In minimum mode, the processor issues one ALE with no qualifying bus control signals. In maximum mode the processor issues appropriate HALT status on S2

, S1, S0 and the 82C88 bus controller issues one ALE. The 80C86 will not leave the “HALT” state when a local bus “hold” is entered while in “HALT”. In this case, the processor reissues the HALT indicator at the end of the local bus hold. An NMI or interrupt request (when interrupts enabled) or RESET will force the 80C86 out of the “HALT” state.

Read/Modify/Write (Semaphore)

Operations Via Lock

The LOCK status information is provided by the processor when consecutive bus cycles are required during the execution of an instruction. This gives the processor the capability of performing read/modify/write operations on memory (via the Exchange Register With Memory instruction, for example) without another system bus master receiving intervening memory cycles. This is useful in multiprocessor system configurations to accomplish “test and set lock” operations. The LOCK signal is activated (forced LOW) in the clock cycle following decoding of the software “LOCK” prefix instruction. It is deactivated at the end of the last bus cycle of the instruction following the “LOCK” prefix instruction. While LOCK is active a request on a RQ/GT pin will be recorded and then honored at the end of the LOCK.

External Synchronization Via TEST

As an alternative to interrupts, the 80C86 provides a single software-testable input pin (TEST

). This input is utilized by executing a WAIT instruction. The single WAIT instruction is repeatedly executed until the TEST

input goes active (LOW). The execution of WAIT does not consume bus cycles once the queue is full.

If a local bus request occurs during WAIT execution, the 80C86 three-states all output drivers while inputs and I/O pins are held at valid logic levels by internal bus-hold circuits. If interrupts are enabled, the 80C86 will recognize interrupts and process them when it regains control of the bus. The WAIT instruction is then refetched, and re-executed.

TABLE 4. 80C86 REGISTER

AH AL

AX BX

BH CH

CX DX

FLAGSHFLAGS

SP BP

CS DS SS ES

ACCUMULATOR BASE

BL CL

COUNT DATA

STACK POINTER BASE POINTER

SOURCE INDEX DESTINATION INDEX

INSTRUCTION POINTER

STATUS FLAG

CODE SEGMENT DATA SEGMENT

STACK SEGMENT EXTRA SEGMENT

Basic System Timing

Typical system configurations for the processor operating in minimum mode and in maximum mode are shown in Figures 6A and 6B, respectively. In minimum mode, the MN/MX

pin is strapped to VCC and the processor emits bus control signals (e.g. RD MN/MX

, WR, etc.) directly. In maximum mode, the

pin is strapped to GND and the processor emits coded status information which the 82C88 bus controller uses to generate MULTIBUS compatible bus control signals. Figure 3 shows the signal timing relationships.

System Timing - Minimum System

The read cycle begins in T1 with the assertion of the Address Latch Enable (ALE) signal. The trailing (low-going) edge of this signal is used to latch the address information, which is valid on the address/data bus (AD0-AD15) at this time, into the 82C82/82C83 latch. The BHE

and A0 signals address the low, high or both bytes. From T1 to T4 the M/lO signal indicates a memory or I/O operation. At T2, the address is removed from the address/data bus and the bus

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