International Rrectifier IRS2336D User Manual

May 9, 2008
IRS2336(D)
Features
Drives up to six IGBT/MOSFET power devices
Gate drive supplies up to 20 V per channel
Integrated bootstrap functionality (IRS2336(4)D)
Over-current protection
Over-temperature shutdown input
Advanced input filter
Integrated deadtime protection
Shoot-through (cross-conduction) protection
Undervoltage lockout for V
Enable/disable input and fault reporting
Adjustable fault clear timing
Separate logic and power grounds
3.3 V input logic compatible
Tolerant to negative transient voltage
Designed for use with bootstrap power supplies
Matched propagation delays for all channels
-40°C to 125°C operating range
RoHS compliant
Lead-Free
CC
& V
BS
Typical Applications
Appliance motor drives
Servo drives
Micro inverter drives
General purpose three phase inverters
Typical Connection Diagram
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HIGH VOLTAGE 3 PHASE GATE DRIVER IC
Product Summary
Topology 3 Phase
V
V
Io+ & I
tON & t
Deadtime (typical) 275 ns
600 V
OFFSET
IRS2336(D) 10 V – 20 V
IRS23364D 11.5 V – 20 V
(typical) 200 mA & 350 mA
o-
(typical) 530 ns & 530 ns
OFF
OUT
Package Options
28-Lead PDIP 28-Lead SOIC Wide Body
48-Lead MLPQ7X7 44-Lead PLCC (without 14 leads) (without 12 leads)
IRS23364D
IRS2336x(D) Family
Table of Contents Page
Description 3
Feature Comparison 3
Simplified Block Diagram 4
Typical Application Diagram 4
Qualification Information 5
Absolute Maximum Ratings 6
Recommended Operating Conditions 7
Static Electrical Characteristics 8-9
Dynamic Electrical Characteristics 10
Functional Block Diagram 11-12
Input/Output Pin Equivalent Circuit Diagram 13-14
Lead Definitions 15-16
Lead Assignments 17
Application Information and Additional Details 18-34
Parameter Temperature Trends 35-38
Package Details 39-42
Tape and Reel Details 43-45
Part Marking Information 46
Ordering Information 47
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2
IRS2336x(D) Family
Description
The IRS2336xD are high voltage, high speed, power MOSFET and IGBT gate drivers with three high-side and three low-side referenced output channels for 3-phase applications. This IC is designed to be used with low-cost bootstrap power supplies; the bootstrap diode functionality has been integrated into this device to reduce the component count and the PCB size. Proprietary HVIC and latch immune CMOS technologies have been implemented in a rugged monolithic structure. The floating logic input is compatible with standard CMOS or LSTTL outputs (down to 3.3 V logic). A current trip function which terminates all six outputs can be derived from an external current sense resistor. Enable functionality is available to terminate all six outputs simultaneously. An open-drain FAULT signal is provided to indicate that a fault (e.g., over-current, over-temperature, or undervoltage shutdown event) has occurred. Fault conditions are cleared automatically after a delay programmed externally via an RC network connected to the RCIN input. The output drivers feature a high-pulse current buffer stage designed for minimum driver cross-conduction. Shoot-through protection circuitry and a minimum deadtime circuitry have been integrated into this IC. Propagation delays are matched to simplify the HVIC’s use in high frequency applications. The floating channels can be used to drive N-channel power MOSFETs or IGBTs in the high-side configuration, which operate up to 600 V.
Feature Comparison: IRS2336xD Family
Part Number Input Logic UVLO V
IRS2336(D) HIN/N, LIN/N 8.9 V/ 8.2 V 0.46 V 530 ns, 530 ns 10 V – 20 V
IRS23364D HIN, LIN 11.1 V/ 10.9 V 0.46 V 530 ns, 530 ns 11.5 V – 20 V
t
IT,TH
ON
, t
V
OFF
OUT
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3
Simplified Block Diagram
IRS2336x(D) Family
Typical Application Diagram
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4
Qualification Information†
Qualification Level
Moisture Sensitivity Level
IRS2336x(D) Family
Industrial††
Comments: This family of ICs has passed JEDEC’s Industrial qualification. IR’s Consumer qualification level is granted by extension of the higher Industrial level.
SOIC28W
MLPQ7X7
PLCC44
(per IPC/JEDEC J-STD-020)
(per IPC/JEDEC J-STD-020)
MSL3
MSL3
†††
, 260°C
†††
, 245°C
Not applicable
ESD
IC Latch-Up Test
RoHS Compliant
PDIP28
Human Body Model
Machine Model
Charged Device Model
††††
(per JEDEC standard JESD22-A114)
(per EIA/JEDEC standard EIA/JESD22-A115)
(per JEDEC standard JESD22-C101)
(non-surface mount package style)
Class 2
Class B
Class IV
Class I, Level A
(per JESD78)
Yes
† ††
††† Higher MSL ratings may be available for the specific package types listed here. Please contact your
†††† Charged Device Model classification is based on SOIC28W package.
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information.
International Rectifier sales representative for further information.
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5
IRS2336x(D) Family
V
ns
W
ºC
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to V
unless otherwise stated in the table. The thermal resistance
SS
and power dissipation ratings are measured under board mounted and still air conditions. Voltage clamps are included between V
& COM (25 V), VCC & VSS (20 V), and VB & VS (20 V).
CC
Symbol Definition Min Max Units
V
CC
V
IN
V
RCIN
V
B
VS High-side floating well supply return voltage
Low side supply voltage -0.3
Logic input voltage (HIN, LIN, ITRIP, EN)
IRS2336(D) VSS-0.3 VSS+5.2 IRS23364D V
-0.3 VCC+0.3
SS
RCIN input voltage VSS-0.3 VCC+0.3
High-side floating well supply voltage -0.3
-20†
V
B
620
V
20
+0.3
B
VHO Floating gate drive output voltage VS-0.3 VB+0.3 VLO Low-side output voltage COM-0.3 VCC+0.3
V
Fault output voltage VSS-0.3 VCC+0.3
FLT
COM Power ground VCC-25 VCC+0.3 dVS/dt Allowable VS offset supply transient relative to VSS PW
High-side input pulse width 500
HIN
28-Lead PDIP 28-Lead
PD
Package power dissipation @ T
+25ºC
A
SOICW 44-Lead PLCC 48-Lead MLPQ7X7 28-Lead PDIP 28-Lead
Rth
Thermal resistance, junction to ambient
JA
SOICW 44-Lead PLCC 48-Lead MLPQ7X7
T
J
T
S
T
L
Junction temperature Storage temperature -55 150 Lead temperature (soldering, 10 seconds)
— — 1.6 — — 2.0 — — 78 — — —
50 V/ns
1.5
2.0
83
63
ºC/W
63
150
300
† All supplies are tested at 25 V. An internal 20 V clamp exists for each supply.
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6
IRS2336x(D) Family
Recommended Operating Conditions
For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to V (V
-COM) = (VB-VS) = 15 V.
CC
Symbol Definition Min Max Units
V
CC
V
IN
V
B
VS
VS(t)
Low-side supply voltage
HIN, LIN, & EN input voltage
High-side floating well supply voltage
High-side floating well supply offset voltage Transient high-side floating supply voltage
VHO Floating gate drive output voltage Vs V
VLO Low-side output voltage COM VCC
COM Power ground -5 5
V
FAULT output voltage VSS V
FLT
V
RCIN input voltage VSS V
RCIN
V
ITRIP input voltage VSS V
ITRIP
T
A
Ambient temperature -40 125 ºC
Logic operation for
V
of –8 V to 600 V. Logic state held for
S
DT97-3 for more details.
†† Operational for transient negative V
the Application Information section of this datasheet for more details.
unless otherwise stated in the table. The offset rating is tested with supplies of
SS
IRS2336(D) 10 20 IRS23364D 11.5 20 IRS2336(D) VSS+5 IRS23364D
VSS
V
CC
IRS2336(D) VS+10 VS+20 IRS23364D V
††
V
of –8 V to –VBS. Please refer to Design Tip
S
of VSS - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to
S
+11.5 VS+20
S
COM-8 600
-50 600
B
CC
CC
+5
SS
V
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7
IRS2336x(D) Family
V
BSUV
Static Electrical Characteristics
(VCC-COM) = (VB-VS) = 15 V. TA = 25oC unless otherwise specified. The VIN and IIN parameters are referenced to V
and are applicable to all six channels. The VO and IO parameters are referenced to respective VS and COM and
SS
are applicable to the respective output leads HO or LO. parameters are referenced to V
.
S
Symbol Definition Min Typ Max Units Test Conditions
supply undervoltage positive
V
V
CCUV
V
CCUV
V
CCUVHY
V
BSUV+
V
BSUV-
V
BSUVHY
ILK
I
QBS
I
QCC
CC
+
going threshold
supply undervoltage negative
V
CC
-
going threshold
supply undervoltage
V
CC
hysteresis V
BS
going threshold V
BS
going threshold
supply undervoltage
V
BS
hysteresis
supply undervoltage positive
supply undervoltage negative
High-side floating well offset supply leakage Quiescent V
Quiescent V
supply current
BS
supply current
CC
VOH High level output voltage drop, V
IRS2336(D) 8 8.9 9.8 IRS23364D 10.4 11.1 11.6 IRS2336(D) 7.4 8.2 9 IRS23364D 10.2 10.9 11.4 IRS2336(D) 0.3 0.7 IRS23364D IRS2336(D) 8 8.9 9.8 IRS23364D 10.4 11.1 11.6 IRS2336(D) 7.4 8.2 9 IRS23364D 10.2 10.9 11.4 IRS2336(D) 0.3 0.7 IRS23364D
IRS2336 IR2336(4)D
BIAS-VO
VOL Low level output voltage drop, VO
I
Output high short circuit pulsed current 120 200
o+
I
Output low short circuit pulsed current 250 350
o-
VIH
V
IN,CLAMP
I
HIN+
I
HIN-
I
LIN+
I
LIN-
V
RCIN,TH
V
RCIN,HY
I
RCIN
R
ON,RCIN
VIL
Logic “0” input voltage Logic “1” input voltage Logic “1” input voltage Logic “0” input voltage Input voltage clamp (HIN, LIN, ITRIP and EN)
Input bias current (HO = High)
Input bias current (HO = Low)
Input bias current (LO = High)
Input bias current (LO = Low)
RCIN positive going threshold RCIN hysteresis
RCIN input bias current
RCIN low on resistance
IRS2336(D) 4.8 5.2 5.65
IRS2336(D) IRS23364D IRS2336(D) IRS23364D IRS2336(D) IRS23364D IRS2336(D) IRS23364D
The
parameters are referenced to VSS. The
V
CCUV
0.2
V NA
— — — — — — — — —
2.5
— — — — — — — — — — — — — —
0.2
70 120
2 3 3 4
50 V
µA
All inputs are in the
mA
B
0.90 1.4 V
0.40 0.6 V V
mA
0.8
V
O
=15 V,VIN=5 V,
V
O
150 200 VIN = 0 V 120 165 110 150
150 200 120 165
1
µA
110 150
8 3
50 100
1
— —
1 µA V
V
RCIN
= VS = 600 V
off state
I
= 20 mA
O
=0 V,VIN=0 V,
PW 10 µs
PW 10 µs
NA
I
= 100 µA
IN
V
= 4 V
IN
V
= 0 V
IN
V
= 4 V
IN
= 0 V
V
IN
NA
= 0 V or 15 V
I = 1.5 mA
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IRS2336x(D) Family
Static Electrical Characteristics (continued)
Symbol Definition Min Typ Max Units Test Conditions
V
ITRIP positive going threshold 0.37 0.46 0.55
IT,TH+
V
ITRIP negative going threshold
IT,TH-
V
ITRIP hysteresis
IT,HYS
I
“High” ITRIP input bias current
ITRIP+
I
“Low” ITRIP input bias current
ITRIP-
V
Enable positive going threshold
EN,TH+
V
Enable negative going threshold 0.8
EN,TH-
I
“High” enable input bias current
EN+
I
“Low” enable input bias current
EN-
R
FAULT low on resistance
ON,FLT
RBS
Internal BS diode Ron (IRS2336(4)D)
IRS2336(D) IRS23364D
IRS2336(D) IRS23364D
— —
— —
0.4
0.07
5 20 5 40
— — — —
— —
5 20
120 165
— — —
50 100 I = 1.5 mA
200
— —
1
2.5
1
V
µA
V
µA
NA
VIN = 4 V
VIN = 0 V
NA
VIN = 4 V
VIN = 0 V
NA
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9
IRS2336x(D) Family
Dynamic Electrical Characteristics
VCC= VB = 15 V, VS = VSS = COM, TA = 25oC, and CL = 1000 pF unless otherwise specified.
Symbol Definition Min Typ Max Units Test Conditions
t
ON
t
OFF
t t
t
FIL,IN
tEN
t
FILTER,EN
t
FLTCLR
t
ITRIP
tBL ITRIP blanking time
t
FLT
DT Deadtime 190 275 420
MDT
MT
PM
† The minimum width of the input pulse is recommended to exceed 500 ns to ensure the filtering time of the
†† This parameter applies to all of the channels. Please see the application section for more details. ††† PM is defined as PW
Turn-on propagation delay 400 530 750 Turn-off propagation delay 400 530 750 Turn-on rise time
R
Turn-off fall time
F
Input filter time (HIN, LIN, ITRIP)
Enable low to output shutdown propagation delay
— —
200 350 510
350 460 650 V
125 190
50 75
Enable input filter time 100 200
FAULT clear time RCIN: R = 2 M, C = 1 nF
ITRIP to output shutdown propagation delay
1.3 1.65 2 ms
500 750 1200 V
400
ITRIP to FAULT propagation delay 400 600 950
††
DT matching
Delay matching time (t
Pulse width distortion
†††
ON
††
, t
)
OFF
— — — — 50
— —
input filter is exceeded.
- PW
IN
OUT
.
60
75
ns
ns
= 0 V & 5 V
V
IN
= 0 V or 5 V
IN, VEN
NA
= 0 V or 5 V
V
IN
V
= 0 V
ITRIP
= 5 V
ITRIP
= 0 V or 5 V
V
IN
V
= 5 V
ITRIP
= 0 V & 5 V without
V
IN
external deadtime
V
= 0 V & 5 V with external
IN
deadtime larger than DT
PW input=10 µs
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Functional Block Diagram: IRS2336(D)
IRS2336x(D) Family
Note: IRS2336 is without the “Integrated BootFET”
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Functional Block Diagram: IRS23364D
IRS2336x(D) Family
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Input/Output Pin Equivalent Circuit
IRS2336x(D) Family
Diagrams: IRS2336(D)
V
CC
ITRIP or EN
V
SS
ESD
Diode
ESD
Diode
R
PD
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13
Input/Output Pin Equivalent Circuit
IRS2336x(D) Family
Diagrams: IRS23364D
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14
IRS2336x(D) Family
Lead Definitions: IRS2336(D)
Symbol Description
VCC Low-side supply voltage
VSS Logic ground
VB1 High-side gate drive floating supply (phase 1)
VB2 High-side gate drive floating supply (phase 2)
VB3 High-side gate drive floating supply (phase 3)
VS1 High voltage floating supply return (phase 1)
VS2 High voltage floating supply return (phase 2)
VS3 High voltage floating supply return (phase 3)
HIN1/N Logic inputs for high-side gate driver outputs (phase 1); input is out-of-phase with output
HIN2/N Logic inputs for high-side gate driver outputs (phase 2); input is out-of-phase with output
HIN3/N Logic inputs for high-side gate driver outputs (phase 3); input is out-of-phase with output
LIN1/N Logic inputs for low-side gate driver outputs (phase 1); input is out-of-phase with output
LIN2/N Logic inputs for low-side gate driver outputs (phase 2); input is out-of-phase with output
LIN3/N Logic inputs for low-side gate driver outputs (phase 3); input is out-of-phase with output
HO1 High-side driver outputs (phase 1)
HO2 High-side driver outputs (phase 2)
HO3 High-side driver outputs (phase 3)
LO1 Low-side driver outputs (phase 1)
LO2 Low-side driver outputs (phase 2)
LO3 Low-side driver outputs (phase 3)
COM Low-side gate drive return
FAULT/N
EN
ITRIP
RCIN
Indicates over-current, over-temperature (ITRIP), or low-side undervoltage lockout has occurred. This pin has negative logic and an open-drain output. The use of over-current and over-
temperature protection requires the use of external components. Logic input to shutdown functionality. Logic functions when EN is high (i.e., positive logic). No effect on FAULT and not latched.
Analog input for over-current shutdown. When active, ITRIP shuts down outputs and activates
FAULT and RCIN low. When ITRIP becomes inactive, FAULT stays active low for an externally
set time t An external RC network input used to define the FAULT CLEAR delay (t equal to R*C. When RCIN > 8 V, the FAULT pin goes back into an open-drain high-impedance state.
, then automatically becomes inactive (open-drain high impedance).
FLTCLR
approximately
FLTCLR)
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