Excellent Latch Immunity on All Inputs & Outputs
+/- 50V/ns dV/dt immunity
ESD Protection on All Pins
8-lead SOIC or PDIP package
1.1 usec (typ.) internal deadtime
Description
The IRS2153D is based on the popular IR2153 selfoscillating half-bridge gate driver IC using a more
advanced silicon platform, and incorporates a high
voltage half-bridge gate driver with a front end oscillator
similar to the industry standard CMOS 555 timer. HVIC
and latch immune CMOS technologies enable rugged
monolithic construction. The output driver features a high
pulse current buffer stage designed for minimum driver
cross-conduction. Noise immunity is achieved with low
di/dt peak of the gate drivers.
Typical Connection Diagram
+ AC Rectified Line
VOFFSET 600V Max
Duty Cycle 50%
Driver source/sink
current
Vclamp 15.4V typ.
Deadtime 1.1us typ.
180/260mA typ.
Package
IRS2153DPBF IRS2153DSPBF
PDIP8 SO8
RVCC
CVCC
- AC Rectified Line
VCC
RT
CT
COM
1
RT
2
CT
3
IRS2153D
4
VB
8
HO
7
VS
6
5
LO
CBOOT
MHS
L
RL
MLS
1
IRS2153D(S)PbF
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All
voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead.
The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air
conditions.
Parameter
Symbol Definition Min. Max. Units
VB High Side Floating Supply Voltage -0.3 625 V
VS High Side Floating Supply Offset Voltage VB - 25 VB + 0.3 V
VHO High-Side Floating Output Voltage VS – 0.3 VB + 0.3 V
VLO Low-Side Output Voltage -0.3 VCC + 0.3 V
IRT R
VRT R
VCT C
ICC Supply Current (Note 1) --- 20 mA
IOMAX Maximum allowable current at LO and HO due to external
dVS/dt
PD
PD
R
Thermal Resistance, Junction to Ambient, 8-Pin DIP --- 85 ºC/W
θJA
R
Thermal Resistance, Junction to Ambient, 8-Pin SOIC --- 128 ºC/W
θJA
TJ Junction Temperature -55 150
TS Storage Temperature -55 150 ºC
TL Lead Temperature (Soldering, 10 seconds) --- 300
Pin Current -5 5 mA
T
Pin Voltage -0.3 VCC + 0.3 V
T
Pin Voltage -0.3 VCC + 0.3 V
T
-500 500
power transistor Miller effect.
Allowable Offset Voltage Slew Rate -50 50 V/ns
Maximum Power Dissipation @ T
Maximum Power Dissipation @ T
≤ +25ºC, 8-Pin DIP
A
≤ +25ºC, 8-Pin SOIC
A
--- 1.0 W
--- 0.625 W
Note 1:
This IC contains a zener clamp structure between the chip V
and COM which has a nominal
CC
breakdown voltage of 15.4V. Please note that this supply pin should not be driven by a DC, low
impedance power source greater than the V
specified in the Electrical Characteristics section.
CLAMP
2
f
IRS2153D(S)PbF
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Parameter
Symbol Definition Min. Max. Units
VBS High Side Floating Supply Voltage VCC - 0.7 V
VS Steady State High Side Floating Supply Offset Voltage -3.0 (Note 2) 600 V
VCC Supply Voltage V
ICC Supply Current (Note 3) 5 mA
TJ Junction Temperature -40 125 ºC
CCUV
+0.1V V
+
CC CLAMP
V
CLAMP
V
Note 2:
Note 3:
Care should be taken to avoid output switching conditions where the V
ground by more than 5V.
Enough current should be supplied to the
clamping the voltage at this pin.
pin of the IC to keep the internal 15.6V zener diode
V
CC
node flies inductively below
S
Recommended Component Values
Parameter
Symbol Component Min. Max. Units
RT Timing Resistor Value 1
CT C
Pin Capacitor Value 330 --- pF
T
---
kΩ
IRS2153D Frequency vs. RT
Frequency (Hz)
1000000
100000
10000
CT Values
330p
470pF
1nF
1000
2.2nF
4.7nF
100
10nF
10
1000 100001000001000000
RT (Ohm)
3
IRS2153D(S)PbF
Electrical Characteristics
VBIAS (VCC, VBS) = 14V, CT = 1 nF, VS=0V and TA = 25°C unless otherwise specified. The output voltage and current (VO and IO)
parameters are referenced to COM and are applicable to the respective output leads: HO or LO.