Datasheet IR2151S, IR2151 Datasheet (International Rectifier)

Features

n Floating channel designed for bootstrap operation

Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune

n Undervoltage lockout
n Programmable oscillator frequency

f =

×+ ×

1

1.4 (R 75 ) C

TT

Ω

nMatched propagation delay for both channels
n Low side output in phase with R

T

Descr iption

The IR2151 is a high voltage, high speed, self-os­cillating power MOSFET and IGBT driver with both high
and low side referenced output channels. Proprietar y
HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. The front end fea­tures a programmable oscillator which is similar to the
555 timer. The output drivers f eature a high pulse cur­rent buff er stage and an internal deadtime designed f or
minimum driver cross-conduction. Propagation dela ys
for the two channels are matched to simplify use in
50% duty cycle applications. The floating channel can
be used to drive an N-channel power MOSFET or IGBT
in the high side configuration that operates off a high
voltage rail up to 600 volts.

Data Sheet No. PD-6.034G

IR2151

SELF-OSCILLATING HALF-BRIDGE DRIVER

Product Summary

V

OFFSET

600V max.

Duty Cycle 50%

IO+/- 100 mA / 210 mA

V

OUT

10 - 20V

Deadtime (typ.) 1.2 µs

Packages

Typical Connection

up to 600V

V

CC

V

B

V

S

HO

LOCOM

R

T

C

T

TO

LOAD

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-187

IR2151

B-188 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL

Parameter Value

Symbol Definition Min. Max. Units

V

B

High Side Floating Supply Absolute Voltage VS + 10 VS + 20

V

S

High Side Floating Supply Offset Voltage — 600

V

HO

High Side Floating Output Voltage V

S

V

B

V

LO

Low Side Output Voltage 0 V

CC

I

CC

Supply Current (Note 1) — 5 mA

T

A

Ambient Temperature -40 125 °C

Pa rameter Value

Symbol Definition Min. Max. Units

V

B

High Side Floating Supply Voltage -0.3 625

V

S

High Side Floating Supply Offset Voltage VB - 25 VB + 0.3

V

HO

High Side Floating Output Voltage VS - 0.3 V

B

+ 0.3

V

LO

Low Side Output Voltage -0.3 VCC + 0.3

V

RT

RT V oltage -0.3 VCC + 0.3

V

CT

CT Voltage -0.3 V

CC

+ 0.3

I

CC

Supply Current (Note 1) — 25

I

RT

RT Output Current -5 5

dVs/dt Allowable Offset Supply Voltage Transient — 50 V/ns

P

D

Package Power Dissipation @ TA ≤ +25°C (8 Lead DIP) — 1.0

(8 Lead SOIC) — 0.625

R

θJA

Thermal Resistance, Junction to Ambient (8 Lead DIP) — 125

(8 Lead SOIC) — 200

T

J

Junction Temperature — 150

T

S

Storage Temperature -55 150 °C

T

L

Lead Temperature (Soldering, 10 seconds) — 300

Absolute Maximum Ratings

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param­eters are absolute voltages referenced to COM. The Thermal Resistance and Po wer Dissipation ratings are measured
under board mounted and still air conditions.

Recommended Operating Conditions

The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. The V

S

offset rating is tested with all supplies biased at 15V differential.

V

°C/W

W

mA

V

structure between the chip VCC and COM which has a nominal breakdo wn voltage of 15.6V. Therefore, the IC
supply voltage is normally derived by forcing current into the supply lead (typically by means of a high value
resistor connected between the chip V

CC

and the rectified line voltage and a local decoupling capacitor from

V

CC

to COM) and allowing the internal zener clamp circuit to deter mine the nominal supply voltage. There-

fore, this circuit should not be dri ven by a DC, low impedance power source of greater than V

CLAMP

.

Note 1: Because of the IR2151’s application specificity toward off-line supply systems, this IC contains a zener clamp

IR2151

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-189

Parameter Value

Symbol Definition Min. Typ. Max. Units Test Conditions

t

r

Turn-On Rise Time — 80 120

t

f

Turn-Off Fall Time — 40 70

DT Deadtime 0.50 1.20 2.25 µs

DR

T

Duty Cycle 48 50 52 %

Dynamic Electrical Characteristics

V

BIAS

(VCC, VBS) = 12V, CL = 1000 pF and TA = 25°C unless otherwise specified.

ns

Parameter Value

Symbol Definition Min. Typ. Max. Units Test Conditions

f

OSC

Oscillator Frequency 19.4 20.0 20.6 RT = 35.7 kΩ

94 100 106 RT = 7.04 kΩ

V

CLAMP

VCC Zener Shunt Clamp Voltage 14.4 15.6 16.8 ICC = 5 mA

V

CT+

2/3 VCC Threshold 7.8 8.0 8.2 V

V

CT-

1/3 VCC Threshold 3.8 4.0 4.2

V

CTUV

CT Undervoltage Lockout — 20 50 2.5V<VCC<V

CCUV+

V

RT+

RT High Level Output Voltage, VCC - R

T

— 0 100 IRT = -100 µA
— 200 300 IRT = -1 mA

V

RT-

RT Low Level Output Voltage — 20 50 IRT = 100 µ A

— 200 300 IRT = 1 mA

V

RTUV

RT Undervoltage Lockout, VCC - R

T

— 0 100 2.5V<VCC<V

CCUV+

V

OH

High Level Output V oltage, V

BIAS

- V

O

— — 100 IO = 0A

V

OL

Low Level Output V oltage, V

O

— — 100 IO = 0A

I

LK

Offset Supply Leakage Current — — 50 VB = VS = 600V

I

QBS

Quiescent VBS Supply Current — 10 50

I

QCC

Quiescent VCC Supply Current — 400 950

I

CT

CT Input Current — 0.001 1.0

V

CCUV+

VCC Supply Undervoltage Positive Going 7.7 8.4 9.2
Threshold

V

CCUV-

VCC Supply Undervoltage Negative Going 7.4 8.1 8.9
Threshold

V

CCUVH

VCC Supply Undervoltage Lockout Hysteresis 200 50 0 — mV

I

O+

Output High Short Circuit Pulsed Current 100 125 — VO = 0V

I

O-

Output Low Short Circuit Pulsed Current 210 2 50 — VO = 15V

Static Electrical Characteristics

V

BIAS

(VCC, VBS) = 12V, CL = 1000 pF, CT = 1 nF and TA = 25°C unless otherwise specified. The VIN, VTH and I

IN

parameters are referenced to COM. The VO and IO parameters are referenced to COM and are applicable to the
respective output leads: HO or LO.

kHz

mV

V

mA

µA

IR2151

B-190 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL

Lead Definitions

Lead

Symbol Description

R

T

Oscillator timing resistor input,in phase with LO for normal IC operation

C

T

Oscillator timing capacitor input, the oscillator frequency according to the following equation:

f =

×+ ×

1

1.4 (R 75 ) C

TT

Ω

where 75Ω is the effective impedance of the RT output stage

V

B

High side floating supply
HO High side gate dri ve output
V

S

High side floating supply return
V

CC

Low side and logic fixed supply
LO Low side gate drive output
COM L ow side return

Functional Block Diagram

Lead Assignments

8 Lead DIP SO-8

IR2151 IR2151S

V

B

PULSE

GEN

DELAY

HV
LEVEL
SHIFT

V

CC

PULSE
FILTER

DEAD

TIME

LO

HO

V

S

COM

R
S

Q

15.6V

C

T

R

T

UV

DETECT

+

-

+

-

RQ

SQ

R

R

R

DEAD

TIME

IR2151

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-191

Thickness of Gate Oxide 800Å
Connections Material P oly Silicon

First Width 5 µm
La yer Spacing 6 µm

Thickness 5000Å

Material Al - Si - Cu (Si: 1.0%, Cu ±0.5%)
Second Width 6 µm
La yer Spacing 9 µm

Thickness 20,000Å

Contact Hole Dimension 5 µm X 5 µm
Insulation Layer Material PSG (SiO2)

Thickness 1.7 µm

P assivation Material PSG (SiO2)

Thickness 1.7 µm

Method of Saw Full Cut
Method of Die Bond Ablebond 84 - 1
Wire Bond Method Thermo Sonic

Material Au (1.0 mil / 1.3 mil)

Leadframe Material Cu

Die Area Ag

Lead Plating Pb : Sn (37 : 63)

P ackage Types 8 Lead PDIP / SO-8

Materials EME6300 / MP150 / MP190

Remarks:

Device Information

Process & Design Rule HVDCMOS 4.0 µ m
Transistor Count 231
Die Siz e 68 X 101 X 26 (mil)
Die Outline

IR2151

B-192 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL

Figure 1. Input/Output Timing Diagram Figure 2. Switching Time Waveform Definitions

Figure 3. Deadtime Wavefor m Definitions

HO

V

CC

V

CLAMP

V

CCUV

+

R

T

C

T

LO

R

T

(LO)

t

r

t

f

LO
HO

50%

50%

90% 90%

10% 10%

R

T

(HO)

R

T

HO

50% 50%

90%

10%

LO

90%

10%

DT