International Rectifier IR 5001 Service Manual

Data Sheet No.PD60229

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IR5001

UNIVERSAL ACTIVE ORING CONTROLLER

DESCRIPTION

The IR5001 is a universal high-speed controller and
N-channel power MOSFET driver for Active ORing and
reverse polarity protection applications. The output voltage
of the IR5001 is determined based on the polarity of the
voltage difference on its input terminals. In particular, if the
current flow through an N-channel ORing FET is from
source to drain, the output of the IR5001 will be pulled
high to Vcc, thus turning the Active ORing FET on. If the
current reverses direction and flows from drain to source
(due to a short-circuit failure of the source, for example),
the IC will quickly switch the Active ORing FET off. Typical
turn-off delay for the IR5001 is only 130nS, which helps t
minimize voltage sags on the redundant dc voltage.

Both inputs to the IC (INN and INP) as well as Vline
input contain integrated high voltage resistors and internal
clamps. This makes the IR5001 suitable for applications a
voltages up to 100V, and with a minimum number o
external components.

FEATURES



Controller / driver IC in an SO-8 package for
implementation of Active ORing / reverse polarit
protection using N-channel Power MOSFETs



Suitable for both input ORing (for carrier class
telecom equipment) as well as output ORing fo
redundant DC-DC and AC-DC power supplies



130ns Typical Turn-Off delay time



3A Peak Turn-Off gate drive current



Asymmetrical offset voltage of the internal high-speed
comparator prevents potential oscillations at light load



Ability to withstand continuous gate short conditions



Integrated voltage clamps on both comparator inputs
allow continuous application of up to 100V



Option to be powered either directly from 36-75V
universal telecom bus (100V max), or from an
external bias supply and bias resistor



Input/Output pins to determine the state of the Active
ORing circuit and power system redundancy

APPLICATIONS

-48V/-24V Input Active ORing for carrier class communication equipment



Reverse input polarity protection for DC-DC power supplies



24V/48V output active ORing for redundant AC-DC rectifiers



Low output voltage (12V, 5V, 3.3V...) active ORing for redundant DC-DC and AC-DC power supplies

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Active ORing of multiple voltage regulators for redundant processor power

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TYPICAL APPLICATION

+48V input

FET Check Puls e

-48V input A

-48V input B

A

B

FET A Status

Fet B Status

IR5001

Vline

Vcc

FETch

FETst

IR5001

Vline

Vcc

FETch

FETst

Vout

Gnd

INN

INP

Vout

Gnd

INN

INP

Figure 1 - Typical application of the IR5001 in - 48V input,

carrier class telecommunications equipment.

DC

DC

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PACKAGE / ORDERING

INFORMATION

Top View

Vline

1

2

Vcc

3

FETch

4

FETst

θJA=128°C/W

Ordering P/N Package

IR5001S 8 - Pin SOIC

8

Vout

7

Gnd

6

INN

5

INP

1

IR5001

Vli

VINP=0; VINN

,

ABSOLUTE MAXIMUM RATINGS

Vline Voltage -5.0V to 100V (continuous)
Vcc Voltage -0.5V to 15VDC
Icc Current 5mA
INN, INP Voltage -5.0V to 100V (continuous)
FETch, FETst -0.5V to 5.5V
FETst Sink Current 10mA
Junction Temperature -40°C to 125°C
Storage Temperature Range -65°C to 150°C

CAUTION:

1. Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This
is a stress only rating and operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied.

2. This device is ESD sensitive. Use of standard ESD handling precautions is required.

.

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over Vline = 36V to 100V; Vcc is decoupled with 0.1uF to
Gnd, CL=10nF at Vout; INP is connected to Gnd. Typical values refer to TA=25°C. Minimum and maximum limits
apply to TA= 0°C to 85°C temperature range and are 100% production-tested at both temperature extremes. Low
duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature.

PARAMETERS SYMBOL TEST CONDITION MIN TYP MAX UNITS

Vline=25V 0.14 0.3 0.5

Bias Section

Vline Bias Current

VCC output voltage Vcc(out) Vline=25V 10.2 12.5 13.9 V

UVLO Section

UVLO ON Threshold Voltage

UVLO OFF Threshold Voltage Vcc(OFF)

UVLO Hysteresis 1.6 2.3 2.8 V

Input Comparator Section

Input Offset Voltage (VINP­VINN)

Input Hysteresis Voltage Vhyst

(INN) Input Bias Current I(INN) VINP=0V, VINN=36V 0.2 0.5 0.9

(INP) Input Bias Current I(INP) VINN=0V, VINP=36V 0.2 0.5 0.9

Iline

Vcc(ON)

Vos

ne=open,

Vcc increased until Vout switches

Vline=open, VINP=0, VINN=-

0.3V, Vcc is decreased until
Vout switches from HI to LO

VINP=0V and VINN Ramping up,

VOUT changes from HI to LO,

VINP=0,VINN ramping down,

Vline=36V 0.2 0.5 0.75

Vline=100V, Note 1 1.2 1.7 2.2

= -

0.3V

from LO to HI

Fig.3

Figures 3 and 4

Note 2

8.3 9.6 10.9

5.7 7.2 8.5

-7.9 -4. 0 0

13 31 44

mA

mV

mA

V

2

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IR5001

PARAMETERS SYMBOL TEST CONDITION MIN TYP MAX UNITS

Output Section

High Level Output Voltage

Low Level Output Voltage Vout LO IOL=100mA, V(INN)=+0.3V 0.1 0.1 V
Turn-On DelayTime td(on) 5 27 45 us
Rise Time tr 0.1 0.7 5 ms
Turn-Off Delay Time td(off) 110 130 170
Fall Time tf 10 26 39

FETch and FETst

FETch Sink Current

FETch Output Delay Time FETch_pd Note 1 0.8 1.8 us
FETch Threshold Vth(FETch) 0.9 1.2 1.5 V

FETst Threshold Voltage Vth(FETst)

FETst Low Level Output
Voltage

Vout HI

I(FETch) FETch=5V -0.5 -1.1 -2 uA

VOL Isink=1mA, V(INN)=-0.5V 0 50 100 mV

Vline=25V, IOH=50uA,

V(INN)=-0.3V

Vout switching from LO to HI, Fig.5

Vout switching from HI to LO, Fig.5 ns

5k resistor from FETst to 5V logic

bias.

V(INP) = Gnd, V(INN) ramping down

from 0 until FETst switches to Low.

9.5 12 14 V

-525 -300 -200 mV

Note 1: Guaranteed by design but not tested in production.
Note 2: Low Vcc output voltage corresponds to low UVLO voltage

PIN DESCRIPTIONS

PIN# PIN SYMBOL PIN DESCRIPTION

1 Vline

2Vcc

3FETch

4FETst

5INP

6INN

IC power supply pin for 36V to 75V input communications systems.
Minimum 25V has to be applied at this pin to bias the IC.

Output pin of the internal s hunt regulator, or input pin for biasing the IC via
external resistor. This pin is internally regulated at 12.5V ty pical. A
minimum 0.1uF capacitor must be connected from this pin to Gnd of IR5001.

FET check input pin. Together with FET status output pin, the FETch pin
can be used to determine the state of the Ac tive ORing circuit and power
system redundancy .

FET status output pin. Together with FETch input pin, the FETst pin c an be
used to determine the state of the Active ORing circuit and power system
redundancy.

Positive input of internal comparator. This pin should connect to the source
of N-channel Active ORing MOS FET.

Negative input pin of internal comparator. This pin should connect to the
drain of N-channel Active ORing MOSFET.

7 Gnd Ground pin of the IR5001.

8 Vout

Output pin for the IR5001. This pin is used to directly drive the gate of the
Active Oring N-Channel MOSFE T.

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3

IR5001

BLOCK DIAGRAM

50K

1

LINE

V

2

Vcc

INP

INN

5

6

12V Shunt

Regulator

REF

5V, V
Generator

70K

clamp

70K

clamp

8

V

5V

1.25V
9V

UVLO

3.5mV

28mV

5V

12V

Level

Shifter

OUT

7

Gnd

5V

4

FETst

0.3V

1.25V

4

FETch

3

2uA

Figure 2 - Simplified block diagram of the IR5001.

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