International Rectifier IR2130S, IR2130J, IR2130, IR2110L6, IR2110E6 Datasheet

Features

n Floating channel designed for bootstrap operation

Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune

n Gate drive supply range from 10 to 20V
n Undervoltage lockout for all channels
n Over-current shutdown turns off all six drivers
n Independent half-bridge drivers
n Matched propagation delay for all channels
n Outputs out of phase with inputs

Description

The IR2130 is a high voltage, high speed power
MOSFET and IGBT driver with three independent high
and lo w side referenced output channels. Proprietar y
HVIC technology enables ruggediz ed monolithic con­struction. Logic inputs are compatib le with 5V CMOS
or LSTTL outputs. A ground-referenced oper ational
amplifier provides analog feedback of bridge current
via an external current sense resistor. A current tr ip
function which terminates all six outputs is also de­rived from this resistor. An open drain

FAULT signal
indicates if an ov er-current or undervoltage shutdown
has occurred. The output drivers feature a high pulse
current buffer stage designed for minimum driver
cross-conduction. Propagation delays are matched
to simplify use at high frequencies. The floating chan­nels can be used to drive N-channel power MOSFETs
or IGBTs in the high side configuration which oper­ate up to 600 volts.

Data Sheet No. PD-6.019F

IR2130

3-PHASE BRIDGE DRIVER

Product Summary

V

OFFSET

600V max.

IO+/- 200 mA / 420 mA

V

OUT

10 - 20V

t

on/off

(typ.) 675 & 425 ns

Deadtime (typ.) 2.5 µs

Packages

Typical Connection

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-135

IR2130

B-136 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL

Parameter Value

Symbol Definition Min. Max. Units

V

B1,2,3

High Side Floating Supply Voltage V

S1,2,3

+ 10 V

S1,2,3

+ 20

V

S1,2,3

High Side Floating Offset Voltage Note 1 600

V

HO1,2,3

High Side Floating Output Voltage V

S1,2,3

V

B1,2,3

V

CC

Low Side and Logic Fixed Supply Voltage 10 20

V

SS

Logic Ground -5 5

V

LO1,2,3

Low Side Output Voltage 0 V

CC

V

IN

Logic Input Voltage (

HIN1,2,3 , LIN1,2,3 & ITRIP) V

SS

VSS + 5

V

FLT

FAULT

Output Voltage V

SS

V

CC

V

CAO

Operational Amplifier Output Voltage V

SS

5

V

CA-

Operational Amplifier Inverting Input Voltage V

SS

5

T

A

Ambient Temperature -40 125 °C

ra¸aaeuer Valoe

eyibil DnfMnntioa MiU. Msx¸ Bn,t,

V

i1h2S3

H gl aiiegFloptin outpmy¸Vol3a5e -0.S 52,

V

i1,2S3

H gl aidegFOoften Oftset¸VBl,a,e V

152V3

1- 23 +

B0,3,¸

+ 1.3

V

HOg, ,i

eiFhoStde loapitgVOutaue V olt2g3 -

S1,3,V

1 2.3 +

B0,3,ı

+ C.3

V

Cd

on ioeia diLegicuFixydVSlpale -o.t¸g5 -0S3 2o

V

S

LugdcVGro-n2 ¸CC 25 V

ıC

+ 0.3

V

LO1,2,3

Low Side Output Voltage -0.3 V

CC

+ 0.3

V

IN

Logic Input Voltage (

HIN1,2,3 , LIN1,2,3 & ITRIP) V

SS

- 0.3 V

CC

+ 0.3

V

FLT

FAULT Output Voltage 3

SV

C +.0 3

Cı

V A.3

V

CtO

Oae amilnfl A plipitrVOutauu ¸oSt ge V¸SC- 0 3 V

ıC

V +A0.3

r

Ct-

OaeramilnfleA pnieitrnI vnrui goItput VVlSa-e 3SV C +.3 3

C¸

V /.t

dlSwdb AlOowael uffsyt Slpale Voatsge tr—n5i¸n/ s 50 V/nc

P

e

PawkrgD soier iins@pTt on 2 TA¸≤2+ 5eC (28PLea¸ .Iı) — 1.5

(28ILea— 1O6C) ¸ 1.( 4

44 Ce¸d¸P.Cı) — 2.0

R

θaA

TeeimtlnRes suanci, Jtn tmon no Ambient (28 Lead DIP) — 83

(28 Lead SOIC) — 78 °C/W

(44 Lead PLCC) — 63

T

J

Junction Temperature — 150

T

S

Storage Temperature -55 150 eC

T

L

Lead ueep(rotdre nS,l1e iego d0)s—con0s) ´ ¸ 0 `

bsoiuue MaximumıRbtongs

Absxlmtm Matimus iadicgt nuitaie s stainsdblymnt heco dawaiehtdamhge eoiteemdyvocc ma lc ur.tAll valrageepara ­rtebs aeuaesollate oetages rdftr nSe. To VS0. The Thermal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions. Additional information s sFognrin 5iguheo g0 t3rıu¸hP5r.

Note 1: Logic operational for VS of (VS0 - 5V) to (VS0 + 600V). Logic state held for VS of (VS0 - 5V) to (VS0 - VBS).

Recommended Operating Conditions

The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. All voltage parameters are absolute voltages referenced to VS0. The VS offset rating is tested
with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in Figure 54.

V

V

IR2130

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-137

Parameter Value

Symbol Definition Figure Min. Typ. Max. Units Test Conditions

V

IH

Logic “0” Input Voltage (OUT = LO) 21 2.2 — —

V

IL

Logic “1” Input Voltage (OUT = HI) 22 — — 0.8

V

IT,TH+

ITRIP Input Positive Going Threshold 23 40 0 490 5 80

V

OH

High Level Output Voltage, V

BIAS

- VO 24 — — 100 mV VIN = 0V, IO = 0A

V

OL

Low Level Output Voltage , VO 25 — — 100 VIN = 5V, IO = 0A

I

LK

Offset Supply Leakage Current 26 — — 50 VB = VS = 600V

I

QBS

Quiescent VBS Supply Current 27 — 15 30 VIN = 0V or 5V

I

QCC

Quiescent VCC Supply Current 28 — 3.0 4.0 mA VIN = 0V or 5V

I

IN+

Logic “1” Input Bias Current (OUT = HI) 29 — 450 650 VIN = 0V

I

IN-

Logic “0” Input Bias Current (OUT = LO) 30 — 225 400 µA VIN = 5V

I

ITRIP+

“High” ITRIP Bias Current 31 — 75 150 ITRIP = 5V

I

ITRIP-

“Low” ITRIP Bias Current 32 — — 100 nA ITRIP = 0V

V

BSUV+

VBS Supply Undervoltage Positive Going 33 7.5 8.35 9.2
Threshold

V

BSUV-

VBS Supply Undervoltage Negativ e Going 34 7.1 7.95 8.8
Threshold

V

CCUV+

VCC Supply Undervoltage Positive Going 35 8.3 9.0 9.7
Threshold

V

CCUV-

VCC Supply Undervoltage Negative Going 36 8.0 8.7 9.4
Threshold

R

on,FLT

FAULT

Low On-Resistance 37 — 55 75 Ω

Parameter Value

Symbol Definition Figure Min. Typ. Max. Units Test Conditions

t

on

Tur n-On Propagation Delay 11 500 675 850

t

off

Tur n-Off Propagation Delay 12 300 425 550 V

IN

= 0 & 5V

t

r

Tur n-On Rise Time 13 — 80 125 V

S1,2,3

= 0 to 600V

t

f

Tur n-Off Fall Time 14 — 35 55

t

itrip

ITRIP to Output Shutdown Prop. Delay 15 40 0 660 920 VIN, V

ITRIP

= 0 & 5V

t

bl

ITRIP Blanking Time — — 400 — V

ITRIP

= 1V

t

flt

ITRIP to

FAULT

Indication Delay 16 335 590 845 V

IN

, V

ITRIP

= 0 & 5V

t

flt,in

Input Filter Time (All Six Inputs) — — 310 — V

IN

= 0 & 5V

t

fltclr

LIN1,2,3

to

FAULT

Clear Time 17 6.0 9.0 12.0 V

IN

, V

ITRIP

= 0 & 5V

DT Deadtime 18 1.3 2.5 3.7 V

IN

= 0 & 5V

SR+ Operational Amplifier Slew Rate (+) 19 4.4 6.2 —

SR- Operational Amplifier Slew Rate (-) 20 2.4 3.2 —

Dynamic Electrical Characteristics

V

BIAS

(VCC, V

BS1,2,3

) = 15V, V

S0,1,2,3

= VSS, CL = 1000 pF and TA = 25°C unless otherwise specified. The dynamic

electrical characteristics are defined in Figures 3 through 5.

Static Electrical Characteristics

V

BIAS

(VCC, V

BS1,2,3

) = 15V, V

S0,1,2,3

= VSS and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters

are referenced to VSS and are applicable to all six logic input leads:

HIN1,2,3

&

LIN1,2,3. The V

O

and IO parameters

are referenced to V

S0,1,2,3

and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.

V

V/µ s

µs

ns

V

µA

IR2130

B-138 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL

Parameter Value

Symbol Definition Figure Min. Typ. Max. Units Test Conditions

I

O+

Output High Short Circuit Pulsed Current 38 200 250 — VO = 0V, V

IN

= 0V

PW ≤ 10 µs

I

O-

Output Low Short Circuit Pulsed Current 39 420 500 — VO = 15V, V

IN

= 5V

PW ≤ 10 µs

V

OS

Operational Amplifer Input Offset Voltage 4 0 — — 30 mV VS0 = V

CA-

= 0.2V

I

CA-

CA- Input Bais Current 41 — — 4.0 nA V

CA-

= 2.5V

CMRR Op. Amp. Common Mode Rejection Ratio 42 60 80 — VS0=V

CA-

=0.1V & 5V

PSRR Op. Amp. Power Supply Rejection Ratio 43 55 75 — VS0 = V

CA-

= 0.2V

VCC = 10V & 20V

V

OH,AMP

Op. Amp. High Level Output Voltage 44 5.0 5.2 5.4 V V

CA-

= 0V, VS0 = 1V

V

OL,AMP

Op. Amp. Low Level Output Voltage 45 — — 2 0 mV V

CA-

= 1V, VS0 = 0V

I

SRC,AMP

Op. Amp. Output Source Current 46 2.3 4.0 — V

CA-

= 0V, VS0 = 1V
V

CAO

= 4V

I

SRC,AMP

Op. Amp. Output Sink Current 47 1.0 2.1 — V

CA-

= 1V, VS0 = 0V
V

CAO

= 2V

I

O+,AMP

Operational Amplifier Output High Short 48 — 4.5 6.5 V

CA-

= 0V, VS0 = 5V

Circuit Current V

CAO

= 0V

I

O-,AMP

Operational Amplifier Output Low Shor t 49 — 3.2 5.2 V

CA-

= 5V, VS0 = 0V

Circuit Current V

CAO

= 5V

Static Electrical Characteristics -- Continued

V

BIAS

(VCC, V

BS1,2,3

) = 15V, V

S0,1,2,3

= VSS and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters

are referenced to V

SS

and are applicable to all six logic input leads:

HIN1,2,3

&

LIN1,2,3

. The V

O

and IO parameters

are referenced to V

S0,1,2,3

and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.

mA

dB

mA

Lead Assignments

28 Lead DIP 44 Lead PLCC w/o 12 Leads 28 Lead SOIC (Wide Body)

IR2130 IR2130J IR2130S

P art Number

IR2130

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-139

Lead

Symbol Description

Logic inputs for high side gate driver outputs (HO1,2,3), out of phase
Logic inputs for low side gate driver output (LO1,2,3), out of phase
Indicates over-current or undervoltage lockout (low side) has occurred, negative logic

V

CC

Low side and logic fixed supply
ITRIP Input for over-current shutdown
CAO Output of current amplifier
CA- Negative input of current amplifier
V

SS

Logic ground
V

B1,2,3

High side floating supplies
HO1,2,3 High side gate drive outputs
V

S1,2,3

High side floating supply returns
LO1,2,3 Low side gate drive outputs
V

S0

Low side return and positive input of current amplifier

Functional Block Diagram

Lead Definitions

LIN1,2,3

HIN1,2,3

FAULT

IR2130

B-140 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL

Thickness of Gate Oxide 800Å
Connections Material P oly Silicon

First Width 4 µm
Layer Spacing 6 µm

Thickness 5000Å

Material Al - Si (Si: 1.0% ±0.1%)
Second Width 6 µm
Layer Spacing 9 µm

Thickness 20,000Å

Contact Hole Dimension 8 µm X 8 µm
Insulation Layer Material PSG (SiO2)

Thickness 1.5 µm

P assivation Material PSG (SiO2)
(1) Thickness 1.5 µm
P assivation Material Proprietary*
(2) Thickness Proprietary*
Method of Saw Full Cut
Method of Die Bond Ablebond 84 - 1
Wire Bond Method Thermo Sonic

Material A u (1.0 mil / 1.3 mil)

Leadframe Material Cu

Die Area Ag

Lead Plating Pb : Sn (37 : 63)

P ackage Types 28 Lead PDIP & SOIC / 44 Lead PLCC

Materials EME6300 / MP150 / MP190

Remarks: * Patent Pending

Device Information

Process & Design Rule HVDCMOS 4.0 µ m
Transistor Count 700
Die Siz e 126 X 175 X 26 (mil)
Die Outline

IR2130

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-141

Figure 3. Deadtime Waveform Definitions Figure 4. Input/Output Switching Time Waveform

Definitions

Figure 1. Input/Output Timing Diagram Figure 2. Floating Supply Voltage Transient T est Circuit

Figure 5. Overcurrent Shutdown Switching Time

Waveform Definitions

Figure 6. Diagnostic Feedback Operational Amplifier

Circuit

CAO

V

S0

CA-

V

SS

V

CC

V

SS

+

-

LO1,2,3

HO1,2,3

ITRIP

DT DT

t

r

t

on

t

off

t

f

50% 50%

90% 90%

10% 10%

50% 50%

50% 50%

50%

50%

50% 50%

50%

t

flt

t

itrip

t

fltclr

FAULT

LIN1,2,3

HIN1,2,3

FAULT

HIN1,2,3

LIN1,2 ,3

HO1,2,3

LO1,2,3

LIN1,2,3

ITRIP

LO1,2,3

HIN1,2,3
LIN1,2,3

LO1,2,3

HO1,2,3