International Rectifier IR2125 Datasheet

Data Sheet No. PD-6.017D

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IR2125

CURRENT LIMITING SINGLE CHANNEL DRIVER

Features

n Floating channel designed for bootstrap operation

Fully operational to +500V
Tolerant to negative transient voltage
dV/dt immune

n Gate drive supply range from 12 to 18V
n Undervoltage lockout
n Current detection and limiting loop to limit driven

power transistor current

n Error lead indicates fault conditions and programs

shutdown time

n Output in phase with input

Description

The IR2125 is a high voltage, high speed power

MOSFET and IGBT driver with over-current limit­ing protection circuitry. Proprietary HVIC and latch
immune CMOS technologies enable r uggedized
monolithic construction. Logic inputs are compat­ible with standard CMOS or LSTTL outputs. The
output driver features a high pulse current buffer
stage designed for minimum driver cross-conduc­tion. The protection circuitry detects over-current
in the driven power transistor and limits the gate
drive voltage. Cycle by cycle shutdown is pro­grammed by an external capacitor which directly
controls the time interval between detection of the
over-current limiting conditions and latched shut-

Product Summary

V

OFFSET

IO+/- 1A / 2A

V

OUT

V

CSth

t

(typ.) 150 & 150 ns

on/off

500V max.

12 - 18V

230 mV

Package

down. The floating channel can be used to drive an
N-channel power MOSFET or IGBT in the high or
low side configuration which operates up to 500
volts.

Typical Connection

V

CC

IN

V

CC

IN
ERR
COM

V

OUT

CS

V

up to 500V

B

S

TO

LOAD

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-107

IR2125

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Absolute Maximum Ratings

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param­eters are absolute voltages referenced to COM. The Ther mal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions.

Parameter Value

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

IN

V

ERR

V

CS

dVs/dt Allowable Offset Supply Voltage Transient — 50 V/ns

P

D

R

θJA

T

J

T

S

T

L

High Side Floating Supply Voltage -0.3 525
High Side Floating Offset Voltage VB - 25 VB + 0.3
High Side Floating Output Voltage VS - 0.3 V
Logic Supply Voltage -0.3 25 V
Logic Input Voltage -0.3 V
Error Signal Voltage -0.3 V
Current Sense Voltage VS - 0.3 V

Package Power Dissipation @ TA ≤ +25°C — 1.0 W
Thermal Resistance, Junction to Ambient — 125 °C/W
Junction Temperature — 150
Storage Temperature -55 150 °C
Lead Temperature (Soldering, 10 seconds) — 300

CC
CC

B

B

+ 0.3

+ 0.3
+ 0.3

+ 0.3

Recommended Operating Conditions

The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. The V

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

IN

V

ERR

V

CS

T

A

Note 1: Logic operational for VS of -5 to +500V. Logic state held for VS of -5V to -VBS.

High Side Floating Supply Voltage VS + 12 VS + 18
High Side Floating Offset Voltage Note 1 500
High Side Floating Output Voltage V
Logic Supply Voltage 0 18 V
Logic Input Voltage 0 V
Error Signal Voltage 0 V
Current Sense Signal Voltage V
Ambient Temperature -40 125 °C

B-108 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL

offset rating is tested with all supplies biased at 15V differential.

S

Parameter Value

S

S

V

B

CC
CC

V

B

Dynamic Electrical Characteristics

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V

(VCC, VBS) = 15V, CL = 3300 pF and TA = 25°C unless otherwise specified. The dynamic electrical characteristics

BIAS

are measured using the test circuit shown in Figures 3 through 6.

Parameter Value

Symbol Definition Figure Min. Typ. Max. Units Test Conditions

t

on

t

off

t

sd

t
t

t

cs

t

err

Turn-On Propagation Delay 7 — 150 200
Tur n-Off Propagation Delay 8 — 150 19 0
ERR Shutdown Propagation Delay 9 — 1.7 2.2 µs
Turn-On Rise Time 10 — 43 60

r

Tur n-Off Fall Time 11 — 26 35

f

CS Shutdown Propagation Delay 12 — 0.7 1.2
CS to ERR Pull-Up Propagation Delay 13 — 9.0 12 C

Static Electrical Characteristics

V

(VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to

BIAS

COM. The VO and IO parameters are referenced to VS.

Parameter Value

Symbol Definition Figure Min. Typ. Max. Units Test Conditions

V

IH

V

V

CSTH+

V

CSTH-

V

OH

V

OL

I

LK

I

QBS

I

QCC

I

IN+

I

IN-

I

CS+

I

CS-

V

BSUV+

V

BSUV-

V

CCUV+

V

CCUV-

I

ERR

I

ERR+

I

ERR-

I

O+

I

O-

Logic “1” Input Voltage 14 2.2 — — VCC = 12V to 18V
Logic “0” Input Voltage 15 — — 0.8 VCC = 12V to 18V

IL

CS Input Positive Going Threshold 16 150 230 320 VCC = 12V to 18V
CS Input Negative Going Threshold 17 130 200 260 VCC = 12V to 18V
High Level Output Voltage, V
Low Level Output V oltage, V

BIAS

O

- V

Offset Supply Leakage Current 20 — — 50 VB = VS = 500V
Quiescent VBS Supply Current 21 — 400 1000 VIN = VCS = 0V or 5V
Quiescent VCC Supply Current 22 — 700 1200 VIN = VCS = 0V or 5V
Logic “1” Input Bias Current 23 — 4.5 10 µA VIN = 5V
Logic “0” Input Bias Current 24 — — 1.0 VIN = 0V
“High” CS Bias Current 25 — 4.5 10 VCS = 3V
“Low” CS Bias Current 26 — — 1.0 VCS = 0V
VBS Supply Undervoltage Positive Going 27 8.5 9.2 10.0
Threshold
VBS Supply Undervoltage Negative Going 28 7.7 8.3 9.0
Threshold
VCC Supply Undervoltage Positive Going 29 8.3 8.9 9.6
Threshold
VCC Supply Undervoltage Negative Going 30 7.3 8.0 8.7
Threshold
ERR Timing Charge Current 31 65 100 130 VIN = 5V, VCS = 3V

ERR Pull-Up Current 32 8.0 15 — VIN = 5V, VCS = 3V

ERR Pull-Down Current 33 16 30 — VIN = 0V
Output High Short Circuit Pulsed Current 34 1.0 1.6 — VO = 0V, V

Output Low Short Circuit Pulsed Current 35 2.0 3.3 — VO = 15V, V

IR2125

ns

ns

µs

V

O

18 — — 100 IO = 0A

mV

19 — — 100 IO = 0A

V

µA

mA

A

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-109

= 270 pF

ERR

ERR < V

ERR > V

IN

PW ≤ 10 µs

PW ≤ 10 µs

ERR+

ERR+

= 5V

= 0V

IN

IR2125

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Functional Block Diagram

V

ERR

COM

CC

UV

DETECT

UP

IN

1.8V

1.8V

SHUTDOWN

ERROR
TIMING

LATCHED

SHIFTERS

PULSE

GEN

QR

S

PULSE

FILTER

HV

LEVEL

SHIFT

UV

DETECT

PULSE
FILTER

V

B

HV

LEVEL

SHIFT

R
R
S

PULSE

GEN

DOWN
SHIFTERS

Q

PRE

DRIVER

AMPLIFER

500ns

BLANK

COMPARATOR

BUFFER

0.23V

-

+

Lead Definitions

Lead

Symbol Description

V

CC

IN Logic input for gate driver output (HO), in phase with HO
ERR Serves multiple functions; status reporting, linear mode timing and cycle by cycle logic

COM Logic ground
V

B

HO
V

S

CS

Logic and gate drive supply

shutdown

High side floating supply
High side gate drive output
High side floating supply return

Current sense input to current sense comparator

V

HO

V

CS

B

S

Lead Assignments

B-110 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL

8 Lead DIP

IR2125

Part Number

Device Information

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Process & Design Rule HVDCMOS 4.0 µm
Transistor Count 410
Die Size 104 X 111 X 26 (mil)
Die Outline

Thickness of Gate Oxide 800Å
Connections Material Poly Silicon

Contact Hole Dimension 8 µm X 8 µm
Insulation Layer Material PSG (SiO2)

Passivation Material PSG (SiO2)
(1) Thickness 1.5 µm
Passivation Material Proprietary*
(2) Thickness Proprietary*
Method of Saw Full Cut
Method of Die Bond Ablebond 84 - 1
Wire Bond Method Thermo Sonic

Leadframe Material Cu

Pa ckage Types 8 Lead PDIP

Remarks: * Patent Pending

IR2125

First Width 4 µm
Layer Spacing 6 µm

Thickness 5000Å

Material Al - Si (Si: 1.0% ±0.1%)
Second Width 6 µm
Layer Spacing 9 µm

Thickness 20,000Å

Thickness 1.5 µm

Material Au (1.0 mil / 1.3 mil)

Die Area Ag

Lead Plating Pb : Sn (37 : 63)

Materials EME6300 / MP150 / MP190

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-111