Inter-m SYSTEM-2120, SYSTEM-2240 Service Manual

SERVICE

MANUAL

MULTI P.A COMBINATION

AMPLIFIER

SYSTEM-2120/2240

www.inter-m.com

MADE IN KOREA

NO: 9007919920

Electrical Adjustment Procedure 1
Micom Data (CD) 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
Micom Data (TUNER) 13, 14, 15, 16
Micom Data (DECK) 17, 18, 19, 20
Specifications

21, 22

Electrical Parts List

23, 24, 25, 26, 27, 28, 29

Top and Bottom View of P.C. Board

30, 31, 32, 33, 34, 35, 36

Wiring Diagram

37

Block Diagram

38
Schematic Diagram 39, 40, 41, 42, 43, 44, 45, 46,

Schematic Diagram 47, 48, 49, 50, 51, 52

Exploded View of Cabinet & Chassis / Mechanical Parts List 53, 54
Ass’y Drawing

55, 56

CONTENTS

1

ELECTRICAL ADJUSTMENT PROCEDURE

1. IDLE CURRENT

2. DECK SPEED ADJUSTMENT

CONDITION (USE MCC-112 TEST TAPE)

TEST POINT LEVEL

POINT

ADJUSTMENT

AMP IDLE

R773 4mV SVR701

CURRENT

TEST POINT LEVEL

POINT

ADJUSTMENT

DECK SPEED OUTPUT 30000±50Hz SVR301

MICOM DATA (CD)

2

KA9258D
4-Channel Motor Driver

PIN ASSIGNMENTS

28-SSOPH-375

3

PIN DEFINITIONS

Pin Number Pin Name I/O Pin Function Description

1 DO1.1 O Diver output
2 DO1.2 O Diver output
3 DI1.1 I Diver input
4 DI1.2 I Diver input
5 REG – Regulator
6 REO O Regulator output
7 MUTE I Mute
8 GND1 – Ground 1

9 DI2.1 I Diver input
10 DI2.2 I Diver input
11 DO2.1 O Diver output
12 DO2.2 O Diver output
13 GND2 – Ground 2
14 OPOUT O Op-amp output
15 OPIN(–) I Op-amp input (–)
16 OPIN(+) I Op-amp input (+)
17 DO3.1 O Diver output
18 DO3.2 O Diver output
19 DI3.1 I Diver input
20 DI3.2 I Diver input
21 V

CC1

– Supply voltage

22 V

CC2

– Supply voltage
23 VREF I 2.5V bias voltage
24 DI4.1 I Diver input
25 DI4.2 I Diver input
26 DO4.1 O Diver output
27 DO4.2 O Diver output
28 GND3 – Ground 3

4

KA3082
Bi-Directional DC Motor Driver

PIN ASSIGNMENTS

PIN DEFINITIONS

10-SIP

Pin Number Pin Name I/O Pin Function Description

1 GND – Ground
2V

O1

O Output 1

3V

Z1

– Phase compensation

4V

CTL

IMotor speed control

5V

IN1

I Input 1

6V

IN2

I Input 2

7SV

CC

– Supply voltage (Signal)
8PVCC– Supply voltage (Power)
9C

Z2

– Phase compensation

10 V

OZ

O Output 2

5

INTERNAL BLOCK DIAGRAM

7

PIN CONFIGURATIONS

6

CXD2589Q
CD Digital Signal Processor

BLOCK DIAGRAM

80 pin QFP (Plastic)

8

PIN DEFINITIONS

Pin No. Symbol I/O Description

1V

SS

– – GND
2 LMUT O 1,0 Left-channel zero detection flag
3 RMUT O 1,0 Right-channel zero detectio flag
4 SQCK I SQSO readout clock input
5 SQSO O 1,0 Sub Q 80-bit serial output
6 SENS O 1,0 SENS output to CPU
7DATAI Serial data input from CPU
8 XLAT I Latch input from CPU. Serial data is latched at the falling edge
9 CLOC I Serial data transfer clock input from CPU

10 SEIN I SENS input from SSP
11 CNIN I Track jump count signal input
12 DATO O 1,0 Serial data output to SSP
13 XLTO O 1,0 Serial data latch output to SSP. Latched at the falling edge
14 CLKO O 1,0 Serial data transfer clock output to SSP
15 SPOA I Microcomuter extended interface (input A)
16 SPOB I Microcomuter extended interface (input B)
17 XLON O 1,0 Microcomuter extended interface (output)
18 FOK I Focus OK input

Used for SENS output and the servo auto sequencer

19 V

DD

– – Power supply (+5V)

20 V

SS

– – GND

21 MDP O 1,Z,0 Spindle motor servo control
22 PWMI I Spindle motor external control input
23 TEST I TEST pin; normally GND
24 TES1 I TEST pn; normally GND
25 VPCO O 1,Z,0 Charge pump output for the wide-band EFM PLL
26 VCKI I VCO2 oscillation input for the wide-band EFM PLL
27 V16M O 1,0 VCO2 oscillation output for the wide-band EFM PLL
28 VCTL I VCO2 conrol v oltage input for the wide-band EFM PLL
29 PCO O 1,Z,0 Master PLL charge pump output
30 FILO O Analog Master PLL (slave=digital PLL) Filter output
31 FILI I Master PLL filter input
32 AV

SS

– – Analog GND

33 CL TV I Master VCO control voltage input
34 AV

DD

– – Analog power supply (+5V)

35 RF I EFM signal input
36 BIAS I Constant current input of the asymmetry circuit
37 ASYI I Asymmetry comparator voltage input
38 ASYO O 1,0 EFM full-swing output (low=VSS, high=VDD)
39 LRCK O 1,0 D/A interface. LR clock output f=FS
40 LRCKI I LR clock input
41 PCMD O 1,0 D/A interface. Serial data output (two’s complement, MSB first)
42 PCMDI I D/A interface. Serial data input (two’s complement, MSB first)
43 BCK O 1,0 D/A interface. Bit clock output
44 BCKI I D/A interface. Bit clock input
45 V

SS

– – GND

9

Pin No. Pin Name I/O Description

46 V

DD

– – Power supply (+5V)
47 XUGF O 1,0 XUGF output. Switched to MNT1 or RFCK output b y a command
48 XPCK O 1,0 XPLCK output. Switched to MNT0 output by a command
49 GFS O 1,0 GFS output. Switched to MNT3 or XRAOF output by a command
50 C2PO O 1,0 C2PO output. Switched to GTOP output by a command
51 XTSL I Crystal selector input. Low: 16.9344MHz; high: 33.8688MHz
52 C4M O 1,0 4.2336MHz output. 1/4 frequency-divided VCKI output in CAV-W mode
53 DOUT O 1,0 Digital Out output
54 EMPH O 1,0 Outputs a high signal when the playback disc has emphasis, and a

low signal when there is no emphasis

55 EMPHI I Inputs a high signal when de-demphasis is on, and a low signal when

de-emphasis is off
56 WFCK O 1,0 WFCK output
57 SCOR O 1,0 Outputs a high signal when either subcode sync S0 or S1 is detected
58 SBSO O 1,0 Sub P to W serial output
59 EXCK I SBSO readout clock input
60 V

SS

– – GND

61 V

DD

– – Power supply (+5V)
62 SYSM I Mute input. Active when high
63 AV

SS

– – Analog GND
64 AV

DD

– – Analog power supply (+5V)
65 AOUT1 O Left-channel analog output
66 AIN1 I Left-channel operational amplifier input
67 LOUT1 O Left-channel LINE output
68 AV

SS

– – Analog GND
69 XV

DD

Power supply for master clock

70 XTAI I Crystal oscillation circuit input. Input the external master clock via

this pin
71 XTAO O Crystal oscillation circuit output
72 XV

SS

GND for master clock
73 AV

SS

– – Analog GND
74 LOUT2 O Right-channel LINE output
75 AIN2 I Right-channel operational amplifier input
76 AOUT2 O Right-channel analog output
77 AV

DD

– – Analog power supply (+5V)
78 AV

SS

– – Analog GND
79 XRST I System reset. Reset when low
80 V

DD

– – Power supply (+5V)

Notes) • PCMD is an MSB first, two’s complement output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window open.)

• XUGF is the frame sync obtained from the EFM signal, and a negative pulse. It is the signal before sync protection.

• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK and the EFM
signal transition point coincide.

• GFS goes high when the frame sync and the insertion protection timing match.

• RFCK is derived with the crystal accuracy. This signal has a cycle of 136µs (during normal speed).

• C2PO represents the data error status.

• XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin.

11

CXP83232A/83240A
CMOS 8-bit Single Chip Microcomputer

BLOCK DIAGRAM

100 pin QFP (Plastic) 100 pin LQFP (Plastic)

10

CXA2542AQ
RF Signal Processing Servo Amplifier for CD Player

BLOCK DIAGRAM

48 pin QFP (Plastic)

12

PIN ASSIGNMENTS

Note) 1. NC(Pin 90) is always connected to VDD.

2. V

SS (Pin 41 and 91) are both connected to GND.

MICOM DATA (TUNER)

13

OVERVIEW

The KS57C3316 single-chip CMOS microcontroller has been designed for high performance using
Samsung’s newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).

With features such as LCD direct capability, 4-channel A/D converter, 8-bit timer/counter, watch timer and
PLL frequency synthesizer, it offers you an excellent design solution for a wide variety of applications that
require LCD functions and audio applications.

Up to 56 pins of the 80-pin QFP package, it can be dedicated to I/O. Eight vectored interrupts provide fast
response to internal and external events. In addition, the KS57C3316’s advanced CMOS technology
provides for low power consumption and a wide operating voltage range.

OTP

The KS57C3316 microcontroller is also available in OTP (One Time Programmable) version, KS57P3316.
The KS57P3316 microcontroller has an on-chip 16-Kbyte one-time-programmable EPROM instead of
masked ROM. The KS57P3316 is comparable to KS57C3316, both in function and in pin configuration.

BLOCK DIAGRAM

15

Program

StatusWord

Arithmetic

and

LogicUnit

InstructionDecoder

Internal

Interrupts

RESET

Interrupt

Control

Block

Instruction

Register

Clock

16K-Byte

ProgramMemory

512x4-Bit

DataMemory

Timer/

Counter0

XIN

XOUT

Program

Counter

I/OPort6

I/OPort5

Stack

Pointer

PLL

Synthesizer

LCDDriver/

Controller

Watchdog

Timer

Basic

Timer

A/D

Converter

P5.0/ADC0

P5.3/ADC3

P5.1/ADC1

P5.2/ADC2

Serial

I/OPort

I/OPort4

I/OPort3

I/OPort2

I/OPort0

OutputPort

7,8,9,10

OutputPort

11,12,13

IF

Counter

P4.0/

SCK

P4.3/CLO

P4.1/SO

P4.2/SI

P3.0

P3.3

P3.1

P3.2

P2.0

P2.3

P2.1

P2.2

P1.0/INT0

P1.3/INT4

P1.1/INT1

P1.2/INT2

P10.0-P10.3

/SEG12-SEG15

P7.0-P7.3

/SEG0-SEG3

P9.0-P9.3

/SEG8-SEG11

P8.0-P8.3

/SEG4-SEG7

P6.0-P6.3

KS0-KS3

P13.0-P13.3

/SEG24-SEG27

P12.0-P12.3

/SEG20-SEG23

P11.0-P11.3

/SEG16-SEG19

BIAS

VLC0-VLC2

COM0-COM3

VCOAM

VCOFM

EO

AMIF

FMIF

CE

XTIN

XTOUT

InputPort1

P0.0/BTCO

P0.3/BUZ

P0.1/TCLO0

P0.2/TCL0

Watch

Timer

INT0-INT4

FEATURES

Memory

• 512-nibble RAM

• 16K-byte ROM

I/O Pins

• Input only: 4 pins

• Output only: 28 pins

• I/O: 24 pins

LCD Controller/Driver

• Maximum 14-digit LCD direct drive capability

• 28 segment x 4 common signals

• Display modes: Static, 1/2 duty (1/2 bias)
1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)

8-Bit Basic Timer

• Programmable interval timer functions

• Watch-dog timer function

8-Bit Timer/Counter

• Programmable 8-bit timer

• External event counter

• Arbitrary clock frequency output

• External clock signal divider

• Serial I/O interface clock generator

Watch Timer

• Time interval generation
: 0.5 s, 3.9 ms at 32.768 kHz

• Frequency outputs to BUZ pin

• Clock source generation for LCD

8-Bit Serial I/O Interface

• 8-bit transmit/receive mode

• 8-bit receive mode

• Data direction selectable (LSB-first or MSB-first)

• Internal or external clock source

A/D Converter

• 4-channels with 8-bit resolution

Bit Sequential Carrier Buffer

• Support 16-bit serial data transfer in arbitrary
format

PLL Frequency Synthesizer

• Level=300 mVp-p (min)

• AMVCO range=0.5 MHz to 30 MHz

• FMVCO range=30 MHz to 150 MHz

16-Bit Intermediate Frequency (IF) Counter

• Level=300 mVp-p (min)

• AMIF rante=100 kHz to 1 MHz

• FMIF range=5 MHz to 15 MHz

Interrupts

• Four internal vectored interrupts

• Four external vectored interrupts

• Two quasi-interrupts

Memory-Mapped I/O Structure

• Data memory bank 15

Three Power-Down Modes

• Idle: Only CPU clock stops

• Stop1: Main system or subsystem clock stops

• Stop2: Main system and subsystem clock stop

• CE low: PLL and IFC stop

Oscillation Sources

• Crystal or ceramic oscillator for main system
clock

• Crystal for subsystem clock

• Main system clock frequency: 4.5 MHz (Typ)

• Subsystem clock frequency: 32.768 kHz (Typ)

• CPU clock divider circuit (by 4, 8, or 64)

Instruction Execution Times

• 0.9, 1.8, 14.2 µs at 4.5 MHz

• 122 µs at 32.768 kHz (subsystem)

Operating Temperature

• –40°C to 85°C

Operating Voltage Range

• 1.8V to 5.5V at 3 MHz

• PLL/IFC operation: 2.5V to 3.5V or 4.0V to 5.5V

Package Type

• 80-pin QFP

14

PIN ASSIGNMENTS

16

KS57C3316

(80-QFP-TopView)

P4.1/SO

P4.2/SI

P4.3/CLO
P5.0/ADC0
P5.1/ADC1
P5.2/ADC2
P5.3/ADC3

P6.0/KS0

P6.1/KS1

P6.2/KS2

P6.3/KS3

V

DD

0

V

SS

0

X

OUT

X

IN

TEST

XT

IN

XT

OUT

RESET

BIAS
VLC0
VLC1
VLC2

COM0

FMIF
AMIF
V

SS

1
VCOAM
VCOFM
P2.3
P2.2
P2.1
P2.0
SEG27/P13.3
SEG26/P13.2
SEG25/P13.1
SEG24/P13.0
SEG23/P12.3
SEG22/P12.2
SEG21/P12.1
SEG20/P12.0
SEG19/P11.3
SEG18/P11.2
SEG17/P11.1
SEG16/P11.0
SEG15/P10.3
SEG14/P10.2
SEG13/P10.1

656667686970717273747576777879

80

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

403938373635343332313029282726

25

SEG12/P10.0

SEG11/P9.3

SEG10/P9.2

SEG9/P9.1

SEG8/P9.0

SEG7/P8.3

SEG6/P8.2

SEG5/P8.1

SEG4/P8.0

SEG3/P7.3

SEG2/P7.2

SEG1/P7.1

SEG0/P7.0

COM3

COM2

COM1

V

DD1

E0

CE

P3.0

P3.1

P3.2

P3.3

P0.0/BTCO

P0.1/TCLO0

P0.2/TCL0

P0.3/BUZ

P1.0/INT0

P1.1/INT1

P1.2/INT2

P1.3/INT4

P4.0/

SCK

MICOM DATA (DECK)

17

SAM8 PRODUCT FAMILY (S3C8465)

Samsung’s new SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a
wide range of integrated peripherals, and various mask-programmable ROM sizes

A dual address/data bus architecture and a large number of bit-or nibble-configurable I/O ports provide a
flexible programming environment for applications with varied memory and I/O requirements.
Timer/counters with selectable operating modes are included to support real-time operations. Many SAM8
microcontrollers have an external interface that provides access to external memory and other peripheral
devices.

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be
assigned to one interrupt level at a time.

KS88C2416/C4632 MICROCONTROLLER (S3C8465)

The KS88C4616/C4632 single-chip 8-bit microcontroller is designed for useful 10-bit resolution A/D
converter, UART, SIO, ZCD extended PWM application field. Its powerful SAM87 CPU architecture
includes. The internal register file is logically expanded to increase the on-chip register space.

The KS88C4616/C4632 has 16/32 K bytes of on-chip program ROM. A sophisticated bus interface enables
access to external memory and other peripherals when you use the chip in ROM-less mode. Following
Samsung’s modular design approach, the following peripherals are integrated with the SAM87 core:

– Large number of programmable I/O ports (total 56 pins)
– One asynchronous UART module
– One synchronous SIO module
– Analog-to-digital converter with eight input channels and 10-bit resolution
– One 8-bit basic timer for watchdog function
– One 8-bit timer/counter with three operating modes (timer 0)
– One 8-bit timer for zero-cross detection circuit (timer 2)
– Two general-purpose 16-bit timer/counters with four operating modes (timer module 1)
– PWM block with one capture module, 16-bit timer/counter, PWM extension mode, and two PWM outputs
– One zero cross detection module

The KS88C4616/C4632 is a versatile general-purpose microcontroller that is ideal for use in a wide range
of electronics applications requiring complex timer/counter, PWM, capture, SIO, UART and ZCD functions.
It is available in a 64-pin SDIP or 64-pin QFP package.

OTP

The KS88P4632 is an OTP (One Time Programmable) version of the KS88C4616/C4632 microcontroller.
The KS88P4632 microcontroller has an on-chip 32-Kbyte one-time-programmable EPROM instead of a
masked ROM. The KS88P4632 is comparable to the KS88C4616/C4632, both in function and in pin
configuration.