Datasheet TN28F001BX-T90 Datasheet (Intel Corporation)

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1-MBIT (128K x 8)

BOOT BLOCK FLASH MEMORY

28F001BX-T/28F001BX-B/28F001BN-T/28F001BN-B

High-Integration Blocked Architecture Ð One 8 KB Boot Block w/Lock Out Ð Two 4 KB Parameter Blocks Ð One 112 KB Main Block

100,000 Erase/Program Cycles Per Block

Simplified Program and Erase Ð Automated Algorithms via On-Chip

Write State Machine (WSM)

SRAM-Compatible Write Interface

Deep Power-Down Mode Ð 0.05 mAI

Typical

Ð 0.8 mAI

Typical

12.0Vg5% V

High-Performance Read Ð 70/75 ns, 90 ns, 120 ns, 150 ns

Maximum Access Time

Ð 5.0V

10% V

Hardware Data Protection Feature Ð Erase/Write Lockout during Power

Transitions

Advanced Packaging, JEDEC Pinouts Ð 32-Pin PDIP Ð 32-Lead PLCC, TSOP

ETOXTMII Nonvolatile Flash Technology Ð EPROM-Compatible Process Base Ð High-Volume Manufacturing

Experience

Extended Temperature Options

Intel’s 28F001BX-B and 28F001BX-T combine the cost-effectiveness of Intel standard flash memory with features that simplify write and allow block erase. These devices aid the system designer by combining the functions of several components into one, making boot block flash an innovative alternative to EPROM and EEPROM or battery-backed static RAM. Many new and existing designs can take advantage of the 28F001BX’s integration of blocked architecture, automated electrical reprogramming, and standard processor interface.

The 28F001BX-B and 28F001BX-T are 1,048,576 bit nonvolatile memories organized as 131,072 bytes of 8 bits. They are offered in 32-pin plastic DIP, 32-lead PLCC and 32-lead TSOP packages. Pin assignment conform to JEDEC standards for byte-wide EPROMs. These devices use an integrated command port and state machine for simplified block erasure and byte reprogramming. The 28F001BX-T’s block locations provide compatibility with microprocessors and microcontrollers that boot from high memory, such as Intel’s MCS

-186 family, 80286, i386TM, i486TM, i860TMand 80960CA. With exactly the same memory segmentation, the 28F001BX-B memory map is tailored for microprocessors and microcontrollers that boot from low memory, such as Intel’s MCS-51, MCS-196, 80960KX and 80960SX families. All other features are identical, and unless otherwise noted, the term 28F001BX can refer to either device throughout the remainder of this document.

The boot block section includes a reprogramming write lock out feature to guarantee data integrity. It is designed to contain secure code which will bring up the system minimally and download code to the other locations of the 28F001BX. Intel’s 28F001BX employs advanced CMOS circuitry for systems requiring highperformance access speeds, low power consumption, and immunity to noise. Its access time provides no-WAIT-state performance for a wide range of microprocessors and microcontrollers. A deep-powerdown mode lowers power consumption to 0.25 mW typical through V

, crucial in laptop computer, handheld instru-

mentation and other low-power applications. The RP

power control input also provides absolute data protec-

tion during system powerup or power loss.

Manufactured on Intel’s ETOX process base, the 28F001BX builds on years of EPROM experience to yield the highest levels of quality, reliability, and cost-effectiveness.

NOTE: The 28F001BN is equivalent to the 28F001BX.

28F001BX-T/28F001BX-B

290406– 1

Figure 1. 28F001BX Block Diagram

Table 1. Pin Description

Symbol Type Name and Function

A0–A

INPUT ADDRESS INPUTS for memory addresses. Addresses are internally latched during

a write cycle.

DQ0–DQ7INPUT/ DATA INPUTS/OUTPUTS: Inputs data and commands during memory write

cycles; outputs data during memory, Status Register and Identifier read cycles. The

OUTPUT

data pins are active high and float to tri-state off when the chip is deselected or the outputs are disabled. Data is internally latched during a write cycle.

INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and

sense amplifiers. CE

is active low; CEÝhigh deselects the memory device and

reduces power consumption to standby levels.

INPUT POWERDOWN: Puts the device in deep powerdown mode. RPÝis active low;

high gates normal operation. RP

VHHallows programming of the boot

block. RP

also locks out erase or write operations when active low, providing data protection during power transitions. RPÝactive resets internal automation. Exit from deep powerdown sets device to Read Array mode.

INPUT OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a

read cycle. OE

is active low. OE

VHH(pulsed) allows programming of the

boot block.

INPUT WRITE ENABLE: Controls writes to the Command Register and array blocks. WE

is active low. Addresses and data are latched on the rising edge of the WEÝpulse.

ERASE/PROGRAM POWER SUPPLY for erasing blocks of the array or programming bytes of each block. Note: With V

PPL

max, memory contents

cannot be altered.

DEVICE POWER SUPPLY: (5Vg10%)

GND GROUND

28F001BX-T/28F001BX-B

28F010

GND

290406– 2

28F010

Figure 2. DIP Pin Configuration

28F010

290406– 3

28F010

GND

Figure 3. TSOP Lead Configuration

28F001BX-T/28F001BX-B

290406– 4

Figure 4. PLCC Lead Configuration

APPLICATIONS

The 28F001BX flash ‘boot block’ memory augments the non-volatility, in-system electrical erasure and reprogrammability of Intel’s standard flash memory by offering four separately erasable blocks and integrating a state machine to control erase and program functions. The specialized blocking architecture and automated programming of the 28F001BX provide a full-function, non-volatile flash memory ideal for a wide range of applications, including PC boot/BIOS memory, minimum-chip embedded program memory and parametric data storage. The 28F001BX combines the safety of a hardware-protected 8-KByte boot block with the flexibility of three separately reprogrammable blocks (two 4-KByte parameter blocks and one 112-KByte code block) into one versatile, cost-effective flash memory. Additionally, reprogramming one block does not affect code stored in another block, ensuring data integrity.

The flexibility of flash memory reduces costs throughout the life cycle of a design. During the early stages of a system’s life, flash memory reduces prototype development and testing time, allowing the system designer to modify in-system software electrically versus manual removal of components. During production, flash memory provides flexible firmware for just-in-time configuration, reducing system inventory and eliminating unnecessary handling and less reliable socketed connections. Late in the life cycle, when software updates or code ‘‘bugs’’ are often unpredictable and costly, flash memory reduces update costs by allowing the manufacturers to send floppy updates versus a technician. Alternatively, remote updates over a communication link are possible at speeds up to 9600 baud due to flash memory’s fast programming time.

28F001BX-T/28F001BX-B

Reprogrammable environments, such as the personal computer, are ideal applications for the 28F001BX. The internal state machine provides SRAM-like timings for program and erasure, using the Command and Status Registers. The blocking scheme allows BIOS update in the main and parameter blocks, while still providing recovery code in the boot block in the unlikely event a power failure occurs during an update, or where BIOS code is corrupted. Parameter blocks also provide convenient configuration storage, backing up SRAM and battery configurations. EISA systems, for example, can store hardware configurations in a flash parameter block, reducing system SRAM.

Laptop BIOSs are becoming increasingly complex with the addition of power management software and extended system setup screens. BIOS code complexity increases the potential for code updates after the sale, but the compactness of laptop designs makes hardware updates very costly. Boot block flash memory provides an inexpensive update solution for laptops, while reducing laptop obsolescence. For portable PCs and hand-held equipment, the deep powerdown mode dramatically lowers sys-

tem power requirements during periods of slow operation or sleep modes.

The 28F001BX gives the embedded system designer several desired features. The internal state machine reduces the size of external code dedicated to the erase and program algorithms, as well as freeing the microcontroller or microprocessor to respond to other system requests during program and erasure. The four blocks allow logical segmentation of the entire embedded software: the 8-KByte block for the boot code, the 112-KByte block for the main program code and the two 4-KByte blocks for updatable parametric data storage, diagnostic messages and data, or extensions of either the boot code or program code. The boot block is hardware protected against unauthorized write or erase of its vital code in the field. Further, the powerdown mode also locks out erase or write operations, providing absolute data protection during system powerup or power loss. This hardware protection provides obvious advantages for safety related applications such as transportation, military, and medical. The 28F001BX is well suited for minimum-chip embedded applications ranging from communications to automotive.

290406– 5

Figure 5. 28F001BX-T in a 80C188 System

290406– 6

Figure 6. 28F001BX-B in a 80C51 System

28F001BX-T/28F001BX-B

PRINCIPLES OF OPERATION

The 28F001BX introduces on-chip write automation to manage write and erase functions. The write state machine allows for 100% TTL-level control inputs, fixed power supplies during erasure and programming, minimal processor overhead with RAM-like write timings, and maximum EPROM compatiblity.

After initial device powerup, or after return from deep powerdown mode (see Bus Operations), the 28F001BX functions as a read-only memory. Manipulation of external memory-control pins yield standard EPROM read, standby, output disable or Intelligent Identifier operations. Both Status Register and Intelligent Identifiers can be accessed through the Command Register when V

PPL

This same subset of operations is also available when high voltage is applied to the V

pin. In addi-

tion, high voltage on V

enables successful erasure and programming of the device. All functions associated with altering memory contentsÐprogram, erase, status, and inteligent IdentifierÐare accessed via the Command Register and verified through the Status Register.

Commands are written using standard microprocessor write timings. Register contents serve as input to the WSM, which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for programming or erase operations. With the appropriate command written to the register, standard microprocessor read timings output array data, access the intelligent identifier codes, or output program and erase status for verification.

Interface software to initiate and poll progress of internal program and erase can be stored in any of the 28F001BX blocks. This code is copied to, and executed from, system RAM during actual flash memory update. After successful completion of program and/or erase, code execution out of the 28F001BX is again possible via the Read Array command. Erase suspend/resume capability allows system software to suspend block erase and read data/execute code from any other block.

Command Register and Write Automation

An on-chip state machine controls block erase and byte program, freeing the system processor for other tasks. After receiving the erase setup and erase confirm commands, the state machine controls block pre-conditioning and erase, returning progress via the Status Register. Programming is similarly controlled, after destination address and expected data are supplied. The program algorithm of past Intel Flash Memories is now regulated by the state machine, including program pulse repetition where required and internal verification and margining of data.

Data Protection

Depending on the application, the system designer may choose to make the V

power supply switchable (available only when memory updates are required) or hardwired to V

PPH

. When V

PPL

, memory contents cannot be altered. The 28F001BX Command Register architecture provides protection from unwanted program or erase operations even when high voltage is applied to V

. Additionally, all

functions are disabled whenever V

is below the

write lockout voltage V

LKO

, or when RPÝis at VIL. The 28F001BX accommodates either design practice and encourages optimization of the processormemory interface.

The two-step program/erase write sequence to the Command Register provides additional software write protection.

1FFFF

8-KByte BOOT BLOCK

1DFFF

1E000

4-KByte PARAMETER BLOCK

1CFFF

1D000

4-KByte PARAMETER BLOCK

1BFFF

1C000

112-KByte MAIN BLOCK

00000

Figure 7. 28F001BX-T Memory Map

1FFFF

112-KByte MAIN BLOCK

03FFF

04000

4-KByte PARAMETER BLOCK

02FFF

03000

4-KByte PARAMETER BLOCK

01FFF

02000

8-KByte BOOT BLOCK

00000

Figure 8. 28F001BX-B Memory Map

28F001BX-T/28F001BX-B

BUS OPERATION

Flash memory reads, erases and writes in-system via the local CPU. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.

Read

The 28F001BX has three read modes. The memory can be read from any of its blocks, and information can be read from the Intelligent Identifier or the Status Register. V

can be at either V

PPL

or V

PPH

The first task is to write the appropriate read mode command to the Command Register (array, Intelligent Identifier, or Status Register). The 28F001BX automatically resets to Read Array mode upon initial device powerup or after exit from deep powerdown. The 28F001BX has four control pins, two of which must be logically active to obtain data at the outputs. Chip Enable (CE

) is the device selection control, and when active enables the selected memory device. Output Enable (OE

) is the data input/output

(DQ

–DQ7) direction control, and when active drives data from the selected memory onto the I/O bus. RP

and WEÝmust also be at VIH. Figure 12

illustrates read bus cycle waveforms.

Output Disable

With OEÝat a logic-high level (VIH), the device outputs are disabled. Output pins (DQ

–DQ7) are

placed in a high-impedance state.

Standby

CEÝat a logic-high level (VIH) places the 28F001BX in standby mode. Standby operation disables much of the 28F001BX’s circuitry and substantially reduces device power consumption. The outputs (DQ

–

) are placed in a high-impedance state indepen-

dent of the status of OE

. If the 28F001BX is deselected during erase or program, the device will continue functioning and consuming normal active power until the operation is completed.

Deep Power-Down

The 28F001BX offers a 0.25 mWVCCpower-down feature, entered when RP

is at VIL. During read

modes, RP

low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. The 28F001BX requires time t

PHQV

(see AC Characteristics-Read Only Operations) after return from power-down until initial memory access outputs are valid. After this wakeup interval, normal operation is restored. The Command Register is reset to Read Array, and the Status Register is cleared to value 80H, upon return to normal operation.

During erase or program modes, RP

low will abort either operation. Memory contents of the block being altered are no longer valid as the data will be partially programmed or erased. Time t

PHWL

after

goes to logic-high (VIH) is required before an-

other command can be written.

Table 2. 28F001BX Bus Operations

Mode Notes RPÝCEÝOEÝWEÝA9A0V

0–7

Read 1, 2, 3 V

XX X D

OUT

Output Disable 2 V

X X X High Z

Standby 2 V

X X X X X High Z

Deep Power Down 2 V

X X X X X X High Z

Intelligent Identifier (Mfr) 2, 3, 4 V

VIDV

X 89H

Intelligent Identifier (Device) 2, 3, 4, 5 V

VIDV

X 94H, 95H

Write 2, 6, 7, 8 V

XX X D

NOTES:

1. Refer to DC Characteristics. When V

PPL

, memory contents can be read but not programmed or erased.

2. X can be V

or VIHfor control pins and addresses, and V

PPL

or V

PPH

for VPP.

3. See DC Characteristics for V

PPL,VPPH,VHH

and VIDvoltages.

4. Manufacturer and device codes may also be accessed via a Command Register write sequence. Refer to Table 3. A

1–A8

10–A16

VIL.

5. Device ID

94H for the 28F001BX-T and 95H for the 28F001BX-B.

6. Command writes involving block erase or byte program are successfully executed only when V

PPH

7. Refer to Table 3 for valid D

during a write operation.

8. Program or erase the boot block by holding RP

at VHHor toggling OEÝto VHH. See AC Waveforms for program/erase

operations.

28F001BX-T/28F001BX-B

The use of RPÝduring system reset is important with automated write/erase devices. When the system comes out of reset it expects to read from the flash memory. Automated flash memories provide status information when accessed during write/ erase modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization would not occur because the flash memory would be providing the status information instead of array data. Intel’s Flash Memories allow proper CPU initialization following a system reset through the use of the RP

input. In this application RPÝis controlled by the same RESET

signal that resets the system CPU.

Intelligent Identifier Operation

The Intelligent Identifier operation outputs the manufacturer code, 89H; and the device code, 94H for the 28F001BX-T and 95H for the 28F001BX-B. Programming equipment or the system CPU can then automatically match the device with its proper erase and programming algorithms.

PROGRAMMING EQUIPMENT

and OEÝat a logic low level (VIL), with A9at

high voltage V

(see DC Characteristics) activates this operation. Data read from locations 00000H and 00001H represent the manufacturer’s code and the device code respectively.

IN-SYSTEM PROGRAMMING

The manufacturer- and device-codes can also be read via the Command Register. Following a write of 90H to the Command Register, a read from address location 00000H outputs the manufacturer code (89H). A read from address 00001H outputs the device code (94H for the 28F001BX-T and 95H for the 28F001BX-B). It is not necessary to have high voltage applied to V

to read the Intelligent Identifiers

from the Command Register.

Write

Writes to the Command Register allow read of device data and Intelligent Identifiers. They also control inspection and clearing of the Status Register. Additionally, when V

PPH

, the Command Register controls device erasure and programming. The contents of the register serve as input to the internal state machine.

The Command Register itself does not occupy an addressable memory location. The register is a latch used to store the command and address and data information needed to execute the command. Erase

Setup and Erase Confirm commands require both appropriate command data and an address within the block to be erased. The Program Setup Command requires both appropriate command data and the address of the location to be programmed, while the Program command consists of the data to be written and the address of the location to be programmed.

The Command Register is written by bringing WE

to a logic-low level (VIL) while CEÝis low. Addresses and data are latched on the rising edge of WE

Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the AC Waveform for Write Operations, Figure 13, for specific timing parameters.

COMMAND DEFINITIONS

When V

PPL

is applied to the VPPpin, read operations from the Status Register, intelligent identifiers, or array blocks are enabled. Placing V

PPH

on V

enables successful program and erase operations as well.

Device operations are selected by writing specific commands into the Command Register. Table 3 defines these 28F001BX commands.

Read Array Command

Upon initial device powerup and after exit from deep-powerdown mode, the 28F001BX defaults to Read Array mode. This operation is also initiated by writing FFH into the Command Register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the Command Register contents are altered. Once the internal write state machine has started an erase or program operation, the device will not recognize the Read Array command, until the WSM has completed its operation. The Read Array command is functional when V

PPL

or V

PPH

Intelligent Identifier Command for In-System Programming

The 28F001BX contains an Intelligent Identifier operation to supplement traditional PROM-programming methodology. The operation is initiated by writing 90H into the Command Register. Following the command write, a read cycle from address 00000H retrieves the manufacturer code of 89H. A read cycle from address 00001H returns the device code of 94H (28F001BX-T) or 95H (28F001BX-B). To terminate the operation, it is necessary to write another valid command into the register. Like the Read Array command, the Intelligent Identifier command is functional when V

PPL

or V

PPH

28F001BX-T/28F001BX-B

Table 3. 28F001BX Command Definitions

Command Cycles

Req’d

Bus

Notes

First Bus Cycle Second Bus Cycle

Operation Address Data Operation Address Data

Read Array/Reset 1 1 Write X FFH

Intelligent Identifier 3 2, 3, 4 Write X 90H Read IA IID

Read Status Register 2 3 Write X 70H Read X SRD

Clear Status Register 1 Write X 50H

Erase Setup/Erase Confirm 2 2 Write BA 20H Write BA D0H

Erase Suspend/Erase Resume 2 Write X B0H Write X D0H

Program Setup/Program 2 2, 3 Write PA 40H Write PA PD

NOTES:

1. Bus operations are defined in Table 2.

2. IA

Identifier Address: 00H for manufacturer code, 01H for device code.

Address within the block being erased.

Address of memory location to be programmed.

3. SRD

Data read from Status Register. See Table 4 for a description of the Status Register bits.

Data to be programmed at location PA. Data is latched on the rising edge of WEÝ.

IID

Data read from Intelligent Identifiers.

4. Following the Intelligent Identifier command, two read operations access manufacture and device codes.

5. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.

Read Status Register Command

The 28F001BX contains a Status Register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. The Status Register may be read at any time by writing the Read Status Register command (70H) to the Command Register. After writing this command, all subsequent read operations output data from the Status Register, until another valid command is written to the Command Register. The contents of the Status Register are latched on the falling edge of OE

or CEÝ, which-

ever occurs last in the read cycle. OE

or CE

must be toggled to VIHbefore further reads to update the Status Register latch. The Read Status Register command functions when V

PPL

PPH

Clear Status Register Command

The Erase Status and Program Status bits are set to ‘‘1’’ by the Write State Machine and can only be

reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 4). By allowing system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in sequence). The Status Register may then be polled to determine if an error occurred during that series. This adds flexibility to the way the device may be used.

Additionally, the V

Status bit (SR.3), when set to ‘‘1’’, MUST be reset by system software before further byte programs or block erases are attempted. To clear the Status Register, the Clear Status Register command (50H) is written to the Command Register. The Clear Status Register command is functional when V

PPL

or V

PPH

28F001BX-T/28F001BX-B

Table 4. 28F001BX Status Register Definitions

WSMS ESS ES PS VPPS R R R

76543210

SR.7eWRITE STATE MACHINE STATUS

Ready

Busy

SR.6

ERASE SUSPEND STATUS

Erase Suspended

Erase In Progress/Completed

SR.5

ERASE STATUS

Error in Block Erasure

Successful Block Erase

SR.4

PROGRAM STATUS

Error in Byte Program

Successful Byte Program

SR.3

VPPSTATUS

VPPLow Detect; Operation Abort

VPPOK

SR.2–SR.0

RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use and should be masked out when polling the Status Register.

NOTES:

The Write State Machine Status Bit must first be checked to determine program or erase completion, before the Program or Erase Status bits are checked for success.

If the Program AND Erase Status bits are set to ‘‘1s’’ during an erase attempt, an improper command sequence was entered. Attempt the operation again.

If V

low status is detected, the Status Register must be cleared before another program or erase operation is attempted.

The V

Status bit, unlike an A/D converter, does not

provide continuous indication of V

level. The WSM in-

terrogates the V

level only after the program or erase command sequences have been entered and informs the system if V

has not been switched on. The VPPStatus bit is not guaranteed to report accurate feedback between V

PPL

and V

PPH

Erase Setup/Erase Confirm Commands

Erase is executed one block at a time, initiated by a two-cycle command sequence. An Erase Setup command (20H) is first written to the Command Register, followed by the Erase Confirm command (D0H). These commands require both appropriate command data and an address within the block to be erased. Block preconditioning, erase and verify are all handled internally by the Write State Machine, invisible to the system. After receiving the two-command erase sequence, the 28F001BX automatically outputs Status Register data when read (see Figure 10; Block Erase Flowchart). The CPU can detect the completion of the erase event by checking the WSM Status bit of the Status Register (SR.7).

When the Status Register indicates that erase is complete, the Erase Status bit should be checked. If erase error is detected, the Status Register should be cleared. The Command Register remains in Read Status Register Mode until further commands are issued to it.

This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, block erasure can only occur when V

PPH

. In the absence of this high voltage, memory contents are protected against erasure. If block erase is attempted while V

PPL

the V

Status bit will be set to ‘‘1’’. Erase attempts

while V

PPL

PPH

produce spurious results

and should not be attempted.

Erase Suspend/Erase Resume Commands

The Erase Suspend Command allows erase sequence interruption in order to read data from another block of memory. Once the erase sequence is started, writing the Erase Suspend command (B0H) to the Command Register requests that the WSM suspend the erase sequence at a predetermined point in the erase algorithm. The 28F001BX continues to output Status Register data when read, after the Erase Suspend command is written to it. Polling the WSM Status and Erase Suspend Status bits will determine when the erase operation has been suspended (both will be set to ‘‘1s’’).

At this point, a Read Array command can be written to the Command Register to read data from blocks other than that which is suspended. The only other valid commands at this time are Read Status Register (70H) and Erase Resume (D0H), at which time the WSM will continue with the erase sequence. The Erase Suspend Status and WSM Status bits of the Status Register will be cleared. After the Erase Resume command is written to it, the 28F001BX automatically outputs Status Register data when read (see Figure 11; Erase Suspend/Resume Flowchart).

28F001BX-T/28F001BX-B

Program Setup/Program Commands

Programming is executed by a two-write sequence. The program Setup command (40H) is written to the Command Register, followed by a second write specifying the address and data (latched on the rising edge of WE

) to be programmed. The WSM then takes over, controlling the program and verify algorithms internally. After the two-command program sequence is written to it, the 28F001BX automatically outputs Status Register data when read (see Figure 9; Byte Program Flowchart). The CPU can detect the completion of the program event by analyzing the WSM Status bit of the Status Register. Only the Read Status Register command is valid while programming is active.

When the Status Register indicates that programming is complete, the Program Status bit should be checked. If program error is detected, the Status Register should be cleared. The internal WSM verify only detects errors for ‘‘1s’’ that do not successfully program to ‘‘0s’’. The Command Register remains in Read Status Register mode until further commands are issued to it. If byte program is attempted while V

PPL

, the VPPStatus bit will be set to ‘‘1’’.

Program attempts while V

PPL

PPH

pro-

duce spurious results and should not be attempted.

EXTENDED ERASE/PROGRAM CYCLING

EEPROM cycling failures have always concerned users. The high electrical field required by thin oxide EEPROMs for tunneling can literally tear apart the oxide at defect regions. To combat this, some suppliers have implemented redundancy schemes, reducing cycling failures to insignificant levels. However, redundancy requires that cell size be doubled; an expensive solution.

Intel has designed extended cycling capability into its ETOX flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell size or complexity. First, an advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell subjected to the tunneling electrical field is onetenth that of common EEPROMs, minimizing the probability of oxide defects in the region. Finally, the peak electric field during erasure is approximately 2 Mv/cm lower than EEPROM. The lower electric field greatly reduces oxide stress and the probability of failure.

The 28F001BX-B and 28F001BX-T are capable of 100,000 program/erase cycles on each parameter block, main block and boot block.

ON-CHIP PROGRAMMING ALGORITHM

The 28F001BX integrates the Quick Pulse programming algorithm of prior Intel Flash Memory devices on-chip, using the Command Register, Status Register and Write State Machine (WSM). On-chip integration dramatically simplifies system software and provides processor-like interface timings to the Command and Status Registers. WSM operation, internal program verify and V

high voltage presence are monitored and reported via appropriate Status Register bits. Figure 9 shows a system software flowchart for device programming. The entire sequence is performed with VPPat V

PPH

. Program

abort occurs when RP

transitions to VIL,orV

drops to V

PPL

. Although the WSM is halted, byte data is partially programmed at the location where programming was aborted. Block erasure or a repeat of byte programming will initialize this data to a known value.

ON-CHIP ERASE ALGORITHM

As above, the Quick Erase algorithm of prior Intel Flash Memory devices is now implemented internally, including all preconditioning of block data. WSM operation, erase success and V

high voltage presence are monitored and reported through the Status Register. Additionally, if a command other than Erase Confirm is written to the device after Erase Setup has been written, both the Erase Status and Program Status bits will be set to ‘‘1’’. When issuing the Erase Setup and Erase Confirm commands, they should be written to an address within the address range of the block to be erased. Figure 10 shows a system software flowchart for block erase.

Erase typically takes 1 –4 seconds per block. The Erase Suspend/Erase Resume command sequence allows interrupt of this erase operation to read data

from a block other than that in which erase is being performed. A system software flowchart is

shown in Figure 11.

The entire sequence is performed with V

at V

PPH

Abort occurs when RP

transitions to VILor V

falls to V

PPL

, while erase is in progress. Block data is partially erased by this operation, and a repeat of erase is required to obtain a fully erased block.

28F001BX-T/28F001BX-B

BOOT BLOCK PROGRAM AND ERASE

The boot block is intended to contain secure code which will minimally bring up a system and control programming and erase of other blocks of the device, if needed. Therefore, additional ‘‘lockout’’ protection is provided to guarantee data integrity. Boot block program and erase operations are enabled through high voltage V

on either RPÝor OEÝ, and the normal program and erase command sequences are used. Reference the AC Waveforms for Program/Erase.

If boot block program or erase is attempted while RP

is at VIH, either the Program Status or Erase

Status bit will be set to ‘‘1’’, reflective of the opera-

tion being attempted and indicating boot block lock. Program/erase attempts while V

produce spurious results and should not be attempted.

In-System Operation

For on-board programming, the RP

pin is the most convenient means of altering the boot block. Before issuing Program or Erase confirms commands, RP

must transition to VHH. Hold RPÝat this high voltage throughout the program or erase interval (until after Status Register confirm of successful completion). At this time, it can return to V

or VIL.

290406– 7

Bus

Command Comments

Operation

Write Program Datae40H

Setup Address

Byte to be

Programmed

Write Program Data to be programmed

Address

Byte to be

Programmed

Read Status Register Data.

Toggle OE

or CEÝto

update Status Register

Standby Check SR.7

Ready, 0eBusy

Repeat for subsequent bytes.

Full status check can be done after each byte or after a sequence of bytes.

Write FFH after the last byte programming operation to reset the device to Read Array Mode.

Bus

Command Comments

Operation

Standby Check SR.3

VPPLow Detect

Standby Check SR.4

Byte Program Error

SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine.

SR.4 is only cleared by the Clear Status Register Command, in cases where multiple bytes are programmed before full status is checked.

If error is detected, clear the Status Register before attempting retry or other error recovery.

Figure 9. 28F001BX Byte Programming Flowchart

28F001BX-T/28F001BX-B

290406– 8

Bus

Command Comments

Operation

Write Erase Datae20H

Setup Address

Within Block to be erased

Write Erase Data

D0H

Address

Within Block to be erased

Read Status Register Data.

Toggle OE

or CEÝto update Status

Standby Check SR.7

Ready, 0eBusy

Repeat for subsequent blocks.

Full status check can be done after each block or after a sequence of blocks.

Write FFH after the last block erase operation to reset the device to Read Array Mode.

Bus

Command Comments

Operation

Standby Check SR.3

VPPLow Detect

Standby Check SR.4, 5

Both 1

Command Sequence Error

Standby Check SR.5

Block Erase Error

SR.3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine.

SR.5 is only cleared by the Clear Status Register Command, in cases where multiple blocks are erased before full status is checked.

If error is detected, clear the Status Register before attempting retry or other error recovery.

Figure 10. 28F001BX Block Erase Flowchart

28F001BX-T/28F001BX-B

290406– 9

Bus

Command Comments

Operation

Write Erase DataeB0H

Suspend

Write Erase Datae70H

Status Register

Standby/ Read Status Register

Read Check SR.7

Ready, 0eBusy

Toggle OE

or CEÝto

Update Status Register

Standby Check SR.6

Suspended

Write Read Array DataeFFH

Read Read array data from

block other than that being erased.

Write Erase Resume Data

D0H

Figure 11. 28F001BX Erase Suspend/Resume Flowchart

Programming Equipment

For PROM programming equipment that cannot bring RP

to high voltage, OEÝprovides an alter-

nate boot block access mechanism. OE

must tran-

sition to V

a minimum of 480 ns before the initial

program/erase setup command and held at V

at least 480 ns after program or erase confirm commands are issued to the device. After this interval, OE

can return to normal TTL levels.

DESIGN CONSIDERATIONS

Three-Line Output Control

Flash memories are often used in larger memory arrays. Intel provides three control inputs to accommo-

date multiple memory connections. Three-line control provides for:

a) lowest possible memory power dissipation

b) complete assurance that data bus contention will

not occur

To efficiently use these control inputs, an address decoder should enable CE

, while OEÝshould be connected to all memory devices and the system’s READ

control line. This assures that only selected memory devices have active outputs while deselected memory devices are in Standby Mode. RP

should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.

28F001BX-T/28F001BX-B

Power Supply Decoupling

Flash memory power switching characteristics require careful device coupling. System designers are interested in 3 supply current issues; standby current levels (I

), active current levels (ICC) and transient

peaks producted by falling and rising edges of CE

. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 mF ceramic capacitor connected between its V

and GND, and between its VPPand GND. These high frequency, low inherent-inductance capacitors should be placed as close as possible to the device. Additionally, for every 8 devices, a 4.7 mF electrolytic capacitor should be placed at the array’s power supply connection between V

and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.

VPPTrace on Printed Circuit Boards

Programming flash memories, while they reside in the target system, requires that the printed circuit board designer pay attention to the V

power sup-

ply trace. The V

pin supplies the memory cell current for programming. Use similar trace widths and layout considerations given to the V

power bus.

Adequate V

supply traces and decoupling will de-

crease V

voltage spikes and overshoots.

VCC,VPP,RPÝTransitions and the Command/Status Registers

Programming and erase completion are not guaranteed if V

drops below V

PPH

. If the VPPStatus bit of the Status Register (SR.3) is set to ‘‘1’’, a Clear Status Register command MUST be issued before further program/erase attempts are allowed by the WSM. Otherwise, the Program (SR.4) or Erase (SR.5) Status bits of the Status Register will be set to ‘‘1’’ if error is detected. RP

transitions to V

during program and erase also abort the operations. Data is partially altered in either case, and the command sequence must be repeated after normal operation is restored. Device poweroff, or RP

tran-

sitions to V

, clear the Status Register to initial val-

ue 80H.

The Command Register latches commands as issued by system software and is not altered by V

or CEÝtransitions or WSM actions. Its state upon powerup, after exit from Deep-Powerdown or after V

transitions below V

LKO

, is FFH, or Read Array

Mode.

After program or erase is complete, even after V

transitions down to V

PPL

, the Command Register must be reset to read array mode via the Read Array command if access to the memory array is desired.

Power Up/Down Protection

The 28F001BX is designed to offer protection against accidental erasure or programming during power transitions. Upon power-up, the 28F001BX is indifferent as to which power supply, V

or VCC, powers up first. Power supply sequencing is not required. Internal circuitry in the 28F001BX ensures that the Command Register is reset to Read Array mode on power up.

A system designer must guard against spurious writes for V

voltages above V

LKO

when VPPis

active. Since both WE

and CEÝmust be low for a

command write, driving either to V

will inhibit writes. The Command Register architecture provides an added level of protection since alteration of memory contents only occurs after successful completion of the two-step command sequences.

Finally, the device is disabled, until RP

is brought

to V

, regardless of the state of its control inputs.

This provides an additional level of protection.

28F001BX Power Dissipation

When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash nonvolatility increases usable battery life because the 28F001BX does not consume any power to retain code or data when the system is off.

In addition, the 28F001BX’s Deep-Powerdown mode ensures extremely low power dissipation even when system power is applied. For example, laptop and other PC applications, after copying BIOS to DRAM, can lower RP

to VIL, producing negligible power consumption. If access to the boot code is again needed, as in case of a system RESET

, the part

can again be accessed, following the t

PHAV

wakeup

cycle required after RP

is first raised back to VIH. The first address presented to the device while in powerdown requires time t

PHAV

, after RPÝtransitions high, before outputs are valid. Further accesses follow normal timing. See AC CharacteristicsÐRead-Only Operations and Figure 12 for more information.

28F001BX-T/28F001BX-B

ABSOLUTE MAXIMUM RATINGS*

Operating Temperature

During Read АААААААААААААААААААА0

Cto70§C

(1)

During Erase/Program ААААААААААА0§Cto70§C

(1)

Operating Temperature

During Read ААААААААААААААА

40§Ctoa85§C

(2)

During Erase/Program ААААААb40§Ctoa85§C

(2)

Temperature under Bias АААААААААb10§Cto80§C

(1)

Temperature under Bias АААААААb20§Ctoa90§C

(2)

Storage TemperatureАААААААААААААb65§Cto125§C

Voltage on Any Pin

(except A

,RPÝ,OEÝ,VCCand VPP)

with Respect to GND АААААААААА

2.0V to 7.0V

(3)

Voltage on A9,RPÝ, and OE

with Respect to GND АААААААb2.0V to 13.5V

(3, 4)

VPPProgram Voltage

with Respect to GND During Erase/Program АААААА

2.0V to 14.0V

(3, 4)

VCCSupply Voltage

with Respect to GND АААААААААА

2.0V to 7.0V

(3)

Output Short Circuit CurrentААААААААААААА100 mA

(5)

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability.

OPERATING CONDITIONS

Symbol Parameter Min Max Unit

Operating Temperature

(1)

070

Operating Temperature

(2)

40 85

Supply Voltage 4.50 5.50 V

NOTES:

1. Operating temperature is for commercial product defined by this specification.

2. Operating temperature is for extended temperature product defined by this specification.

3. Minimum DC voltage is

0.5V on input/output pins. During transitions, this level may undershoot tob2.0V for periods

20 ns. Maximum DC voltage on input/output pins is V

0.5V which, during transitions, may overshoot to V

2.0V

for periods

20 ns.

4. Maximum DC voltage on A

or VPPmay overshoot toa14.0V for periodsk20 ns.

5. Output shorted for no more than one second. No more than one output shorted at a time.

DC CHARACTERISTICS

5.0Vg10%, T

0§Ctoa70§C

Symbol Parameter Notes Min Typ Max Unit Test Conditions

Input Load Current 1

1.0 mAV

VCCMax

VCCor GND

Output Leakage Current 1

10 mAV

VCCMax

OUT

VCCor GND

CCS

VCCStandby Current 1.2 2.0 mA V

VCCMax

30 100 mAV

VCCMax

0.2V

CCD

VCCDeep Power-Down Current 1 0.05 1.0 mARP

GNDg0.2V

28F001BX-T/28F001BX-B

DC CHARACTERISTICS (Continued)

5.0Vg10%, T

0§Ctoa70§C

Symbol Parameter Notes Min Typ Max Unit Test Conditions

CCR

VCCRead Current 1 13 30 mA V

VCCMax, CE

fe8 MHz, I

OUT

0mA

CCP

VCCProgramming Current 1 5 20 mA Programming in Progress

CCE

VCCErase Current 1 6 20 mA Erase in Progress

CCESVCC

Erase Suspend Current 1, 2 5 10 mA Erase Suspended

PPS

VPPStandby Current 1

g1g

10 mAV

90 200 mAV

PPD

VPPDeep Power-Down Current 1 0.80 1.0 mARP

GNDg0.2V

PPP

VPPProgramming Current 1 6 30 mA V

PPH

Programming in Progress

PPE

VPPErase Current 1 6 30 mA V

PPH

Erase in Progress

PPESVPP

Erase Suspend Current 1 90 300 mAV

PPH

Erase Suspended

A9Intelligent Identifier Current 1 90 500 mAA

Input Low Voltage

0.5 0.8 V

Input High Voltage 2.0 V

0.5 V

Output Low Voltage 0.45 V V

VCCMin

5.8 mA

Output High Voltage 2.4 V V

VCCMin

2.5 mA

A9Intelligent Identifier Voltage 11.5 13.0 V

PPLVPP

during Normal Operations 3 0.0 6.5 V

PPHVPP

during Prog/Erase Operations 11.4 12.0 12.6 V

LKOVCC

Erase/Write Lock Voltage 2.5 V

RPÝ,OEÝUnlock Voltage 11.4 12.6 V Boot Block Prog/Erase

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at V

5.0V, V

12.0V, T

25§C. These currents

are valid for all product versions (packages and speeds).

2. I

CCES

is specified with the device deselected. If the 28F001BX is read while in Erase Suspend mode, current draw is the

sum of I

CCES

and I

CCR

3. Erase/Programs are inhibited when V

PPL

and not guaranteed in the range between V

PPH

and V

PPL

28F001BX-T/28F001BX-B

DC CHARACTERISTICS

5.0Vg10%, T

40§Ctoa85§C

Symbol Parameter Notes Min Typ Max Unit Test Conditions

Input Load Current 1

1.0 mAV

VCCMax

VCCor GND

Output Leakage Current 1

10 mAV

VCCMax

OUT

VCCor GND

CCSVCC

Standby Current 1.2 2.0 mA V

VCCMax

30 150 mAV

VCCMax

0.2V

CCDVCC

Deep Power-Down Current 1 0.05 2.0 mARP

GNDg0.2V

CCRVCC

Read Current 1 13 35 mA V

VCCMax, CE

fe8 MHz, I

OUT

0mA

CCPVCC

Programming Current 1 5 20 mA Programming in Progress

CCEVCC

Erase Current 1 6 20 mA Erase in Progress

CCESVCC

Erase Suspend Current 1, 2 5 10 mA Erase Suspended

PPSVPP

Standby Current 1

g1g

15 mAV

90 400 mAV

PPDVPP

Deep Power-Down Current 1 0.80 1.0 mARP

GNDg0.2V

PPPVPP

Programming Current 1 6 30 mAV

PPH

Programming in Progress

PPEVPP

Erase Current 1 6 30 mA V

PPH

Erase in Progress

PPESVPP

Erase Suspend Current 1 90 400 mAV

PPH

Erase Suspended

A9Intelligent Identifier Current 1 90 500 mAA

Input Low Voltage

0.5 0.8 V

Input High Voltage 2.0 V

0.5 V

Output Low Voltage 0.45 V V

VCCMin

5.8 mA

OH1

Output High Voltage (TTL) 2.4 V V

VCCMin

2.5 mA

OH2

Output High Voltage (CMOS) 0.85 V

VCCMin

2.5 mA

0.4 V

VCCMin

100 mA

A9Intelligent Identifier Voltage 11.5 13.0 V

PPLVPP

during Normal Operations 3 0.0 6.5 V

PPHVPP

during Prog/Erase Operations 11.4 12.0 12.6 V

LKOVCC

Erase/Write Lock Voltage 2.5 V

RPÝ,OEÝUnlock Voltage 11.4 12.6 V Boot Block Prog/Erase

28F001BX-T/28F001BX-B

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at V

5.0V, V

12.0V, T

25§C. These currents

are valid for all product versions (packages and speeds).

2. I

CCES

is specified with the device deselected. If the 28F001BX is read while in Erase Suspend mode, current draw is the

sum of I

CCES

and I

CCR

3. Erase/Programs are inhibited when V

PPL

and not guaranteed in the range between V

PPH

and V

PPL

CAPACITANCE

(1)

25§C, fe1 MHz

Symbol Parameter Max Unit Conditions

Input Capacitance 8 pF V

OUT

Output Capacitance 12 pF V

OUT

NOTE:

1. Sampled, not 100% tested.

AC INPUT/OUTPUT REFERENCE WAVEFORM

290406– 10

A.C. test inputs are driven at VOH(2.4 V

TTL

) for a Logic ‘‘1’’ and VOL(0.45 V

TTL

) for a Logic ‘‘0’’. Input timing begins at

(2.0 V

TTL

) and VIL(0.8 V

TTL

). Output timing ends at VIHand VIL. Input rise and fall times (10% to 90%)k10 ns.

STANDARD TEST CONFIGURATION AC TESTING LOAD CIRCUIT

290406– 11

100 pF

Includes Jig Capacitance

3.3 kX

HIGH SPEED TEST CONFIGURATION AC TESTING LOAD CIRCUIT

290406– 23

30 pF

Includes Jig Capacitance

3.3 kX

28F001BX-T/28F001BX-B

AC CHARACTERISTICSÐRead-Only Operations

(1)

Symbol Parameter Notes

28F001BX-70 28F001BX-90

Units

5V V

10%

30 pF 100 pF 100 pF

Min Max Min Max Min Max

AVAVtRC

Read Cycle Time 70 75 90 ns

AVQVtACC

Address to Output Delay 70 75 90 ns

ELQVtCE

CEÝto Output Delay 2 70 75 90 ns

PHQVtPWH

RPÝto Output Delay 600 600 600 ns

GLQVtOE

OEÝto Output Delay 2 27 30 35 ns

ELQXtLZ

CEÝto Output in Low Z 3 0 0 0 ns

EHQZtHZ

CEÝto Output in High Z 3 55 55 35 ns

GLQXtOLZ

OEÝto Output in Low Z 3 0 0 0 ns

GHQZtDF

OEÝto Output in High Z 3 30 30 30 ns

tOHOutput Hold from 3 0 0 0 ns

Address CEÝ,orOE

Change, Whichever Occurs First

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements.

2. OE

may be delayed up to tCE–tOEafter the falling edge of CEÝwithout impact on tCE.

3. Sampled, but not 100% tested.

4. See High Speed Test Configuration.

5. See Standard Test Configuration.

28F001BX-T/28F001BX-B

AC CHARACTERISTICSÐRead-Only Operations

(1)

E28F001BX-150

Unit

E28F001BX-120 TE28F001BX-150

Versions

(2)

10% N28F001BX-120 N28F001BX-150

P28F001BX-120 TN28F001BX-150

P28F001BX-150

Symbol Parameter Notes Min Max Min Max

AVAVtRC

Read Cycle Time 120 150 ns

AVQVtACC

Address to Output Delay 120 150 ns

ELQVtCE

CEÝto Output Delay 3 120 150 ns

PHQVtPWH

RPÝHigh to Output Delay 600 600 ns

GLQVtOE

OEÝto Output Delay 3 50 55 ns

ELQXtLZ

CEÝto Output Low Z 4 0 0 ns

EHQZtHZ

CEÝHigh to Output High Z 4 55 55 ns

GLQXtOLZ

OEÝto Output Low Z 4 0 0 ns

GHQZtDF

OEÝHigh to Output High Z 4 30 30 ns

Output Hold from 4 0 0 ns Addresses, CEÝor OE

Change, Whichever is First

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements.

2. Model Number Prefixes: E

TSOP (Standard Pinout), NePLCC, PePDIP, TeExtended Temperature. Refer to

standard test configuration.

3. OE

may be delayed up to tCE–tOEafter the falling edge of CEÝwithout impact on tCE.

4. Sampled, not 100% tested.

28F001BX-T/28F001BX-B

Figure 12. AC Waveform for Read Operations

290406– 12

28F001BX-T/28F001BX-B

AC CHARACTERISTICSÐWrite/Erase/Program Operations

(1, 9)

Symbol Parameter Notes

28F001BX-70 28F001BX-90

Units

5V V

(10)

10%

(11)

10%

(11)

30 pF 100 pF 100 pF

Min Max Min Max Min Max

AVAVtWC

Write Cycle Time 70 75 90 ns

PHWLtPS

RPÝHigh Recovery to WE

2 480 480 480 ns

Going Low

ELWLtCS

CEÝSetup to WEÝGoing Low 10 10 10 ns

WLWHtWP

WEÝPulse Width 35 40 40 ns

PHHWHtPHS

RPÝVHHSetup to WEÝGoing 2 100 100 100 ns High

VPWHtVPSVPP

Setup to WEÝGoing High 2 100 100 100 ns

AVWHtAS

Address Setup to WEÝGoing 3 35 40 40 ns High

DVWHtDS

Data Setup to WEÝGoing High 4 35 40 40 ns

WHDXtDH

Data Hold from WEÝHigh 10 10 10 ns

WHAXtAH

Address Hold from WEÝHigh 10 10 10 ns

WHEHtCH

CEÝHold from WEÝHigh 10 10 10 ns

WHWLtWPH

WEÝPulse Width High 35 35 35 ns

WHQV1

Duration of Programming 5, 6, 7 15 15 15 ms Operation

WHQV2

Duration of Erase Operation 5, 6, 7 1.3 1.3 1.3 sec (Boot)

WHQV3

Duration of Erase Operation 5, 6, 7 1.3 1.3 1.3 sec (Parameter)

WHQV4

Duration of Erase Operation 5, 6, 7 3.0 3.0 3.0 sec (Main)

WHGL

Write Recovery before Read 0 0 0 ms

QVVLtVPHVPP

Hold from Valid SRD 2, 6 0 0 0 ns

QVPHtPHH

RPÝVHHHold from Valid SRD 2, 7 0 0 0 ns

PHBR

Boot-Block Relock Delay 2 100 100 100 ns

NOTES:

1. Read timing characteristics during erase and program operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid A

for byte programming or block erasure.

4. Refer to Table 3 for valid D

for byte programming or block erasure.

5. The on-chip Write State Machine incorporates all program and erase system functions and overhead of standard Intel Flash Memory, including byte program and verify (programming) and block precondition, precondition verify, erase and erase verify (erasing).

6. Program and erase durations are measured to completion (SR.7

1). VPPshould be held at V

PPH

until determination of

program/erase success (SR.3/4/5

0).

7. For boot block programming and erasure, RP

should be held at VHHuntil determination of program/erase success

(SR.3/4/5

0).

8. Alternate boot block access method.

9. Erase/Program Cycles on extended temperature products is 10,000 cycles.

10. See high speed test configuration.

11. See standard test configuration.

28F001BX-T/28F001BX-B

AC CHARACTERISTICSÐWrite/Erase/Program Operations

(1, 9)

Versions V

10%

(10)

28F001BX-120 28F001BX-150

Unit

Symbol Parameter Notes Min Max Min Max

AVAVtWC

Write Cycle Time 120 150 ns

PHWLtPS

RPÝHigh Recovery to WEÝGoing Low 2 480 480 ns

ELWLtCS

CEÝSetup to WEÝGoing Low 10 10 ns

WLWHtWP

WEÝPulse Width 50 50 ns

PHHWHtPHS

RPÝVHHSetup to WEÝGoing High 2 100 100 ns

VPWHtVPSVPP

Setup to WEÝGoing High 2 100 100 ns

AVWHtAS

Address Setup to WEÝGoing High 3 50 50 ns

DVWHtDS

Data Setup to WEÝGoing High 4 50 50 ns

WHDXtDH

Data Hold from WEÝHigh 10 10 ns

WHAXtAH

Address Hold from WEÝHigh 10 10 ns

WHEHtCH

CEÝHold from WEÝHigh 10 10 ns

WHWLtWPH

WEÝPulse Width High 50 50 ns

WHQV1

Duration of Programming Operation 5, 6, 7 15 15 ms

WHQV2

Duration of Erase Operation (Boot) 5, 6, 7 1.3 1.3 sec

WHQV3

Duration of Erase Operation (Parameter) 5, 6, 7 1.3 1.3 sec

WHQV4

Duration of Erase Operation (Main) 5, 6, 7 3.0 3.0 sec

WHGL

Write Recovery before Read 0 0 ms

QVVLtVPHVPP

Hold from Valid SRD 2, 6 0 0 ns

QVPHtPHH

RPÝVHHHold from Valid SRD 2, 7 0 0 ns

PHBR

Boot-Block Relock Delay 2 100 100 ns

PROM Programmer Specifications

Versions V

10% 28F001BX-120 28F001BX-150

Unit

Symbol Parameter Notes Min Max Min Max

GHHWL

OEÝVHHSetup to WEÝGoing Low 2, 8 480 480 ns

WHGH

OEÝVHHHold from WEÝHigh 2, 8 480 480 ns

NOTES:

1. Read timing characteristics during erase and program operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid A

for byte programming or block erasure.

4. Refer to Table 3 for valid D

for byte programming or block erasure.

6. Program and erase durations are measured to completion (SR.7

1). VPPshould be held at V

PPH

until determination of

program/erase success (SR.3/4/5

0).

7. For boot block programming and erasure, RP

should be held at VHHuntil determination of program/erase success

(SR.3/4/5

0).

8. Alternate boot block access method.

9. Erase/Program Cycles on extended temperature products is 10,000 cycles.

10. See standard test configuration.

28F001BX-T/28F001BX-B

ERASE AND PROGRAMMING PERFORMANCE

Parameter Notes

28F001BX-120 28F001BX-150

Unit

Min Typ

(1)

Max Min Typ

(1)

Max

Boot Block Erase Time 2 2.10 14.9 2.10 14.9 Sec

Boot Block Program Time 2 0.15 0.52 0.15 0.52 Sec

Parameter Block Erase Time 2 2.10 14.6 2.10 14.6 Sec

Parameter Block Program Time 2 0.07 0.26 0.07 0.26 Sec

Main Block Erase Time 2 3.80 20.9 3.80 20.9 Sec

Main Block Program Time 2 2.10 7.34 2.10 7.34 Sec

Chip Erase Time 2 10.10 65 10.10 65 Sec

Chip Program Time 2 2.39 8.38 2.39 8.38 Sec

NOTES:

1. 25

C, 12.0 VPP.

2. Excludes System-Level Overhead.

28F001BX-T/28F001BX-B

290406– 19

Figure 13. 28F001BX Typical

Programming Capability

290406– 20

Figure 14. 28F001BX Typical

Programming Time at 12V

290406– 21

Figure 15. 28F001BX Typical Erase Capability

290406– 22

Figure 16. 28F001BX Typical Erase Time at 12V

28F001BX-T/28F001BX-B

Figure 17. AC Waveform for Write Operations

290406– 13

28F001BX-T/28F001BX-B

290406– 15

Figure 18. Alternate Boot Block Access Method Using OE

28F001BX-T/28F001BX-B

AC CHARACTERISTICS FOR CEÝ-CONTROLLED WRITES

(1)

Symbol Parameter Notes

28F001BX-70 28F001BX-90

Units

5V V

(8)

10%

(9)

10%

(9)

30 pF 100 pF 100 pF

Min Max Min Max Min Max

AVAVtWC

Write Cycle Time 70 75 90 ns

PHELtPS

RPÝHigh Recovery to CE

2 480 480 480 ns

Going Low

WLELtWS

WEÝSetup to CEÝGoing Low 0 0 0 ns

ELEHtCP

CEÝPulse Width 50 55 55 ns

PHHEHtPHS

RPÝVHHSetup to CEÝGoing 2 100 100 100 ns High

VPEHtVPSVPP

Setup to CEÝGoing High 2 100 100 100 ns

AVEHtAS

Address Setup to CEÝGoing 3 35 40 40 ns High

DVEHtDS

Data Setup to CEÝGoing High 4 35 40 40 ns

EHDXtDH

Data Hold from CEÝHigh 10 10 10 ns

EHAXtAH

Address Hold from CEÝHigh 10 10 10 ns

EHWHtWH

WEÝHold from CEÝHigh 0 0 0 ns

EHELtEPH

CEÝPulse Width High 20 20 20 ns

EHQV1

Duration of Programming 5, 6 15 15 15 ms Operation

EHQV2

Duration of Erase Operation 5, 6 1.3 1.3 1.3 sec (Boot)

EHQV3

Duration of Erase Operation 5, 6 1.3 1.3 1.3 sec (Parameter)

EHQV4

Duration of Erase Operation 5, 6 3.0 3.0 3.0 sec (Main)

EHGL

Write Recovery before Read 0 0 0 ms

QVVLtVPHVPP

Hold from Valid SRD 2, 5 0 0 0 ns

QVPHtPHH

RPÝVHHHold from Valid SRD 2, 6 0 0 0 ns

PHBR

Boot-Block Relock Delay 2 100 100 100 ns

NOTES:

1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE

and WEÝ. In systems where

defines the write pulse width (within a longer WEÝtiming waveform), all set-up, hold and inactive WEÝtimes should

be measured relative to the CE

waveform.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid A

for byte programming or block erasure.

4. Refer to Table 3 for valid D

for byte programming or block erasure.

5. Program and erase durations are measured to completion (SR.7

1). VPPshould be held at V

PPH

until determination of

program/erase success (SR.3/4/5

0).

6. For boot block programming and erasure, RP

should be held at VHHuntil determination of program/erase success

(SR.3/4/5

0).

7. Alternate boot block access method.

8. See high speed test configuration.

9. See standard text configuration.

28F001BX-T/28F001BX-B

AC CHARACTERISTICS FOR CEÝ-CONTROLLED WRITES

(1)

Versions V

10% 28F001BX-120 28F001BX-150

Unit

Symbol Parameter Notes Min Max Min Max

AVAVtWC

Write Cycle Time 120 150 ns

PHELtPS

RPÝHigh Recovery to CEÝGoing Low 2 480 480 ns

WLELtWS

WEÝSetup to CEÝGoing Low 0 0 ns

ELEHtCP

CEÝPulse Width 70 70 ns

PHHEHtPHS

RPÝVHHSetup to CEÝGoing High 2 100 100 ns

VPEHtVPSVPP

Setup to CEÝGoing High 2 100 100 ns

AVEHtAS

Address Setup to CEÝGoing High 3 50 50 ns

DVEHtDS

Data Setup to CEÝGoing High 4 50 50 ns

EHDXtDH

Data Hold from CEÝHigh 10 10 ns

EHAXtAH

Address Hold from CEÝHigh 15 15 ns

EHWHtWH

WEÝHold from CEÝHigh 0 0 ns

EHELtEPH

CEÝPulse Width High 25 25 ns

EHQV1

Duration of Programming Operation 5, 6 15 15 ms

EHQV2

Duration of Erase Operation (Boot) 5, 6 1.3 1.3 sec

EHQV3

Duration of Erase Operation (Parameter) 5, 6 1.3 1.3 sec

EHQV4

Duration of Erase Operation (Main) 5, 6 3.0 3.0 sec

EHGL

Write Recovery before Read 0 0 ms

QVVLtVPHVPP

Hold from Valid SRD 2, 5 0 0 ns

QVPHtPHH

RPÝVHHHold from Valid SRD 2, 6 0 0 ns

PHBR

Boot-Block Relock Delay 2 100 100 ns

PROM Programmer Specifications

Versions V

10% 28F001BX-120 28F001BX-150

Unit

Symbol Parameter Notes Min Max Min Max

GHHEL

OEÝVHHSetup to CEÝGoing Low 2, 7 480 480 ns

EHGH

OEÝVHHHold from CEÝHigh 2, 7 480 480 ns

NOTES:

1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE

and WEÝ. In systems where

defines the write pulse width (within a longer WEÝtiming waveform), all set-up, hold and inactive WEÝtimes should

be measured relative to the CE

waveform.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid A

for byte programming or block erasure.

4. Refer to Table 3 for valid D

for byte programming or block erasure.

5. Program and erase durations are measured to completion (SR.7

1). VPPshould be held at V

PPH

until determination of

program/erase success (SR.3/4/5

0).

6. For boot block programming and erasure, RP

should be held at VHHuntil determination of program/erase success

(SR.3/4/5

0).

7. Alternate boot block access method.

28F001BX-T/28F001BX-B

Figure 19. Alternate AC Waveform for Write Operations

290406– 16

28F001BX-T/28F001BX-B

ORDERING INFORMATION

290406– 18

VALID COMBINATIONS:

32-Lead TSOP 32-Lead PLCC 32-Pin PDIP

Commercial E28F001BX-T70 N28F001BX-T70 P28F001BX-T70

E28F001BX-T90 N28F001BX-T90 P28F001BX-T90

E28F001BX-T120 N28F001BX-T120 P28F001BX-T120

E28F001BX-T150 N28F001BX-T150 P28F001BX-T150

E28F001BX-B70 N28F001BX-B70 P28F001BX-B70

E28F001BX-B90 N28F001BX-B90 P28F001BX-B90

E28F001BX-B120 N28F001BX-B120 P28F001BX-B120

E28F001BX-B150 N28F001BX-B150 P28F001BX-B150

Extended TE28F001BX-T90 TN28F001BX-T90 TP28F001BX-T90

TE28F001BX-T150 TN28F001BX-T150 TP28F001BX-B90

TE28F001BX-B90 TN28F001BX-B90

TE28F001BX-B150 TN28F001BX-B150

ADDITIONAL INFORMATION

References

Order Number Document

292046 AP-316 ‘‘Using Flash Memory for In-System Reprogrammable Nonvolatile Storage’’

292077 AP-341 ‘‘Designing an Updateable BIOS Using Flash Memory’’

292161 AP-608 ‘‘Implementing a Plug and Play BIOS Using Intel’s Boot Block Flash Memory’’

292178 AP-623 ‘‘Multi-Site Layout Planning Using Intel’s Boot Block Flash Memory’’

294005 ER-20 ‘‘ETOX II Flash Memory Technology’’

28F001BX-T/28F001BX-B

Revision History

Number Description

-004 Removed Preliminary classification.

Latched address A

in Figure 5.

Updated Boot Block Program and Erase section: ‘‘If boot block program or erase is attempted while RP

is at VIH, either the Program Status or Erase Status bit will be set to ‘‘1’’,

reflective of the operation being attempted and indicating boot block lock.’’

Updated Figure 11, 28F001BX Erase Suspend/Resume Flowchart

Added DC Characteristics typical current values

Combined VPPStandby current and VPPRead current into one VPPStandby current spec with two test conditions (DC Characteristics table)

Added maximum program/erase times to Erase and Programming Performance table.

Added Figures 13 – 16

Added Extended Temperature proliferations

-005 PWD changed to RPÝfor JEDEC standardization compatibility

Revised symbols, i.e.; CE,OE, etc. to CEÝ,OEÝ, etc.

-006 Added specifications for -90 and -70 product versions.

Added VOHCMOS Specification.

-007 Added reference to 28F001BN.

Datasheet TN28F001BX-T90 Datasheet (Intel Corporation)

Specifications and Main Features

Frequently Asked Questions

User Manual