The Intel® Desktop Board YA810E may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized
errata are documented in the Intel Desktop Board YA810E Specification Update.
December 1999
Order Number A00984-001
Revision History
RevisionRevision HistoryDate
-001First release of the Intel® Desktop Board YA810E Technical Product
Specification.
This product specification applies to only standard YA810E boards with BIOS identifier
YA810E10A.86A.
Changes to this specification will be published in the Intel® Desktop Board YA810E Specification
Update before being incorporated into a revision of this document.
December 1999
Information in this doc um ent is provided in connection wi t h Intel products. No license, express or implied, by estoppel or
otherwise, to any intell ectual property rights is granted by this document. E x cept as provided in Intel's Terms and
Conditions of Sale for such products, Intel assumes no liability whatsoever, and I nt el dis claims any express or implied
warranty, relating to sale and/or use of I ntel products including liability or warranties relat i ng t o f i t ness for a particular
purpose, merchantability, or infringement of any patent, copyright or other int ellec t ual propert y right. Intel products are not
intended for use in medical, l i f e saving, or life sustai ni ng appl i cations.
Intel may make changes t o specifications and produc t descriptions at any tim e, without notice.
The YA810E board may contain des i gn def ects or errors known as errata that m ay cause the product to deviat e from
published specificat i ons. Current characterized errata are available on request.
Contact your local Int el sales office or your distributor to obtain the latest specifications before pl acing your product order.
Copies of documents whic h hav e an orderi ng number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777,
Germany 44-0-1793-421-333, other Countries 708-296-9333.
†
Third-party brands and names are the property of their respective owners.
Copyright 1999, Intel Corporation. All rights reserved.
Preface
This Technical Product Specification (TPS) specifies the board layout, components, connectors,
power and environmental requirements, and the BIOS for the YA810E desktop board. It describes
the standard product and available manufacturing options.
Intended Audience
The TPS is intended to provide detailed, technical information about the YA810E board and its
components to the vendors, system integrators, and other engineers and technicians who need this
level of information. It is specifically not intended for general audiences.
What This Document Contains
ChapterDescription
1A description of the hardware used on this board
2A map of the resources of the board
3The features supported by the BIOS Setup program
4The contents of the BIOS Setup program’s menus and submenus
5A description of the BIOS error messages, beep codes, and POST codes
Typographical Conventions
This section contains information about the conventions used in this specification. Not all of these
symbols and abbreviations appear in all specifications of this type.
Notes, Cautions, and Warnings
NOTE
✏
Notes call attention to important information.
CAUTION
Cautions are included to help you avoid damaging hardware or losing data.
WARNING
Warnings indicate conditions which, if not observed, can cause personal injury.
#Used after a signal name to identify an active-low signal (such as USBP0#)
(NxnX)When used in the description of a component, N indicates component type, xn are the relative
coordinates of its location on the YA810E board, and X is the instance of the particular part at
that general location. For example, J5J1 is a connector, located at 5J. It is the first connector in
the 5J area.
KBKilobyte (1024 bytes)
KbitKilobit (1024 bits)
MBMegabyte (1,048,576 bytes)
MbitMegabit (1,048,576 bits)
GBGigabyte (1,073,741,824 bytes)
xxhAn address or data value ending with a lowercase h indicates a hexadecimal value.
x.x VVolts. Voltages are DC unless otherwise specified.
†
This symbol is used to indicate third-party brands and names that are the property of their
Table 1 summarizes the YA810E board’s major features.
Table 1.Feature Summary
Form Factor
Processor
Memory
Chipset
Direct AGP Video
Audio
I/O Control
Peripheral Interfaces
BIOS
LAN Controller
Instantly Available PC
FlexATX (9.0 inches by 7.5 inches)
Support for either an:
®
• Intel
• Intel
• Two 168-pin dual inline memory module (DIMM) sockets
• Supports up to 512 MB of 100 MHz non-ECC synchronous DRAM (SDRAM)
• Support for serial presence detect (SPD) and non-SPD DIMMs
Intel® 810E chipset, consisting of:
• Intel
• Intel
• Intel
• Intel 82810E DC-133 GMCH
• VGA port connector on back panel
Audio Codec ’97 (AC’97) compatible audio subsystem, consisting of the
following:
• Intel 82801AA ICH (AC link output)
• Analog Devices AD1881 analog codec
LPC47B277 Low Pin Count (LPC) I/O controller
• Three back-panel mounted universal serial bus (USB) ports
• Two IDE interfaces with Ultra DMA support
• Intel/AMI BIOS stored in an Intel 82802AB 4 Mbit firmware hub (FWH)
• Support for Advanced Configuration and Power Interface (ACPI), Plug and
Intel
• Support for
• Suspend-to-RAM support
• Wake from USB ports
Pentium® III processor with 512 KB L2 cache (in an FCPGA package)
®
Celeron™ processor with 128 KB L2 cache (in a PGA package)
®
82810E Graphics/Memory Controller Hub (GMCH)
®
82801AA I/O Controller Hub (ICH)
®
82802AB 4 Mbit Firmware Hub (FWH)
Play, and SMBIOS
®
82559 local area network (LAN) controller
PCI Local Bus Specification
, Revision 2.2
NOTE
✏
The YA810E board is designed to support only USB-aware operating systems.
For information aboutRefer to
The board’s compliance level with ACPI, Plug and Play, and SMBIOSTable 3, page 16
12
Product Description
1.1.2 Manufacturing Options
Table 2 describes the YA810E board’s manufacturing options. Not every manufacturing option is
available in all marketing channels. Please contact your Intel representative to determine which
manufacturing options are available to you.
Table 2.Manufacturing Options
Legacy I/O
Connectors
Diagnostic LEDs
USB
Slimline IDE
Enhanced Video
Management
Level 4
• One back panel 9-pin serial port connector, or one internal serial port connector
• One back panel 25-pin parallel port connector
• PS/2 keyboard and mouse connectors
Extended diagnostics back-panel four-LED set
Two internal USB ports are available for front panel access
ATA-5 compliant connector
4 MB SDRAM display cache (optional)
Hardware monitor
the Phoenix Web site at:
http://www.ptltd.com/
techs/specs.html
continued
16
Table 3.Specifications (continued)
Reference
Name
LPC
FlexATXFlexATX Addendum to
MicroATX
PCI
Plug and Play
SDRAM
DIMMs
(64-and 72-bit)
SMBIOS
Specification
Title
Low Pin Count
Interface Specification
the microATX
Specification,
Version 1.0
microATX
Motherboard Interface
Specification
SFX Power Supply
Design Guide
PCI Local Bus
Specification
PCI Bus Power
Management Interface
Specification
Plug and Play BIOS
Specification
PC SDRAM
Unbuffered DIMM
Specification
PC SDRAM DIMM
Specification
PC Serial Presence
Detect (SPD)
Specification
System Management
BIOS
Version, Revision Date and
Ownership
Version 1.0,
September 29, 1997,
Intel Corporation.
Version 1.0
March 1999,
Intel Corporation.
Version 1.0, December 1997,
Intel Corporation.
Version 1.0, December 1997,
Intel Corporation.
Version 2.2,
December 18, 1998,
PCI Special Interest Group.
Version 1.1,
December 18, 1998,
PCI Special Interest Group.
Version 1.0a,
May 5, 1994,
Compaq Computer Corp.,
Phoenix Technologies Ltd., and
Intel Corporation.
Version 1.0, February 1998,
Intel Corporation.
Version 1.5, November 1997,
Intel Corporation.
Version 1.2A, December 1997,
Intel Corporation.
Version 2.3.1,
August 12, 1998,
Award Software International Inc.,
Dell Computer Corporation,
Hewlett-Packard Company,
Intel Corporation,
International Business Machines
Corporation,
Phoenix Technologies Limited,
American Megatrends Inc.,
SystemSoft Corporation, and
Compaq Computer Corporation.
Version 1.1,
September 23, 1998,
Compaq Computer Corporation,
Intel Corporation, Microsoft
Corporation, and NEC.
Version 2.0,
December 18, 1998,
Intel Corporation.
This specification is
available from:
http://www.usb.org/
developers
http://www.usb.org/
developers
http://developer.intel.com/
ial/WfM/wfmspecs.htm
18
Product Description
1.4 Processor
CAUTION
The YA810E board supports processors that draw a maximum of 22 A. Using a processor that
draws more than 22 A can damage the processor, the board, and the power supply. See the
processor’s data sheet for current usage requirements.
CAUTION
Before installing or removing the processor, make sure that AC power has been removed by
unplugging the power cord from the computer. Failure to do so could damage the processor and
the board.
The YA810E board supports either an Intel Pentium III processor (FCPGA package), or an Intel
Celeron processor (PGA package) as shown in Table 4. The host bus speed is automatically
selected.
Table 4.Supported Processors
Processor TypeProcessor DesignationHost Bus Speed (MHz)L2 Cache Size (KB)
Pentium III processors500E, 550E, and 600E100512
533B and 600B133512
533EB, 600EB, 667, and 733133256
Celeron processors300A, 333, 366, 400, 433, 466,
500, and 533
66128
All supported onboard memory can be cached, up to the cachability limit of the processor.
For information aboutRefer to
Processor support for the YA810E boardhttp://support.intel.com/support/motherboards/desktop
Processor data sheetshttp://www.intel.com/design/litcentr
To be compliant with applicable Intel® SDRAM memory specifications, the YA810E board should
be populated with DIMMs that support the Serial Presence Detect (SPD) data structure. If your
memory modules do not support SPD, the BIOS will attempt to configure the memory controller for
normal operation; however, the DIMMs may not function at their optimum speed.
CAUTION
Before installing or removing memory, make sure that AC power has been removed by unplugging
the power cord from the computer. Failure to do so could damage the memory and the board.
CAUTION
Because the main system memory is also used as video memory, the board requires 100 MHz
SDRAM DIMMs even though the processor’s host bus speed is 66 MHz. It is highly recommended
that SPD DIMMs be used, since this allows the BIOS to read the SPD data and program the
chipset to accurately configure memory settings for optimum performance. If non-SPD memory is
installed, the BIOS will attempt to correctly configure the memory settings, but performance and
reliability may be impacted.
The YA810E board has two DIMM sockets. The minimum memory size is 16 MB and the
maximum memory size is 512 MB. The BIOS automatically detects memory type, size, and
speed. Memory can be installed in one or both sockets. Memory size can vary between sockets.
The YA810E board supports the following memory features:
• 3.3 V, 168-pin DIMMs with gold-plated contacts
• 100 MHz SDRAM
• Serial Presence Detect (SPD) or non-SPD memory (BIOS recovery requires SPD DIMMs)
• Non-ECC (64-bit) memory
• Unbuffered single- or double-sided DIMMs
The board is designed to support DIMMs in the configurations listed in Table 5 below.
Table 5.System Memory Configuration
DIMM SizeNon-ECC Configuration
16 MB2 Mbit x 64
32 MB4 Mbit x 64
64 MB8 Mbit x 64
128 MB16 Mbit x 64
256 MB32 Mbit x 64
For information aboutRefer to
The
PC Serial Presence Detect Specification
Obtaining copies of PC SDRAM specificationshttp://www.intel.com/design/pcisets/memory
20
Table 3, page 16
1.6 Intel® 810E Chipset
The Intel 810E chipset consists of the following devices:
•82810E Graphics Memory Controller Hub (GMCH) with Accelerated Hub Architecture
(AHA) bus
• 82801AA I/O Controller Hub (ICH) with AHA bus
• 82802AB Firmware Hub (FWH)
The chipset provides the host, memory, display, and I/O interfaces shown in Figure 3.
Product Description
66/100/133 MHz
Host Bus
ATA33/66USB
810E Chipset
100 MHz
SDRAM
Bus
Display
Interface
82810E
Graphics Memory
Controller Hub
(GMCH)
AHA
Bus
82801AA I/O Controller Hub
(ICH)
SMBus
PCI Bus
AC Link
Figure 3. Intel 810E Chipset Block Diagram
For information aboutRefer toThe Intel 810E chipsethttp://www.developer.intel.comThe resources used by the chipsetChapter 2The chipset’s compliance with ACPI and AC ‘97Table 3, page 16
Direct (integrated) AGP is a high-performance bus (independent of the PCI bus) for graphicsintensive applications, such as 3D applications. AGP overcomes certain limitations of the PCI bus
related to handling large amount of graphics data with the following features:
• Pipelined memory read and write operations that hide memory access latency
• Demultiplexing of address and data on the bus for nearly 100 percent bus efficiency
For information aboutRefer to
The location of the VGA port connectorFigure 6, page 46
Obtaining the
Accelerated Graphics Port Interface Specification
Table 3, page 16
1.6.2 USB
The YA810E board has five USB ports; one USB peripheral can be connected to each port. For
more than five USB devices, an external hub can be connected to any of the ports. Three USB
ports are implemented with stacked back panel connectors. The other two ports can be routed via a
cable to the front panel. The YA810E board fully supports UHCI and uses UHCI-compatible
software drivers. USB features include:
•Support for self-identifying peripherals that can be connected or disconnected while the
computer is running
• Automatic mapping of function to driver and configuration
• Support for isochronous and asynchronous transfer types over the same set of wires
• Support for up to 127 physical devices
• Guaranteed bandwidth and low latencies appropriate for telephony, audio, and other
applications
•Error-handling and fault-recovery mechanisms built into the protocol
NOTE
✏
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device or a low-speed USB device is attached to the cable. Use
shielded cable that meets the requirements for full-speed devices.
For information aboutRefer to
The location of the USB connectors on the back panelFigure 6, page 46
The signal names of the USB connectors on the back panelTable 19, page 47
The location of the USB connectors on the front panelFigure 7, page 50
The signal names of the USB connectors on the front panelTable 32, page 53
The USB and UHCI specificationsTable 3, page 16
22
Product Description
1.6.3 IDE Support
The YA810E board has two independent bus-mastering IDE interfaces. These interfaces support:
• ATAPI devices (such as CD-ROM drives)
• ATA devices using the transfer modes listed in Table 56 on page 85
The BIOS supports logical block addressing (LBA) and extended cylinder head sector (ECHS)
translation modes. The drive reports the transfer rate and translation mode to the BIOS.
The YA810E board supports laser servo (LS-120) diskette technology through its IDE interfaces.
The LS-120 drive can be configured as a boot device by setting the BIOS Setup program’s Boot
menu to one of the following:
• ARMD-FDD (ATAPI removable media device – floppy disk drive)
• ARMD-HDD (ATAPI removable media device – hard disk drive)
The board has two IDE interface connectors. The primary IDE connector is a standard 40-pin IDE
interface. The secondary IDE connector is a 50-pin Slimline IDE connector, intended for use with
devices such as 2.5-inch hard disk drives and mobile CD-ROM drives. The Slimline IDE
connector has the standard IDE interface pins but also includes audio and power signals.
For information aboutRefer to
The location of the IDE connectorsFigure 7, page 50
The signal names of the primary IDE connectorTable 28, page 51
The signal names of the Slimline IDE connectorTable 29, page 52
The real-time clock is compatible with DS1287 and MC146818 components. The clock provides a
time-of-day clock and a multicentury calendar with alarm features and century rollover. The realtime clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are reserved for
BIOS use.
A coin-cell battery powers the real-time clock and CMOS memory. When the computer is not
plugged into a wall socket, the battery has an estimated life of three years. When the computer is
plugged in, the 3.3 V standby current from the power supply extends the life of the battery. The
clock is accurate to ± 13 minutes/year at 25 ºC with 3.3 VSB applied.
The time, date, and CMOS values can be specified in the BIOS Setup program. The CMOS values
can be returned to their defaults by using the BIOS Setup program.
NOTE
✏
If the battery and AC power fail, standard defaults, not custom defaults, will be loaded into CMOS
SRAM at power on.
NOTE
✏
The recommended method of accessing the date in systems with Intel® desktop boards is indirectly
from the Real-Time Clock (RTC) via the BIOS. The BIOS on Intel desktop boards contains a
century checking and maintenance feature. This feature checks the two least significant digits of
the year stored in the RTC during each BIOS request (INT 1Ah) to read the date and, if less than
80 (i.e., 1980 is the first year supported by the PC), updates the century byte to 20. This feature
enables operating systems and applications using the BIOS date/time services to reliably
manipulate the year as a four-digit value.
For information aboutRefer to
Proper date access in systems with Intel de sktop boardshttp://support.intel.com/support/year2000/
24
1.7 I/O Controller
The LPC47B277 I/O controller provides the following features:
• Low pin count (LPC) interface
• 3.3V operation
• One serial port (optional)
• Plug and Play compatible register set
• One parallel port with Extended Capabilities Port (ECP) and Enhanced Parallel Port
(EPP) support (optional)
• PS/2-style mouse and keyboard interfaces (optional)
• Intelligent power management, including a programmable wake up event interface
• PME (Power Management Event) interface
• Fan control:
One fan control output
One fan tachometer input
The BIOS Setup program provides configuration options for the I/O controller.
Product Description
For information aboutRefer to
The LPC47B277 I/O controllerwww.smsc.com/main/catalog/lpc47b27x.html
1.7.1 Serial Port (Optional)
The YA810E board has one serial port connector the location of which is a manufacturing option.
The serial port’s NS16C550-compatible UART supports data transfers at speeds up to
115.2 kbits/sec with BIOS support. The serial port can be assigned as COM1 (3F8h), COM2
(2F8h), COM3 (3E8h), or COM4 (2E8h).
For information aboutRefer to
The location of the back panel serial port connectorFigure 6, page 46
The signal names of the back panel serial port connectorTable 20, page 47
The location of the optional midboard serial port connectorFigure 7, page 50
The signal names of the optional midboard serial port connectorTable 35, page 54
The connector for the multimode bidirectional parallel port is a 25-pin D-Sub connector located on
the back panel. In the BIOS Setup program, the parallel port can be configured for the following:
†
•Output only (PC AT
-compatible mode)
• Bi-directional (PS/2 compatible)
• EPP
• ECP
For information aboutRefer to
The location of the parallel port connectorFigure 6, page 46
The signal names of the parallel port connectorTable 21, page 48
1.7.3 PS/2 Keyboard and Mouse (Optional)
PS/2 keyboard and mouse connectors are located on the back panel. The +5 V lines to these
†
connectors are protected with a PolySwitch
connection after an overcurrent condition is removed.
circuit that, like a self-healing fuse, reestablishes the
NOTE
✏
The keyboard is supported in the bottom PS/2 connector and the mouse is supported in the top
PS/2 connector. Power to the computer should be turned off before a keyboard or mouse is
connected or disconnected.
The keyboard controller contains the AMI keyboard and mouse controller code, provides the
keyboard and mouse control functions, and supports password protection for power-on/reset. A
power-on/reset password can be specified in the BIOS Setup program.
The keyboard controller also supports the hot-key sequence <Ctrl><Alt><Del> for a software
reset. This key sequence resets the computer’s software by jumping to the beginning of the BIOS
code and running the power-on self-test (POST).
For information aboutRefer to
The location of the keyboard and mouse connectorsFigure 6, page 46
The signal names of the keyboard and mouse connectorsTable 18, page 47
26
1.8 Graphics Subsystem
The Intel 82810E DC-133 GMCH graphics memory controller hub component provides the
following graphics support features:
• Integrated 2-D and 3-D graphics engines
• Integrated hardware motion compression engine
• Integrated 230 MHz DAC
Table 6 lists the refresh rates supported by the graphics subsystem.
Table 6.Supported Graphics Refresh Rates
ResolutionAvailable Refresh Rates (Hz)
640 x 200 x 16 colors70
640 x 350 x 16 colors70
640 x 400 x 256 colors60, 70, 75, 85
640 x 400 x 64 K colors60, 70, 75, 85
640 x 400 x 16 M colors70
640 x 480 x 16 colors60, 72, 75, 85
640 x 480 x 256 colors60, 70, 72, 75, 85
640 x 480 x 32 K colors60, 75, 85
640 x 480 x 64 K colors60, 70, 72, 75, 85
640 x 480 x 16 M colors60, 70, 72, 75, 85
800 x 600 x 256 colors60, 75, 85
800 x 600 x 32 K colors60, 70, 72, 75, 85
800 x 600 x 64 K colors60, 70, 72, 75, 85
800 x 600 x 16 M colors60, 70, 72, 75, 85
1024 x 768 x 256 colors60, 70, 75, 85
1024 x 768 x 32 K colors60, 75, 85
1024 x 768 x 64 K colors60, 70, 72, 75, 85
1024 x 768 x 16 M colors60, 70, 72, 75, 85
1056 x 800 x 16 colors70
1280 x 1024 x 256 colors60, 70, 72, 75, 85
1280 x 1024 x 32 K colors60, 75, 85
1280 x 1024 x 64 K colors60, 70, 72, 75
1280 x 1024 x 16 M colors60, 70, 72, 75, 85
Product Description
For information aboutRefer to
Obtaining graphics software and utilitieshttp://support.intel.com/support/motherboards/desktop
The YA810E board includes an Audio Codec ’97 (AC ’97) compatible audio subsystem consisting
of these devices:
• Intel 82801AA ICH (AC link output)
• Analog Devices AD1881 analog codec
Figure 4 is a block diagram of the audio subsystem.
5 W
Audio
Amp
Mic In
CD-ROM
Line
Out
OM09488
82801AA
I/O Controller Hub (ICH)
AC Link
AD1881
Analog
Codec
Figure 4. Block Diagram of Audio Subsystem with AD1881 Codec
Features of the audio subsystem include:
• Independent channels for PCM in, PCM out, and Mic in
• 16-bit stereo I/O up to 48 kHz
• Multiple sample rates
For information aboutRefer to
Obtaining audio software and utilitieshttp://support.intel.com/support/motherboards/desktop
1.9.1 AD1881 Analog Codec
The AD1881 is a fully AC ’97 compliant codec. The codec's features include:
• 16-bit stereo full-duplex operation
• High quality CD-ROM input with ground sense
• Stereo line level output
• Power management support
• Full duplex variable sampling rate (7 kHz to 48 kHz) with 1 Hz resolution
• Phat
28
†
Stereo 3-D stereo enhancement
1.9.2 Audio Connectors
The audio connectors include the following:
• ATAPI CD-ROM (connects an internal ATAPI CD-ROM drive to the audio mixer)
• Line out (front panel audio connector and back panel)
• Line in (front panel audio connector and back panel)
For information aboutRefer to
The location of the front panel audio connectorsFigure 7, page 50
The signal names of the front panel audio connectorsTable 26, page 51
The location of the ATAPI CD-ROM connectorFigure 7, page 50
The signal names of the ATAPI CD-ROM connectorTable 30, page 52
The back panel audio connectorsSection 2.8.1, page 46
The front panel line out connectorSection 2.8.3, page 55
✏ NOTE
Product Description
Some of the audio connectors are optional and are not installed on all versions of the board.
1.10 Hardware Monitor Component (Optional)
The hardware monitor component provides low-cost instrumentation capabilities. The features of
the component include:
• Internal ambient temperature sensing
• Remote thermal diode sensing for direct monitoring of processor temperature
• Power supply monitoring (+12, +5, +3.3, +2.5, V
acceptable values
• SMBus interface
• The hardware monitor component enables the board to be compatible with the Wired for
Management (WfM) specification.
For information aboutRefer to
The board’s compatibility with the WfM specificationTable 3, page 16