Intel Xeon X3360, Xeon X3370, Xeon X3350, Xeon X3320, Xeon X3380 Specification
...
Intel® Xeon® Processor 3300
Series
Specification Update
- on 45 nm Process in the 775-land LGA Package
January 2012
Reference Number: 309007-011
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2 Intel® Xeon® Processor 3300 Series
Specifcation Update January 2012
Contents
Revision History .................................................................................................................5
Preface...............................................................................................................................6
Summary Tables of Changes.............................................................................................8
Identification Information..................................................................................................14
Component Identification Information...............................................................................15
Errata................................................................................................................................17
Specification Changes......................................................................................................40
Specification Clarifications ...............................................................................................41
Documentation Changes..................................................................................................42
Intel® Xeon® Processor 3300 Series 3
Specifcation Update January 2012
4 Intel® Xeon® Processor 3300 Series
Specifcation Update January 2012
Revision History
Version Description Date
-001 Initial release January 2008
-002 Added Erratum AAA52 February 1, 2008
-003
-004
-005 Added Errata AAA58-AAA60 July 2008
-006 Added Errata AAA61-AAA62 August 2008
-007
-008 Updated Component Identification section with L3360 processor info February 2009
-009 Updated Component Identification section with X3380 processor info March 2, 2009
-010 Updated Erratum AAA1 March 11, 2009
-011
Added Errata AAA53-AAA54
Updated Erratum AAA18
Added Errata AAA55-AAA57
Added Spec Clarification AAA1
Added Errata AAA63-AAA75
Updated Erratum table with M0/R0/E0 info
Updated Component Information Table
Added Erratum AAA76
Added Erratum AAA77
February 13, 2008
May 2008
January 2009
January 2012
Intel® Xeon® Processor 3300 Series 5
Specification Update January 2012
Preface
This document is an update to the specifications contained in the documents listed in
the following Affected Documents/Related Documents table. It is a compilation of
device and document errata and specification clarifications and changes, and is
intended for hardware system manufacturers and for software developers of
applications, operating system, and tools.
Information types defined in the Nomenclature section of this document are
consolidated into this update document and are no longer published in other
documents. This document may also contain information that has not been previously
published.
Affected Documents
®
Intel
Xeon® Processor 3300 Series Datasheet 319005
Related Documents
®
Intel
64 and IA-32 Architectures Software Developer’s Manual Volume 1:
Basic Architecture
®
64 and IA-32 Architectures Software Developer’s Manual Volume 2A:
Intel
Instruction Set Reference Manual A–M
®
64 and IA-32 Architectures Software Developer’s Manual Volume 2B:
Intel
Instruction Set Reference Manual, N–Z
®
64 and IA-32 Architectures Software Developer’s Manual Volume 3A:
Intel
System Programming Guide
®
64 and IA-32 Architectures Software Developer’s Manual Volume 3B:
Intel
System Programming Guide
Document Title Document Number
Document Title Document Location
http://www.intel.com/products/
processor/manuals/index.htm
Nomenclature
S-Spec Number is a five-digit code used to identify products. Products are
differentiated by their unique characteristics (for example, core speed, L2 cache size,
package type, and so forth) as described in the processor identification information
table. Care should be taken to read all notes associated with each S-Spec number
Errata are design defects or errors. Errata may cause the processor’s behavior to
deviate from published specifications. Hardware and software designed to be used with
any given stepping must assume that all errata documented for that stepping are
present on all devices.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in the next release of the specifications.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications will
be incorporated in the next release of the specifications.
6 Intel® Xeon® Processor 3300 Series
Specification Update January 2012
Documentation Changes include typos, errors, or omissions from the current
published specifications. These changes will be incorporated in the next release of the
specifications.
Note: Errata remain in the specification update throughout the product’s life cycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon request.
Specification changes, specification clarifications and documentation changes are
removed from the specification update when the appropriate changes are made to the
appropriate product specification or user documentation (datasheets, manuals, and so
forth).
Intel® Xeon® Processor 3300 Series 7
Specification Update January 2012
Summary Tables of Changes
The following table indicates the Specification Changes, Errata, Specification
Clarifications or Documentation Changes, which apply to the listed MCH steppings.
Intel intends to fix some of the errata in a future stepping of the component, and to
account for the other outstanding issues through documentation or Specification
Changes as noted. This table uses the following notations:
Codes Used in Summary Table
Stepping
X: Erratum, Specification Change or Clarification that
(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification
Status
Doc: Document change or update that will be implemented.
Plan Fix: This erratum may be fixed in a future stepping of the
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.
Row
Shaded: This item is either new or modified from the previous version of the
Item Numbering
Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
specification updates:
applies to this stepping.
change does not apply to listed stepping.
product.
document.
A = Intel® Xeon® processor 7000 sequence
C = Intel® Celeron® processor
D = Intel® Xeon® processor 2.80 GHz
E = Intel® Pentium® III processor
F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D
processor
I = Intel® Xeon® processor 5000 series
J = 64-bit Intel® Xeon® processor MP with 1 MB L2 cache
K = Mobile Intel® Pentium® III processor
8 Intel® Xeon® Processor 3300 Series
Specification Update January 2012
L = Intel® Celeron® D processor
M = Mobile Intel® Celeron® processor
N = Intel® Pentium® 4 processor
O = Intel® Xeon® processor MP
P = Intel ® Xeon® processor
Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Th reading technology
on 90-nm process technology
R = Intel® Pentium® 4 processor on 90 nm process
S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2
cache versions)
T = Mobile Intel® Pentium® 4 processor-M
U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache
V = Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA
package
W= Intel® Celeron® M processor
X = Intel® Pentium® M processor on 90nm process with 2-MB L2 cache and
Intel® processor A100 and A110 with 512-KB L2 cache
Y = Intel® Pentium® M processor
Z = Mobile Intel® Pentium® 4 processor with 533 MHz system bus
AA = Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor
Extreme Edition 955, 965
AB = Intel® Pentium® 4 processor 6x1 sequence
AC = Intel® Celeron® processor in 478 pin package
AD = Intel® Celeron® D processor on 65 nm processor
AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65 nm
process
AF = Intel® Xeon® processor LV
AG = Intel® Xeon® processor 5100 series
AH = Intel® Core™ 2 Duo/Solo processor for Intel® Centrino® Duo processor
technology
AI = Intel® Core™ 2 Extreme processor X6800 and Intel® Core™ 2 Duo desktop
processor E6000 and E4000 sequence
AJ = Intel® Xeon® processor 5300 series
AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel®
Core™ 2 Quad processor Q6000 sequence
AL = Intel® Xeon® processor 7100 series
AM= Intel® Celeron® processor 400 sequence
AN = Intel® Pentium® dual-core processor
AO = Intel® Xeon® processor 3200 series
AP = Intel® Xeon® processor 3000 series
AQ = Intel® Pentium® dual-core desktop processor E2000 sequence
Intel® Xeon® Processor 3300 Series 9
Specification Update January 2012
AR = Intel® Celeron® processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series
AT = Intel® Celeron® processor 200 series
AV = Intel® Core™ 2 Extreme Processor QX9650 Intel® Core™ 2 Extreme
Processor QX9650 and Intel® Core™ 2 Quad Processor Q9000 Series
AW = Intel® Core™ 2 Duo desktop processor E8000 and E7000 series
AX = Intel® Xeon® processor 5400 series
AY = Intel® Xeon® processor 5200 series
AAA = Intel® Xeon® processor 3300 series
AAB = Intel® Xeon® processor 3100 series
AAC= Intel® Celeron® dual-core processor E1000 series
The Specification Updates for the Pentium® processor, Pentium® Pro processor, and
other Intel products do not use this convention.
Table 1. Errata (Sheet 1 of 4)
NO C0 M0 C1 M1 E0 R0 Plan ERRATA
AAA1 XX X X X X No Fix
AAA2 X X X X X X No Fix
AAA3 X X X X X X No Fix
AAA4 X X X X X X No Fix Non-Temporal Data Store May be Observed in Wrong Program Order
AAA5 X X X X X X No Fix
AAA6 X X X X X X No Fix
AAA7 X X X X X X No Fix
AAA8 X X X X X X No Fix
AAA9 X X X X X X No Fix
AAA10XXX XXXNo FixPerformance Monitoring Event MISALIGN_MEM_REF May Over Count
AAA11XXX XXXNo FixThe Processor May Report a #TS Instead of a #GP Fault
AAA12XXX XXXNo FixCode Segment limit violation may occur on 4 Gigabyte limit check
AAA13XXX XXXNo Fix
AAA14XXX XXXNo Fix
AAA15XXX XXXNo Fix
AAA16XXX XXXNo Fix
EFLAGS Discrepancy on a Page Fault After a Multiprocessor TLB
Shootdown
EFLAGS Discrepancy on Page Fault After a Translation Change
INVLPG Operation for Large (2M/4M) Pages May be Incomplete
Under Certain Conditions
Store to WT Memory Data May be Seen in Wrong Order by Two
Subsequent Loads
Page Access Bit May be Set Prior to Signaling a Code Segment Limit
Fault
Updating Code Page Directory Attributes without TLB Invalidation
May Result in Improper Handling of Code #PF
Storage of PEBS Record Delayed Following Execution of MOV SS or
STI
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
A REP STOS/MOVS to a MONITOR/MWAIT Address Range May
Prevent Triggering of the Monitoring Hardware
A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
Last Branch Records (LBR) Updates May be Incorrect after a Task
Switch
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-Ordering Violations.
Upper 32 bits of ‘From’ Address Reported thr ough B T Ms or B TSs May
be Incorrect
10 Intel® Xeon® Processor 3300 Series
Specification Update January 2012
Table 1. Errata (Sheet 2 of 4)
NO C0 M0 C1 M1 E0 R0 Plan ERRATA
AAA17 X X X X X X No Fix
AAA18 X X X X X X No Fix
AAA19 X X X X X X No Fix Store Ordering May be Incorrect between WC and WP Memory Types
AAA20 X X X X X X No Fix
AAA21 X X X X X X No Fix
AAA22 X X X X X X No Fix
AAA23 X X X X X X No Fix
AAA24 X X X X X X No Fix
AAA25 X X X X X X No Fix
AAA26 X X X X X X No Fix
AAA27 X X X X X X No Fix
AAA28 X X X X X X No Fix INIT Does Not Clear Global Entries in the TLB
AAA29 X X X X X X No Fix Split Locked Stores May not Trigger the Monitoring Hardware
AAA30 X X X X X X No Fix
AAA31 X X X X X X No Fix
AAA32 X X X X X X No Fix
AAA33 X X X X X X No Fix An Asynchronous MCE During a Far Transfer May Corrupt ESP
AAA34 X X X X X X Plan Fix
AAA35 X X X X X X No Fix
AAA36 X X X X X X No Fix
AAA37 X X X X Fixed
AAA38 X X X X X X No Fix
AAA39 X X X X X X No Fix
AAA40 X X X X X X No Fix
AAA41 X X X X Fixed
AAA42 X X X X X X No Fix
Address Reported by Machine-Check Architecture (MCA) on Singlebit L2 ECC Errors May be Incorrect
Code Segment Limit/Canonical Faults on RSM May be Serviced
before Higher Priority Interrupts/Exceptions
EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after
Shutdown
Premature Execution of a Load Operation Prior to Exception Handler
Invocation
Performance Monitoring Events for Retired Instructions (C0H) May
Not Be Accurate
Returning to Real Mode from SMM with EFLAGS.VM Set May Result in
Unpredictable System Behavior
CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or
Equal to 248 May Terminate Early
Writing the Local Vector Table (LVT) when an Interrupt is Pending
May Cause an Unexpected Interrupt
Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
Before Higher Priority Interrupts
VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the
Last Exception Record (LER ) MSR
Programming the Digital Thermal Sensor (D TS) Threshold May Cause
Unexpected Thermal Interrupts
Writing Shared Unaligned Data that Crosses a Cache Line without
Proper Semaphores or Barriers May Expose a Memory Ordering Issue
General Protection (#GP) Fault May Not Be Signaled on Data
Segment Limit Violation above 4-G Limit
CPUID Reports Architectural Performance Monitoring Version 2 is
Supported, When Only Version 1 Capabilities are Available
B0-B3 Bits in DR6 May Not be Properly Cleared Af ter Code
Breakpoint
An xTPR Update Transaction Cycle, if Enabled, May be Issued to the
FSB after the Processor has Issued a Stop-Grant Special Cycle
Performance Monitoring Event IA32_FIXED_CTR2 May Not Function
Properly when Max Ratio is a Non-Integer Core-to-Bus Ratio
Instruction Fetch May Cause a Liv elock During Snoop s of the L1 Data
Cache
Use of Memory Aliasing with Inconsistent Memory T yp e may Cause a
System Hang or a Machine Check Exception
A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to
Memory-Ordering Violations
VM Exit with Exit Reason “TPR Below Th reshold” Can Cause the
Blocking by MOV/POP SS and Blocking by STI Bits to be Cleared in
the Guest Interruptibility-State Field
Using Memory Type Aliasing with cacheable and WC Memory Types
May Lead to Memory Ordering Violations
Intel® Xeon® Processor 3300 Series 11
Specification Update January 2012
Table 1. Errata (Sheet 3 of 4)
NO C0 M0 C1 M1 E0 R0 Plan ERRATA
AAA43XXX XXXNo Fix
AAA44 X X X X Fixed NMIs May Not Be Blocked by a VM-Entry Failure
AAA45 X X X X Fixed
AAA46 X X X X Fixed
AAA47 X X X X Fixed
AAA48XXX XXXPlan Fix
AAA49 X X X X Fixed
AAA50XXX XXXNo Fix
AAA51XXX XXXNo Fix
AAA52XXX XXXPlan Fix
AAA53XXX XXXNo Fix
AAA54XXX XXXNo Fix
AAA55XXX XXXNo Fix
AAA56XXX XXXNo Fix
AAA57XXX XXXNo Fix
AAA58XXX XXXPlan FixPSI# Signal Asserted During Reset
AAA59XXX XXXNo Fix
AAA60XXX XXXNo Fix
AAA61XXX XXXNo Fix
AAA62XXX XXXNo Fix
AAA63XXX XXXNo Fix
AAA64 X X No Fix
AAA65 X X No Fix VM Entry May Use Wrong Address to Access Virtual-APIC Page
AAA66 X X No Fix XRSTORE Instruction May Cause Extra Memory Reads
AAA67 X X Plan Fix CPUID Instruction May Return Incorrect Brand String
AAA68 X X No Fix
VM Exit Caused by a SIPI Results in Zero to be Saved to the Guest
RIP Field in the VMCS
Partial Streaming Load Instruction Sequence May Cause the
Processor to Hang
Self/Cross Modifying Code May Not be Detected or May Cause a
Machine Check Exception
Data TLB Eviction Condition in the Middle of a Cacheline Split Load
Operation May Cause the Processor to Hang
Update of Read/Write (R/W) or User/Super visor (U/S) or Presen t (P)
Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
RSM Instruction Execution under Certain Conditions May Cause
Processor Hang or Unexpected Instruction Execution Results
Benign Exception after a Double Fault May Not Cause a Triple Fault
Shutdown
LER MSRs May be Incorrectly UpdatedThe LER (Last Exception
Record) MSRs, MSR_LER_FROM_LIP (1DDH) and MSR_LER_TO_LIP
(1DEH) may contain incorrect values after any of the following:
Short Nested Loops That Span Multiple 16-Byte Boundaries May
Cause a Machine Check Exception or a System Hang
An Enabled Debug Breakpoint or Single Step Trap May Be T aken after
MOV SS/POP SS Instruction if it is Followed by an Instruction That
Signals a Floating Point Exception
IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check
Error Reporting Enable Correctly
A VM Exit Due to a Fault While Delivering a Software Interrupt May
Save Incorrect Data into the VMCS
A VM Exit Occurring in IA-32e Mode May Not Produce a VMX Abort
When Expected
IRET under Certain Conditions May Cause an Unexpected Alignment
Check Exception
Thermal Interrupts are Dropped During and While Exiting Deep
Power Down State
VM Entry May Fail When Attempting to Set
IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN
Corruption of CS Segment Register During RSM While Transitioning
From Real Mode to Protected Mode
LBR, BTS, BTM May Report a Wrong Address when an Exception/
Interrupt Occurs in 64-bit Mode
Memory Ordering Violation With Stores/Loads Crossing a Cacheline
Boundary
Processor May Hold-off / Delay a PECI Transaction Longer than
Specified by the PECI Protocol
Global Instruction TLB Entries May Not be Invalidat ed on a VM Exit or
VM Entry
12 Intel® Xeon® Processor 3300 Series
Specification Update January 2012
Table 1. Errata (Sheet 4 of 4)
NO C0 M0 C1 M1 E0 R0 Plan ERRATA
AAA69 X X No Fix
AAA70 X X No Fix
AAA71 X X No Fix INIT Incorrectly Resets IA32_LSTAR MSR
AAA72 X X No Fix
AAA73 X X No Fix
AAA74 X X No Fix Store Ordering Violation When Using XSAVE
AAA75 X X Plan Fix
AAA76 X X X X X X No Fix
AAA77 X X X X X X No Fix Intel® Trusted Execution Technology ACM Revocation
Number SPECIFICATION CHANGES
- There are no Specification Changes in this Specification Update revision.
Number SPECIFICATION CLARIFICATIONS
- There are no Specification Clarifications in this Specification Update revision.
When Intel® Deep Power-Down State is Being Used,
IA32_FIXED_CTR2 May Return Incorrect Cycle Counts
Enabling PECI via the PECI_CTL MSR Does Not Enable PECI and May
Corrupt the CPUID Feature Flags
The XRSTOR Instruction May Fail to Cause a General-Protection
Exception
The XSAVE Instruction May Erroneously Set Reserved Bits in the
XSTATE_BV Field
Unsynchronized Cross-Modifying Code Operations Can Cause
Unexpected Instruction Execution Results
A 64-bit Register IP-relative Instruction May Return Unexpected
Results
Number DOCUMENTATION CHANGES
- There are no Documentation Changes in this Specification Update revision.
Intel® Xeon® Processor 3300 Series 13
Specification Update January 2012
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