Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor, SL7PH - Xeon 3.6 GHz/800MHz/1MB CPU Processor, Xeon Series Specification

64-bit Intel® Xeon® Processor
with 800 MHz System Bus (1 MB
and 2 MB L2 Cache Versions)

Specification Update

June 2006

Notice: The 64-bit Intel
versions) may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are documented in this
specification update.

®

Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache

Document Number: 302402-022

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logo, Pentium, Pentium III Xeon, Celeron, Intel NetBurst and In te l Xeon are trad emarks or re giste red trad emarks of Intel Cor pora tion or

2 64-bit Intel® Xeon® Processor with 800 MHz System Bus

(1 MB and 2 MB L2 Cache Versions) Specification Update

Contents

Revision History .................................................................................................................5

Preface...............................................................................................................................6

Identification Information....................................................................................................7

Summary Table of Changes.............................................................................................12

Errata................................................................................................................................19

Specification Changes......................................................................................................44

Specification Clarifications ...............................................................................................45

Documentation Changes..................................................................................................46

64-bit Intel® Xeon® Processor with 800 MHz System Bus 3
(1 MB and 2 MB L2 Cache Versions) Specification Update

4 64-bit Intel® Xeon® Processor with 800 MHz System Bus

(1 MB and 2 MB L2 Cache Versions) Specification Update

Revision History

Version Description Date

-001 • Initial release of the document. July 2004

-002 • Removed erratum P18 and renumbered existing errata. July 2004

-003 • Added errata S32-S35. Renamed errata numbering from P to S. August 2004

-004 • Removed erratum S29 and renumbered existing errata.

• Added errata S35-S65.

• Added E0 step processor information to Table 1, “Identification

Information”.

• Added new notes to T able2, “64-bit Intel® Xeon® Processor with 800

MHz System Bus (1 MB and 2 MB L2 Cache Versions) Identification
Information” and deleted unnecessary notes.

• Added Table 3, “DP Platform Population Matrix for the 64-bit Intel®

Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2
Cache Versions) FC-PGA4 Package”.

-005 • Added errata S66-S73. October 2004

-006 • Updated S-Spec table, code key, and mixed steppings statement to
include Low Voltage Intel® Xeon® processor

• Added errata S74-S75.

-007 • Updated erratum S26. Added errata S76and S77. December 2004

-008 • Added errata S78-S79; added additional text to “Mixed Steppings In
DP Systems” chapter.

-009 • Added 2 MB L2 cache version of the 64-bit Intel® Xeon® processor
with 800 MHz system bus; added errata S80-S81; added S-spec
numbers SL7ZC, SL7ZD, SL7ZE, and SL7ZF to Table 2.

-010 • Updated errata S28 and S53; updated summary table entries for S19
and S43.

-011 • Updated Table 2; added erratum S82; updated plans colu mn for
erratum S27; added Specification Clarification 1.

-012 • Updated steppings affected for erratum S27. May 2005

-013 • Updated Table 2. June 2005

-014 • Added erratum S83. Updated relevant document lists. July 2005

-015 • Updated summary table entry for S19. Added erratum S84. August 2005

-016 • Added errata S85 and S86. Added S-spec numbers to Table 2. Added
R-0 stepping to summary table of changes. Updated summary table
entries. Removed duplicate erratum S33.

-017 • Added erratum S87. Updated letters in Codes used in Summary
Table. Corrected S-spec notes for 3.40 GHz entries.

-018 • Added errata S88 and S89. Updated steppings affected for S22.
Updated Mixed Steppings in DP Systems section.

-019 • Added erratum S90. December 2005

-020 • Added erratum S91. Updated erratum S17. January 2006

-021 • Added erratum S1S and S92. May 2006

-022 • Added erratum S93. June 2006

Revision History

September 2004

November 2004

January 2005

February 2005

March 2005

April 2005

September 2005

October 2005

November 2005

64-bit Intel® Xeon® Processor with 800 MHz System Bus 5
(1 MB and 2 MB L2 Cache Versions) Specification Update

Preface

Preface

This document is an update to the specifications contained in the following documents:

1. 64-bit Intel
Link: http://developer/design/xeon/datashts/306249.htm

2. Intel
Link: http://developer/design/xeon/datashts/302355.htm

This document is intended for hardware system manufacturers and software developers of
applications, operating systems, or tools.

Nomenclature

S-Spec Number is a five-digit code used to identify products. Products are differentiated by their
unique characteristics, e.g., core speed, L2 cache size, package type, etc. as described in the
processor identification information table. Care should be taken to read all notes associated with
each S-Spec number.

Errata are design defects or errors. Errata may cause the processor’s behavior to deviate from
published specifications. Hardware and software designed to be used with any given processor
must assume that all errata documented for that processor are present on all devices unless
otherwise noted.

Specification Changes are modifications to the current published specifications. These changes
will be incorporated in the next release of the specifications.

Specification Clarifications describe a specification in greater detail or further highlight a
specification’s impact to a complex design situation. These clarifications will be incorporated in
the next release of the specifications.

Documentation Changes include typos, errors, or omissions from the current published
specifications. These changes will be incorporated in the next release of the specifications.

®

Xeon® Processor with 2 MB L2 Cache Datasheet (Document Number 306249)

®

Xeon® Processor with 800 MHz System Bus Datasheet (Document Number 302355)

6 64-bit Intel® Xeon® Processor with 800 MHz System Bus

(1 MB and 2 MB L2 Cache Versions) Specification Update

Identification Information

Identification Information

64-bit Intel® Xeon® Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Package Markings
(604-pin FC-mPGA4 Package)

Figure 1. Top-Side Processor Marking Example

Intel Confidential

2D Matrix Includes
ATPO and Serial Number
(front end mark)

Pin 1 Indicator

Figure 2. Bottom-Side Marking Example

Pin 1 Indicator

Pin Field

Cavity

with

Components

Text Line1
Text Line2

Text Line3

The 64-bit Intel® Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2 cache
versions) can be identified by the following values:

SL7DV

80546KE0461M

FPO – Serial Number

S-Spec

64-bit Intel® Xeon® Processor with 800 MHz System Bus 7
(1 MB and 2 MB L2 Cache Versions) Specification Update

Identification Information

Table 1. Identification Information

1

Family

1111b 0011b 0000b
1111b 0100b 0000b

NOTES:

1. The Family corresponds to bits [11:8] of the EDX regist er after RESE T, bits [11: 8] of the
EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the
generation field of the Device ID registers accessible through Boundary Sca n

2. The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the
EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the
model field of the Device ID registers accessible through Boundary Scan.

3. Brand ID returns 0000b, which means that Brand ID is unsupported in this processor.

Model

2

Brand ID

3

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers
after the CPUID instruction is executed with a 2 in the EAX register. Please refer to the Intel
Processor Identification and the CPUID Instruction Application Note (AP-485) for further
information on the CPUID instruction.

Table 2. 64-bit Intel® Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache

Versions) Identification Information (Sheet 1 of 2)

S-Spec

SL7DV D-0 0F34h 2.80 800 1 MB 01 604-pin micro-PGA with 42.5 x

SL7HF 1
SL7DW D-0 0F34h 3 800 1 MB 01 604-pin micro-PGA with 42.5 x
SL7HG 1
SL7DX D-0 0F34h 3.20 800 1 MB 01 604-pin micro-PGA with 42.5 x
SL7HH 1
SL7DY D-0 0F34h 3.40 800 1 MB 01 604-pin micro-PGA with 42.5 x

SL7HJ 1, 2, 3

SL7DZ D-0 0F34h 3.60 800 1 MB 01 604-pin micro-PGA with 42.5 x
SL7HK 1, 2, 3
SL7PD E-0 0F41h 2.80 800 1 MB 01 604-pin micro-PGA with 42.5 x

SL7TB 1, 4, 6

SL7PE E-0 0F41h 3 800 1 MB 01 604-pin micro-PGA with 42.5 x

SL7TC 1, 4, 6

SL7PF E-0 0F41h 3.20 800 1 MB 01 604-pin micro-PGA with 42.5 x

SL7TD 1, 4, 6
SL7PG E-0 0F41h 3.40 800 1 MB 01 604-pin micro-PGA with 42.5 x

SL7TE 1, 3, 4, 6
SL7PH E-0 0F41h 3.60 800 1 MB 01 604-pin micro-PGA with 42.5 x

SL7VF 1, 2, 3, 4,

SL84B E-0 0F41h 2.80 800 1 MB 01 604-pin micro-PGA with 42.5 x

SL8KN G-1 0F49h 2.80 800 1 MB 01 604-pin micro-PGA with 42.5 x

Core

Stepping

CPUID

Core

Freq

(GHz)

Data Bus

Freq

(MHz)

L2

Cache

Size

Processor

Package
Revision

Package and Revision Notes

42.5 mm FC-PGA4 package

42.5 mm FC-PGA4 package

42.5 mm FC-PGA4 package

2, 3

42.5 mm FC-PGA4 package

2, 3

42.5 mm FC-PGA4 package

4, 6

42.5 mm FC-PGA4 package

4, 6

42.5 mm FC-PGA4 package

4, 6

42.5 mm FC-PGA4 package

3, 4, 6

42.5 mm FC-PGA4 package

2, 3, 4, 6

42.5 mm FC-PGA4 package
6

4, 5, 6

42.5 mm FC-PGA4 package

4, 6

42.5 mm FC-PGA4 package

8 64-bit Intel® Xeon® Processor with 800 MHz System Bus

(1 MB and 2 MB L2 Cache Versions) Specification Update

Identification Information

Table 2. 64-bit Intel® Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache

Versions) Identification Information (Sheet 2 of 2)

S-Spec

SL8KP G-1 0F49h 3 800 1 MB 01 604-pin micro-PGA with 42.5 x

SL8KQ G-1 0F49h 3.20 800 1 MB 01 604-pin micro-PGA with 42.5 x

SL8KR G-1 0F49h 3.40 800 1 MB 01 604-pin micro-PGA with 42.5 x

SL8KS G-1 0F49h 3.60 800 1 MB 01 604-pin micro-PGA with 42.5 x

SL8RW G-1 0F49h 2.80 800 1 MB 01 604-pin micro-PGA with 42.5 x

SL7ZC N-0 0F43h 3.60 800 2 MB 01 604-pin micro-PGA with 42.5 x

SL7ZD N-0 0F43h 3.40 800 2 MB 01 604-pin micro-PGA with 42.5 x

SL7ZE N-0 0F43h 3.20 800 2 MB 01 604-pin micro-PGA with 42.5 x

SL7ZF N-0 0F43h 3 800 2 MB 01 604-pin micro-PGA with 42.5 x

SL8P7 R-0 0F4Ah 2.80 800 2 MB 01 604-pin micro-PGA with 42.5 x

SL8P6 R-0 0F4Ah 3 800 2 MB 01 604-pin micro-PGA with 42.5 x

SL8P5 R-0 0F4Ah 3.20 800 2 MB 01 604-pin micro-PGA with 42.5 x

SL8P4 R-0 0F4Ah 3.40 800 2 MB 01 604-pin micro-PGA with 42.5 x

SL8P3 R-0 0F4Ah 3.60 800 2 MB 01 604-pin micro-PGA with 42.5 x

SL8P2 R-0 0F4Ah 3.80 800 2 MB 01 604-pin micro-PGA with 42.5 x

SL8SV R-0 0F4Ah 3 800 2 MB 01 604-pin micro-PGA with 42.5 x

SL8T3 R-0 0F4Ah 3.20 800 2 MB 01 604-pin micro-PGA with 42.5 x

Core

Stepping

CPUID

Core

Freq

(GHz)

Data Bus

Freq

(MHz)

L2

Cache

Size

Processor

Package
Revision

Package and Revision Notes

42.5 mm FC-PGA4 package

42.5 mm FC-PGA4 package

42.5 mm FC-PGA4 package

42.5 mm FC-PGA4 package

42.5 mm FC-PGA4 package

42.5 mm FC-PGA4 package

42.5 mm FC-PGA4 package

42.5 mm FC-PGA4 package

42.5 mm FC-PGA4 package

42.5 mm FC-PGA4 package

42.5 mm FC-PGA4 package

42.5 mm FC-PGA4 package

42.5 mm FC-PGA4 package

42.5 mm FC-PGA4 package

42.5 mm FC-PGA4 package

42.5 mm FC-PGA4 package

42.5 mm FC-PGA4 package

4, 6

4, 6

3, 4, 6

2, 3, 4, 6

4, 5, 6

2, 3, 4, 6

2, 3, 4, 6

2, 4, 6

2, 4, 6

2, 3, 4, 6

2, 4, 6

2, 4, 6

2, 3, 4, 6

2, 3, 4, 6

2, 3, 4, 6

2, 3, 4, 5,

6

2, 4, 6, 7

NOTES:

1. These are Intel boxed processors.

2. These parts have Thermal Monitor 2 (TM2) feature enabled. For D-0 stepping, TM2 is enabled on 3.40 GHz and above, but it is
NOT supported.

3. These parts are enabled for Enhanced Intel SpeedStep

4. These parts are enabled for Enhanced Halt State (C1E).

5. These parts are LV (low-power) processors.

6. These parts have Execute Disable bit functionality.

7. These parts are MV (mid-power) processors.

64-bit Intel® Xeon® Processor with 800 MHz System Bus 9
(1 MB and 2 MB L2 Cache Versions) Specification Update

®

Technology (EIST).

Identification Information

Mixed Steppings in DP Systems

Intel Corporation fully supports mixed steppings of the 64-bit Intel Xeon processor with 800 MHz
system bus as well as mixed steppings of the 64-bit Intel Xeon processor with 2 MB L2 cache. The
following list and processor matrix describes the requirements to support mixed steppings:

• Mixed steppings are only supported with processors that have identical family numbers as

indicated by the CPUID instruction.

• While Intel has done nothing to specifically prevent processors operating at differing

frequencies from functioning within a multiprocessor system, there may be uncharacterized
errata that exist in such configurations. Intel does not support such configurations. In mixed
stepping systems, all processors must operate at identical frequencies (i.e., the highest
frequency rating commonly supported by all processors).

• While there are no known issues associated with the mixing of processors with differing cache

sizes in a multiprocessor system, and Intel has done nothing to specifically prevent such
system configurations from operating, Intel does not support such configurations since there
may be uncharacterized errata that exist. In mixed stepping systems, all processors must be of
the same cache size.

• While Intel believes that certain customers may wish to perform validation of system

configurations with mixed frequencies, cache sizes or voltages and that those efforts are an
acceptable option to our customers, customers would be fully responsible for the validation of
such configurations.

• Intel requires that the proper microcode update be loaded on each processor operating in a

multiprocessor system. Any processor that does not have the proper microcode update loaded
is considered by Intel to be operating out of specification.

• The workarounds identified in this and following specification updates must be properly

applied to each processor in the system. Certain errata are specific to the multiprocessor
environment. Errata for all processor steppings will affect system performance if not properly
worked around. Also see Also see Table 2 and Table 3 for additional details on which
processors are affected by specific errata.

• In mixed stepping systems, the processor with the lowest feature-set, as determined by the

CPUID Feature Bytes, must be the Bootstrap Processor (BSP). In the event of a tie in
feature-set, the tie should be resolved by selecting the BSP as the processor with the lowest
stepping as determined by the CPUID instruction.

• While there are no known issues associated with the mixing of processors of different

power-optimization segments (i.e. LV or MV) in a multiprocessor system, and Intel has done
nothing to specifically prevent such system configurations from operating, Intel does not
support such configurations since there may be uncharacterized errata that exist. In mixed
stepping systems, all processors must be of the same power-optimization segment.

10 64-bit Intel® Xeon® Processor with 800 MHz System Bus

(1 MB and 2 MB L2 Cache Versions) Specification Update

Identification Information

Table 3. DP Platfor m Population Matrix for the 64-bit Intel® Xeon® Processor with 800 MHz

System Bus (1 MB and 2 MB L2 Cache Versions) FC-PGA4 Package

Processor Signature / Core

Stepping

0F34h / D-0 NI NI NI X X
0F41h / E-0 NI NI NI X X
0F49h / G-1 NI NI NI X X
0F43h / N-0 X X X NI NI
0F4Ah / R-0 X X X NI NI

NOTES:

1. X = Mixing processors of different steppings is not supported. This stepping/frequency is not supported in DP .

2. NI = Currently no known issues associated with mixing these steppings.

3. TBD = No issues are expected, however further investigation is required to fully validate this DP solution.

0F34h / D-0 0F41h / E-0 0F49h / G-1 0F43h / N-0 0F4Ah / R-0

64-bit Intel® Xeon® Processor with 800 MHz System Bus 11
(1 MB and 2 MB L2 Cache Versions) Specification Update

Summary Table of Changes

Summary Table of Changes

The following table indicates the Errata, Documentation Changes, Specification Clarifications, or
Specification Changes that apply to Intel processors. Intel intends to fix some of the errata in a
future stepping of the component, and to account for the other outstanding issues through
documentation or specification changes as noted. This table uses the following notation:

Codes Used In Summary Table

X: Erratum, Specification Change or Clarification that applies to the

given processor stepping.

(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification change does

not apply to listed stepping.
Doc: Document change or update that will be implemented.
Plan Fix: This erratum may be fixed in a future of the product.
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.

Change bar to left of table row indicates this item is either new or

modified from the previous version of this document.
Each Specification Update item will be prefixed with a capital letter to distinguish the product. The

key below details the letters that are used in Intel’s microprocessor Specification Updates:
A=Intel
B = Mobile Intel

C=Intel
D = Dual-Core Intel
E=Intel
F=Intel
G=Intel
H = Mobile Intel
J = 64-bit Intel
K = Mobile Intel
L=Intel
M = Mobile Intel
N=Intel
O=Intel
P=Intel
Q = Mobile Intel

®

Pentium® II processor

®

®

Celeron® processor

®

Pentium® III processor

®

Pentium® processor Extreme Edition and Intel® Pentium® D processor

®

Pentium® III Xeon® processor

®

Celeron® D processor

®
®

Xeon® processor MP

®

Xeon® processor

Pentium® II processor

®

Xeon® processor 2.80 GHz

®

Celeron® processor at 466/433/400/366/333/300 and 266 MHz

®

Xeon® processor MP with 1 MB L2 cache

®

Pentium® III processor

®

Celeron® processor

Pentium® 4 processor

®

Pentium® 4 processor supporting Hyper-Threading Technology on 90 nm

process technology
R=Intel
S = 64-bit Intel

®

Pentium® 4 processor on 90 nm process

®

Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache

versions)
T = Mobile Intel
U = 64-bit Intel
V = Mobile Intel

®

Pentium® 4 processor-M

®

Xeon® processor MP with up to 8 MB L3 cache

®

Celeron® processor on .13 micron process in micro-FCPGA package

12 64-bit Intel® Xeon® Processor with 800 MHz System Bus

(1 MB and 2 MB L2 Cache Versions) Specification Update

Summary Table of Changes

W= Intel® Celeron® M processor
X=Intel
Y=Intel
Z = Mobile Intel
AC = Intel

The Specification Updates for the Pentium

®

Pentium® M processor on 90 nm process with 2 MB L2 cache

®

Pentium® M processor

®

®

Celeron® processor in 478-pin package

Pentium® 4 processor with 533 MHz system bus

®

processor, Pentium® Pro processor, and other Intel

products do not use this convention.

Errata (Sheet 1 of 5)

No.

S1 XXXXXNo FixTransaction is not retired after BINIT#
S2 XXXXXNo FixInvalid opcode 0FFFh requires a ModRM byte
S3 XXXXXNo FixProcessor may hang due to speculative page walks to

S4 XXXXXNo FixMemory type of the load lock different from its corresponding

S5 XXXXXNo FixMachine Check Architecture error reporting and recovery may

S6 XXXXXNo FixDebug mechanisms may not function as expected
S7 XXXXXNo FixCascading of performance counters does not work correctly

S8 XXXXXNo FixEMON event counting of x87 loads may not work as expected
S9 XXXXXNo FixSystem bus interrupt messages without data and which

S10 XXXXXNo FixThe processor signals page fault exception (#PF) instead of

S11 XXXXXNo FixFSW may not be completely restored after page fault on

S12 XXXXXNo FixProcessor issues inconsistent transaction size attributes for

S13 XXXXXNo FixWhen the processor is in the system management mode

S14 XXXXXNo FixShutdown and IERR# may result due to a machine check

S15 XXXXXNo FixProcessor may hang under certain frequencies and 12.5%

S16 XXXXXNo FixSystem may hang if a fatal cache error causes bus write line

S17 XXXXXNo FixA write to APIC task priority register (TPR) that lowers priority

S18 XXXXXNo FixParity error in the L1 cache may cause the processor to hang
S19 XX FixedSequence of locked operations can cause two threads to

D-0/

0F34h

E-0/

0F41h

G-1/

0F49h

N-0/

0F43h

R-0/

0F4Ah

Plans Errata

non-existent system memory

store unlock

not work as expected

when forced overflow is enabled

receive a hard-failure response may hang the processor

alignment check exception (#AC) on an unlocked
CMPXCHG8B instruction

FRSTOR or FLDENV instructions

locked operation

(SMM), Debug registers may be fully writeable

exception on a Hyper-Threading Technology enabled
processor

STPCLK# duty cycle

(BWL) transaction to occur to the same cache line address as
an outstanding bus read line (BRL) or bus read-invalidate line
(BRIL)

may seem to have not occurred

receive stale data and cause application hang

64-bit Intel® Xeon® Processor with 800 MHz System Bus 13
(1 MB and 2 MB L2 Cache Versions) Specification Update

Summary Table of Changes

Errata (Sheet 2 of 5)

No.

S20 XFixedA 16-bit address wrap resulting from a near branch (jump or

S21 XXXXXNo FixBus locks and SMC detection may cause the processor to

S22 Fixed Incorrect physical address size returned by CPUID instruction
S23 XXXXXNo FixIncorrect debug exception (#DB) may occur when a data

S24 XXXXXNo FixxAPIC may not report some illegal vector errors
S25 XXXXXPlan FixEnabling no-eviction mode (NEM) may prevent the operation

S26 XXXXXPlan FixTPR (Task Priority Register) updates during voltage

S27 XXXXNo FixInteractions between the instruction translation lookaside

S28 XXX FixedSTPCLK# signal assertion under certain conditions may

S29 XXXXXNo FixIncorrect duty cycle is chosen when on-demand clock

S30 XXXXXNo FixMemory aliasing of pages as uncacheable memory type and

S31 XXXXXNo FixUsing STPCLK# and executing code from very slow memory

S32 XXXXXNo FixProcessor provides a 4-byte store unlock after an 8-byte load

S33 Duplicate Erratum: see S5
S34 XXXXXPlan FixExecution of IRET and INTn instructions may cause

S35 XXXXXNo FixData breakpoints on the high half of a floating-point line split

S36 XXXXXNo FixMachine Check Exceptions may not update Last-Exception

S37 XXXXXNo FixMOV CR3 performs incorrect reserved bit checking when in

S38 XXXXXNo FixStores to page tables may not be visible to pagewalks for

S39 XFixedA split store memory access may miss a data breakpoint
S40 XFixedEFLAGS.RF may be incorrectly set after an IRET instruction
S41 XFixedWriting the Echo TPR disable bit in IA32_MISC_ENABLE

S42 XFixedIncorrect access controls to

D-0/

0F34h

E-0/

0F41h

G-1/

0F49h

N-0/

0F43h

R-0/

0F4Ah

Plans Errata

call) may cause an incorrect address to be reported to the
#GP exception handler

temporarily hang

breakpoint is set on an FP instruction

of the second logical processor in a Hyper-Threading
Technology enabled boot strap processor (BSP)

transitions of power management events may cause a system
hang

buffer (ITLB) and the instruction streaming buffer may cause
unpredictable software behavior

cause a system hang

modulation is enabled in a processor supporting
Hyper-Threading Technology

write back (WB) may hang the system

could lead to a system hang

lock

unexpected system behavior

may not be captured

Record MSRs (LERs)

PAE paging

subsequent loads without serializing or invalidating the page
table entry

may cause a #GP fault

MSR_LASTBRANCH_0_FROM_LIP MSR registers

14 64-bit Intel® Xeon® Processor with 800 MHz System Bus

(1 MB and 2 MB L2 Cache Versions) Specification Update