Intel Xeon E5-2600 Series Monitoring Manual

Intel® Xeon® Processor E5-2600
Product Family Uncore Performance
Monitoring Guide

March 2012

Reference Number: 327043-001

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2 Reference Number: 327043-001

Contents

1Introduction..............................................................................................................9

1.1 Introduction .......................................................................................................9

1.2 Uncore PMON Overview.................................. .. ......................... .. .. .......................9

1.3 Section References............................................................................................10

1.4 Uncore PMON - Typical Control/Counter Logic .......................................................11

1.5 Uncore PMU Summary Tables ............................... ..............................................12

1.6 On Parsing and Using Derived Events...................................................................14

1.6.1 On Common Terms found in Derived Events ..............................................15

2 Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring.17

2.1 Uncore Per-Socket Performance Monitoring Control................................................17

2.1.1 Setting up a Monitoring Session ...............................................................17

2.1.2 Reading the Sample Interval....................................................................18

2.2 UBox Performance Monitoring.............................................................................19

2.2.1 Overview of the UBox .............................................................................19

2.2.2 UBox Performance Monitoring Overview ............................................ .. .. ....19

2.2.3 UBox Performance Monitors.....................................................................19

2.2.3.1 UBox Box Level PMON State.......................................................19

2.2.3.2 UBox PMON state - Counter/Control Pairs.....................................20

2.2.4 UBox Performance Monitoring Events....................................... ... ..............21

2.2.5 UBOX Box Events Ordered By Code ..........................................................21

2.2.6 UBOX Box Performance Monitor Event List.................................................21

2.3 Caching Agent (Cbo) Performance Monitoring................................. .......................22

2.3.1 Overview of the CBo...............................................................................22

2.3.2 CBo Performance Monitoring Overview ......................................................23

2.3.2.1 Special Note on CBo Occupancy Events........................................23

2.3.3 CBo Performance Monitors.......................................................................24

2.3.3.1 CBo Box Level PMON State.........................................................27

2.3.3.2 CBo PMON state - Counter/Control Pairs ......................................27

2.3.3.3 CBo Filter Register (Cn_MSR_PMON_BOX_FILTER) ........................28

2.3.4 CBo Performance Monitoring Events..........................................................30

2.3.4.1 An Overview: ............................... .. .. .......................... .. .. ..........30

2.3.4.2 Acronyms frequently used in CBo Events: ....................................30

2.3.4.3 The Queues: .................................... .......................... .. ............31

2.3.5 CBo Events Ordered By Code...................................................................31

2.3.6 CBO Box Common Metrics (Derived Events)...............................................32

2.3.7 CBo Performance Monitor Event List..........................................................34

2.4 Home Agent (HA) Performance Monitoring............................................................45

2.4.1 Overview of the Home Agent ...................................................................45

2.4.2 HA Performance Monitoring Overview.................. .. ... ........................... ......46

2.4.3 HA Performance Monitors........................................................................46

2.4.3.1 HA Box Level PMON State..........................................................46

2.4.3.2 HA PMON state - Counter/Control Pairs........................................47

2.4.4 HA Performance Monitoring Events.......................... .. .. .............................49

2.4.4.1 On the Major HA Structures: ......................................................49

2.4.5 HA Box Events Ordered By Code ..............................................................50

2.4.6 HA Box Common Metrics (Derived Events).................................................50

2.4.7 HA Box Performance Monitor Event List.....................................................51

2.5 Memory Controller (iMC) Performance Monitoring ..................................................59

2.5.1 Overview of the iMC ...............................................................................59

2.5.2 Functional Overview .................. .. ...........................................................59

2.5.3 iMC Performance Monitoring Overview................. .. ............................ .. ......59

2.5.4 iMC Performance Monitors....................... .. ..............................................60

Reference Number: 327043-001 3

2.5.4.1 MC Box Level PMON State ..........................................................60

2.5.4.2 MC PMON state - Counter/Control Pairs........................................61

2.5.5 iMC Performance Monitoring Events...........................................................62

2.5.5.1 An Overview:............................................................................62

2.5.6 iMC Box Events Ordered By Code............................... .. .. ...........................63

2.5.7 iMC Box Common Metrics (Derived Events)................................................63

2.5.8 iMC Box Performance Monitor Event List ....................................................64

2.6 Power Control (PCU) Performance Monitoring ........................................................72

2.6.1 Overview of the PCU ...............................................................................72

2.6.2 PCU Performance Monitoring Overview ......................................................72

2.6.3 PCU Performance Monitors.......................................................................72

2.6.3.1 PCU Box Level PMON State.........................................................73

2.6.3.2 PCU PMON state - Counter/Control Pairs.......................................74

2.6.3.3 Intel® PCU Extra Registers - Companions to PMON HW..................76

2.6.4 PCU Performance Monitoring Events..........................................................76

2.6.4.1 An Overview:............................................................................76

2.6.5 PCU Box Events Ordered By Code.............................................................78

2.6.6 PCU Box Common Metrics (Derived Events)................................................79

2.6.7 PCU Box Performance Monitor Event List....................................................79

2.7 Intel® QPI Link Layer Performance Monitoring.......................................................87

2.7.1 Overview of the Intel® QPI Box................................................................87

2.7.2 Intel® QPI Performance Monitoring Overview.............................................87

2.7.3 Intel® QPI Performance Monitors.............. .. .. ........................... .. ...............88

2.7.3.1 Intel® QPI Box Level PMON State ...............................................88

2.7.3.2 Intel® QPI PMON state - Counter/Control Pairs .............................89

2.7.3.3 Intel® QPI Registers for Packet Mask/Match Facility.......................90

2.7.3.4 Intel® QPI Extra Registers - Companions to PMON HW...................94

2.7.4 Intel® QPI LL Performance Monitoring Events.............................................94

2.7.4.1 An Overview.............................................................................94

2.7.4.2 Acronyms frequently used in Intel® QPI Events: ...........................95

2.7.5 Intel® QPI LL Box Events Ordered By Code................................................95

2.7.6 Intel QPI LL Box Common Metrics (Derived Events).....................................96

2.7.7 Intel® QPI LL Box Performance Monitor Event List ......................................98

2.8 R2PCIe Performance Monitoring.........................................................................111

2.8.1 Overview of the R2PCIe Box...................................................................111

2.8.2 R2PCIe Performance Monitoring Overview................................................111

2.8.3 R2PCIe Performance Monitors.................................................................112

2.8.3.1 R2PCIe Box Level PMON State................... ... .. .. .........................112

2.8.3.2 R2PCIe PMON state - Counter/Control Pairs ................................113

2.8.4 R2PCIe Performance Monitoring Events....................................................114

2.8.4.1 An Overview...........................................................................114

2.8.5 R2PCIe Box Events Ordered By Code.......................................................114

2.8.6 R2PCIe Box Common Metrics (Derived Events) .........................................114

2.8.7 R2PCIe Box Performance Monitor Event List .............................................115

2.9 R3QPI Performance Monitoring..........................................................................119

2.9.1 Overview of the R3QPI Box....................................................................119

2.9.2 R3QPI Performance Monitoring Overview .................................................119

2.9.3 R3QPI Performance Monitors..................................................................120

2.9.3.1 R3QPI Box Level PMON State............................................ ........120

2.9.3.2 R3QPI PMON state - Counter/Control Pairs..................................121

2.9.4 R3QPI Performance Monitoring Events.....................................................122

2.9.4.1 An Overview...........................................................................122

2.9.5 R3QPI Box Events Ordered By Code ........................................................122

2.9.6 R3QPI Box Common Metrics (Derived Events)...........................................123

2.9.7 R3QPI Box Performance Monitor Event List...............................................123

2.10 Packet Matching Reference................................................................................131

4 Reference Number: 327043-001

Figures

1-1 Uncore Sub-system Block Diagram of Intel Xeon Processor E5-2600 Family ................9

1-2 Perfmon Control/Counter Block Diagram...............................................................11

Tables

1-1 Per-Box Performance Monitoring Capabilities.........................................................10

1-2 MSR Space Uncore Performance Monitoring Registers.............................................12

1-3 PCICFG Space Uncore Performance Monitoring Registers ........................................13

2-1 UBox Performance Monitoring MSRs........................... .. .. ............................ ..........19

2-2 U_MSR_PMON_CTL{1- 0} Re g i s t er – F iel d Definitions .............................................20

2-3 U_MSR_PMON_CTR{1-0} Register – Field Definitions.............................................20

2-4 U_MSR_PMON_FIXED_CTL Register – Field Definitions ...........................................21

2-5 U_MSR_PMON_FIXED_CTR Register – Field Definitions...........................................21

2-8 CBo Performance Monitoring MSRs ......................................................................24

2-9 Cn_MSR_PMON_BOX_CTL Register – Field Definitions ............................................27

2-10 Cn_MSR_PMON_CTL{3-0} Register – Field Definitions............................................27

2-11 Cn_MSR_PMON_CTR{3-0} Register – Field Definitions ...........................................28

2-12 Cn_MSR_PMON_BOX_FILTER Register – Field Definitions........................................29

2-13 Opcode Match by IDI Packet Type for Cn_MSR_PMON_BOX_FILTER. opc ...................29

2-33 HA Performance Monitoring MSRs....................................... .. .. ........................... ..46

2-34 HA_PCI_PMON_BOX_CTL Register – Field Defin i tions ......................................... .. ..47

2-35 HA_PCI_PMON_CTL{3-0} Register – Field Definitions.............................................47

2-36 HA_PCI_PMON_CTR{3-0} Register – Field Definitions ............................................48

2-37 HA_PCI_PMON_BOX_OPCODEMATCH Register – Field Definitions............................48

2-38 HA_PCI_PMON_BOX_ADDRMATCH1 Register – Field Definitions...............................48

2-39 HA_PCI_PMON_BOX_ADDRMATCH0 Register – Field Definitions...............................49

2-59 iMC Performance Monitoring MSRs................................... ............................ .. .. ....60

2-60 MC_CHy_PCI_PMON_BOX_CTL Register – Field Definitions......................................60

2-61 MC_CHy_PCI_PMON_CTL{3-0} Register – Field Definitions .....................................61

2-62 MC_CHy_PCI_PMON_FIXED_CTL Register – Field Definitions ................................... 62

2-63 MC_CHy_PCI_PMON_CTR{FIXED,3-0} Register – Field Definitions ...........................62

2-73 PCU Performance Monitoring MSRs ......................................................................72

2-74 PCU_MSR_PMON_BOX_CTL Register – Field Definitions ..........................................73

2-75 PCU_MSR_PMON_CTL{3-0} Register – Field Definitions..........................................74

2-76 PCU_MSR_PMON_CTR{3-0} Register – Field Definitions .........................................75

2-77 PCU_MSR_PMON_BOX_FILTER Reg i s ter – F i el d De finitions......................................76

2-78 PCU_MSR_CORE_C6_CTR Register – Field Definitions.............................................76

2-79 PCU_MSR_CORE_C3_CTR Register – Field Definitions.............................................76

2-80 PCU Configuration Examples...............................................................................77

2-84 Intel® QPI Performance Monitoring Registers........................................................88

2-85 Q_Py_PCI_PMON_BOX_CTL Register – Field Definitions ..........................................89

2-86 Q_Py_PCI_PMON_CTL{3-0} Register – Field Definitions..........................................89

2-87 Q_Py_PCI_PMON_CTR{3-0} Register – Field Definitions .........................................90

2-88 Q_Py_PCI_PMON_PKT_MATCH1 Registers.............................................................91

2-89 Q_Py_PCI_PMON_PKT_MATCH0 Registers.............................................................91

2-90 Q_Py_PCI_PMON_PKT_MASK1 Registers...............................................................92

2-91 Q_Py_PCI_PMON_PKT_MASK0 Registers...............................................................92

2-92 Message Events Derived from the Match/Mask filters..............................................93

Reference Number: 327043-001 5

2-93 QPI_RATE_STATUS Register – Field Definitions ......................................................94

2-104 R2PCIe Performance Monitoring Registers ..... ......................................................112

2-105 R2_PCI_PMON_BOX_CTL Register – Field Definitions ............................................112

2-106 R2_PCI_PMON_CTL{3-0} Register – Field Definitions............................................113

2-107 R2_PCI_PMON_CTR{3-0} Register – Field Definitions ...........................................113

2-118 R3QPI Performance Monitoring Registers ............................................................120

2-119 R3_Ly_PCI_PMON_BOX_CTL Register – Field Definitions .......................................120

2-120 R3_Ly_PCI_PMON_CTL{2-0} Register – Field Definitions.......................................121

2-121 R3_Ly_PCI_PMON_CTR{2-0} Register – Field Definitions ......................................121

2-142 Intel® QuickPath Interconnect Packet Message Classes ........................................131

2-143 Opcode Match by Message Class........................................................................131

2-144 Opcodes (Alphabetical Listing)...........................................................................132

6 Reference Number: 327043-001

Revision History

Revision Description Date

327043-001 Initial release. March 2012

§

Reference Number: 327043-001 7

8 Reference Number: 327043-001

Introduction

1 Introduction

1.1 Introduction

The uncore subsystem of the Intel® Xeon® processor E5-2600 product family is shown in Figure 1-1.
The uncore subsystem also applies to the Intel® Xeon® processor E5-1600 product family in a
single-socket platform
CBox caching agent to the power controller unit (PCU), integrated memory controller (iMC) and home
agent (HA), to name a few. Most of these components provide similar performance monitoring
capabilities.

Figure 1-1. Uncore Sub-system Block Diagram of Intel Xeon Processor E5-2600 Family

1

. The uncore sub-system consists of a variety of components, r anging from the

1.2 Uncore PMON Overview

The uncore performance monitoring facilities are organized into per-component performance
monitoring (or ‘PMON’) units. A PMON unit within an uncore component may contain one of more
sets of counter registers. With the exception of the UBox, each PMON unit provides a unit-level
control register to synchronize actions across the counters within the box (e.g., to start/stop
counting).

1. The uncore sub-system in Intel® CoreTM i7-3930K and i7-3820 processors are derived from
above, hence most of the descriptions of this document also apply.

Reference Number: 327043-001 9

Introduction

Events can be collected by reading a set of local counter registers. Each counter register is paired with
a dedicated control register used to specify what to count (i.e. through the event select/umask fields)
and how to count it. Some units provide the ability to specify additional information that can be used
to ‘filter’ the monitored events (e.g., C-box; see Section 2.3.3.3, “CBo Filter Register

(Cn_MSR_PMON_BOX_FILTER)”).

Uncore performance monitors represent a per-socket resource that is not meant to be affected by
context switches and thread migration performed by the OS, it is recommended that the monitoring
software agent establish a fixed affinity binding to prevent cross-talk of event counts from different
uncore PMU.

The programming interface of the counter registers and control registers fall into two address spaces:

• Accessed by MSR are PMON registers within the Cbo units, PCU, and U-Box, see Table 1-2.

• Access by PCI device configuration space are PMON registers within the HA, iMC, Intel® QPI,
R2PCIe and R3QPI units, see Table 1-3.

Irrespective of the address-space difference and with only minor exceptions, the bit-granular layout of
the control registers to program event code, unit mask, start/stop, and signal filtering via threshold/
edge detect are the same.

The general performance monitoring capabilities of each box are outlined in the following table.

Table 1-1. Per-Box Performance Monitoring Capabilities

Box # Boxes

C-Box 8 4 1 N Y 44
HA 1 4 4 Y Y 48
iMC 1

(4 channels)
PCU 1 4 (+2) 4 N N 48
QPI 1

(2 ports)
R2PCIe 1 4 1 N N 44
R3QPI 1

(2 links)

U-Box 1 2 (+1) 0 N/A N 44

# Counters/

Box

4 (+1)

(per channel)

(per port)

# Queue
Enabled

4

31N N44

Bus

Lock?

4N N 48

4N Y? 48

Packet Match/

Mask Filters?

Bit Width

1.3 Section References

The following sections provide a breakdown of the performance monitoring capabilities for each box.

• Section 2.1, “Uncore Per-Socket Performance Monitoring Control”

• Section 2.2, “UBox Performance Monitoring”

• Section 2.3, “Caching Agent (Cbo) Performance Monitoring”

• Section 2.6, “Power Control (PCU) Performance Monitoring”

• Section 2.4, “Home Agent (HA) Performance Monitoring”

• Section 2.5, “Memory Controller (iMC) Performance Monitoring”

• Section 2.7, “Intel® QPI Link Layer Performance Monitoring”

• Section 2.9, “R3QPI Performance Monitoring”

• Section 2.8, “R2PCIe Performance Monitoring”

• Section 2.10, “Packet Matching Reference”

10 Reference Number: 327043-001

Introduction

1.4 Uncore PMON - Typical Control/Counter Logic

Following is a diagram of the standard perfmon counter block illustrating how event information is
routed and stored within each counter and how its paired control register helps to select and filter the
incoming information. Details for how control bits affect event information is presented in each of the
box subsections of Chapter 2, with some summary information below.

Note: The PCU uses an adaptation of this block (refer to Section 2.6.3, “PCU Performance

Monitors” more information). Also note that only a subset of the available control bits

are presented in the diagram.

Figure 1-2. Perfmon Control/Counter Block Diagram

Selecting What To Monitor: The main task of a configuration register is to select the event to be

monitored by its respective data counter. Setting the .ev_sel and .umask fields performs the event
selection.

Telling HW that the Control Register Is Set: .en bit must be set to 1 to enable counting. Once
counting has been enabled in the box and global level of the Performance Monitoring H ier archy (refer
to Section 2.1.1, “Setting up a Monitoring Session” for more information), the paired data register will
begin to collect events.

Reference Number: 327043-001 11

Introduction

Additional control bits include:
Applying a Threshold to Incoming Events: .thresh - since most counters can increment by a

value greater than 1, a threshold can be applied to generate an event based on the outcome of the
comparison. If the .thresh is set to a non-zero value, that value is compared against the incoming
count for that event in each cycle. If the incoming count is >= the threshold value, then the event
count captured in the data register will be incremented by 1.

Using the threshold field to generate additional events can be particularly useful when applied to a
queue occupancy count. For example, if a queue is known to contain eight entries, it may be useful to
know how often it contains 6 or more entires (i.e. Almost Full) or when it contains 1 or more entries
(i.e. Not Empty).

Note: The .invert and .edge_det bits follow the threshold comparison in sequence. If a user

wishes to apply these bits to events that only increment by 1 per cycle, . thresh must be
set to 0x1.

Inverting the Threshold Comparison: .invert - Changes the .thresh test condition to ‘<‘.
Counting State Transitions Instead of per-Cycle Events: .edge_det - Rather than accumulating

the raw count each cycle (for events that can increment by 1 per cycle), the register can capture
transitions from no event to an event incoming (i.e. the ‘Rising Edge’).

1.5 Uncore PMU Summary Tables

Following is a list of the registers provided in the Uncore for Performance Monitoring. It should be
noted that the PMON interfaces are split between MSR space (U, CBo and PCU) and PCICFG space.

Table 1-2. MSR Space Uncore Performance Monitoring Registers (Sheet 1 of 2)

Box MSR Addresses Description

C-Box Counters

C-Box 7

C-Box 6

C-Box 5

C-Box 4

C-Box 3

0xDF9-0xDF6 Counter Registers

0xDF4 Counter Filters

0xDF3-0xDF0 Counter Config Registers

0xDE4 Box Control

0xDD9-0xDD6 Counter Registers

0xDD4 Counter Filters

0xDD3-0xDD0 Counter Config Registers

0xDC4 Box Control

0xDB9-0xDB6 Counter Registers

0xDB4 Counter Filters

0xDB3-0xDB0 Counter Config Registers

0xDA4 Box Control

0xD99-0xD96 Counter Registers

0xD94 Counter Filters

0xD93-0xD90 Counter Config Registers

0xD84 Box Control

0xD79-0xD76 Counter Registers

0xD74 Counter Filters

0xD73-0xD70 Counter Config Registers

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Introduction

Table 1-2. MSR Space Uncore Per formance Monitoring Registers (Sheet 2 of 2)

Box MSR Addresses Description

0xD64 Box Control

C-Box 2

C-Box 1

C-Box 0

PCU Counters

U-Box Counters

For U-Box

0xD59-0xD56 Counter Registers

0xD54 Counter Filters

0xD53-0xD50 Counter Config Registers

0xD44 Box Control

0xD39-0xD36 Counter Registers

0xD34 Counter Filters

0xD33-0xD30 Counter Config Registers

0xD24 Box Control

0xD19-0xD16 Counter Registers

0xD14 Counter Filters

0xD13-0xD10 Counter Config Registers

0xD04 Box Control

0xC39-0xC36 Counter Registers

0xC24 Box Control

0xC34 Counter Filters
0xC33-0xC30 Counter Config Registers
0x3FC-0x3FD Fixed Counters (Non-PMON)

0xC17-0xC16 Counter Registers
0xC11-0xC10 Counter Config Registers

0xC09-0xC08 Fixed Counter/Config Register

Table 1-3. PCICFG Space Uncore Performance Monitoring Registers (Sheet 1 of 2)

Box

PCICFG Register

Addresses

R3QPI D19:F5,6 F(5,6) for Link 0,1

F4 Box Control
E0-D8 Counter Config Registers
B4-A0 Counter Registers

R2PCIe D19:F1

F4 Box Control
E4-D8 Counter Config Registers
BC-A0 Counter Registers

iMC D16:F0,1,4,5

F4 Box Control

F0 Counter Config Register (Fixed)

Reference Number: 327043-001 13

F(0,1,4,5) For Channel 0,1,2,3

Description

Introduction

Table 1-3. PCICFG Space Uncore Performance Monitoring Registers (She et 2 of 2)

Box

HA D14:F1

QPI D8,9:F2 D(8,9) for Port 0,1

QPI Mask/Match D8,9:F6 D(8,9) for Port 0,1

QPI Misc D8,9:F0 D(8,9) for Port 0,1

PCICFG Register

Addresses

E4-D8 Counter Config Registers (General)

D4-D0 Counter Register (Fixed)

BC-A0 Counter Registers (General)

F4 Box Control
E4-D8 Counter Config Registers
BC-A0 Counter Registers

48-40 Opcode/Addr Match Filters

F4 Box Control
E4-D8 Counter Config Registers
BC-A0 Counter Registers

23C-238 Mask 0,1
22C-228 Match 0,1

D4 QPI Rate Status

Description

1.6 On Parsing and Using Derived Events

For many of the sections in the chapter covering the Performance Monitoring capabilites of each box,
a set of commonly measured metrics or ‘Derived Events’ have been included. For the most part,
these derived events are simple mathetmatical combinations of events found within the box. (e.g.
[SAMPLE]) However, there are some extensions to the notation used by the metrics.

Following is a breakdown of a Derived Event to illustrate many of the notations used. To calculcate
“Average Number of Data Read Entries that Miss the LLC when the TOR is not empty”.

(TOR_OCCUPANCY.MISS_OPCODE / COUNTER0_OCCUPANCY{edge_det,thresh=0x1}))
with:Cn_MSR_PMON_BOX_FILTER.opc=0x182.

Requires programming an extra control register (often for filtering):

• For a single field: with:Register_Name.field=value1

• For multiple fields: with:Register_Name.{field1,field2,...}={value1,value2,...}

•e.g.,

Requires reading a fixed data register

• For the case where the metric requires the information contained in a fixed data register, the

with:Cn_MSR_PMON_BOX_FILTER.{opc,nid}={0x182,my_node}

pnemonic for the register will be included in the equation. Software will be responsible for
configuring the data register and setting it to start counting with the other events used by the
metric.

14 Reference Number: 327043-001

Introduction

•e.g., POWER_THROTTLE_CYCLES.RANKx / MC_Chy_PCI_PMON_CTR_FIXED

Requires more input to software to determine the specific event/subevent

• In some cases, there may be multiple events/subevents that cover the same information across
multiple like hardware units. Rather than manufacturing a derived event for each combination,
the derived event will use a lower case variable in the event name.

•e.g., POWER_CKE_CYCLES.RANKx / MC_Chy_PCI_PMON_CTR_FIXED where ‘x’ is a variable to cover
events POWER_CKE_CYCLES.RANK0 through POWER_CKE_CYCLES.RANK7

Requires setting extra control bits in the register the event has been programmed in:

• event_name[.subevent_name]{ctrl_bit[=value],}

•e.g.,

NOTE: If there is no [=value] specified it is assumed that the bit must be set to 1.

Requires gathering of extra information outside the box (often for common terms):

• See following section for a breakdown of common terms found in Derived Events.

COUNTER0_OCCUPANCY{edge_det,thresh=0x1}

1.6.1 On Common Terms found in Derived Events

To convert a Latency term from a count of clocks to a count of nanoseconds:

•(Latency Metric) - {Box}_CLOCKTICKS * (1000 / UNCORE_FREQUENCY)

To convert a Bandwidth term from a count of raw bytes at the operating clock to GB/sec:

•((Traffic Metric in Bytes) / (SAMPLE_INTERVAL / (TSC_SPEED * 1000000))) /
GB_CONVERSION

• e.g., For READ_MEM_BW, an event derived from iMC:CAS_COUNT.RD * 64, which is the amount
of memory bandwidth consumed by read requests, put ‘READ_MEM_BW’ into the bandwidth term
to convert the measurement from raw bytes to GB/sec.

Following are some other terms that may be found wi thin Metrics and how they should be interpreted.

• GB_CONVERSION: 1024^3

• TSC_SPEED: Time Stamp Counter frequency in MHz

• SAMPLE_INTERVAL = TSC end time - TSC start time.

§

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2 Intel® Xeon® Processor E5-

2600 Product Family Uncore
Performance Monitoring

2.1 Uncore Per-Socket Performance Monitoring Control

The uncore PMON does not support interrupt based sampling. T o manage the large number of counter
registers distributed across many units and collect event data efficiently, this section describes the
hierarchical technique to start/stop/restart event counting that a software agent may need to perform
during a monitoring session.

2.1.1 Setting up a Monitoring Session

On HW reset, all the counters are disabled. Enabling is hierarchical. So the following steps, which
include programming the event control registers and enabling the counters to begin collecting events,
must be taken to set up a monitoring session. Section 2.1.2 co vers the steps to stop/re-start counter
registers during a monitoring session.

For each box in which events will be measured: Skip (a) and (b) for U-Box monitoring.
a) Enable each box to accept the freeze signal to start/stop/re-start all counter registers in that box
e.g., set Cn_MSR_PMON_BOX_CTL.frz_en to 1

Note: Recommended: set the .frz_en bits during the setup phase for each box a user intends

to monitor, and left alone for the duration of the monitoring session.

b) Freeze the box’s counters while setting up the monitoring session.
e.g., set Cn_MSR_PMON_BOX_CTL.frz to 1

For each event to be measured within each box:

c) Enable counting for each monitor
e.g. Set C0_MSR_PMON_CTL2.en to 1

Note: Recommended: set the .en bit for all counters in each box a user intends to monitor,

and left alone for the duration of the monitoring session.

d) Select event to monitor if the event control register hasn’t been programmed:

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Program the .ev_sel and .umask bits in the control register with the encodings necessary to capture
the requested event along with any signal conditioning bits (.thresh/.edge_det/.invert) used to qualify
the event.

e.g., Set C0_MSR_PMON_CT2.{ev_sel, umask} to {0x03, 0x1} in order to capture
LLC_VICTIMS.M_STATE in CBo 0’s C0_MSR_PMON_CTR2.

Note: It is also important to program any additional filter registers used to further qualify the

events (e.g., setting the opcode match field in Cn_MSR_BOX_FILTER to qualify
TOR_INSERTS by a specific opcode).

Back to the box level:

e) Reset counters in each box to ensure no stale values have been acquired from previous sessions.

• For each CBo, set Cn_MSR_PMON_BOX_CTL[1:0] to 0x2.

• For each Intel® QPI Port, set Q_Py_PCI_PMON_BOX_CTL[1:0] to 0x2.

• Set PCU_MSR_PMON_BOX_CTL[1:0] to 0x2.

• For each Link, set R3QPI_PCI_PMON_BOX_CTL[1:0] to 0x2.

• Set R2PCIE_PCI_PMON_BOX_CTL[1:0] to 0x2.

Note: The UBox does not have a Unit Control register and neither the iMC nor the HA have a

reset bit in their Unit Control register. The counters in the UBox, the HA each populated
DRAM channel in the iMC will need to be manually reset by writing a 0 in each data
register.

Back to the box level:

f) Commence counting at the box level by unfreezing the counters in each box
e.g., set Cn_MSR_PMON_BOX_CTL.frz to 0
And with that, counting will begin.

Note: The UBox does not have a Unit Control register. Once enabled and programmed with a

valid event, they will be collecting events. For somewhat better synchronization, a user
can keep the U_MSR_PMON_CTL.ev_sel at 0x0 while enabled and write it with a valid
value just prior to unfreezing the registers in other boxes.

2.1.2 Reading the Sample Interval

Software can poll the counters whenever it chooses.
a) Polling - before reading, it is recommended that software freeze the counters in each box in which

counting is to take place (by setting *_PMON_BOX_CTL.frz_en and .frz to 1). After reading the event
counts from the counter registers, the monitoring agent can choose to reset the event counts to avoid
event-count wrap-around; or resume the counter register without resetting their values. The latter
choice will require the monitoring agent to check and adjust for potential wrap-around situations.

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2.2 UBox Performance Monitoring

2.2.1 Overview of the UBox

The UBox serves as the system configuration controller for the Intel Xeon Processor E5-2600 family
uncore.

In this capacity, the UBox acts as the central unit for a variety of functions:

• The master for reading and writing physically distributed registers across the uncore using the
Message Channel.

• The UBox is the intermediary for interrupt traffic, receiving interrupts from the sytem and
dispatching interrupts to the appropriate core.

• The UBox serves as the system lock master used when quiescing the platform (e.g., Intel® QPI
bus lock).

2.2.2 UBox Performance Monitoring Overview

The UBox supports event monitoring through two programmable 44-bit wide counters
(U_MSR_PMON_CTR{1:0}), and a 48-bit fixed counter which increments each u-clock. Each of these
counters can be programmed (U_MSR_PMON_CTL{1:0}) to monitor any UBox event.

For information on how to setup a monitoring session, refer to Section 2.1, “Uncore Per- Sock et

Performance Monitoring Control”

.

2.2.3 UBox Performance Monitors

Table 2-1. UBox Performance Monitoring MSRs

MSR Name

U_MSR_PMON_CTR1 0x0C17 64 U-Box PMON Counter 1
U_MSR_PMON_CTR0 0x0C16 64 U-Box PMON Counter 0

U_MSR_PMON_CTL1 0x0C11 64 U-Box PMON Control for Counter 1
U_MSR_PMON_CTL0 0x0C10 32 U-Box PMON Control for Counter 0

U_MSR_PMON_UCLK_FIXED_CTR 0x0C09 64 U-Box PMON UCLK Fixed Counter
U_MSR_PMON_UCLK_FIXED_CTL 0x0C08 32 U-Box PMON UCLK Fixed Counter Control

MSR

Address

2.2.3.1 UBox Box Level PMON State

The following registers represent the state governing all box-level PMUs in the UBox.

Size

(bits)

Description

U

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2.2.3.2 UBox PMON state - Counter/Control Pairs

The following table defines the layout of the UBox performance monitor control registers. The main
task of these configuration registers is to select the event to be monitored by their respective data
counter (.ev_sel, .umask). Additional control bits are provided to shape the incoming events (e.g.
.invert, .edge_det, .thresh) as well as provide additional functionality for monitoring software (.rst).

Table 2-2. U_MSR_PMON_CTL{1-0} Register – Field D efinitions

Field Bits Attr

rsv 31:29 RV 0 Reserved (?)
thresh 28:24 RW 0 Threshold used in counter comparison.
invert 23 RW 0 Invert comparison against Threshold.

en 22 RW 0 Local Counter Enable.
rsv 21:20 RV 0 Reserved. SW must write to 0 for proper operation.
rsv 19 RV 0 Reserved (?)
edge_det 18 RW 0 When set to 1, rather than measuring the event in each cycle it

rst 17 WO 0 When set to 1, the corresponding counter will be cleared to 0.
umask 15:8 RW 0 Select subevents to be counted within the selected event.
ev_sel 7:0 RW 0 Select event to be counted.

HW

Reset

Val

Description

0 - comparison will be ‘is event increment >= threshold?’.
1 - comparison is inverted - ‘is event increment < threshol d?’

NOTE: .invert is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.

Also, if .edge_det is set to 1, the counter will increment when a 1
to 0 transition (i.e. falling edge) is detected.

is active, the corresponding counter will incr ement when a 0 to 1
transition (i.e. rising edge) is detected.

When 0, the counter will increment in each cycle that the event
is asserted.

NOTE: .edge_det is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.

The UBox performance monitor data registers are 44-bit wide. Should a counter ov erflow (a carry out
from bit 43), the counter will wrap and continue to collect events.

If accessible, software can continuously read the data registers without disabling event collection.

Table 2-3. U_MSR_PMON_CTR{1-0} Register – Field Definitions

Field Bits Attr

rsv 63:44 RV 0 Reserved (?)
event_count 43:0 RW-V 0 44-bit performance event counter

HW

Reset

Val

Description

The Global UBox PMON registers also include a fixed counter that increments at UCLK for each cycle it
is enabled.

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Table 2-4. U_MSR_PMON_FIXED_CTL Register – Field Definitions

Field Bits Attr

rsv 31:23 RV 0 Reserved (?)
en 22 RW 0 Enable counter when global enable is set.
rsv 21:20 RV 0 Reserved. SW must write to 0 for proper operation.
rsv 19:0 RV 0 Reserved ( ?)

HW

Rese

t Val

Description

Table 2-5. U_MSR_PMON_FIXED_CTR Register – Field Definitions

Field Bits Attr

rsv 63:44 RV 0 Reserved (?)
event_count 43:0 RW-V 0 48-bit performance event counter

HW

Reset

Val

Description

2.2.4 UBox Performance Monitoring Events

The set of events that can be monitored in the UBox are summarized in Section 2.2.

2.2.5 UBOX Box Events Ordered By Code

The following table summarizes the directly measured UBOX Box events.

Table 2-6. Performance Monitor Events for UBOX

Symbol Name

EVENT_MSG 0x42 0 0-1 1 VLW Received
LOCK_CYCLES 0x44 0 0-1 1 IDI Lock/SplitLock Cycles

Event

Code

Extra

Select

Bit

Ctrs

Max

Inc/

Cyc

Description

2.2.6 UBOX Box Performance Monitor Event List

The section enumerates the uncore performance monitoring events for the UBOX Box.

EVENT_MSG

• Title: VLW Received

• Category: EVENT_MSG Events

• Event Code: 0x42

• Max. Inc/Cyc: 1, Register Restrictions: 0-1

• Definition: Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread

to filter on using NCUPMONCTRLGLCTR.ThreadID.

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Table 2-7. Unit Masks for EVENT_MSG

Extension

VLW_RCVD bxxxxxxx1
MSI_RCVD bxxxxxx1x
IPI_RCVD bxxxxx1xx
DOORBELL_RCVD bxxxx1xxx
INT_PRIO bxxx1xxxx

umask
[15:8]

Description

LOCK_CYCLES

• Title: IDI Lock/SplitLock Cycles

• Category: LOCK Events

• Event Code: 0x44

• Max. Inc/Cyc: 1, Register Restrictions: 0-1

• Definition: Number of times an IDI Lock/SplitLock sequence was started

2.3 Caching Agent (Cbo) Performance Monitoring

2.3.1 Overview of the CBo

The LLC coherence engine (CBo) manages the interface between the core and the last level cache
(LLC). All core transactions that access the LLC are directed from the core to a CBo via the ring
interconnect. The CBo is responsible for managing data delivery from the LLC to the requesting core.
It is also responsible for maintaining coherence between the cores within the socket that share the
LLC; generating snoops and collecting snoop responses from the local cores when the MESIF protocol
requires it.

So, if the CBo fielding the core request indicates that a core within the socket owns the line (for a
coherent read), the request is snooped to that local core. That same CBo will then snoop all peers
which might have the address cached (other cores, remote sockets, etc) and send the request to the
appropriate Home Agent for conflict checking, memory requests and writebacks.

In the process of maintaining cache coherency within the socket, the CBo is the gate keeper for all

®

QuickPath Interconnect (Intel® QPI) messages that originate in the core and is responsible for

Intel
ensuring that all Intel

®

QPI messages that pass through the socket’s LLC remain coherent.

The CBo manages local conflicts by ensuring that only one request is issued to the system for a
specific cacheline.

The uncore contains up to eight instances of the CBo, each assigned to manage a distint 2.5MB slice
of the processor’s total LLC capacity. A slice that can be up to 20-way set associative. For processors
with fewer than 8 2.5MB LLC slices, the CBo Boxes or missing slices will still be active and track ring
traffic caused by their co-located core even if they have no LLC related traffic to track (i.e. hits/
misses/snoops).

Every physical memory address in the system is uniquely associated with a single CBo instance via a
proprietary hashing algorithm that is designed to keep the distribution of traffic across the CBo
instances relatively uniform for a wide range of possible address patterns. This enables the individual
CBo instances to operate independently , each man aging its slice of the physical address space without
any CBo in a given socket ever needing to communicate with the other CBos in that same socket.

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2.3.2 CBo Performance Monitoring Overview

Each of the CBos in the uncore supports event monitoring through four 44-bit wide counters
(Cn_MSR_PMON_CTR{3:0}). Event programming in the CBo is restricted such that each events can
only be measured in certain counters within the CBo. For example, counter 0 is dedicated to
occupancy events. No other counter may be used to capture occupancy events.

• Counter 0: Queue-occupancy-enabled counter that tracks all events

• Counter 1: Basic counter that tracks all but queue occupancy events

• Counter 2: Basic counter that tracks ring events and the occupancy companion event
(COUNTER0_EVENT).

• Counter 3: Basic counter that tracks ring events and the occupancy companion event
(COUNTER0_EVENT).

CBo counter 0 can increment by a maximum of 20 per cycle; counters 1-3 can increment by 1 per
cycle.

Some uncore performance events that monitor transaction activities require additional details that
must be programmed in a filter register. Each Cbo provides one filter register and allows only one
such event be programmed at a given time, see Section 2.3.3.3.

For information on how to setup a monitoring session, refer to Section 2.1, “Uncore Per- Sock et

Performance Monitoring Control”

.

2.3.2.1 Special Note on CBo Occupancy Events

Although only counter 0 supports occupancy events, it is possible to program coounters 1-3 to
monitor the same occupancy event by selecting the “OCCUPANCY_COUNTER0” event code on
counters 1-3.

This allows:

• Thresholding on all four counters.

While one can monitor no more than one queue at a time, it is possible to setup different queue
occupancy thresholds on each of the four counters. For example, if one wanted to monitor the
IRQ, one could setup thresholds of 1, 7, 14, and 18 to get a picture of the time spent at different
occupancies in the IRQ.

• Average Latency and Average Occupancy

It can be useful to monitor the average occupancy in a queue as well as the average number of
items in the queue. One could program counter 0 to accumulate the occupancy, counter 1 with
the queue’s allocations event, and counter 2 with the OCCUPANCY_COUNTER0 event and a
threshold of 1. Latency could then be calculated by counter 0 / counter 1, and occupancy by
counter 0 / counter 2.

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2.3.3 CBo Performance Monitors

Table 2-8. CBo Performance Monitoring MSRs (Sheet 1 of 4)

MSR Name

CBo 0 PMON Registers
Generic Counters

C0_MSR_PMON_CTR3 0x0D19 64 CBo 0 PMON Counter 3
C0_MSR_PMON_CTR2 0x0D18 64 CBo 0 PMON Counter 2
C0_MSR_PMON_CTR1 0x0D17 64 CBo 0 PMON Counter 1
C0_MSR_PMON_CTR0 0x0D16 64 CBo 0 PMON Counter 0

Box-Level Filter

C0_MSR_PMON_BOX_FILTER 0x0D14 32 CBo 0 PMON Filter

Generic Counter Control

C0_MSR_PMON_CTL3 0x0D13 32 CBo 0 PMON Control for Counter 3
C0_MSR_PMON_CTL2 0x0D12 32 CBo 0 PMON Control for Counter 2
C0_MSR_PMON_CTL1 0x0D11 32 CBo 0 PMON Control for Counter 1
C0_MSR_PMON_CTL0 0x0D10 32 CBo 0 PMON Control for Counter 0

Box-Level Control/Status

C0_MSR_PMON_BOX_CTL 0x0D04 32 CBo 0 PMON Box-Wide Control

CBo 1 PMON Registers
Generic Counters

C1_MSR_PMON_CTR3 0x0D39 64 CBo 1 PMON Counter 3
C1_MSR_PMON_CTR2 0x0D38 64 CBo 1 PMON Counter 2
C1_MSR_PMON_CTR1 0x0D37 64 CBo 1 PMON Counter 1
C1_MSR_PMON_CTR0 0x0D36 64 CBo 1 PMON Counter 0

Box-Level Filter

C1_MSR_PMON_BOX_FILTER 0x0D34 32 CBo 1 PMON Filter

Generic Counter Control

C1_MSR_PMON_CTL3 0x0D33 32 CBo 1 PMON Control for Counter 3
C1_MSR_PMON_CTL2 0x0D32 32 CBo 1 PMON Control for Counter 2
C1_MSR_PMON_CTL1 0x0D31 32 CBo 1 PMON Control for Counter 1
C1_MSR_PMON_CTL0 0x0D30 32 CBo 1 PMON Control for Counter 0

Box-Level Control/Status

C1_MSR_PMON_BOX_CTL 0x0D24 32 CBo 1 PMON Box-Wide Control

MSR

Address

Size

(bits)

Description

CBo 2 PMON Registers
Generic Counters

C2_MSR_PMON_CTR3 0x0D59 64 CBo 2 PMON Counter 3
C2_MSR_PMON_CTR2 0x0D58 64 CBo 2 PMON Counter 2
C2_MSR_PMON_CTR1 0x0D57 64 CBo 2 PMON Counter 1
C2_MSR_PMON_CTR0 0x0D56 64 CBo 2 PMON Counter 0

Box-Level Filter

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Table 2-8. CBo Performance Moni toring MSRs (Sheet 2 of 4)

MSR Name

C2_MSR_PMON_BOX_FILTER 0x0D54 32 CBo 2 PMON Filter

Generic Counter Control

C2_MSR_PMON_CTL3 0x0D53 32 CBo 2 PMON Control for Counter 3
C2_MSR_PMON_CTL2 0x0D52 32 CBo 2 PMON Control for Counter 2
C2_MSR_PMON_CTL1 0x0D51 32 CBo 2 PMON Control for Counter 1
C2_MSR_PMON_CTL0 0x0D50 32 CBo 2 PMON Control for Counter 0

Box-Level Control/Status

C2_MSR_PMON_BOX_CTL 0x0D44 32 CBo 2 PMON Box-Wide Control

CBo 3 PMON Registers
Generic Counters

C3_MSR_PMON_CTR3 0x0D79 64 CBo 3 PMON Counter 3
C3_MSR_PMON_CTR2 0x0D78 64 CBo 3 PMON Counter 2
C3_MSR_PMON_CTR1 0x0D77 64 CBo 3 PMON Counter 1
C3_MSR_PMON_CTR0 0x0D76 64 CBo 3 PMON Counter 0

Box-Level Filter

C3_MSR_PMON_BOX_FILTER 0x0D74 32 CBo 3 PMON Filter

Generic Counter Control

C3_MSR_PMON_CTL3 0x0D73 32 CBo 3 PMON Control for Counter 3
C3_MSR_PMON_CTL2 0x0D72 32 CBo 3 PMON Control for Counter 2
C3_MSR_PMON_CTL1 0x0D71 32 CBo 3 PMON Control for Counter 1
C3_MSR_PMON_CTL0 0x0D70 32 CBo 3 PMON Control for Counter 0

Box-Level Control/Status

C3_MSR_PMON_BOX_CTL 0x0D64 32 CBo 3 PMON Box-Wide Control

MSR

Address

Size

(bits)

Description

CBo 4 PMON Registers
Generic Counters

C4_MSR_PMON_CTR3 0x0D99 64 CBo 4 PMON Counter 3
C4_MSR_PMON_CTR2 0x0D98 64 CBo 4 PMON Counter 2
C4_MSR_PMON_CTR1 0x0D97 64 CBo 4 PMON Counter 1
C4_MSR_PMON_CTR0 0x0D96 64 CBo 4 PMON Counter 0

Box-Level Filter

C4_MSR_PMON_BOX_FILTER 0x0D94 32 CBo 4 PMON Filter

Generic Counter Control

C4_MSR_PMON_CTL3 0x0D93 32 CBo 4 PMON Control for Counter 3
C4_MSR_PMON_CTL2 0x0D92 32 CBo 4 PMON Control for Counter 2
C4_MSR_PMON_CTL1 0x0D91 32 CBo 4 PMON Control for Counter 1
C4_MSR_PMON_CTL0 0x0D90 32 CBo 4 PMON Control for Counter 0

Box-Level Control/Status

C4_MSR_PMON_BOX_CTL 0x0D84 32 CBo 4 PMON Box-Wide Control

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Table 2-8. CBo Performance Monitoring MSRs (Sheet 3 of 4)

MSR Name

CBo 5 PMON Registers
Generic Counters

C5_MSR_PMON_CTR3 0x0DB9 64 CBo 5 PMON Counter 3
C5_MSR_PMON_CTR2 0x0DB8 64 CBo 5 PMON Counter 2
C5_MSR_PMON_CTR1 0x0DB7 64 CBo 5 PMON Counter 1
C5_MSR_PMON_CTR0 0x0DB6 64 CBo 5 PMON Counter 0

Box-Level Filter

C5_MSR_PMON_BOX_FILTER 0x0DB4 32 CBo 5 PMON Filter

Generic Counter Control

C5_MSR_PMON_CTL3 0x0DB3 32 CBo 5 PMON Control for Counter 3
C5_MSR_PMON_CTL2 0x0DB2 32 CBo 5 PMON Control for Counter 2
C5_MSR_PMON_CTL1 0x0DB1 32 CBo 5 PMON Control for Counter 1
C5_MSR_PMON_CTL0 0x0DB0 32 CBo 5 PMON Control for Counter 0

Box-Level Control/Status

C5_MSR_PMON_BOX_CTL 0x0DA4 32 CBo 5 PMON Box-Wide Control

CBo 6 PMON Registers
Generic Counters

C6_MSR_PMON_CTR3 0x0DD9 64 CBo 6 PMON Counter 3
C6_MSR_PMON_CTR2 0x0DD8 64 CBo 6 PMON Counter 2
C6_MSR_PMON_CTR1 0x0DD7 64 CBo 6 PMON Counter 1
C6_MSR_PMON_CTR0 0x0DD6 64 CBo 6 PMON Counter 0

Box-Level Filter

C6_MSR_PMON_BOX_FILTER 0x0DD4 32 CBo 6 PMON Filter

Generic Counter Control

C6_MSR_PMON_CTL3 0x0DD3 32 CBo 6 PMON Control for Counter 3
C6_MSR_PMON_CTL2 0x0DD2 32 CBo 6 PMON Control for Counter 2
C6_MSR_PMON_CTL1 0x0DD1 32 CBo 6 PMON Control for Counter 1
C6_MSR_PMON_CTL0 0x0DD0 32 CBo 6 PMON Control for Counter 0

Box-Level Control/Status

C6_MSR_PMON_BOX_CTL 0x0DC4 32 CBo 6 PMON Box-Wide Control

MSR

Address

Size

(bits)

Description

CBo 7 PMON Registers
Generic Counters

C7_MSR_PMON_CTR3 0x0DF9 64 CBo 7 PMON Counter 3
C7_MSR_PMON_CTR2 0x0DF8 64 CBo 7 PMON Counter 2
C7_MSR_PMON_CTR1 0x0DF7 64 CBo 7 PMON Counter 1
C7_MSR_PMON_CTR0 0x0DF6 64 CBo 7 PMON Counter 0

Box-Level Filter

C7_MSR_PMON_BOX_FILTER 0x0DF4 32 CBo 7 PMON Filter

Generic Counter Control

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Table 2-8. CBo Performance Moni toring MSRs (Sheet 4 of 4)

MSR Name

C7_MSR_PMON_CTL3 0x0DF3 32 CBo 7 PMON Control for Counter 3
C7_MSR_PMON_CTL2 0x0DF2 32 CBo 7 PMON Control for Counter 2
C7_MSR_PMON_CTL1 0x0DF1 32 CBo 7 PMON Control for Counter 1
C7_MSR_PMON_CTL0 0x0DF0 32 CBo 7 PMON Control for Counter 0

Box-Level Control/Status

C7_MSR_PMON_BOX_CTL 0x0DE4 32 CBo 7 PMON Box-Wide Control

MSR

Address

Size

(bits)

Description

2.3.3.1 CBo Box Level PMON State

The following registers represent the state governing all box-level PMUs in the CBo.
In the case of the CBo, the Cn_MSR_PMON_BOX_CTL register governs what happens when a freeze

signal is received (.frz_en). It also provides the ability to manually freeze the counters in the box
(.frz) and reset the generic state (.rst_ctrs and .rst_ctrl).

Table 2-9. Cn_MSR_PMON_BOX_CTL Register – Field Definitions

Field Bits Attr

rsv 31:18 RV 0 Reserved (?)
rsv 17 RV 0 Reserved; SW must write to 0 else behavior is undefined.
frz_en 16 WO 0 Freeze Enable.

HW

Reset

Val

Description

If set to 1 and a freeze signal is received, the counters will be

stopped or ‘frozen’, else the freeze signal will be ignored.
rsv 15:9 RV 0 Reserved (?)
frz 8 WO 0 Freeze.

If set to 1 and the .frz_en is 1, the counters in this box will be

frozen.
rsv 7:2 RV 0 Reserved (?)
rst_ctrs 1 WO 0 Reset Counters.

When set to 1, the Counter Registers will be reset to 0.
rst_ctrl 0 WO 0 Reset Control.

U

When set to 1, the Counter Control Registers will be reset to 0.

2.3.3.2 CBo PMON state - Counter/Control Pairs

The following table defines the layout of the CBo performance monitor control registers. The main
task of these configuration registers is to select the event to be monitored by their respective data
counter (.ev_sel, .umask). Additional control bits are provided to shape the incoming events (e.g.
.invert, .edge_det, .thresh) as well as provide additional functionality for monitoring software (.rst).

Table 2-10. Cn_MSR_PMON_CTL{3-0} Re gister – Field Definitions (Sheet 1 of 2)

Field Bits Attr

thresh 31:24 RW-V 0 Threshold used in counter comparison.

HW

Reset

Val

Description

Reference Number: 327043-001 27

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-10. Cn_MSR_PMON_CTL{3-0} Register – Field Definitions (Sheet 2 of 2)

Field Bits Attr

invert 23 RW-V 0 Invert comparison against Threshold.

en 22 RW-V 0 Local Counter Enable.
rsv 21:20 RV 0 Reserved; SW must write to 0 else behavior is undefined.
tid_en 19 RW-V 0 TID Filter Enable
edge_det 18 RW-V 0 When set to 1, rather than measuring the event in each cycle it

rst 17 WO 0 When set to 1, the corresponding counter will be cleared to 0.
rsv 16 RV 0 Reserved. SW must write to 0 else behavior is undefined.
umask 15:8 RW-V 0 Select subevents to be counted within the selected event.
ev_sel 7:0 RW-V 0 Select event to be counted.

HW

Reset

Val

Description

0 - comparison will be ‘is event increment >= threshold?’.
1 - comparison is inverted - ‘is event increment < threshol d?’

NOTE: .invert is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.

Also, if .edge_det is set to 1, the counter will increment when a 1
to 0 transition (i.e. falling edge) is detected.

is active, the corresponding counter will incr ement when a 0 to 1
transition (i.e. rising edge) is detected.

When 0, the counter will increment in each cycle that the event
is asserted.

NOTE: .edge_det is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.

The CBo performance monitor data registers are 44b wide. Should a counter overflow (a carry out
from bit 43), the counter will wrap and continue to collect events.If accessible, software can
continuously read the data registers without disabling event collection.

Table 2-11. Cn_MSR_PMON_CTR{3-0} Register – Field Definitions

Field Bits Attr

rsv 63:44 RV 0 Reserved (?)
event_count 43:0 RW-V 0 44-bit performance event counter

HW

Reset

Val

Description

2.3.3.3 CBo Filter Register (Cn_MSR_PMON_BOX_FILTER)

In addition to generic event counting, each CBo provides a MATCH register that allows a user to filter
various traffic as it applies to specific events (see Event Section for more information). LLC_LOOKUP
may be filtered by the cacheline state, QPI_CREDITS may be filtered by link while TOR_INSERTS and
TOR_OCCUPANCY may be filtered by the opcode of the queued request as well as the corresponding
NodeID.

Any of the CBo events may be filtered by Thread/Core-ID. To do so, the control register’s .tid_en bit
must be set to 1 and the tid field in the FILTER register filled out.

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Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Note: Not all transactions can be associated with a specific thread. For example, when a

snoop triggers a WB, it does not have an associated thread. Transactions that are
associated with PCIe will come from “0x1E” (b11110).

Note: Only one of these filtering criteria may be applied at a time.

Table 2-12. Cn_MSR_PMON_BOX_FILTER Register – Field Definitions

Field Bits Atrtr

opc
(7b IDI Opcode?

w/top 2b 0x3)

state 22:18 RW 0 Select state to monitor for LLC_LOOKUP event. Setting multiple

nid 17:10 0 0 Match on Target NodeID.

rsv 9:8 RV 0 Reserved (?)
rsv 7:5 RV 0 Reserved (?)
tid 4:0 0 0 [3:1] Core-ID

31:23 RW 0 Match on Opcode (see

HW

Reset

Val

Description

IDI Packet Type for

Table 2-13, “Opcode Match by

Cn_MSR_PMON_BOX_FILTER.opc”)

NOTE: Only tracks opcodes that come from the IRQ. It is not

possible to track snoops (from IPQ) or other transactions from

the ISMQ.

bits in this field will allow a user to track multiple states.

b1xxxx - ‘F’ state.

bx1xxx - ‘M’ state

bxx1xx - ‘E’ state.

bxxx1x - ‘S’ state.

bxxxx1 - ‘I’ state.

NID is a mask filter with each bit representing a different Node in

the system. 0x01 would filter on NID 0, 0x2 would filter on NID

1, etc

[0] Thread 1/0

When .tid_en is 0; the specified counter will count ALL events

Thread-ID 0xF is reserved for non- associated requests such as: -

LLC victims - PMSeq - External Snoops

Refer to Table 2-144, “Opcodes (Alphabetical Listing)” for definitions of the opcodes found in the
following table.

Table 2-13. Opcode Match by IDI Packet Type for Cn_MSR_PMON_BOX_FILTER.opc (Sheet

1 of 2)

opc

Value

0x180 RFO Demand Data RFO
0x181 CRd Demand Code Read
0x182 DRd Demand Data Read
0x187 PRd Partial Reads (UC)
0x18C WCiLF Streaming Store - Full
0x18D WCiL Streaming Store - Partial
0x190 PrefRFO Prefetch RFO into LLC but don’t pass to L2. Includes Hints
0x191 PrefCode Prefetch Code into LLC but don’t pass to L2. Includes Hints
0x192 PrefData Prefetch Data into LLC but don’t pass to L2. Includes Hints

Reference Number: 327043-001 29

Opcode Defn

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-13. Opcode Match by IDI Packet Type for Cn_MSR_PMON_BOX_FILTER.opc (Sheet

2 of 2)

opc

Value

0x194 PCIWiLF PCIe Write (non-allocating)
0x195 PCIPRd PCIe UC Read
0x19C PCIItoM PCIe Write (allocating)
0x19E PCIRdCur PCIe read current
0x1C4 WbMtoI Request writeback Modified invalidate line
0x1C5 WbMtoE Request writeback Modified set to Exclusive
0x1C8 ItoM Request Invalidate Line
0x1E4 PCINSRd PCIe Non-Snoop Read
0x1E5 PCINSWr PCIe Non-Snoop Write (partial)
0x1E6 PCINSWrF PCIe Non-Snoop Read (full)

Opcode Defn

2.3.4 CBo Performance Monitoring Events

2.3.4.1 An Overview:

The performance monitoring events within the CBo include all events internal to the LLC as well as
events which track ring related activity at the CBo/Core ring stops.

CBo performance monitoring events can be used to track LLC access rates, LLC hit/miss rates, LLC
eviction and fill rates, and to detect evidence of back pressure on the LLC pipelines. In addition, the
CBo has performance monitoring events for tracking MESI state transitions that occur as a result of
data sharing across sockets in a multi-socket system. And finally, there are events in the CBo for
tracking ring traffic at the CBo/Core sink inject points.

Every event in the CBo is from the point of view of the LLC and is not associated with any specific core
since all cores in the socket send their LLC transactions to all CBos in the socket. However, the PMON
logic in the CBo provides a thread-id field in the Cn_MSR_PMON_BOX_FILTER register which can be
applied to the CBo events to obtain the interactions between specific cores and threads.

There are separate sets of counters for each CBo instance. For any event, to get an aggregate count
of that event for the entire LLC, the counts across the CBo instances must be added together. The
counts can be averaged across the CBo instances to get a view of the typical count of an event from
the perspective of the individual CBos. Indiv idual per-CBo deviations from the a ver age can be used to
identify hot-spotting across the CBos or other evidences of non-uniformity in LLC behavior across the
CBos. Such hot-spotting should be rare, though a repetitive polling on a fixed physical address is one
obvious example of a case where an analysis of the deviations across the CBos would indicate hot­spotting.

2.3.4.2 Acronyms frequently used in CBo Events:

The Rings:
AD (Address) Ring - Core Read/Write Requests and Intel QPI Snoops. Carries Intel QPI requests and

snoop responses from C to Intel® QPI.
BL (Block or Data) Ring - Data == 2 transfers for 1 cache line

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AK (Acknowledge) Ring - Acknowledges Intel® QPI to CBo and CBo to Core. Carries snoop responses

from Core to CBo.
IV (Invalidate) Ring - CBo Snoop requests of core caches

Internal CBo Queues:

IRQ - Ingress Request Queue on AD Ring. Associated with requests from core.
IPQ - Ingress Probe Queue on AD Ring. Associated with snoops from Intel® QPI LL.
ISMQ - Ingress Subsequent Messages (response queue). Associated with messages responses to

ingress requests (e.g. data responses, Intel QPI complete messages, core snoop response messages
and GO reset queue).

TOR - Table Of Requests. Tracks pending CBo transactions.
RxR (aka IGR) - “Receive from Ring” referring to Ingress (requests from the Cores) queues.
TxR (aka EGR) - “Transmit to Ring” referring to Egress (requests headed for the Ring) queues.

2.3.4.3 The Queues:

There are several internal occupancy queue counters, each of which is 5bits wide and dedicated to its
queue: IRQ, IPQ, ISMQ, QPI_IGR, IGR, EGR and the TOR.

2.3.5 CBo Events Ordered By Code

The following table summarizes the directly measured CBO Box events.

Table 2-14. Performance Monitor Events for CBO (Sheet 1 of 2)

Symbol Name

CLOCKTICKS 0x00 0-3 1 Uncore Clocks
TxR_INSERTS 0x02 0-1 1 Egress Allocations
TxR_ADS_USED 0x04 0-1 1
RING_BOUNCES 0x05 0-1 1 Number of LLC responses that bounced on

RING_SRC_THRTL 0x07 0-1 1
RxR_OCCUPANCY 0x11 0 20 Ingress Occupancy
RxR_EXT_STARVED 0x12 0-1 1 Ingress Arbiter Blocking Cycles
RxR_INSERTS 0x13 0-1 1 Ingress Allocations
RING_AD_USED 0x1B 2-3 1 AD Ring In Use
RING_AK_USED 0x1C 2-3 1 AK Ring In Use
RING_BL_USED 0x1D 2-3 1 BL Ring in Use
RING_IV_USED 0x1E 2-3 1 BL Ring in Use
COUNTER0_OCCUPANCY 0x1F 1-3 20 Counter 0 Occupancy
ISMQ_DRD_MISS_OCC 0x21 0-1 20
RxR_IPQ_RETRY 0x31 0-1 1 Probe Queue Retries
RxR_IRQ_RETRY 0x32 0-1 1 Ingress Request Queue Rejects

Event

Code

Ctrs

Max

Inc/

Cyc

Description

the Ring.

Reference Number: 327043-001 31

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-14. Performance Monitor Events for CBO (Sheet 2 of 2)

Symbol Name

RxR_ISMQ_RETRY 0x33 0-1 1 ISMQ Retries
LLC_LOOKUP 0x34 0-1 1 Cache Lookups
TOR_INSERTS 0x35 0-1 1 TOR Inserts
TOR_OCCUPANCY 0x36 0 20 TOR Occupancy
LLC_VICTIMS 0x37 0-1 1 Lines Victimized
MISC 0x39 0-1 1 Cbo Misc

Event

Code

Ctrs

Max

Inc/

Cyc

Description

2.3.6 CBO Box Common Metrics (Derived Events)

The following table summarizes metrics commonly calculated from CBO Box events.

Table 2-15. Metrics Derived from CBO Events (Sheet 1 of 3)

Symbol Name:

Definition

AVG_INGRESS_DEPTH:
Average Depth of the Ingress Queue
through the sample interval

AVG_INGRESS_LATENCY:
Average Latency of Requests through the
Ingress Queue in Uncore Clocks

AVG_INGRESS_LATENCY_WHEN_NE:
Average Latency of Requests through the
Ingress Queue in Uncore Clocks when Ingress
Queue has at least one entry

AVG_TOR_DRDS_MISS_WHEN_NE:
Average Number of Data Read Entries that
Miss the LLC when the TOR is not empty.

AVG_TOR_DRDS_WHEN_NE:
Average Number o f Data Re ad Entries when
the TOR is not empty.

AVG_TOR_DRD_HIT_LATENCY:
Average Latency of Data Reads through the
TOR that hit the LLC

AVG_TOR_DRD_LATENCY:
Average Latency of Data Read Entries
making their way through the TOR

AVG_TOR_DRD_LOC_MISS_LATENCY:
Average Latency of Data Reads through the
TOR that miss the LLC and were satsified by
Locally HOMed Memory. Only valid at
processor level == don't add counts across
Cbos. NOTE: Count imperfect. Will be
polluted by remote hits where memory's
home node is local memory.

AVG_TOR_DRD_MISS_LATENCY:
Average Latency of Data Reads through the
TOR that miss the LLC

RxR_OCCUPANCY.IRQ / SAMPLE_INTERVAL

RxR_OCCUPANCY.IRQ / RxR_INSERTS.IRQ

RxR_OCCUPANCY.IRQ /
COUNTER0.OCCUPANCY{edge_det,thresh=0x1}

(TOR_OCCUPANCY.MISS_OPCODE /
COUNTER0_OCCUPANCY{edge_det,thresh=0x1}))
with:Cn_MSR_PMON_BOX_FILTER.opc=0x182

(TOR_OCCUPANCY.OPCODE /
COUNTER0_OCCUPANCY{edge_det,thresh=0x1})
with:Cn_MSR_PMON_BOX_FILTER.opc=0x182

((TOR_OCCUPANCY.OPCODE ­TOR_OCCUPANCY.MISS_OPCODE) / (TOR_INSERTS.OPCODE ­TOR_INSERTS.MISS_OPCODE))
with:Cn_MSR_PMON_BOX_FILTER.opc=0x182

(TOR_OCCUPANCY.OPCODE / TOR_INSERTS.OPCODE)
with:Cn_MSR_PMON_BOX_FILTER.opc=0x182

(TOR_OCCUPANCY.MISS_OPCODE /
TOR_INSERTS.MISS_OPCODE)
with:Cn_MSR_PMON_BOX_FILTER.{opc,nid}={0x182,my_node
}

(TOR_OCCUPANCY.MISS_OPCODE /
TOR_INSERTS.MISS_OPCODE)
with:Cn_MSR_PMON_BOX_FILTER.opc=0x182

Equation

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Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-15. Metrics Derived from CBO Events (Sheet 2 of 3)

Symbol Name:

Definition

AVG_TOR_DRD_REM_MISS_LATENCY:
Average Latency of Data Reads through the
TOR that miss the LLC and were satsified by a
Remote cache or Remote Memory . Only valid
at processor level == don't add counts across
Cbos.

CYC_INGRESS_BLOCKED:
Cycles the Ingress Request Queue arbiter
was Blocked

CYC_INGRESS_STARVED:
Cycles the Ingress Request Queue was in
Internal Starvation

CYC_USED_DNEVEN:
Cycles Used in the Down direction, Even
polarity

CYC_USED_DNODD:
Cycles Used in the Down direction, Odd
polarity

CYC_USED_UPEVEN:
Cycles Used in the Up direction, Even
polarity

CYC_USED_UPODD:
Cycles Used in the Up direction, Odd
polarity

INGRESS_REJ_V_INS:
Ratio of Ingress Request Entries that were
rejected vs. inserted

LLC_DRD_MISS_PCT:
LLC Data Read miss ratio

LLC_DRD_RFO_MISS_TO_LOC_MEM:
LLC Data Read and RFO misses satisfied by
locally HOMed memory. Only valid at
processor level == don't add counts across
Cbos. NOTE: Count imperfect. Will be
polluted by remote hits where memory's
home node is local memory.

LLC_DRD_RFO_MISS_TO_REM_MEM:
LLC Data Read and RFO misses satisfied by
a remote cache or remote memory. Only
valid at processor level == don't add counts
across Cbos.

LLC_MPI:
LLC Misses Per Instruction (code, read, RFO
and prefetches)

LLC_PCIE_DATA_BYTES:
LLC Miss Data from PCIe in Number of
Bytes

LLC_RFO_MISS_PCT:
LLC RFO Miss Ratio

MEM_WB_BYTES:
Data written back to memory in Number of
Bytes

Equation

(TOR_OCCUPANCY.MISS_OPCODE /

TOR_INSERTS.MISS_OPCODE)

with:Cn_MSR_PMON_BOX_FILTER.{opc,nid}={0x182,other_no

des}

RxR_EXT_STARVED.IRQ / SAMPLE_INTERVAL

RxR_INT_STARVED.IRQ / SAMPLE_INTERVAL

RING_BL_USED.DN_EVEN / SAMPLE_INTERVAL

RING_BL_USED.DN_ODD / SAMPLE_INTERVAL

RING_BL_USED.UP_EVEN / SAMPLE_INTERVAL

RING_BL_USED.UP_ODD / SAMPLE_INTERVAL

RxR_INSERTS.IRQ_REJECTED / RxR_INSERTS.IRQ

LLC_LOOKUP.DATA_READ

(Cn_MSR_PMON_BOX_FILTER.state=0x1) /

LLC_LOOKUP.DATA_READ

(Cn_MSR_PMON_BOX_FILTER.state=0x1F)

(TOR_INSERTS.NID_MISS_OPCODE

with:Cn_MSR_PMON_BOX_FILTER.{opc,nid}={0x182,my_node

} + TOR_INSERTS.NID_MISS_OPCODE

with:Cn_MSR_PMON_BOX_FILTER.{opc,nid}={0x180,my_node

} ) / (TOR_INSERTS.NID_MISS_OPCODE

with:Cn_MSR_PMON_BOX_FILTER.{opc,nid}={0x182,0xF} +

TOR_INSERTS.NID_MISS_OPCODE

with:Cn_MSR_PMON_BOX_FILTER.{opc,nid}={0x180,0xF} )

(TOR_INSERTS.NID_MISS_OPCODE

with:Cn_MSR_PMON_BOX_FILTER.{opc,nid}={0x182,other_no

des} + TOR_INSERTS.NID_MISS_OPCODE

with:Cn_MSR_PMON_BOX_FILTER.{opc,nid}={0x180,other_no

des} ) / (TOR_INSERTS.NID_MISS_OPCODE

with:Cn_MSR_PMON_BOX_FILTER.{opc,nid}={0x182,0xF} +

TOR_INSERTS.NID_MISS_OPCODE

with:Cn_MSR_PMON_BOX_FILTER.{opc,nid}={0x180,0xF} )

LLC_LOOKUP.ANY (Cn_MSR_PMON _BOX_FILTER.state=0x1) /

INST_RETIRED.ALL (on Core)

TOR_INSERTS.OPCODE

with:Cn_MSR_PMON_BOX_FILTER.opc=0x19C * 64

(TOR_INSERTS.MISS_OPCODE / TOR_INSERTS.OPCODE)

with:Cn_MSR_PMON_BOX_FILTER.opc=0x180

LLC_VICTIMS.M_STATE * 64

Reference Number: 327043-001 33

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-15. Metrics Derived from CBO Events (Sheet 3 of 3)

Symbol Name:

Definition

PCIE_DATA_BYTES:
Data from PCIe in Number of Bytes

RING_THRU_DNEVEN_BYTES:
Ring throughput in the Down direction,
Even polarity in Bytes

RING_THRU_DNODD_BYTES:
Ring throughput in the Down direction, Odd
polarity in Bytes

RING_THRU_UPEVEN_BYTES:
Ring throughput in the Up direction, Even
polarity in Bytes

RING_THRU_UPODD_BYTES:
Ring throughput in the Up direction, Odd
polarity in Bytes

(TOR_INSERTS.OPCODE
with:Cn_MSR_PMON_BOX_FILTER.opc=0x194 +
TOR_INSERTS.OPCODE
with:Cn_MSR_PMON_BOX_FILTER.opc=0x19C) * 64

RING_BL_USED.DN_EVEN * 32

RING_BL_USED.DN_ODD * 32

RING_BL_USED.UP_EVEN * 32

RING_BL_USED.UP_ODD * 32

Equation

Note: LLC_MPI only makes sense when measured either in the processor or at the system

level. There is no correlation between a specific CBo andthe instructions retired in a
specific core. Therefore it is necessary to add the LLC_LOOKUP term across all CBos
and divide by either all instructions retired in a core or all instructions retired across all
cores.

2.3.7 CBo Performance Monitor Event List

The section enumerates the performance monitoring events for the CBO Box.

CLOCKTICKS

• Title: Uncore Clocks

• Category: UCLK Events

• Event Code: 0x00

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition:

COUNTER0_OCCUPANCY

• Title: Counter 0 Occupancy

• Category: OCCUPANCY Events

• Event Code: 0x1F

• Max. Inc/Cyc: 20, Register Restrictions: 1-3

• Definition: Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a

user to capture occupancy related information by filtering the Cb0 occupancy count captured in
Counter 0. The filtering available is found in the control register - threshold, invert and edge
detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue
has an entry.

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Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

ISMQ_DRD_MISS_OCC

• Title:

• Category: ISMQ Events

• Event Code: 0x21

• Max. Inc/Cyc: 20, Register Restrictions: 0-1

• Definition:

LLC_LOOKUP

• Title: Cache Lookups

• Category: CACHE Events

• Event Code: 0x34

• Max. Inc/Cyc: 1, Register Restrictions: 0-1

• Definition: Counts the number of times the LLC was accessed - this includes code, data,

prefetches and hints coming from L2. This has numerous filters available. Note the non-standard
filtering equation. This event will count requests that lookup the cache multiple times with multiple
increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Other­wise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.

• NOTE: Bit 0 of the umask must always be set for this event. This allows us to match a given state
(or states). The state is programmed in Cn_MSR_PMON_BOX_FIL TER.state. The state field is a bit
mask, so you can select (and monitor) multiple states at a time. 0 = I (miss), 1 = S, 2 = E, 3 = M,
4 = F. For example, if you wanted to monitor F and S hits, you could set 10010b in the 5-bit state
field. To monitor any lookup, set the field to 0x1F.

Table 2-16. Unit Masks for LLC_LOOKUP

Extension

DATA_READ b00000011 CBoFilter[2

WRITE b00000101 CBoFilter[2

REMOTE_SNOOP b00001001 CBoFilter[2

NID b01000001 CBoFilter[2

umask
[15:8]

Filter Dep Description

2:18]

2:18]

2:18]

2:18],
CBoFilter[1
7:10]

Data Read Request:
Read transactions

Write Requests:
This includes all write transactions -- both Cachable
and UC.

External Snoop Request:
Filters for only snoop requests coming from the remote
socket(s) through the IPQ.

RTID:
Match a given RTID destination NID. The NID is
programmed in Cn_MSR_PMON_BOX_FILTER.nid. In
conjunction with STATE = I, it is possible to monitor
misses to specific NIDs in the system.

LLC_VICTIMS

• Title: Lines Victimized

• Category: CACHE Events

• Event Code: 0x37

• Max. Inc/Cyc: 1, Register Restrictions: 0-1

• Definition: Counts the number of lines that were victimized on a fill. This can be filtered by the

state that the line was in.

Table 2-17. Unit Masks for LLC_VICTIMS (Sheet 1 of 2)

Extension

M_STATE bxxxxxxx1 Lines in M state
E_STATE bxxxxxx1x Lines in E state

Reference Number: 327043-001 35

umask
[15:8]

Filter Dep Description

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-17. Unit Masks for LLC_VICTIMS (Sheet 2 of 2)

Extension

S_STATE bxxxxx1xx Lines in S State
MISS bxxxx1xxx
NID bx1xxxxxx CBoFilter[1

umask
[15:8]

7:10]

MISC

• Title: Cbo Misc

• Category: MISC Events

• Event Code: 0x39

• Max. Inc/Cyc: 1, Register Restrictions: 0-1

• Definition: Miscellaneous events in the Cbo.

Table 2-18. Unit Masks for MISC

Extension

RSPI_WAS_FSE bxxxxxxx1 Silent Snoop Eviction:

WC_ALIASING bxxxxxx1x Write Combining Aliasing:

STARTED bxxxxx1xx
RFO_HIT_S bxxxx1xxx RFO HitS:

umask
[15:8]

Counts the number of times when a Snoop hit in FSE states and
triggered a silent eviction. This is useful because this information is
lost in the PRE encodings.

Counts the number of times that a USWC write (WCIL(F)) transaction
hit in the LLC in M state, triggering a WBMtoI followed by the USWC
write. This occurs when there is WC aliasing.

Number of times that an RFO hit in S state. This is useful for
determining if it might be good for a workload to use RspIWB instead
of RspSWB.

Filter Dep Description

Victimized Lines that Match NID:
The NID is programmed in
Cn_MSR_PMON_BOX_FILTER. nid. In conjunction with
STATE = I, it is possible to monitor misses to specific
NIDs in the system.

Description

RING_AD_USED

• Title: AD Ring In Use

• Category: RING Events

• Event Code: 0x1B

• Max. Inc/Cyc: 1, Register Restrictions: 2-3

• Definition: Counts the number of cycles that the AD ring is being used at this ring stop. This

includes when packets are passing by and when packets are being sunk, but does not include when
packets are being sent from the ring stop. We really hav e two rings in JKT -- a clockwise ring and a
counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and
"DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half
of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In
other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because
they are on opposite sides of the ring.

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Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-19. Unit Masks for RING_AD_USED

Extension

UP_EVEN bxxxxxxx1 Up and Even:

UP_ODD bxxxxxx1x Up and Odd:

DOWN_EVEN bxxxxx1xx Down and Even:

DOWN_ODD bxxxx1xxx Down and Odd:

umask
[15:8]

Description

Filters for the Up and Even ring polarity.

Filters for the Up and Odd ring polarity.

Filters for the Down and Even ring polarity.

Filters for the Down and Odd ring polarity.

RING_AK_USED

• Title: AK Ring In Use

• Category: RING Events

• Event Code: 0x1C

• Max. Inc/Cyc: 1, Register Restrictions: 2-3

• Definition: Counts the number of cycles that the AK ring is being used at this ring stop. This

includes when packets are passing by and when packets are being sunk, but does not include when
packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a
counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and
"DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half
of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In
other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because
they are on opposite sides of the ring.

Table 2-20. Unit Masks for RING_AK_USED

Extension

UP_EVEN bxxxxxxx1 Up and Even:

UP_ODD bxxxxxx1x Up and Odd:

DOWN_EVEN bxxxxx1xx Down and Even:

DOWN_ODD bxxxx1xxx Down and Odd:

umask
[15:8]

Description

Filters for the Up and Even ring polarity.

Filters for the Up and Odd ring polarity.

Filters for the Down and Even ring polarity.

Filters for the Down and Odd ring polarity.

RING_BL_USED

• Title: BL Ring in Use

• Category: RING Events

• Event Code: 0x1D

• Max. Inc/Cyc: 1, Register Restrictions: 2-3

• Definition: Counts the number of cycles that the BL ring is being used at this ring stop. This

includes when packets are passing by and when packets are being sunk, but does not include when
packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a
counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and
"DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half
of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In
other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because
they are on opposite sides of the ring.

Reference Number: 327043-001 37

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-21. Unit Masks for RING_BL_USED

Extension

UP_EVEN bxxxxxxx1 Up and Even:

UP_ODD bxxxxxx1x Up and Odd:

DOWN_EVEN bxxxxx1xx Down and Even:

DOWN_ODD bxxxx1xxx Down and Odd:

umask
[15:8]

Filters for the Up and Even ring polarity.

Filters for the Up and Odd ring polarity.

Filters for the Down and Even ring polarity.

Filters for the Down and Odd ring polarity.

RING_BOUNCES

• Title: Number of LLC responses that bounced on the Ring.

• Category: RING Events

• Event Code: 0x05

• Max. Inc/Cyc: 1, Register Restrictions: 0-1

• Definition:

Table 2-22. Unit Masks for RING_BOUNCES

Extension

AK_CORE bxxxxxx1x Acknowledgements to core
BL_CORE bxxxxx1xx Data Responses to core
IV_CORE bxxxx1xxx Snoops of processor's cache.

umask
[15:8]

Description

Description

RING_IV_USED

• Title: BL Ring in Use

• Category: RING Events

• Event Code: 0x1E

• Max. Inc/Cyc: 1, Register Restrictions: 2-3

• Definition: Counts the number of cycles that the IV ring is being used at this ring stop. This

includes when packets are passing by and when packets are being sunk, but does not include when
packets are being sent from the ring stop. There is only 1 IV ring in JKT. Therefore, if one wants to
monitor the "Even" ring, they should select both UP_EVEN and DN_EVEN. To monitor the "Odd"
ring, they should select both UP_ODD and DN_ODD.

Table 2-23. Unit Masks for RING_IV_USED

Extension

ANY b00001111 Any:

umask
[15:8]

Description

Filters any polarity

RING_SRC_THRTL

• Title:

• Category: RING Events

• Event Code: 0x07

• Max. Inc/Cyc: 1, Register Restrictions: 0-1

• Definition:

38 Reference Number: 327043-001

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

RxR_EXT_STARVED

• Title: Ingress Arbiter Blocking Cycles

• Category: INGRESS Events

• Event Code: 0x12

• Max. Inc/Cyc: 1, Register Restrictions: 0-1

• Definition: Counts cycles in external starvation. This occurs when one of the ingress queues is

being starved by the other queues.

Table 2-24. Unit Masks for RxR_EXT_STARVED

Extension

IRQ bxxxxxxx1 IPQ:

IPQ bxxxxxx1x IRQ:

ISMQ bxxxxx1xx ISMQ:

ISMQ_BIDS bxxxx1xxx ISMQ_BID:

umask
[15:8]

Description

IRQ is externally starved and therefore we are blocking the IPQ.

IPQ is externally startved and therefore we are blocking the IRQ.

ISMQ is externally starved and therefore we are blocking both IRQ
and IPQ.

Number of times that the ISMQ Bid.

RxR_INSERTS

• Title: Ingress Allocations

• Category: INGRESS Events

• Event Code: 0x13

• Max. Inc/Cyc: 1, Register Restrictions: 0-1

• Definition: Counts number of allocations per cycle into the specified Ingress queue.

• NOTE: IRQ_REJECTED should not be Ored with the other umasks.

Table 2-25. Unit Masks for RxR_INSERTS

Extension

IRQ bxxxxxxx1 IRQ
IRQ_REJECTED bxxxxxx1x IRQ Rejected
IPQ bxxxxx1xx IPQ
VFIFO bxxx1xxxx VFIFO:

umask
[15:8]

Description

Counts the number of allocations into the IRQ Ord ering FIFO . In JKT,
it is necessary to keep IO requests in order. Therefore, they are
allocated into an ordering FIFO that sits next to the IRQ, and must be
satisfied from the FIFO in order (with respect to each other). This
event, in conjunction with the Occupancy Accumulator event, can be
used to calculate average lifetime in the FIFO. Transactions are
allocated into the FIFO as soon as they enter the Cachebo (and the
IRQ) and are deallocated from the FIFO as soon as they are
deallocated from the IRQ.

RxR_IPQ_RETRY

• Title: Probe Queue Retries

• Category: INGRESS_RETRY Events

• Event Code: 0x31

• Max. Inc/Cyc: 1, Register Restrictions: 0-1

• Definition: Number of times a snoop (probe) request had to retry. Filters exist to cover some of

the common cases retries.

Reference Number: 327043-001 39

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-26. Unit Masks for RxR_IPQ_RETRY

Extension

ANY bxxxxxxx1 Any Reject:

FULL bxxxxxx1x No Egress Credits:

ADDR_CONFLICT bxxxxx1xx Address Conflict:

QPI_CREDITS bxxx1xxxx No Intel® QPI Credits

umask
[15:8]

Counts the number of times that a request form the IPQ was retried
because of a TOR reject. TOR r ejects from the IPQ can b e caused b y
the Egress being full or Address Conflicts.

Counts the number of times that a request form the IPQ was retried
because of a TOR reject from the Egress being full. IPQ requests
make use of the AD Egress for regular respo nses, the BL egress to
forward data, and the AK egress to return credits.

Counts the number of times that a request form the IPQ was retried
because of a TOR reject from an address conflicts. Address conflicts
out of the IPQ should be rare. They will generally only occur if two
different sockets are sending requests to the same address at the
same time. This is a true "conflict" case, unlike the IPQ Address
Conflict which is commonly caused by prefetching characteristics.

RxR_IRQ_RETRY

• Title: Ingress Request Queue Rejects

• Category: INGRESS_RETRY Events

• Event Code: 0x32

• Max. Inc/Cyc: 1, Register Restrictions: 0-1

• Definition:

Table 2-27. Unit Masks for RxR_IRQ_RETRY (Sheet 1 of 2)

Description

Extension

ANY bxxxxxxx1 Any Reject:

FULL bxxxxxx1x No Egress Credits:

ADDR_CONFLICT bxxxxx1xx Address Conflict:

umask
[15:8]

Counts the number of IRQ retries that occur. Requests from the IRQ
are retried if they are rejected from the TOR pipeline for a variety of
reasons. Some of the most common reasons include if the Egress is
full, there are no RTIDs, or there is a Physical Address match to
another outstanding request.

Counts the number of times that a request from the IRQ was retried
because it failed to acquire an entry in the Egress. The egress is the
buffer that queues up for allocating onto the ring. IRQ requests can
make use of all four rings and all four Egresses. If any of the queues
that a given request needs to make use of are full, the request will be
retried.

Counts the number of times that a request from the IRQ was retried
because of an address match in the TOR. In order to maintain
coherency, requests to the same address are not allowed to pass
each other up in the Cbo. Therefore, if there is an outstanding
request to a given address, on e cann ot issue another request to that
address until it is complete. This comes up most commonly with
prefetches. Outstanding prefetches occasionally will not complete
their memory fetch and a demand request to the same address will
then sit in the IRQ and get retried until the prefetch fills the data into
the LLC. Therefore, it will not be uncommon to see this case in high
bandwidth streaming workloads when the LLC Prefetcher in the core
is enabled.

Description

40 Reference Number: 327043-001

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-27. Unit Masks for RxR_IRQ_RETRY (Sheet 2 of 2)

Extension

RTID bxxxx1xxx No RTIDs:

QPI_CREDITS bxxx1xxxx No Intel® QP I Credits:

umask
[15:8]

Counts the number of times that requests from the IRQ were retried
because there were no RTIDs available. RTIDs are required after a
request misses the LLC and needs to send sno ops and/or reque sts to
memory. If there are no RTIDs available, requests will queue up in
the IRQ and retry until one becomes available. Note that there are
multiple RTID pools for the different sockets. There may be cases
where the local RTIDs are all used, but requests destined for remote
memory can still acquire an RTID because there are remote RTIDs
available. This event does not provide any filtering for this case.

Number of requests rejects because of lack of Intel® QPI Ingress
credits. These credits are required in order to send transactions to
the Intel® QPI agent. Please see the QPI_IGR_CREDITS events for
more information.

Description

RxR_ISMQ_RETRY

• Title: ISMQ Retries

• Category: INGRESS_RETRY Events

• Event Code: 0x33

• Max. Inc/Cyc: 1, Register Restrictions: 0-1

• Definition: Number of times a transaction flowing through the ISMQ had to retry . Transaction pass

through the ISMQ as responses for requests that already exist in the Cbo. Some examples include:
when data is returned or when snoop responses come back from the cores.

Table 2-28. Unit Masks for RxR_ISMQ_RETRY

Extension

ANY bxxxxxxx1 Any Reject:

FULL bxxxxxx1x No Egress Credits:

RTID bxxxx1xxx No RTIDs:

QPI_CREDITS bxxx1xxxx No Intel® QP I Credits
IIO_CREDITS bxx1xxxxx No IIO Credits:

umask
[15:8]

Counts the total number of times that a request from the ISMQ
retried because of a TOR reject. ISMQ requests generally will not
need to retry (or at least ISMQ retries are less common than IRQ
retries). ISMQ requests will retry if they are not able to acquire a
needed Egress credit to get onto the ring, or for cache evictions that
need to acquire an RTID. Most ISMQ requests already hav e an RT ID,
so eviction retries will be less common here.

Counts the number of times that a request from the ISMQ retried
because of a TOR reject caused by a lack of Egress credits. The
egress is the buffer that queues up for allocating onto the ring. If
any of the Egress queues that a given request needs to make use of
are full, the request will be retried.

Counts the number of times that a request from the ISMQ retried
because of a TOR reject caused by no R TIDs. M-state cache evictions
are serviced through the ISMQ, and must acquire an RTID in order to
write back to memory . If no RTIDs are available, they will be retried.

Number of times a request attempted to acquire the NCS/NCB credit
for sending messages on BL to the IIO. There is a single credit in
each CBo that is shared between the NCS and NCB message classes
for sending transactions on the BL ring (such as read data) to the
IIO.

Description

Reference Number: 327043-001 41

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

RxR_OCCUPANCY

• Title: Ingress Occupancy

• Category: INGRESS Events

• Event Code: 0x11

• Max. Inc/Cyc: 20, Register Restrictions: 0

• Definition: Counts number of entries in the specified Ingress queue in each cycle.

• NOTE: IRQ_REJECTED should not be Ored with the other umasks.

Table 2-29. Unit Masks for RxR_OCCUPANCY

Extension

IRQ bxxxxxxx1 IRQ
IRQ_REJECTED bxxxxxx1x IRQ Rejected
IPQ bxxxxx1xx IPQ
VFIFO bxxx1xxxx VFIFO:

umask
[15:8]

Description

Accumulates the number of used entries in the IRQ Ordering FIFO in
each cycle. In JKT, it is necessary to keep IO requests in order.
Therefore, they are allocated into an ordering FIFO that sits next to
the IRQ, and must be satisfied from the FIFO in order (with respect
to each other). This event, in c onjunction with the Allocations ev ent,
can be used to calculate average lifetime in the FIFO. This event can
be used in conjunction with the Not Empty event to c alculate aver age
queue occupancy. T r ansactions are allocated in to the FIFO as so on as
they enter the Cachebo (and the IRQ) and are deallocated from the
FIFO as soon as they are deallocated from the IRQ.

TOR_INSERTS

• Title: TOR Inserts

• Category: TOR Events

• Event Code: 0x35

• Max. Inc/Cyc: 1, Register Restrictions: 0-1

• Definition: Counts the number of entries successfuly inserted into the TOR that match qualifica-

tions specified by the subevent. There are a number of subevent 'filters' but only a subset of the
subevent combinations are valid. Subevents that require an opcode or NID match require the
Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD
Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to
DRD (0x182).

Table 2-30. Unit Masks for TOR_INSERTS (Sheet 1 of 2)

Extension

OPCODE b00000001 CBoFilter[3

EVICTION b00000100 Evictions:

WB b00010000 Writebacks:

42 Reference Number: 327043-001

umask
[15:8]

Filter Dep Description

1:23]

Opcode Match:
Transactions inserted into the TOR that match an
opcode (matched by
Cn_MSR_PMON_BOX_FILTER.opc)

Eviction transactions inserted into the TOR. Evictions
can be quick, such as when the line is in the F, S, or E
states and no core valid bits are set. They can also b e
longer if either CV bits are set (so the cores need to be
snooped) and/or if there is a HitM (in which case it is
necessary to write the request out to memory).

Write transactions inserted into the TOR. This does
not include "RFO", but actual operations that contain
data being sent from the core.

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-30. Unit Masks for TOR_INSERTS (Sheet 2 of 2)

Extension

MISS_OPCODE b00000011 CBoFilter[3

MISS_ALL b00001010 Miss All:

NID_OPCODE b01000001 CBoFilter[3

NID_EVICTION b01000100 CBoFilter[1

NID_ALL b01001000 CBoFilter[1

NID_WB b01010000 CBoFilter[1

NID_MISS_OPCODE b01000011 CBoFilter[3

NID_MISS_ALL b01001010 CBoFilter[1

umask
[15:8]

Filter Dep Description

1:23]

1:23],
CBoFilter[1
7:10]

7:10]

7:10]

7:10]

1:23],
CBoFilter[1
7:10]

7:10]

Miss Opcode Match:
Miss transactions inserted into the TOR that match an
opcode.

All Miss requests inserted into the TOR. 'Miss' means
the allocation requires an RTID. This generally means
that the request was sent to memory or MMIO.

NID and Opcode Matched:
Transactions inserted into the TOR that match a NID
and an opcode.

NID Matched Evictions:
NID matched eviction transactions inserted into the
TOR.

NID Matched:
All NID matched (matches an RTID destination)
transactions inserted into the TOR. The NID is
programmed in Cn_MSR_PMON_BOX_FILTER.nid. In
conjunction with STATE = I, it is possible to monitor
misses to specific NIDs in the system.

NID Matched Writebacks:
NID matched write transactions inserted into the TOR.

NID and Opcode Matched Miss:
Miss transactions inserted into the TOR that match a
NID and an opcode.

NID Matched Miss All:
All NID matched miss requests that were inserted into
the TOR.

TOR_OCCUPANCY

• Title: TOR Occupancy

• Category: TOR Events

• Event Code: 0x36

• Max. Inc/Cyc: 20, Register Restrictions: 0

• Definition: For each cycle, this event accumulates the number of valid entries in the TOR that

match qualifications specified by the subevent. There are a number of subevent 'filters' but only a
subset of the subevent combinations are valid. Subevents that require an opcode or NID match
require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to
count DRD Local Misses, one should select "MISS_OPC_MATCH" and set
Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)

Table 2-31. Unit Masks for TOR_OCCUPANCY (Sheet 1 of 2)

Extension

OPCODE b00000001 CBoFilter[3

EVICTION b00000100 Evictions:

umask
[15:8]

Filter Dep Description

1:23]

Opcode Match:
TOR entries that match an opcode (matched by
Cn_MSR_PMON_BOX_FILTER.opc).

Number of outstanding eviction transactions in the
TOR. Evictions can be quick, such as when the line is
in the F, S, or E states and no core valid bits are set.
They can also be longer if either CV bits are set (so the
cores need to be snooped) and/or if the re is a HitM (in
which case it is necessary to write the request out to
memory).

Reference Number: 327043-001 43

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-31. Unit Masks for TOR_OCCUPANCY (Sheet 2 of 2)

Extension

ALL b00001000 Any:

MISS_OPCODE b00000011 CBoFilter[3

MISS_ALL b00001010 Miss All:

NID_OPCODE b01000001 CBoFilter[3

NID_EVICTION b01000100 CBoFilter[1

NID_ALL b01001000 CBoFilter[1

NID_MISS_OPCODE b01000011 CBoFilter[3

NID_MISS_ALL b01001010 CBoFilter[1

umask
[15:8]

Filter Dep Description

All valid TOR entries. This includes requests that
reside in the TOR for a short time, such as LLC Hits
that do not need to snoop cores or requests that get
rejected and have to be retried through one of the
ingress queues. The TOR is more commonly a
bottleneck in skews with smaller core counts, where
the ratio of RTIDs to TOR entries is larger. Note that
there are reserved TOR entries for various request
types, so it is possible that a given request type be
blocked with an occupancy that is less than 20. Also
note that generally requests will not be able to
arbitrate into the TOR pipeline if there are no available
TOR slots.

1:23]

1:23],
CBoFilter[1
7:10]

7:10]

7:10]

1:23],
CBoFilter[1
7:10]

7:10]

Miss Opcode Match:
TOR entries for miss transactions that match an
opcode. This generally means that the request was
sent to memory or MMIO.

Number of outstanding miss requests in the TOR.
'Miss' means the allocation requires an RTID. This
generally means that the request was sent to memory
or MMIO.

NID and Opcode Matched:
TOR entries that match a NID and an opcode.

NID Matched Evictions:
Number of outstanding NID matched eviction
transactions in the TOR .

NID Matched:
Number of NID matched outstanding requests in the
TOR. The NID is programmed in
Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with
STATE = I, it is possible to monitor misses to specific
NIDs in the system.

NID and Opcode Matched Miss:
Number of outstanding Miss requests in the TOR that
match a NID and an opcode.

NID Matched:
Number of outstanding Miss requests in the TOR that
match a NID.

TxR_ADS_USED

• Title:

• Category: EGRESS Events

• Event Code: 0x04

• Max. Inc/Cyc: 1, Register Restrictions: 0-1

• Definition:

TxR_INSERTS

• Title: Egress Allocations

• Category: EGRESS Events

• Event Code: 0x02

• Max. Inc/Cyc: 1, Register Restrictions: 0-1

• Definition: Number of allocations into the Cbo Egress. The Egress is used to queue up requests

destined for the ring.

44 Reference Number: 327043-001

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-32. Unit Masks for TxR_INSERTS

Extension

AD_CACHE bxxxxxxx1 AD - Cachebo:

AK_CACHE bxxxxxx1x AK - Cachebo:

BL_CACHE bxxxxx1xx BL - Cacheno:

IV_CACHE bxxxx1xxx IV - Cachebo:

AD_CORE bxxx1xxxx AD - Corebo:

AK_CORE bxx1xxxxx AK - Corebo:

BL_CORE bx1xxxxxx BL - Corebo:

umask
[15:8]

Description

Ring transactions from the Cachebo destined for the AD ring. Some
example include outbound requests, snoop requests, and snoop
responses.

Ring transactions from the Cachebo destined for the AK ring. This is
commonly used for credit returns and GO responses.

Ring transactions from the Cachebo destined for the BL ring. This is
commonly used to send data from the cache to various destinations.

Ring transactions from the Cachebo destined for the IV ring. This is
commonly used for snoops to the cores.

Ring transactions from the Corebo destined for the AD ring. This is
commonly used for outbound requests.

Ring transactions from the Corebo destined for the AK ring. This is
commonly used for snoop responses coming from the core and
destined for a Cachebo.

Ring transactions from the Corebo destined for the BL ring. This is
commonly used for transfering writeback data to the cache.

2.4 Home Agent (HA) Performance Monitoring

2.4.1 Overview of the Home Agent

The HA is responsible for the protocol side of memory interactions, including coherent and non­coherent home agent protocols (as defined in the Intel® QuickPath Interconnect Specification).
Additionally, the HA is responsible for ordering memory reads/writes, coming in from the modular
Ring, to a given address such that the iMC (memory controller).

In other words, it is the coherency agent responsible for guarding the memory controller. All requests
for memory attached to the coupled iMC must first be ordered through the HA. As such, it provides
several functions:

• Interface between Ring and iMC:
Regardless of the memory technology, the Home Agent receives memory read and write requests

from the modular ring. It checks the memory transaction type, detects and resolves the coherent
conflict, and finally schedules a corresponding transaction to the memory controller. It is also
responsible for returning the response and completion to the requester.

• Conflict Manager:
All requests must go through conflict management logic in order to ensure coherent consistency.

In other words, the view of data must be the same across all coherency agents regardless of who
is reading or modifying the data. On Intel® QPI, the home agent is responsible for tracking all
requests to a given address and ensuring that the results are consistent.

• Memory Access Ordering Control:

• The Home Agent guarantees the ordering of RAW, WAW and W AR. Home Snoop Protocol Support
(for parts with Directory Support):

Reference Number: 327043-001 45

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

The Home Agent supports Intel® QPI’s home snoop protocol by initiating snoops on behalf of
requests. Closely tied to the directory feature, the home agent has the ability to issue snoops to
the peer caching agents for requests based on the directory information.

• Directory Support:
In order to satisfy performance requirements for the 4 socket and scalable DP segments, the

Home Agent implements a snoop directory which tracks all cachelines residing behind this Home
Agent. This directory is used to reduce the snoop traffic when Intel® QPI bandwidth would
otherwise be strained. The directory is not intended for typical 2S topologies.

2.4.2 HA Performance Monitoring Overview

The HA Box supports event monitoring through four 48-bit wide counters
(HA_PCI_PMON_CTR{3:0}). Each of these counters can be programmed (HA_PCI_PMON_CTL{3:0})
to capture any HA event. The HA counters will increment by a maximum of 8b per cycle.

For information on how to setup a monitoring session, refer to Section 2.1, “Uncore Per-Socket

Performance Monitoring Control”.

2.4.3 HA Performance Monitors

Table 2-33. HA Performance Monitoring MSRs

Register Name

PCICFG Base Address Dev:Func
HA PMON Registers D14:F1

Box-Level Control/Status

HA_PCI_PMON_BOX_CTL F4 32 HA PMON Box-Wide Control

Generic Counter Control

HA_PCI_PMON_CTL3 E4 32 HA PMON Control for Counter 3
HA_PCI_PMON_CTL2 E0 32 HA PMON Control for Counter 2
HA_PCI_PMON_CTL1 DC 32 HA PMON Control for Counter 1
HA_PCI_PMON_CTL0 D8 32 HA PMON Control for Counter 0

Generic Counters

HA_PCI_PMON_CTR3 BC+B8 32x2 HA PMON Counter 3
HA_PCI_PMON_CTR2 B4+B0 32x2 HA PMON Counter 2
HA_PCI_PMON_CTR1 AC+A8 32x2 HA PMON Counter 1
HA_PCI_PMON_CTR0 A4+A0 32x2 HA PMON Counter 0

Box-Level Filter

HA_PCI_PMON_BOX_OPCODEMATCH 48 32 HA PMON Opcode Match
HA_PCI_PMON_BOX_ADDRMATCH1 44 32 HA PMON Address Match 1
HA_PCI_PMON_BOX_ADDRMATCH0 40 32 HA PMON Address Match 0

PCICFG

Address

Size

(bits)

Description

2.4.3.1 HA Box Level PMON State

The following registers represent the state governing all box-level PMUs in the HA Box.

46 Reference Number: 327043-001

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

In the case of the HA, the HA_PCI_PMON_BOX_CTL register governs what happens when a freeze
signal is received (.frz_en). It also provides the ability to manually freeze the counters in the box
(.frz).

Table 2-34. HA_PCI_PMON_BOX_CTL Regi ster – Field Definitions

Field Bits Attr

rsv 31:18 RV 0 Reserved (?)
rsv 17 RV 0 Reserved; SW must write to 0 else behavior is undefined.
frz_en 16 WO 0 Freeze Enable.

rsv 15:9 RV 0 Reserved (?)
frz 8 WO 0 Freeze.

rsv 7:2 RV 0 Reserved (?)
rsv 1:0 RV 0 Reserved; SW must write to 0 else behavior is undefined.

HW

Reset

Val

Description

If set to 1 and a freeze signal is received, the counters will be
stopped or ‘frozen’, else the freeze signal will be ignored.

If set to 1 and the .frz_en is 1, the counters in this box will be
frozen.

2.4.3.2 HA PMON state - Counter/Control Pairs

The following table defines the layout of the HA performance monitor control registers. The main task
of these configuration registers is to select the event to be monitored by their respective data counter
(.ev_sel, .umask). Additional control bits are provided to shape the incoming events (e.g. .invert,
.edge_det, .thresh).

Table 2-35. HA_PCI_PMON_CTL{3-0} Reg i ster – Field Definitions (Sheet 1 of 2)

Field Bits Attr

thresh 31:24 RW-V 0 Threshold used in counter comparison.
invert 23 RW-V 0 Invert comparison against Threshold.

en 22 RW-V 0 Local Counter Enable.
rsv 21:20 RV 0 Reserved. SW must write to 0 else behavior is undefined.
rsv 19 RV 0 Reserved (?)
edge_det 18 RW-V 0 When set to 1, rather than measuring the event in each cycle it

HW

Reset

Val

Description

0 - comparison will be ‘is event increment >= threshold?’.
1 - comparison is inverted - ‘is event increment < threshold?’

NOTE: .invert is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.

Also, if .edge_det is set to 1, the counter will increment when a 1
to 0 transition (i.e. falling edge) is detected.

is active, the corresponding counter will increment when a 0 to 1
transition (i.e. rising edge) is detected.

When 0, the counter will increment in each cycle that the event
is asserted.

NOTE: .edge_det is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.

Reference Number: 327043-001 47

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-35. HA_PCI_PMON_CTL{3-0} Register – F ie l d Definitions (Sheet 2 of 2)

Field Bits Attr

rsv 17:16 RV 0 Reserved. SW must write to 0 else behavior is undefined.
umask 15:8 RW-V 0 Select subevents to be counted within the selected event.
ev_sel 7:0 RW-V 0 Select event to be counted.

HW

Reset

Val

Description

The HA performance monitor data registers are 48-bit wide. Should a counter overflow (a carry out
from bit 47), the counter will wrap and continue to collect events.If accessible, software can
continuously read the data registers without disabling event collection.

Table 2-36. HA_PCI_PMON_CTR{3-0} Register – Field Definitions

Field Bits Attr

rsv 63:48 RV 0 Reserved (?)
event_count 47:0 RW-V 0 48-bit performance event counter

HW

Reset

Val

Description

In addition to generic event counting, each HA provides a pair of Address Match registers and an
Opcode Match register that allow a user to filter incoming packet traffic according to the packet
Opcode, Message Class and Physical Address. The ADDR_OPC_MATCH.FILT event is provided to
capture the filter match as an event. The fields are laid out as follows:

Note: Refer to Table 2-142, “Intel® QuickPath Interconnect Packet Message Classes” and

Table 2-143, “Opcode Match by Message Class” to determine the encodings of the B-

Box Match Register fields.

Table 2-37. HA_PCI_PMON_BOX_OPCODEMATCH Register – Field Definitions

Field Bits Attr

rsv 31:6 RV 0 Reserved (?)
opc 5:0 RWS 0 Match to this incoming (? which polarity?) opcode

HW

Reset

Val

Description

Table 2-38. HA_PCI_PMON_BOX_ADDRMATCH1 Register – Field Definitions

Field Bits Attr

rsv 31:14 RV 0 Reserved (?)
hi_addr 13:0 RWS 0 Match to this System Address - Most Significant 14b of cache

HW

Reset

Val

Description

aligned address [45:32]

48 Reference Number: 327043-001

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-39. HA_PCI_PMON_BOX_ADDRMATCH0 Register – Field Definitions

Field Bits

lo_addr 31:6 RWS 0 Match to this System Address - Least Significant 26b of cache

rsv 5:0 RV 0 Reserved (?)

HW

Reset

Val

HW

Reset

Val

Description

aligned address [31:6]

Note: The address comparison always ignores the lower 12 bits of the physical address, even

if they system is interleaving between sockets at the cache-line level. Therefore, this
mask will always match to an OS virtual page, even if only a fraction of that page is
mapped to the Home Agent under investigation. The mask is not adjusted for large
pages, so matches will only be allowed within 4K granularity.

2.4.4 HA Performance Monitoring Events

The performance monitoring events within the HA include all events internal to the HA as well as
events which track ring related activity at the HA ring stops. Internal events include the ability to
track Directory Activity, Direct2Core Activity, iMC Read/W rite Traffic, time spent dealing with Conflicts,
etc.

Other notable event types:

•iMC RPQ/WPQ Events
Determine cycles the HA is stuck without credits in to the iMCs read/write queues.

•Ring Stop Events
To track Egress and ring utilization (broken down by direction and ring type) statistics, as well as

ring credits between the HA and Intel® QPI.

• Local/Remote Filtering
A number of HA events is extended to support filtering the origination from a local or remote

caching agent .

• Snoop Latency

2.4.4.1 On the Major HA Structures:

The 128-entry TF (Tracker File) holds all transactions that arrive in the HA from the time they arrive
until they are completed and leave the HA. T ransactions could stay in this structure much longer than
they are needed. TF is the critical resource each transaction needs before being sent to the iMC
(memory controller)

TF average occupancy == (valid cnt * 128 / cycles)
TF average latency == (valid cnt * 128 / inserts)

Other Internal HA Queues of Interest:
TxR (aka EGR) - The HA has Egress (responses) queues for each ring (AD , AK, BL) as well as queues

to track credits the HA has to push traffic onto those rings.

Reference Number: 327043-001 49

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

2.4.5 HA Box Events Ordered By Code

The following table summarizes the directly measured HA Box events.

Table 2-40. Performance Monitor Events for HA

Symbol Name

CLOCKTICKS 0x00 0-3 1 uclks
REQUESTS 0x01 0-3 1 Read and Write Requests
TRACKER_INSERTS 0x06 0-3 1 Tracker Allocations
CONFLICT_CYCLES 0x0B 0-3 1 Conflict Checks
DIRECTORY_LOOKUP 0x0C 0-3 1 Directory Lookups
DIRECTORY_UPDATE 0x0D 0-3 1 Directory Updates
TxR_AK_NDR 0x0E 0-3 1 Outbound NDR Ring Transactions
TxR_AD 0x0F 0-3 1 Outbound NDR Ring Transactions
TxR_BL 0x10 0-3 1 Outbound DRS Ring Transactions to Cache
DIRECT2CORE_COUNT 0x11 0-3 1 Direct2Core Messages Sent
DIRECT2CORE_CYCLES_DISABLED 0x12 0-3 1 Cycles when Direct2Core was Disabled
DIRECT2CORE_TXN_OVERRIDE 0x13 0-3 1 Number of Reads that had Direct2Core

RPQ_CYCLES_NO_REG_CREDITS 0x15 0-3 4 iMC RPQ Credits Empty - Regular
WPQ_CYCLES_NO_REG_CREDITS 0x18 0-3 4 HA iMC CHN0 WPQ Credits Empty - Regular
IMC_WRITES 0x1A 0-3 1 HA to iMC Full Line Writes Issued
TAD_REQUESTS_G0 0x1B 0-3 2 HA Requests to a TAD Region - Group 0
TAD_REQUESTS_G1 0x1C 0-3 2 HA Requests to a TAD Region - Group 1
IMC_RETRY 0x1E 0-3 1 Retry Events
ADDR_OPC_MATCH 0x20 0-3 1 Intel® QPI Address/Opcode Match
IGR_NO_CREDIT_CYCLES 0x22 0-3 1 Cycles without Intel® QPI Ingress Credits
TxR_AD_CYCLES_FULL 0x2A 0-3 1 AD Egress Full
TxR_AK_CYCLES_FULL 0x32 0-3 1 AK Egress Full
TxR_BL_CYCLES_FULL 0x36 0-3 1 BL Egress Full

Event

Code

Ctrs

Max

Inc/

Cyc

Description

Overridden

2.4.6 HA Box Common Metrics (Derived Events)

The following table summarizes metrics commonly calculated from HA Box events.

Table 2-41. Metrics Derived from HA Events (Sheet 1 of 2)

Symbol Name:

Definition

PCT_CYCLES_BL_FULL:
Percentage of time the BL Egress Queue is
full

PCT_CYCLES_CONFLICT:
Percentage of time in Conflict Resolution

PCT_CYCLES_D2C_DISABLED:
Percentage of time that Direct2Core was
disabled.

50 Reference Number: 327043-001

TxR_BL_CYCLES_FULL.ALL / SAMPLE_INTERVAL

CONFLICT_CYCLES.CONFLICT / SAMPLE_INTERVAL

DIRECT2CORE_CYCLES_DISABLED / SAMPLE_INTERVAL

Equation

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-41. Metrics Derived from HA Events (Sheet 2 of 2)

Symbol Name:

Definition

PCT_RD_REQUESTS:
Percentage of HA traffic that is from Read
Requests

PCT_WR_REQUESTS:
Percentage of HA traffic that is from Write
Requests

REQUESTS.READS / (REQUESTS.READS + REQUESTS.WRITES)

REQUESTS.WRITES / (REQUESTS.READS +
REQUESTS.WRITES)

Equation

2.4.7 HA Box Performance Monitor Event List

The section enumerates the performance monitoring events for the HA Box.ADDR_OPC_MATCH

• Title: Intel® QPI Address/Opcode Match

• Category: ADDR_OPCODE_MATCH Events

• Event Code: 0x20

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition:

Table 2-42. Unit Masks for ADDR_OPC_MATCH

Extension

FILT b00000011 HA_AddrMa

umask
[15:8]

Filter Dep Description

tch0[31:6],
HA_AddrMa
tch1[13:0],
HA_Opcode
Match[5:0]

Address & Opcode Match

CLOCKTICKS

• Title: uclks

• Category: UCLK Events

• Event Code: 0x00

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of uclks in the HA. This will be slightly different than the count in

the Ubox because of enable/freeze delays. The HA is on the other side of the die from the fixed
Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the Intel®
QPI Agent.

CONFLICT_CYCLES

• Title: Conflict Checks

• Category: CONFLICTS Events

• Event Code: 0x0B

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition:

Reference Number: 327043-001 51

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Table 2-43. Unit Masks for CONFLICT_CYCLES

Extension

NO_CONFLICT bxxxxxxx1 No Conflict:

CONFLICT bxxxxxx1x Conflict Detected:

umask
[15:8]

Counts the number of cycles that we are NOT handling conflicts.

Counts the number of cycles that we are handling conflicts.

DIRECT2CORE_COUNT

• Title: Direct2Core Messages Sent

• Category: DIRECT2CORE Events

• Event Code: 0x11

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Number of Direct2Core messages sent

DIRECT2CORE_CYCLES_DISABLED

• Title: Cycles when Direct2Core was Disabled

• Category: DIRECT2CORE Events

• Event Code: 0x12

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Number of cycles in which Direct2Core was disabled

DIRECT2CORE_TXN_OVERRIDE

• Title: Number of Reads that had Direct2Core Overridden

• Category: DIRECT2CORE Events

• Event Code: 0x13

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Number of Reads where Direct2Core overridden

Description

DIRECTORY_LOOKUP

• Title: Directory Lookups

• Category: DIRECTORY Events

• Event Code: 0x0C

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of transactions that looked up the directory. Can be filtered by

requests that had to snoop and those that did not have to.

• NOTE: Only valid for parts that implement the Directory

Table 2-44. Unit Masks for DIRECTORY_LOOKUP

Extension

SNP bxxxxxxx1 Snoop Needed:

NO_SNP bxxxxxx1x Snoop Not Needed:

52 Reference Number: 327043-001

umask
[15:8]

Description

Filters for transactions that had to send one or more snoops because
the directory bit was set.

Filters for transactions that did not ha ve to send an y sn oops b ecause
the directory bit was clear.

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

DIRECTORY_UPDATE

• Title: Directory Updates

• Category: DIRECTORY Events

• Event Code: 0x0D

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of directory updates that were required. These result in writes to

the memory controller. This can be filtered by directory sets and directory clears.

• NOTE: Only valid for parts that implement the Directory

Table 2-45. Unit Masks for DIRECTORY_UPDATE

Extension

SET bxxxxxxx1 Directory Set:

CLEAR bxxxxxx1x Directory Clear:

ANY bxxxxxx11 Any Directory Update

umask
[15:8]

Description

Filter for directory sets. This occurs when a remote read transact ion
requests memory, bringing it to a remote cache.

Filter for directory clears. This occurs when snoops were sent and all
returned with RspI.

IGR_NO_CREDIT_CYCLES

• Title: Cycles without Intel® QPI Ingress Credits

• Category: QPI_IGR_CREDITS Events

• Event Code: 0x22

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles when the HA does not have credits to send messages to

the Intel® QPI Agent. This can be filtered by the different credit pools and the different links.

Table 2-46. Unit Masks for IGR_NO_CREDIT_CYCLES

Extension

AD_QPI0 bxxxxxxx1 AD to Intel® QPI Link 0
AD_QPI1 bxxxxxx1x AD to Intel® QPI Link 1
BL_QPI0 bxxxxx1xx BL to Intel® QPI Link 0
BL_QPI1 bxxxx1xxx BL to Intel® QPI Link 1

umask
[15:8]

Description

IMC_RETRY

• Title: Retry Events

• Category: IMC_MISC Events

• Event Code: 0x1E

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition:

IMC_WRITES

• Title: HA to iMC Full Line Writes Issued

• Category: IMC_WRITES Events

• Event Code: 0x1A

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the total number of full line writes issued from the HA into the memory control-

ler. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.

Reference Number: 327043-001 53

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-47. Unit Masks for IMC_WRITES

Extension

FULL bxxxxxxx1 Full Line Non-ISOCH
PARTIAL bxxxxxx1x Partial Non-ISOCH
FULL_ISOCH bxxxxx1xx ISOCH Full Line
PARTIAL_ISOCH bxxxx1xxx ISOCH Partial
ALL b00001111 All Writes

umask
[15:8]

Description

REQUESTS

• Title: Read and Write Requests

• Category: REQUESTS Events

• Event Code: 0x01

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the total number of read requests made into the Home Agent. Reads include all

read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).

Table 2-48. Unit Masks for REQUESTS

Extension

READS b00000011 Reads:

WRITES b00001100 Writes:

umask
[15:8]

Description

Incoming ead requests. This is a good proxy for LLC Read Misses
(including RFOs).

Incoming write requests.

RPQ_CYCLES_NO_REG_CREDITS

• Title: iMC RPQ Credits Empty - Regular

• Category: RPQ_CREDITS Events

• Event Code: 0x15

• Max. Inc/Cyc: 4, Register Restrictions: 0-3

• Definition: Counts the number of cycles when there are no "regular" credits available for posting

reads from the HA into the iMC. In order to send reads into the memory controller, the HA must
first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular
credits/buffers that are used by general reads, and "special" requests such as ISOCH reads. This
count only tracks the regular credits Common high banwidth wo rkloads should be able to make use
of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular
and special buffers at the same time. One can filter based on the memory controller channel. One
or more channels can be tracked at a given time.

Table 2-49. Unit Masks for RPQ_CYCLES_NO_REG_CREDITS

Extension

CHN0 bxxxxxxx1 Channel 0:

CHN1 bxxxxxx1x Channel 1:

CHN2 bxxxxx1xx Channel 2:

CHN3 bxxxx1xxx Channel 3:

umask
[15:8]

Description

Filter for memory controller channel 0 only.

Filter for memory controller channel 1 only.

Filter for memory controller channel 2 only.

Filter for memory controller channel 3 only.

54 Reference Number: 327043-001

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

TAD_REQUESTS_G0

• Title: HA Requests to a TAD Region - Group 0

• Category: TAD Events

• Event Code: 0x1B

• Max. Inc/Cyc: 2, Register Restrictions: 0-3

• Definition: Counts the number of HA requests to a given TAD region. There are up to 11 TAD (tar-

get address decode) regions in each home agent. All requests destined for the memory controller
must first be decoded to determine which TAD region they are in. This event is filtered based on
the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applica­tions are using the memory that is spread across the different memory regions. It is particularly
useful for "Monroe" systems that use the TAD to enable individual channels to enter self-refresh to
save power.

Table 2-50. Unit Masks for TAD_REQUESTS_G0

Extension

REGION0 bxxxxxxx1 TAD Region 0:

REGION1 bxxxxxx1x TAD Region 1:

REGION2 bxxxxx1xx TAD Region 2:

REGION3 bxxxx1xxx TAD Region 3:

REGION4 bxxx1xxxx TAD Region 4:

REGION5 bxx1xxxxx TAD Region 5:

REGION6 bx1xxxxxx TAD Region 6:

REGION7 b1xxxxxxx TAD Region 7:

umask
[15:8]

Description

Filters request made to TAD Region 0

Filters request made to TAD Region 1

Filters request made to TAD Region 2

Filters request made to TAD Region 3

Filters request made to TAD Region 4

Filters request made to TAD Region 5

Filters request made to TAD Region 6

Filters request made to TAD Region 7

TAD_REQUESTS_G1

• Title: HA Requests to a TAD Region - Group 1

• Category: TAD Events

• Event Code: 0x1C

• Max. Inc/Cyc: 2, Register Restrictions: 0-3

• Definition: Counts the number of HA requests to a given TAD region. There are up to 11 TAD (tar-

get address decode) regions in each home agent. All requests destined for the memory controller
must first be decoded to determine which TAD region they are in. This event is filtered based on
the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applica­tions are using the memory that is spread across the different memory regions. It is particularly
useful for "Monroe" systems that use the TAD to enable individual channels to enter self-refresh to
save power.

Table 2-51. Unit Masks for TAD_REQUESTS_G1 (Sheet 1 of 2)

Extension

REGION8 bxxxxxxx1 TAD Region 8:

REGION9 bxxxxxx1x TAD Region 9:

Reference Number: 327043-001 55

umask
[15:8]

Description

Filters request made to TAD Region 8

Filters request made to TAD Region 9

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-51. Unit Masks for TAD_REQUESTS_G1 (Sheet 2 of 2)

Extension

REGION10 bxxxxx1xx TAD Region 10:

REGION11 bxxxx1xxx TAD Region 11:

umask
[15:8]

Filters request made to TAD Region 10

Filters request made to TAD Region 11

Description

TRACKER_INSERTS

• Title: Tracker Allocations

• Category: TRACKER Events

• Event Code: 0x06

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of allocations into the local HA tracker pool. This can be used in

conjunction with the occupancy accumulation event in order to calculate average latency. One can­not filter between reads and writes. HA trackers are allocated as soon as a request enters the HA
and is released after the snoop response and data return (or post in the case of a write) and the
response is returned on the ring.

Table 2-52. Unit Masks for TRACKER_INSERTS

Extension

ALL b00000011 All Requests:

umask
[15:8]

Description

Requests coming from both local and remote sockets.

TxR_AD

• Title: Outbound NDR Ring Transactions

• Category: OUTBOUND_TX Events

• Event Code: 0x0F

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of outbound transactions on the AD ring. This can be filtered by

the NDR and SNP message classes. See the filter descriptions for more details.

Table 2-53. Unit Masks for TxR_AD

Extension

NDR bxxxxxxx1 Non-data Responses:

SNP bxxxxxx1x Snoops:

umask
[15:8]

Description

Filter for outbound NDR transactions sent on the AD ring. NDR
stands for "non-data response" and is generally used for completions
that do not include data. AD NDR is used for transactions to remote
sockets.

Filter for outbound SNP transactions sent on the ring. These
transactions are generally snoops being sent out to either remote or
local caching agents. This should be zero if Early Snoop is enabled.

TxR_AD_CYCLES_FULL

• Title: AD Egress Full

• Category: AD_EGRESS Events

• Event Code: 0x2A

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: AD Egress Full

56 Reference Number: 327043-001

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-54. Unit Masks for TxR_AD_CYCLES_FULL

Extension

SCHED0 bxxxxxxx1 Scheduler 0:

SCHED1 bxxxxxx1x Scheduler 1:

ALL bxxxxxx11 All:

umask
[15:8]

Filter for cycles full from scheduler bank 0

Filter for cycles full from scheduler bank 1

Cycles full from both schedulers

TxR_AK_CYCLES_FULL

• Title: AK Egress Full

• Category: AK_EGRESS Events

• Event Code: 0x32

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: AK Egress Full

Table 2-55. Unit Masks for TxR_AK_CYCLES_FULL

Extension

SCHED0 bxxxxxxx1 Scheduler 0:

SCHED1 bxxxxxx1x Scheduler 1:

ALL bxxxxxx11 All:

umask
[15:8]

Filter for cycles full from scheduler bank 0

Filter for cycles full from scheduler bank 1

Cycles full from both schedulers

Description

Description

TxR_AK_NDR

• Title: Outbound NDR Ring Transactions

• Category: OUTBOUND_TX Events

• Event Code: 0x0E

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of outbound NDR transactions sent on the AK ring. NDR stands for

"non-data response" and is generally used for completions that do not include data. AK NDR is
used for messages to the local socket.

TxR_BL

• Title: Outbound DRS Ring Transactions to Cache

• Category: OUTBOUND_TX Events

• Event Code: 0x10

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of DRS messages sent out on the BL ring. This can be filtered by

the destination.

Reference Number: 327043-001 57

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-56. Unit Masks for TxR_BL

Extension

DRS_CACHE bxxxxxxx1 Data to Cache:

DRS_CORE bxxxxxx1x Data to Core:

DRS_QPI bxxxxx1xx Data to Intel® QPI:

umask
[15:8]

Filter for data being sent to the cache.

Filter for data being sent directly to the requesting core.

Filter for data being sent to a remote socket over Intel® QPI.

TxR_BL_CYCLES_FULL

• Title: BL Egress Full

• Category: BL_EGRESS Events

• Event Code: 0x36

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: BL Egress Full

Table 2-57. Unit Masks for TxR_BL_CYCLES_FULL

Extension

SCHED0 bxxxxxxx1 Scheduler 0:

SCHED1 bxxxxxx1x Scheduler 1:

ALL bxxxxxx11 All:

umask
[15:8]

Filter for cycles full from scheduler bank 0

Filter for cycles full from scheduler bank 1

Cycles full from both schedulers

Description

Description

WPQ_CYCLES_NO_REG_CREDITS

• Title: HA iMC CHN0 WPQ Credits Empty - Regular

• Category: WPQ_CREDITS Events

• Event Code: 0x18

• Max. Inc/Cyc: 4, Register Restrictions: 0-3

• Definition: Counts the number of cycles when there are no "regular" credits available for posting

writes from the HA into the iMC. In order to send writes into the memory controller, the HA must
first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular
credits/buffers that are used by general writes, and "special" requests such as ISOCH writes. This
count only tracks the regular credits Common high banwidth wo rkloads should be able to make use
of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular
and special buffers at the same time. One can filter based on the memory controller channel. One
or more channels can be tracked at a given time.

Table 2-58. Unit Masks for WPQ_CYCLES_NO_REG_CREDITS

Extension

CHN0 bxxxxxxx1 Channel 0:

CHN1 bxxxxxx1x Channel 1:

CHN2 bxxxxx1xx Channel 2:

CHN3 bxxxx1xxx Channel 3:

umask
[15:8]

Description

Filter for memory controller channel 0 only.

Filter for memory controller channel 1 only.

Filter for memory controller channel 2 only.

Filter for memory controller channel 3 only.

58 Reference Number: 327043-001

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

2.5 Memory Controller (iMC) Performance Monitoring

2.5.1 Overview of the iMC

The integrated Memory Controller provides the interface to DRAM and communicates to the rest of
the uncore through the Home Agent (i.e. the iMC does not connect to the Ring).

In conjunction with the HA, the memory controller also provides a variety of RAS features, such as
ECC, lockstep, memory access retry, memory scrubbing, thermal throttling, mirroring, and rank
sparing.

2.5.2 Functional Overview

The memory controller is the interface between the home Home Agent (HA) and DRAM, translating
read and write commands into specific memory commands and schedules them with respect to
memory timing. The other main function of the memory controller is advanced ECC support.

Because of the data path affinity to the HA data path, the HA is paired with the memory controller.
The Intel Xeon Processor E5-2600 supports four channels of DDR3 or metaRAM. For DDR3, the

number of DIMMs per channel depends on the speed it is running and the package.

• Support for unbuffered DDR3 and registered DDR3

• Up to four independent DDR3 channels

• Eight independent banks per rank

• Support for DDR3 frequencies of 800,1067, 1333, 1600 GT/s. The speed achievable is
dependent on the number of DIMMs per channel.

• Up to three DIMMs per channel (depends on the speed)

• Support for x4, x8 and x16 data lines per native DDR3 device

• ECC support (correct any error within a x4 device)

• Lockstep support for x8 chipfail

• Open or closed page policy

• Channel Mirroring per socket

• Demand and Patrol Scrubbing support

• Memory Initialization

• Poisoning Support

• Support for LR-DIMMs (load reduced) for a buffered memor y solution dema nding higher capacity
memory subsytems.

• Support for low voltage DDR3 (LV-DDR3, 1.35V)

2.5.3 iMC Performance Monitoring Overview

The iMC supports event monitoring through four 48-bit wide counters
(MC_CHy_PCI_PMON_CTR{3:0}) and one fixed counter (MC_CHy_PCI_PMON_FIXED_CTR) for each
DRAM channel (of which there are 4 in Intel Xeon Processor E5-2600 family) the MC is attached to.
Each of these counters can be programmed (MC_CHy_PCI_PMON_CTL{3:0}) to capture any MC
event. The MC counters will increment by a maximum of 8b per cycle.

Reference Number: 327043-001 59

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

For information on how to setup a monitoring session, refer to Section 2.1, “Uncore Per-Socket

Performance Monitoring Control”.

2.5.4 iMC Performance Monitors

Table 2-59. iMC Performance Monitoring MSRs

Register Name

PCICFG Base Address Dev:Func
MC Channel 0 PMON Registers D16:F0
MC Channel 1 PMON Registers D16:F1
MC Channel 2 PMON Registers D16:F4
MC Channel 3 PMON Registers D16:F5

Box-Level Control/Status

MC_CHy_PCI_PMON_BOX_CTL F4 32 MC Channel y PMON Box-Wide Control

Generic Counter Control

MC_CHy_PCI_PMON_FIXED_CTL F0 32 MC Channel y PMON Control for Fixed Counter
MC_CHy_PCI_PMON_CTL3 E4 32 MC Channel y PMON Control for Counter 3
MC_CHy_PCI_PMON_CTL2 E0 32 MC Channel y PMON Control for Counter 2
MC_CHy_PCI_PMON_CTL1 DC 32 MC Channel y PMON Control for Counter 1
MC_CHy_PCI_PMON_CTL0 D8 32 MC Channel y PMON Control for Counter 0

Generic Counters

MC_CHy_PCI_PMON_FIXED_CTR D4+D0 32x2 MC Channel y PMON Fixed Counter
MC_CHy_PCI_PMON_CTR3 BC+B8 32x2 MC Channel y PMON Counter 3
MC_CHy_PCI_PMON_CTR2 B4+B0 32x2 MC Channel y PMON Counter 2
MC_CHy_PCI_PMON_CTR1 AC+A8 32x2 MC Channel y PMON Counter 1
MC_CHy_PCI_PMON_CTR0 A4+A0 32x2 MC Channel y PMON Counter 0

PCICFG

Address

Size

(bits)

Description

2.5.4.1 MC Box Level PMON State

The following registers represent the state governing all box-level PMUs in the MC Boxes.
In the case of the MC, the MC_CHy_PCI_PMON_BOX_CTL register governs what happens when a

freeze signal is received (.frz_en). It also provides the ability to manually freeze the counters in the
box (.frz) .

Table 2-60. MC_CHy_PCI_PMON_BOX_CTL Register – Field Definitions (Sheet 1 of 2)

Field Bits Attr

rsv 31:18 RV 0 Reserved (?)
rsv 17 RV 0 Reserved; SW must write to 0 else behavior is undefined.
frz_en 16 WO 0 Freeze Enable.

60 Reference Number: 327043-001

HW

Reset

Val

Description

If set to 1 and a freeze signal is received, the counters will be
stopped or ‘frozen’, else the freeze signal will be ignored.

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-60. MC_CHy_PCI_PMON_BOX_CTL Register – Field Definitions (Sheet 2 of 2)

Field Bits Attr

rsv 15:9 RV 0 Reserved (?)
frz 8 WO 0 Freeze.

rsv 7:2 RV 0 Reserved (?)
rsv 1:0 RV 0 Reserved; SW must write to 0 else behavior is undefined.

U

HW

Reset

Val

Description

If set to 1 and the .frz_en is 1, the counters in this box will be
frozen.

2.5.4.2 MC PMON state - Counter/Control Pairs

The following table defines the layout of the MC performance monitor control registers. The main task
of these configuration registers is to select the event to be monitored by their respective data counter
(.ev_sel, .umask). Additional control bits are provided to shape the incoming events (e.g. .invert,
.edge_det, .thresh).

Table 2-61. MC_CHy_PCI_PMON_CTL{3-0} Register – Field Definitions

Field Bits Attr

thresh 31:24 RW-V 0 Threshold used in counter comparison.
invert 23 RW-V 0 Invert comparison against Threshold.

HW

Reset

Val

Description

0 - comparison will be ‘is event increment >= threshold?’.
1 - comparison is inverted - ‘is event increment < threshold?’

NOTE: .invert is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.

Also, if .edge_det is set to 1, the counter will increment when a 1

to 0 transition (i.e. falling edge) is detected.
en 22 RW-V 0 Local Counter Enable.
rsv 21:20 RV 0 Reserved. SW must write to 0 else behavior is undefined.
rsv 19 RV 0 Reserved (?)
edge_det 18 RW-V 0 When set to 1, rather than measuring the event in each cycle it

rsv 17:16 RV 0 Reserved. SW must write to 0 else behavior is undefined.
umask 15:8 RW-V 0 Select subevents to be counted within the selected event.
ev_sel 7:0 RW-V 0 Select event to be counted.

is active, the corresponding counter will increment when a 0 to 1

transition (i.e. rising edge) is detected.

When 0, the counter will increment in each cycle that the event

is asserted.

NOTE: .edge_det is in series following .thresh, Due to this, the

.thresh field must be set to a non-0 value. For events that

increment by no more than 1 per cycle, set .thresh to 0x1.

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Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

All MC performance monitor data registers are 48-bit wide. Should a counter overflow (a carry out
from bit 47), the counter will wrap and continue to collect events.

If accessible, software can continuously read the data registers without disabling event collection.

This is a counter that always tracks the number of DRAM clocks (dclks - half of DDR speed) in the iMC.
The dclk never changes frequency (on a given system), and therefore is a good measure of wall clock
(unlike the Uncore clock which can change frequency based on system load). This clock is gener ally a
bit slower than the uclk (~800MHz to ~1.066GHz) and therefore has less fidelity.

Table 2-62. MC_CHy_PCI_PMON_FIXED_CTL Register – Field Definitions

Field Bits Attr

rsv 31:24 RV 0 Reserved (?)
rsv 23 RV 0 Reserved. SW must write to 0 else behavior is undefined.
en 22 RW-V 0 Local Counter Enable.
rsv 21:20 RV 0 Reserved. SW must write to 0 else behavior is undefined.
rst 19 WO 0 When set to 1, the corresponding counter will be cleared to 0.
rsv 18:0 RV 0 Reserved (?)

HW

Reset

Val

Description

Table 2-63. MC_CHy_PCI_PMON_CTR{FIXED,3-0} Register – Field Definitions

Field Bits Attr

rsv 63:48 RV 0 Reserved (?)
event_count 47:0 RW-V 0 48-bit performance event counter

HW

Reset

Val

Description

2.5.5 iMC Performance Monitoring Events

2.5.5.1 An Overview:

A sampling of events available for monitoring in the iMC:

• Translated commands: Various Read and Write CAS commands

• Memory commands: CAS, Precharge, Refresh, Preemptions, etc,

• Page hits and page misses.

• Page Closing Events

• Control of power consumption: Thermal Throttling by Rank, Time spent in CKE ON mode,
etc.

and many more.

Internal iMC Queues:

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Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

RPQ - Read Pending Queue. NOTE: HA also tracks some information related to the iMC’s RPQ.
WPQ - Write Pending Queue. NOTE: HA also tracks some information related to the iMC’s WPQ.

2.5.6 iMC Box Events Ordered By Code

The following table summarizes the directly measured iMC Box events.

Table 2-64. Performance Monitor Events for iMC

Symbol Name

ACT_COUNT 0x01 0-3 1 DRAM Activate Count
PRE_COUNT 0x02 0-3 1 DRAM Precharge commands.
CAS_COUNT 0x04 0-3 1 DRAM RD _CAS and WR_CAS Commands.
DRAM_REFRESH 0x05 0-3 1 Number of DRAM Refreshes Issued
DRAM_PRE_ALL 0x06 0-3 1 DRAM Precharge All Commands
MAJOR_MODES 0x07 0-3 1 C ycles in a Major Mode
PREEMPTION 0x08 0-3 1 Read Preemption Count
ECC_CORRECTABLE_ERRORS 0x09 0-3 1 ECC Correctable Errors
RPQ_INSERTS 0x10 0-3 1 Read Pending Queue Allocations
RPQ_CYCLES_NE 0x11 0-3 1 Read Pending Queue Not Empty
RPQ_CYCLES_FULL 0x12 0-3 1 Read Pending Queue Full Cycles
WPQ_INSERTS 0x20 0-3 1 Write Pending Queue Allocations
WPQ_CYCLES_NE 0x21 0-3 1 Write Pending Queue Not Empty
WPQ_CYCLES_FULL 0x22 0-3 1 Write Pending Queue Full Cycles
WPQ_READ_HIT 0x23 0-3 1 Write Pending Queue CAM Match
WPQ_WRITE_HIT 0x24 0-3 1 Write Pending Queue CAM Match
POWER_THROTTLE_CYCLES 0x41 0-3 1 Throttle Cycles for Rank 0
POWER_SELF_REFRESH 0x43 0-3 Clock-Enabled Self-Refresh
RPQ_OCCUPANCY 0x80 0-3 22 Read Pending Queue Occupancy
WPQ_OCCUPANCY 0x81 0-3 32 Write Pending Queue Occupancy
POWER_CKE_CYCLES 0x83 0-3 16 CKE_ON_CYCLES by Rank
POWER_CHANNEL_DLLOFF 0x84 0-3 1 Channel DLLOFF Cycles
POWER_CHANNEL_PPD 0x85 0-3 4 Channel PPD Cycles
POWER_CRITICAL_THROTTLE_CYCLES0x86 0-3 1 Critical Throttle Cycles

Event

Code

Ctrs

Max

Inc/

Cyc

Description

2.5.7 iMC Box Common Metrics (Derived Events)

The following table summarizes metrics commonly calculcated from iMC Box events.

Reference Number: 327043-001 63

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-65. Metrics Derived from iMC Events

Symbol Name:

Definition

MEM_BW_READS:
Memory bandwidth consumed by reads.
Expressed in bytes.

MEM_BW_TOTAL:
Total memory bandwidth. Expressed in
bytes.

MEM_BW_WRITES:
Memory bandwidth consumed by writes
Expressed in bytes.

PCT_CYCLES_CRITICAL_THROTTLE:
The percentage of cycles all DRAM ranks in
critical thermal throttling

PCT_CYCLES_DLOFF:
The percentage of cycles all DRAM ranks in
CKE slow (DLOFF) mode

PCT_CYCLES_DRAM_RANKx_IN_CKE:
The percentage of cycles DRAM rank (x)
spent in CKE ON mode.

PCT_CYCLES_DRAM_RANKx_IN_THR:
The percentage of cycles DRAM rank (x)
spent in thermal throttling.

PCT_CYCLES_PPD:
The percentage of cycles all DRAM ranks in
PPD mode

PCT_CYCLES_SELF_REFRESH:
The percentage of cycles Memory is in self
refresh power mode

PCT_RD_REQUESTS:
Percentage of read requests from total
requests.

PCT_REQUESTS_PAGE_EMPTY:
Percentage of memory requests that
resulted in Page Empty

PCT_REQUESTS_PAGE_HIT:
Percentage of memory requests that
resulted in Page Hits

PCT_REQUESTS_PAGE_MISS:
Percentage of memory requests that
resulted in Page Misses

PCT_WR_REQUESTS:
Percentage of write requests from total
requests.

Equation

(CAS_COUNT.RD * 64)

MEM_BW_READS + MEM_BW_WRITES

(CAS_COUNT.WR * 64)

POWER_CRITICAL_THROTTLE_CYCLES /
MC_Chy_PCI_PMON_CTR_FIXED

POWER_CHANNEL_DLOFF / MC_Chy_PCI_PMON_CTR_FIXED

POWER_CKE_CYCLES.RANKx / MC_Chy_PCI_PMON_CTR_FIXED

POWER_THROTTLE_CYCLES.RANKx /
MC_Chy_PCI_PMON_CTR_FIXED

POWER_CHANNEL_PPD / MC_Chy_PCI_PMON_CTR_FIXED

POWER_SELF_REFRESH / MC_Chy_PCI_PMON_CTR_FIXED

RPQ_INSERTS / (RPQ_INSERTS + WPQ_INSERTS)

(ACT_COUNT - PRE_COUNT.PAGE_MISS)/ (CAS_COUNT.RD +
CAS_COUNT.WR)

1 - (PCT_REQUESTS_PAGE_EMPTY +
PCT_REQUESTS_PAGE_MISS)

PRE_COUNT.PAGE_MISS / (CAS_COUNT.RD + CAS_COUNT.WR)

WPQ_INSERTS / (RPQ_INSERTS + WPQ_INSERTS)

2.5.8 iMC Box Performance Monitor Event List

The section enumerates the performance monitoring events for the iMC Box.

ACT_COUNT

• Title: DRAM Activate Count

• Category: ACT Events

• Event Code: 0x01

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

64 Reference Number: 327043-001

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

• Definition: Counts the number of DRAM Activate commands sent on this channel. Activate com-

mands are issued to open up a page on the DRAM devices so that it can be read or written to with a
CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss pre­charges from the number of Activates.

CAS_COUNT

• Title: DRAM RD_CAS and WR_CAS Commands.

• Category: CAS Events

• Event Code: 0x04

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: DRAM RD_CAS and WR_CAS Commands

Table 2-66. Unit Masks for CAS_COUNT

Extension

RD_REG bxxxxxxx1 All DRAM RD_CAS (w/ and w/out auto-pre):

RD_UNDERFILL bxxxxxx1x Underfill Read Issued:

RD b00000011 All DRAM Reads (RD_CAS + Underfills):

WR_WMM bxxxxx1xx DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode:

WR_RMM bxxxx1xxx DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode:

WR b00001100 All DRAM WR_CAS (both Modes):

ALL b00001111 All DRAM W R_CAS (w/ and w/out auto-pre):

umask
[15:8]

Description

Counts the total number or DRAM Read CAS commands issued on
this channel. This includes both regular RD CAS commands as well
as those with implicit Precharge. AutoPre is only used in systems
that are using closed page policy. We do not filter based on major
mode, as RD_CAS is not issued during WMM (with the exception of
underfills).

Counts the number of underfill reads that are issued by the memory
controller. This will generally be about the same as the number of
partial writes, but may be slightly less because of partials hitting in
the WPQ. While it is possible for underfills to be issed in both WMM
and RMM, this event counts both.

Counts the total number of DRAM Read CAS commands issued on
this channel (including underfills).

Counts the total number or DRAM Write CAS commands issued on
this channel while in Write-Maj or-Mode.

Counts the total number of Opportunistic" DRAM Write CAS
commands issued on this channel while in Read-Major-Mode.

Counts the total number of DRAM Write CAS commands issued on
this channel.

Counts the total number of DRAM CAS commands issued on this
channel.

DRAM_PRE_ALL

• Title: DRAM Precharge All Commands

• Category: DRAM_PRE_ALL Events

• Event Code: 0x06

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of times that the precharge all command was sent.

DRAM_REFRESH

• Title: Number of DRAM Refreshes Issued

• Category: DRAM_REFRESH Events

• Event Code: 0x05

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of refreshes issued.

Reference Number: 327043-001 65

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-67. Unit Masks for DRAM_REFRESH

Extension

PANIC bxxxxxx1x
HIGH bxxxxx1xx

umask
[15:8]

Description

ECC_CORRECTABLE_ERRORS

• Title: ECC Correctable Errors

• Category: ECC Events

• Event Code: 0x09

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of ECC errors detected and corrected by the iMC on this channel.

This counter is only useful with ECC DRAM devices. This count will increment one time for each cor­rection regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in inde­pendent channel mode and 8 bit erros in lockstep mode.

MAJOR_MODES

• Title: Cycles in a Major Mode

• Category: MAJOR_MODES Events

• Event Code: 0x07

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the total number of cycles spent in a major mode (selected by a filter) on the

given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.

Table 2-68. Unit Masks for MAJOR_MODES

Extension

READ bxxxxxxx1 Read Major Mode:

WRITE bxxxxxx1x Write Major Mode:

PARTIAL bxxxxx1xx Partial Major Mode:

ISOCH bxxxx1xxx Isoch Major Mode:

umask
[15:8]

Description

Read Major Mode is the default mode for the iMC, as reads are
generally more critical to forward progress than writes.

This mode is triggered when the WPQ hits high occupancy and causes
writes to be higher priority than reads. This can cause blips in the
available read bandwidth in the sys tem and temporarily increase read
latencies in order to achieve better bus utilizations and higher
bandwidth.

This major mode is used to drain starved underfill reads. Regular
reads and writes are blocked and only underfill reads will be
processed.

We group these two modes togethe r so that we can use four cou nters
to track each of the major modes at one time. These major modes
are used whenever there is an ISOCH txn in the memory controller.
In these mode, only ISOCH transactions are processed.

POWER_CHANNEL_DLLOFF

• Title: Channel DLLOFF Cycles

• Category: POWER Events

• Event Code: 0x84

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.

• NOTE: IBT = Input Buffer Termination = Off

66 Reference Number: 327043-001

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

POWER_CHANNEL_PPD

• Title: Channel PPD Cycles

• Category: POWER Events

• Event Code: 0x85

• Max. Inc/Cyc: 4, Register Restrictions: 0-3

• Definition: Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is

enabled, then this can be used to count those cycles. If it is not enabled, then this can count the
number of cycles when that could have been taken advantage of.

• NOTE: IBT = Input Buffer Termination = On

POWER_CKE_CYCLES

• Title: CKE_ON_CYCLES by Rank

• Category: POWER Events

• Event Code: 0x83

• Max. Inc/Cyc: 16, Register Restrictions: 0-3

• Definition: Number of cycles spent in CKE ON mode. The filter allows you to select a rank to mon-

itor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one
rather than doing accumulation. Multiple counters will need to be used to track multiple ranks
simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This
can be determined based on the system programming. These events should commonly be used
with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here.
Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not
necessary).

Table 2-69. Unit Masks for POWER_CKE_CYCLES

Extension

RANK0 bxxxxxxx1 DIMM ID
RANK1 bxxxxxx1x DIMM ID
RANK2 bxxxxx1xx DIMM ID
RANK3 bxxxx1xxx DIMM ID
RANK4 bxxx1xxxx DIMM ID
RANK5 bxx1xxxxx DIMM ID
RANK6 bx1xxxxxx DIMM ID
RANK7 b1xxxxxxx DIMM ID

umask
[15:8]

Description

POWER_CRITICAL_THROTTLE_CYCLES

• Title: Critical Throttle Cycles

• Category: POWER Events

• Event Code: 0x86

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles when the iMC is in critical thermal throttling. When this

happens, all traffic is blocked. This should be rare unless something bad is going on in the platform.
There is no filtering by rank for this event.

POWER_SELF_REFRESH

• Title: Clock-Enabled Self-Refresh

• Category: POWER Events

• Event Code: 0x43

• Max. Inc/Cyc: , Register Restrictions: 0-3

Reference Number: 327043-001 67

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

• Definition: Counts the number of cycles when the iMC is in self-refresh and the iMC still has a

clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter
self-refresh even though some of the cores are still processing. One use of this is for Monroe tech­nology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this
time, so it is not possible to count these cases.

POWER_THROTTLE_CYCLES

• Title: Throttle Cycles for Rank 0

• Category: POWER Events

• Event Code: 0x41

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles while the iMC is being throttled by either thermal con-

straints or by the PCU throttling. It is not possible to distinguish between the two. This can be fil­tered by rank. If multiple ranks are selected and are being throttled at the same time, the counter
will only increment by 1.

Table 2-70. Unit Masks for POWER_THROTTLE_CYCLES

Extension

RANK0 bxxxxxxx1 DIMM ID:

RANK1 bxxxxxx1x DIMM ID
RANK2 bxxxxx1xx DIMM ID
RANK3 bxxxx1xxx DIMM ID
RANK4 bxxx1xxxx DIMM ID
RANK5 bxx1xxxxx DIMM ID
RANK6 bx1xxxxxx DIMM ID
RANK7 b1xxxxxxx DIMM ID

umask
[15:8]

Thermal throttling is performed per DIMM. We support 3 DIMMs per
channel. This ID allows us to filter by ID.

Description

PREEMPTION

• Title: Read Preemption Count

• Category: PREEMPTION Events

• Event Code: 0x08

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of times a read in the iMC preempts another read or write. Gener-

ally reads to an open page are issued ahead of requests to closed pages. This improves the page
hit rate of the system. However, high priority requests can cause pages of active requests to be
closed in order to get them out. This will reduce the latency of the high-priority request at the
expense of lower bandwidth and increased overall average latency.

Table 2-71. Unit Masks for PREEMPTION

Extension

RD_PREEMPT_RD bxxxxxxx1 Read over Read Preemption:

RD_PREEMPT_WR bxxxxxx1x Read over Write Preemption:

68 Reference Number: 327043-001

umask
[15:8]

Description

Filter for when a read preempts another read.

Filter for when a read preempts a write.

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

PRE_COUNT

• Title: DRAM Precharge commands.

• Category: PRE Events

• Event Code: 0x02

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of DRAM Precharge commands sent on this channel.

Table 2-72. Unit Masks for PRE_COUNT

Extension

PAGE_MISS bxxxxxxx1 Precharges due to page miss:

PAGE_CLOSE bxxxxxx1x Precharge due to timer expiration:

umask
[15:8]

Description

Counts the number of DRAM Precharge commands sent on this
channel as a result of page misses. This does not include explicit
precharge commands sent with CAS commands in Auto-Precharge
mode. This does not include PRE commands sent as a result of the
page close counter expiration.

Counts the number of DRAM Precharge commands sent on this
channel as a result of the page close counter expir ing. Th is does no t
include implicit precharge commands sent in auto-precharge mode.

RPQ_CYCLES_FULL

• Title: Read Pending Queue Full Cycles

• Category: RPQ Events

• Event Code: 0x12

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles when the Read Pending Queue is full. When the RPQ is

full, the HA will not be able to issue any additional read requests into the iMC. This count should be
similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just
somewhat smaller to account for the credit return overhead. We generally do not expect to see
RPQ become full except for potentially during Write Major Mode or while running with slow DRAM.
This event only tracks non-ISOC queue entries.

RPQ_CYCLES_NE

• Title: Read Pending Queue Not Empty

• Category: RPQ Events

• Event Code: 0x11

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles that the Read P ending Queue is not empt y. This can then

be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occu­pancy count). The RPQ is used to schedule reads out to the memory controller and to track the
requests. Requests allocate into the RPQ soon after they enter the memory controller, and need
credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after
the CAS command has been issued to memory. This filter is to be used in conjunction with the
occupancy filter so that one can correctly track the average occupancies for schedulable entries and
scheduled requests.

RPQ_INSERTS

• Title: Read Pending Queue Allocations

• Category: RPQ Events

• Event Code: 0x10

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of allocations into the Read Pending Queue. This queue is used to

schedule reads out to the memory controller and to track the requests. Requests allocate into the
RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before

Reference Number: 327043-001 69

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

being sent from the HA to the iMC. They deallocate after the CAS command has been issued to
memory. This includes both ISOCH and non-ISOCH requests.

RPQ_OCCUPANCY

• Title: Read Pending Queue Occupancy

• Category: RPQ Events

• Event Code: 0x80

• Max. Inc/Cyc: 22, Register Restrictions: 0-3

• Definition: Accumulates the occupancies of the Read Pending Queue each cycle. This can then be

used to calculate both the average occupancy (in conjunction with the number of cycles not empty)
and the average latency (in conjunction with the number of allocations). The RPQ is used to sched­ule reads out to the memory controller and to track the requests. Requests allocate into the RPQ
soon after they enter the memory controller, and need credits for an entry in this buffer before
being sent from the HA to the iMC. They deallocate after the CAS command has been issued to
memory.

WPQ_CYCLES_FULL

• Title: Write Pending Queue Full Cycles

• Category: WPQ Events

• Event Code: 0x22

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles when the Write Pending Queue is full. When the WPQ is

full, the HA will not be able to issue any additional read requests into the iMC. This count should be
similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just
somewhat smaller to account for the credit return overhead.

WPQ_CYCLES_NE

• Title: Write Pending Queue Not Empty

• Category: WPQ Events

• Event Code: 0x21

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles that the Write Pending Queue is not empty. This can then

be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accu­mulation count). The WPQ is used to schedule write out to the memory controller and to track the
writes. Requests allocate into the WPQ soon after they enter the memory controller, and need cred­its for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being
issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest
of the system) as soon they have "posted" to the iMC. This is not to be confused with actually per­forming the write to DRAM. Therefore, the average latency for this queue is actually not useful for
deconstruction intermediate write latencies.

WPQ_INSERTS

• Title: Write Pending Queue Allocations

• Category: WPQ Events

• Event Code: 0x20

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of allocations into the Write Pending Queue. This can then be used

to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ
is used to schedule write out to the memory controller and to track the writes. Requests allocate
into the WPQ soon after they enter the memory controller, and need credits for an entry in this buf­fer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write
requests themselves are able to complete (from the perspective of the rest of the system) as soon
they have "posted" to the iMC.

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WPQ_OCCUPANCY

• Title: Write Pending Queue Occupancy

• Category: WPQ Events

• Event Code: 0x81

• Max. Inc/Cyc: 32, Register Restrictions: 0-3

• Definition: Accumulates the occupancies of the Write Pending Queue each cycle. This can then be

used to calculate both the average queue occupancy (in conjunction with the number of cycles not
empty) and the average latency (in conjunction with the number of allocations). The WPQ is used
to schedule write out to the memory controller and to track the writes. Requests allocate into the
WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before
being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests
themselves are able to complete (from the perspective of the rest of the system) as soon they have
"posted" to the iMC. This is not to be confused with actually performing the write to DRAM. There­fore, the average latency for this queue is actually not useful for deconstruction intermediate write
latencies. So, we provide filtering based on if the request has posted or not. By using the "not
posted" filter, we can track how long writes spent in the iMC before completions were sent to the
HA. The "posted" filter, on the other hand, provides information about how much queueing is actu­ally happenning in the iMC for writes before they are actually issued to memory. High average
occupancies will generally coincide with high write major mode counts.

WPQ_READ_HIT

• Title: Write Pending Queue CAM Match

• Category: WPQ Events

• Event Code: 0x23

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of times a request hits in the WPQ (write-pending queue). The iMC

allows writes and reads to pass up other writes to different addresses. Before a read or a write is
issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit,
they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit
will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will
simply update their relevant sections.

WPQ_WRITE_HIT

• Title: Write Pending Queue CAM Match

• Category: WPQ Events

• Event Code: 0x24

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of times a request hits in the WPQ (write-pending queue). The iMC

allows writes and reads to pass up other writes to different addresses. Before a read or a write is
issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit,
they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit
will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will
simply update their relevant sections.

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2.6 Power Control (PCU) Performance Monitoring

2.6.1 Overview of the PCU

The PCU is the primary Power Controller.
The uncore implements a power control unit acting as a core/uncore power and thermal manager. It

runs its firmware on an internal micro-controller and coordinates the socket’s power states.
The PCU algorithmically governs the P-state of the processor, C-state of the core and the package C-

state of the socket. It also enables the core to go to a higher performance state (“turbo mode”) when
the proper set of conditions are met. Conversely, the PCU will throttle the processor to a lower
performance state when a thermal violation occurs.

Through specific events, the OS and the PCU will either promote or demote the C-State of each core
by altering the voltage and frequency. The system power state (S-state) of all the sockets in the
system is managed by the server legacy bridge in coordination with all socket PCUs.

The PCU communicates to all the other units through multiple PMLink interfaces on-die and Message
Channel to access their registers. The OS and BIOS communicates to the PCU thru standardized MSR
registers and ACPI.

The PCU also acts as the interface to external management controllers via PECI and voltage
regulators (NPTM). The DMI interface is the communication path from the southbridge for system
power management.

Note: Many power saving features are tracked as events in their respective units. For

example, Intel® QPI Link Power saving states and Memory CKE statistics are captured
in the Intel® QPI Perfmon and iMC Perfmon respectively.

2.6.2 PCU Performance Monitoring Overview

The uncore PCU supports event monitoring through four 48-bit wide counters
(PCU_MSR_PMON_CTR{3:0}). Each of these counters can be programmed
(PCU_MSR_PMON_CTL{3:0}) to monitor any PCU event. The PCU counters can increment by a
maximum of 4b (?) per cycle.

Two extra 64-bit counters are also provided in the PCU to track C-State Residency. Although
documented in this manual for reference, these counters exist outside of the PMON infrastructure.

For information on how to setup a monitoring session, refer to Section 2.1, “Uncore Per-Socket

Performance Monitoring Control”

.

2.6.3 PCU Performance Monitors

Table 2-73. PCU Performance Monitoring MSRs (Sheet 1 of 2)

MSR Name

Generic Counters

PCU_MSR_PMON_CTR3 0x0C39 64 PCU PMON Counter 3
PCU_MSR_PMON_CTR2 0x0C38 64 PCU PMON Counter 2
PCU_MSR_PMON_CTR1 0x0C37 64 PCU PMON Counter 1

MSR

Address

Size

(bits)

Description

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Table 2-73. PCU Performance Monitoring MSRs ( Sheet 2 of 2)

MSR Name

PCU_MSR_PMON_CTR0 0x0C36 64 PCU PMON Counter 0

Box-Level Filter

PCU_MSR_PMON_BOX_FILTER 0x0C34 32 PCU PMON Filter

Generic Counter Control

PCU_MSR_PMON_CTL3 0x0C33 32 PCU PMON Control for Counter 3
PCU_MSR_PMON_CTL2 0x0C32 32 PCU PMON Control for Counter 2
PCU_MSR_PMON_CTL1 0x0C31 32 PCU PMON Control for Counter 1
PCU_MSR_PMON_CTL0 0x0C30 32 PCU PMON Control for Counter 0

Box-Level Control/Status

PCU_MSR_PMON_BOX_CTL 0x0C24 32 PCU PMON Box-Wide Control

Fixed (Non-PMON) Counters

PCU_MSR_CORE_C6_CTR 0x03FD 64 Fixed C-State Residency Counter
PCU_MSR_CORE_C3_CTR 0x03FC 64 Fixed C-State Residency Counter

MSR

Address

Size

(bits)

Description

2.6.3.1 PCU Box Level PMON State

The following registers represent the state governing all box-level PMUs in the PCU.
In the case of the PCU, the PCU_MSR_PMON_BOX_CTL register governs what happens when a freeze

signal is received (.frz_en). It also provides the ability to manually freeze the counters in the box
(.frz) and reset the generic state (.rst_ctrs and .rst_ctrl).

The PCU provides two extra MSRs that provide additional static performance information to software
but exist outside of the PMON infrastructure (e.g. they can’t be frozen or reset). They are included for
the convenience of software developers need to efficiently access this data.

Table 2-74. PCU_MSR_PMON_BOX_CTL Register – Field Definitions

Field Bits Attr

rsv 31:18 RV 0 Reserved (?)
rsv 17 RV 0 Reserved; SW must write to 0 else behavior is undefined.
frz_en 16 WO 0 Freeze Enable.

rsv 15:9 RV 0 Reserved (?)
frz 8 WO 0 Freeze.

rsv 7:2 RV 0 Reserved (?)
rst_ctrs 1 WO 0 Reset Counters.

rst_ctrl 0 WO 0 Reset Control.

HW

Reset

Val

Description

If set to 1 and a freeze signal is received, the counters will be
stopped or ‘frozen’, else the freeze signal will be ignored.

If set to 1 and the .frz_en is 1, the counters in this box will be
frozen.

When set to 1, the Counter Registers will be reset to 0.

When set to 1, the Counter Control Registers will be reset to 0.

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U

2.6.3.2 PCU PMON state - Counter/Control Pairs

The following table defines the layout of the PCU performance monitor control registers. The main
task of these configuration registers is to select the event to be monitored by their respective data
counter (.ev_sel, .umask). Additional control bits are provided to shape the incoming events (e.g.
.invert, .edge_det, .thresh) as well as provide additional functionality for monitoring software (.rst).

Due to the fact that much of the PCU’s functionality is provided by an embedded microcontroller,
many of the available events are generated by the microcontroller and handed off to the hardware for
capture by the PMON registers. Among the events generated by the microcontroller are occupancy
events allowing a user to measure the number of cores in a given C-state per-cycle. Given this
unique situation, extra control bits are provided to filter the ouput of the these special occupancy
events.

- .occ_invert - Changes the .thresh test condition to ‘<‘ for the occupancy events (when .ev_sel[7] is
set to 1)

- .occ_edge_det - Rather than accumulating the raw count each cycle (for events that can increment
by 1 per cycle), the register can capture transitions from no event to an event incoming for the PCU’ s
occupancy events (when .ev_sel[7] is set to 1).

Table 2-75. PCU_MSR_PMON_CTL{3-0} Register – Field Definitions (Sheet 1 of 2)

Field Bits Attr

occ_edge_det 31 RW-V 0 Enables edge detect for occupancy events (.ev_sel[7] is 1)

occ_invert 30 RW-V 0 Invert comparison against Threshold for the PCU Occupancy

rsv 29 RV 0 Reserved. SW must write to 0 for proper operation.
thresh 28:24 RW-V 0 Threshold used in counter comparison.

HW

Reset

Val

Description

When set to 1, rather than measuring the event in each cycle it
is active, the corresponding counter will incr ement when a 0 to 1
transition (i.e. rising edge) is detected.

When 0, the counter will increment in each cycle that the event
is asserted.

NOTE: .edge_det is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.

events (.ev_sel[7] is 1)

0 - comparison will be ‘is event increment >= threshold?’.
1 - comparison is inverted - ‘is event increment < threshol d?’

NOTE: .invert is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.

Also, if .edge_det is set to 1, the counter will increment when a 1
to 0 transition (i.e. falling edge) is detected.

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Table 2-75. PCU_MSR_PMON_CTL{3-0} Register – Field Definitions (Sheet 2 of 2)

Field Bits Attr

invert 23 RW-V 0 Invert comparison against Threshold.

en 22 RW-V 0 Local Counter Enable.
rsv 21:20 RV 0 Reserved. SW must write to 0 for proper operation.
rsv 19 RV 0 Reserved (?)
edge_det 18 RW-V 0 When set to 1, rather than measuring the event in each cycle it

rst 17 WO 0 When set to 1, the corresponding counter will be cleared to 0.
rsv 16 RV 0 Reserved (?)
occ_sel 15:14 RW-V 0 Select which of three occupancy counters to use.

HW

Reset

Val

Description

0 - comparison will be ‘is event increment >= threshold?’.
1 - comparison is inverted - ‘is event increment < threshold?’

NOTE: .invert is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.

Also, if .edge_det is set to 1, the counter will increment when a 1
to 0 transition (i.e. falling edge) is detected.

is active, the corresponding counter will increment when a 0 to 1
transition (i.e. rising edge) is detected.

When 0, the counter will increment in each cycle that the event
is asserted.

NOTE: .edge_det is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.

01 - Cores in C0
10 - Cores in C3

11 - Cores in C6
rsv 13:8 RV 0 Reserved (?)
ev_sel 7:0 RW-V 0 Select event to be counted.

NOTE: Bit 7 denotes whether the event requires the use of an

occupancy subcounter.

The PCU performance monitor data registers are 48-bit wide. Should a counter overflow (a carry out
from bit 47), the counter will wrap and continue to collect events.

If accessible, software can continuously read the data registers without disabling event collection.

Table 2-76. PCU_MSR_PMON_CTR{3-0} Register – Field Definitions

Field Bits Attr

rsv 63:48 RV 0 Reserved (?)
event_count 47:0 RW-V 0 48-bit performance event counter

HW

Reset

Val

Description

Context sensitive filtering is provided for through the PCU_MSR_PMON_BOX_FILTER register.

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• For frequency/voltage band filters, the multipler is at 100MHz granularity. So, a value of 32
(0x20) would represent a frequency of 3.2GHz.

• Support for limited Frequency/Voltage Band histogramming. Each of the four bands provided for
in the filter may be simultaneous tracked by the corresonding event

Note: Since use of the register as a filter is heavily overloaded, simultaneous application of

this filter to additional events in the same run is severely limited

Table 2-77. PCU_MSR_PMON_BOX_FILTER Register – Field Definitions

Field Bits Attr

rsv 63:48 RV 0 Reserved (?)
filt31_24 31:24 RW-V 0 Band 3 - For Voltage/Frequency Band Event
filt23_16 23:16 RW-V 0 Band 2 - For Voltage/Frequency Band Event
filt15_8 15:8 RW-V 0 Band 1 - For Voltage/Frequency Band Event
filt7_0 7:0 RW-V 0 Band 0 - For Voltage/Frequency Band Event

HW

Reset

Val

Description

2.6.3.3 Intel® PCU Extra Registers - Companions to PMON HW

The PCU includes two extra MSRs that track the number of cycles a core (any core) is in either the C3
or C6 state. As mentioned before, these counters are not part of the PMON infrastructure so they
can’t be frozen or reset with the otherwise controlled by the PCU PMON control registers.

Note: To be clear, these counters track the number of cycles some core is in C3/6 state. It

Table 2-78. PCU_MSR_CORE_C6_CTR Register – Field Definitions

does not track the total number of cores in the C3/6 state in any cycle. F or that, a user
should refer to the regular PCU event list.

Field Bits Attr

event_count 63:0 RW-V 0 64-bit performance event counter

HW

Reset

Val

Description

Table 2-79. PCU_MSR_CORE_C3_CTR Register – Field Definitions

Field Bits Attr

event_count 63:0 RW-V 0 64-bit performance event counter

HW

Reset

Val

Description

2.6.4 PCU Performance Monitoring Events

2.6.4.1 An Overview:

The PCU provides the ability to capture information covering a wide range of the PCU’s functionality
including:

• Number of cores in a given C-state per-cycle

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• Core State Transitions - there are a larger number of events provided to track when cores
transition C-state, when the enter/exit specific C-states, when they receive a C-state demotion,
etc.

• Frequency/Voltage Banding - ability to measure the number of cycles the uncore was operating
within a frequency or voltage ‘band’ that can be specified in a seperate filter register.

Note: Given the nature of many of the PCU events, a great deal of additional information can

be measured by setting the .edge_det bit. By doing so, an event such as “Cycles
Changing Frequency” becomes “Number of Frequency Transitions.

On Occupancy Events:

Because it is not possible to "sync" the PCU occupancy counters by employing tricks such as bus lock
before the events start incrementing, the PCU has provided fixed occupancy counters to track the
major queues.

1. Cores in C0 (4 bits)

2. Cores in C3 (4 bits)

3. Cores in C6 (4 bits)

Some Examples for Unlocking More Advanced Features:

The PCU perfmon implementation/progr amming is more complicated than many of the other units. As
such, it is best to describe how to use them with a couple examples.

• Case 1: Voltage Transtion Cycles (Simple Event)

• Case 2: Cores in C0 (Occupancy Accumulation)

• Case 3: Cycles w/ more than 4 cores in C0 (Occupancy Threshholding)

• Case 4: Transitions into more than 4 cores in C0 (Threshholding + Edge Detect)

• Case 5: Voltage Transition Cycles w/ > 4 Cores in C0

• Case 6: Cycles w/ <4 Cores in C0 and Freq < 2.0GHz

Table 2-80. PCU Configuration Examples

Case

Config 123456

EventSelect 0x03 0x00 0x00 0x00 0x03 0x0B

UseOccupancy 0x0 0x1 0x1 0x1 0x1 0x1

OccSelect 0x00 0x01 0x01 0x01 0 x01 0x01

Threshhold 0x0 0x0 0x5 0x5 0x5 0x4

Invert 0x0 0x0 0x0 0x0 0x0 0x1

Edge Detect 0x0 0x0 0x0 0x0 0x0 0x0

OccInvert 0x0 0x0 0x0 0x0 0x0 0x1

OccEdgeDetect 0x0 0x0 0x0 0x1 0x0 0x0

Filter 0x00 0x00 0x00 0x00 0x00 0x14

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2.6.5 PCU Box Events Ordered By Code

The following table summarizes the directly measured PCU Box events.

Table 2-81. Performance Monitor Events for PCU (Sheet 1 of 2)

Symbol Name

CLOCKTICKS 0x00 0 0-3 1 pclk Cycles
VOLT_TRANS_CYCLES_INCREASE 0x01 0 0-3 1 Cycles Increasing Voltage
VOLT_TRANS_CYCLES_DECREASE 0x02 0 0-3 1 Cycles Decreasing Voltage
VOLT_TRANS_CYCLES_CHANGE 0x03 0 0-3 1 Cycles Changing Voltage
FREQ_MAX_LIMIT_THERMAL_CYCLES0x04 0 0-3 1 Thermal Strongest Upper Limit

FREQ_MAX_POWER_CYCLES 0x05 0 0-3 1 Power Strongest Upper Limit Cycles
FREQ_MAX_OS_CYCLES 0x06 0 0-3 1 OS Strongest Upper Limit Cycles
FREQ_MAX_CURRENT_CYCLES 0x07 0 0-3 1 Current Strongest Upper Limit

PROCHOT_INTERNAL_CYCLES 0x09 0 0-3 1 Internal Prochot
PROCHOT_EXTERNAL_CYCLES 0x0A 0 0-3 1 External Prochot
FREQ_BAND0_CYCLES 0x0B 0 0-3 1 Frequency Residency
FREQ_BAND1_CYCLES 0x0C 0 0-3 1 Frequency Residency
FREQ_BAND2_CYCLES 0x0D 0 0-3 1 Frequency Residency
FREQ_BAND3_CYCLES 0x0E 0 0-3 1 Frequency Residency
DEMOTIONS_CORE0 0x1E 0 0-3 1 Core C State Demotions
DEMOTIONS_CORE1 0x1F 0 0-3 1 Core C State Demotions
DEMOTIONS_CORE2 0x20 0 0-3 1 Core C State Demotions
DEMOTIONS_CORE3 0x21 0 0-3 1 Core C State Demotions
DEMOTIONS_CORE4 0x22 0 0-3 1 Core C State Demotions
DEMOTIONS_CORE5 0x23 0 0-3 1 Core C State Demotions
DEMOTIONS_CORE6 0x24 0 0-3 1 Core C State Demotions
DEMOTIONS_CORE7 0x25 0 0-3 1 Core C State Demotions
MEMORY_PHASE_SHEDDING_CYCLES0x2F 0 0-3 1 Memory Phase Shedding Cycles

Event

Code

Extra

Select

Bit

Ctrs

Max

Inc/

Cyc

Description

Cycles

Cycles

VR_HOT_CYCLES 0x32 0 0-3 1 VR Hot
POWER_STATE_OCCUPANCY 0x80 0 0-3 8 Number of cores in C0
FREQ_TRANS_CYCLES 0x00 1 0-3 1 Cycles spent changing Frequency
FREQ_MIN_IO_P_CYCLES 0x01 1 0-3 1 IO P Limit Strongest Lower Limit

FREQ_MIN_PERF_P_CYCLES 0x02 1 0-3 1 Perf P Limit Strongest Lower Limit

CORE0_TRANSITION_CYCLES 0x03 1 0-3 1 Core C State Transition Cycles
CORE1_TRANSITION_CYCLES 0x04 1 0-3 1 Core C State Transition Cycles
CORE2_TRANSITION_CYCLES 0x05 1 0-3 1 Core C State Transition Cycles
CORE3_TRANSITION_CYCLES 0x06 1 0-3 1 Core C State Transition Cycles
CORE4_TRANSITION_CYCLES 0x07 1 0-3 1 Core C State Transition Cycles
CORE5_TRANSITION_CYCLES 0x08 1 0-3 1 Core C State Transition Cycles
CORE6_TRANSITION_CYCLES 0x09 1 0-3 1 Core C State Transition Cycles

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Table 2-81. Performance Monitor Events for PCU (Sheet 2 of 2)

Symbol Name

CORE7_TRANSITION_CYCLES 0x0A 1 0-3 1 Core C State Transition Cycles
TOTAL_TRANSITION_CYCLES 0x0B 1 0-3 1 Total Core C State Transition Cycles

Event

Code

Extra

Select

Bit

Ctrs

Max

Inc/

Cyc

2.6.6 PCU Box Common Metrics (Derived Events)

The following table summarizes metrics commonly calculated from PCU Box events.

Table 2-82. Metrics Derived from PCU Events

Symbol Name:

Definition

CYC_FREQ_CURRENT_LTD:
Cycles the Max Frequency is limited by
current

CYC_FREQ_OS_LTD:
Cycles the Max Frequency is limited by the
OS

CYC_FREQ_POWER_LTD:
Cycles the Max Frequency is limited by
power

CYC_FREQ_THERMAL_LTD:
Cycles the Max Frequency is limited by
thermal issues

FREQ_MAX_CURRENT_CYCLES / CLOCKTICKS

FREQ_MAX_OS_CYCLES / CLOCKTICKS

FREQ_MAX_POWER_CYCLES / CLOCKTICKS

FREQ_MAX_CURRENT_CYCLES / CLOCKTICKS

Equation

Description

2.6.7 PCU Box Performance Monitor Event List

The section enumerates the performance monitoring events for the PCU Box.

CLOCKTICKS

• Title: pclk Cycles

• Category: PCLK Events

• Event Code: 0x00

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: The PCU runs off a fixed 800 MHz clock. This event counts the number of pclk cycles

measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a
constant rate making it a good measure of actual wall time.

CORE0_TRANSITION_CYCLES

• Title: Core C State Transition Cycles

• Category: CORE_C_STATE_TRANSITION Events

• Event Code: 0x03

• Extra Select Bit: Y

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Number of cycles spent performing core C state transitions. There is one event per

core.

• NOTE: This only tracks the hardware portion in the RCFSM (CFCFSM). This portion is just doing
the core C state transition. It does not include any necessary frequency/voltage transitions.

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CORE1_TRANSITION_CYCLES

• Title: Core C State Transition Cycles

• Category: CORE_C_STATE_TRANSITION Events

• Event Code: 0x04

• Extra Select Bit: Y

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Number of cycles spent performing core C state transitions. There is one event per

core.

CORE2_TRANSITION_CYCLES

• Title: Core C State Transition Cycles

• Category: CORE_C_STATE_TRANSITION Events

• Event Code: 0x05

• Extra Select Bit: Y

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Number of cycles spent performing core C state transitions. There is one event per

core.

CORE3_TRANSITION_CYCLES

• Title: Core C State Transition Cycles

• Category: CORE_C_STATE_TRANSITION Events

• Event Code: 0x06

• Extra Select Bit: Y

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Number of cycles spent performing core C state transitions. There is one event per

core.

CORE4_TRANSITION_CYCLES

• Title: Core C State Transition Cycles

• Category: CORE_C_STATE_TRANSITION Events

• Event Code: 0x07

• Extra Select Bit: Y

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Number of cycles spent performing core C state transitions. There is one event per

core.

CORE5_TRANSITION_CYCLES

• Title: Core C State Transition Cycles

• Category: CORE_C_STATE_TRANSITION Events

• Event Code: 0x08

• Extra Select Bit: Y

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Number of cycles spent performing core C state transitions. There is one event per

core.

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CORE6_TRANSITION_CYCLES

• Title: Core C State Transition Cycles

• Category: CORE_C_STATE_TRANSITION Events

• Event Code: 0x09

• Extra Select Bit: Y

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Number of cycles spent performing core C state transitions. There is one event per

core.

CORE7_TRANSITION_CYCLES

• Title: Core C State Transition Cycles

• Category: CORE_C_STATE_TRANSITION Events

• Event Code: 0x0A

• Extra Select Bit: Y

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Number of cycles spent performing core C state transitions. There is one event per

core.

DEMOTIONS_CORE0

• Title: Core C State Demotions

• Category: CORE_C_STATE_TRANSITION Events

• Event Code: 0x1E

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Filter Dependency: PCUFilter[7:0]

• Definition: Counts the number of times when a configurable cores had a C-state demotion

DEMOTIONS_CORE1

• Title: Core C State Demotions

• Category: CORE_C_STATE_TRANSITION Events

• Event Code: 0x1F

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Filter Dependency: PCUFilter[7:0]

• Definition: Counts the number of times when a configurable cores had a C-state demotion

DEMOTIONS_CORE2

• Title: Core C State Demotions

• Category: CORE_C_STATE_TRANSITION Events

• Event Code: 0x20

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of times when a configurable cores had a C-state demotion

DEMOTIONS_CORE3

• Title: Core C State Demotions

• Category: CORE_C_STATE_TRANSITION Events

• Event Code: 0x21

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Filter Dependency: PCUFilter[7:0]

• Definition: Counts the number of times when a configurable cores had a C-state demotion

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DEMOTIONS_CORE4

• Title: Core C State Demotions

• Category: CORE_C_STATE_TRANSITION Events

• Event Code: 0x22

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Filter Dependency: PCUFilter[7:0]

• Definition: Counts the number of times when a configurable cores had a C-state demotion

DEMOTIONS_CORE5

• Title: Core C State Demotions

• Category: CORE_C_STATE_TRANSITION Events

• Event Code: 0x23

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Filter Dependency: PCUFilter[7:0]

• Definition: Counts the number of times when a configurable cores had a C-state demotion

DEMOTIONS_CORE6

• Title: Core C State Demotions

• Category: CORE_C_STATE_TRANSITION Events

• Event Code: 0x24

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Filter Dependency: PCUFilter[7:0]

• Definition: Counts the number of times when a configurable cores had a C-state demotion

DEMOTIONS_CORE7

• Title: Core C State Demotions

• Category: CORE_C_STATE_TRANSITION Events

• Event Code: 0x25

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Filter Dependency: PCUFilter[7:0]

• Definition: Counts the number of times when a configurable cores had a C-state demotion

FREQ_BAND0_CYCLES

• Title: Frequency Residency

• Category: FREQ_RESIDENCY Events

• Event Code: 0x0B

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Filter Dependency: PCUFilter[7:0]

• Definition: Counts the number of cycles that the uncore was running at a frequency greater than

or equal to the frequency that is configured in the filter. One can use all four counters with this
event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction
with this event to track the number of times that we transitioned into a frequency greater than or
equal to the configurable frequency. One can also use inversion to track cycles when we were less
than the configured frequency.

• NOTE: The PMON control registers in the PCU only update on a frequency transition. Changing
the measuring threshold during a sample interval may introduce errors in the counts. This is espe­cially true when running at a constant frequency for an extended period of time. There is a corner
case here: we set this code on the GV transition. So, if we never GV we will never call this code.
This event does not include transition times. It is handled on fast path.

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FREQ_BAND1_CYCLES

• Title: Frequency Residency

• Category: FREQ_RESIDENCY Events

• Event Code: 0x0C

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Filter Dependency: PCUFilter[15:8]

• Definition: Counts the number of cycles that the uncore was running at a frequency greater than

or equal to the frequency that is configured in the filter. One can use all four counters with this
event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction
with this event to track the number of times that we transitioned into a frequency greater than or
equal to the configurable frequency. One can also use inversion to track cycles when we were less
than the configured frequency.

• NOTE: The PMON control registers in the PCU only update on a frequency transition. Changing
the measuring threshold during a sample interval may introduce errors in the counts. This is espe­cially true when running at a constant frequency for an extended period of time. There is a corner
case here: we set this code on the GV transition. So, if we never GV we will never call this code.
This event does not include transition times. It is handled on fast path.

FREQ_BAND2_CYCLES

• Title: Frequency Residency

• Category: FREQ_RESIDENCY Events

• Event Code: 0x0D

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Filter Dependency: PCUFilter[23:16]

• Definition: Counts the number of cycles that the uncore was running at a frequency greater than

or equal to the frequency that is configured in the filter. One can use all four counters with this
event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction
with this event to track the number of times that we transitioned into a frequency greater than or
equal to the configurable frequency. One can also use inversion to track cycles when we were less
than the configured frequency.

• NOTE: The PMON control registers in the PCU only update on a frequency transition. Changing
the measuring threshold during a sample interval may introduce errors in the counts. This is espe­cially true when running at a constant frequency for an extended period of time. There is a corner
case here: we set this code on the GV transition. So, if we never GV we will never call this code.
This event does not include transition times. It is handled on fast path.

FREQ_BAND3_CYCLES

• Title: Frequency Residency

• Category: FREQ_RESIDENCY Events

• Event Code: 0x0E

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Filter Dependency: PCUFilter[31:24]

• Definition: Counts the number of cycles that the uncore was running at a frequency greater than

or equal to the frequency that is configured in the filter. One can use all four counters with this
event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction
with this event to track the number of times that we transitioned into a frequency greater than or
equal to the configurable frequency. One can also use inversion to track cycles when we were less
than the configured frequency.

• NOTE: The PMON control registers in the PCU only update on a frequency transition. Changing
the measuring threshold during a sample interval may introduce errors in the counts. This is espe­cially true when running at a constant frequency for an extended period of time. There is a corner
case here: we set this code on the GV transition. So, if we never GV we will never call this code.
This event does not include transition times. It is handled on fast path.

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FREQ_MAX_CURRENT_CYCLES

• Title: Current Strongest Upper Limit Cycles

• Category: FREQ_MAX_LIMIT Events

• Event Code: 0x07

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles when current is the upper limit on frequency.

• NOTE: This is fast path, will clear our other limits when it happens. The slow loop portion, which

covers the other limits, can double count EDP. Clearing should fix this up in the next fast path
event, but this will happen. Add up all the cycles and it wontmakesense,butthegeneraldistribution­istrue.'

FREQ_MAX_LIMIT_THERMAL_CYCLES

• Title: Thermal Strongest Upper Limit Cycles

• Category: FREQ_MAX_LIMIT Events

• Event Code: 0x04

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles when thermal conditions are the upper limit on frequency .

This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles
when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled
at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE
looks at the input.

FREQ_MAX_OS_CYCLES

• Title: OS Strongest Upper Limit Cycles

• Category: FREQ_MAX_LIMIT Events

• Event Code: 0x06

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles when the OS is the upper limit on frequency.

• NOTE: Essentially, this event says the OS is getting the frequency it requested.

FREQ_MAX_POWER_CYCLES

• Title: Power Strongest Upper Limit Cycles

• Category: FREQ_MAX_LIMIT Events

• Event Code: 0x05

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles when power is the upper limit on frequency.

FREQ_MIN_IO_P_CYCLES

• Title: IO P Limit Strongest Lower Limit Cycles

• Category: FREQ_MIN_LIMIT Events

• Event Code: 0x01

• Extra Select Bit: Y

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles when IO P Limit is preventing us from dropping the fre-

quency lower. This algorithm monitors the needs to the IO subsystem on both local and remote
sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for
when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.

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FREQ_MIN_PERF_P_CYCLES

• Title: Perf P Limit Strongest Lower Limit Cycles

• Category: FREQ_MIN_LIMIT Events

• Event Code: 0x02

• Extra Select Bit: Y

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles when Perf P Limit is preventing us from dropping the fre-

quency lower. Perf P Limit is an algorithm that takes input from remote sockets when determining
if a socket should drop it's frequency down. This is largely to minimize increases in snoop and
remote read latencies.

FREQ_TRANS_CYCLES

• Title: Cycles spent changing Frequency

• Category: FREQ_TRANS Events

• Event Code: 0x00

• Extra Select Bit: Y

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles when the system is changing frequency. This can not be

filtered by thread ID. One can also use it with the occupancy counter that monitors number of
threads in C0 to estimate the performance impact that frequency transitions had on the system.

MEMORY_PHASE_SHEDDING_CYCLES

• Title: Memory Phase Shedding Cycles

• Category: MEMORY_PHASE_SHEDDING Events

• Event Code: 0x2F

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles that the PCU has triggered memory phase shedding. This

is a mode that can be run in the iMC physicals that saves power at the expense of additional
latency.

• NOTE: Is this the package C one? Yes

POWER_STATE_OCCUPANCY

• Title: Number of cores in C0

• Category: POWER_STATE_OCC Events

• Event Code: 0x80

• Max. Inc/Cyc: 8, Register Restrictions: 0-3

• Definition: This is an occupancy event that tracks the number of cores that are in C0. It can be

used by itself to get the average number of cores in C0, with threshholding to generate histograms,
or with other PCU events and occupancy triggering to capture other details.

Table 2-83. Unit Masks for POWER_STATE_OCCUPANCY

Extension

CORES_C0 b01000000
CORES_C3 b10000000
CORES_C6 b11000000

umask
[15:8]

Description

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PROCHOT_EXTERNAL_CYCLES

• Title: External Prochot

• Category: PROCHOT Events

• Event Code: 0x0A

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles that we are in external PROCHOT mode. This mode is

triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and
must throttle to avoid damaging the chip.

PROCHOT_INTERNAL_CYCLES

• Title: Internal Prochot

• Category: PROCHOT Events

• Event Code: 0x09

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles that we are in Interal PROCHOT mode. This mode is trig-

gered when a sensor on the die determines that we are too hot and must throttle to avoid damaging
the chip.

TOTAL_TRANSITION_CYCLES

• Title: Total Core C State Transition Cycles

• Category: CORE_C_STATE_TRANSITION Events

• Event Code: 0x0B

• Extra Select Bit: Y

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Number of cycles spent performing core C state transitions across all cores.

VOLT_TRANS_CYCLES_CHANGE

• Title: Cycles Changing Voltage

• Category: VOLT_TRANS Events

• Event Code: 0x03

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles when the system is changing voltage. There is no filtering

supported with this event. One can use it as a simple event, or use it conjunction with the occu­pancy events to monitor the number of cores or threads that were impacted by the transition. This
event is calculated by or'ing together the increasing and decreasing events.

VOLT_TRANS_CYCLES_DECREASE

• Title: Cycles Decreasing Voltage

• Category: VOLT_TRANS Events

• Event Code: 0x02

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of cycles when the system is decreasing voltage. There is no filter-

ing supported with this event. One can use it as a simple event, or use it conjunction with the occu­pancy events to monitor the number of cores or threads that were impacted by the transition.

VOLT_TRANS_CYCLES_INCREASE

• Title: Cycles Increasing Voltage

• Category: VOLT_TRANS Events

• Event Code: 0x01

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

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• Definition: Counts the number of cycles when the system is increasing voltage. There is no filter-

ing supported with this event. One can use it as a simple event, or use it conjunction with the occu­pancy events to monitor the number of cores or threads that were impacted by the transition.

VR_HOT_CYCLES

• Title: VR Hot

• Category: VR_HOT Events

• Event Code: 0x32

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition:

2.7 Intel® QPI Link Layer Performance Monitoring

2.7.1 Overview of the Intel® QPI Box

The Intel® QPI Link Layer is responsible for packetizing requests from the caching agent on the way
out to the system interface. As such, it shares responsibility with the CBo(s) as the Intel QPI caching
agent(s). It is responsible for converting CBo requests to Intel QPI messages (i.e. snoop generation
and data response messages from the snoop response) as well as converting/forwarding ring
messages to Intel QPI packets and vice versa.

The Intel® QPI is split into two separate layers. The Intel® QPI LL (link layer) is responsible for
generating, transmitting, and receiving packets with the Intel® QPI link.

R3QPI (Section 2.9, “R3QPI Performance Monitoring”) provides the interface to the Ring for the Link
Layer. It is also the point where VNA/VN0 link credits are acquired.

In each Intel Xeon processor E5-2600, there are two Intel® QPI agents that share a single ring stop.
These links can be connected to a single destination (such as in DP), but also can be connected to two
separate destinations (4s Ring or sDP). Therefore, it will be necessary to count Intel® QPI statistics
for each agent seperately.

The Intel® QPI Link Layer processes two flits per cycle in each direction. In order to accommodate
this, many of the events in the Link Layer can increment by 0, 1, or 2 in each cycle. It is not possible
to monitor Rx (received) and Tx (transmitted) flit information at the same time on the same counter.

2.7.2 Intel® QPI Performance Monitoring Overview

Each Intel® QPI Port in the uncore supports event monitoring through four 48b wide counters
(Q_Py_PCI_PMON_CTR/CTL{3:0}). Each of these four counters can be programmed to count any
Intel® QPI event. The Intel® QPI counters can increment by a maximum of 6b per cycle (???).

Each Intel® QPI Port also includes a mask/match register that allows a user to match packets,
according to various standard packet fields such as message class, opcode, etc, as they leave the
Intel® QPI Port.

For information on how to setup a monitoring session, refer to Section 2.1, “Uncore Per- Sock et

Performance Monitoring Control”

.

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2.7.3 Intel® QPI Performance Monitors

Table 2-84. Intel® QPI Performance Monitoring Registers

Register Name

PCICFG Base Address Dev:Func
QPI Port 0 PMON Registers D8:F2
QPI Port 1 PMON Registers D9:F2

Box-Level Control/Status

Q_Py_PCI_PMON_BOX_CTL F4 32 QPI Port y PMON Box-Wide Control

Generic Counter Control

Q_Py_PCI_PMON_CTL3 E4 32 QPI Port y PMON Control for Counter 3
Q_Py_PCI_PMON_CTL2 E0 32 QPI Port y PMON Control for Counter 2
Q_Py_PCI_PMON_CTL1 DC 32 QPI Port y PMON Control for Counter 1
Q_Py_PCI_PMON_CTL0 D8 32 QPI Port y PMON Control for Counter 0

Generic Counters

Q_Py_PCI_PMON_CTR3 BC+B8 32x2 QPI Port y PMON Counter 3
Q_Py_PCI_PMON_CTR2 B4+B0 32x2 QPI Port y PMON Counter 2
Q_Py_PCI_PMON_CTR1 AC+A8 32x2 QPI Port y PMON Counter 1
Q_Py_PCI_PMON_CTR0 A4+A0 32x2 QPI Port y PMON Counter 0

QPI Mask/Match Port 0 PMON Registers D 8:F6
QPI Mask/Match Port 1 PMON Registers D 9:F6

PCICFG

Address

Size

(bits)

Description

Box-Level Filters

Q_Py_PCI_PMON_PKT_MASK1 23C 32 QPI Port y PMON Packet Filter Mask 1
Q_Py_PCI_PMON_PKT_MASK0 238 32 QPI Port y PMON Packet Filter Mask 0
Q_Py_PCI_PMON_PKT_MATCH1 22C 32 QPI Port y PMON Packet Filter Match 1
Q_Py_PCI_PMON_PKT_MATCH0 228 32 QPI Port y PMON Packet Filter Mask 0

QPI Misc Register Port 0 D8:F0
QPI Misc Register Port 1 D9:F1

Misc (Non-PMON) Counters

QPI_RATE_STATUS 0xD4 32 QPI Rate Status

2.7.3.1 Intel® QPI Box Level PMON State

The following registers represent the state governing all box-level PMUs in each P ort of the Intel® QPI
Box.

In the case of the Intel® QPI Ports, the Q_Py_PCI_PMON_BOX_CTL register governs what happens
when a freeze signal is received (.frz_en). It also provides the ability to manually freeze the counters
in the box (.frz) and reset the generic state (.rst_ctrs and .rst_ctrl).

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Table 2-85. Q_Py_PCI_PMON_BOX_CTL Register – Field Definitions

Field Bits Attr

rsv 31:18 RV 0 Reserved (?)
rsv 17 RV 0 Reserved; SW must write to 0 else behavior is undefined.
frz_en 16 WO 0 Freeze Enable.

rsv 15:9 RV 0 Reserved (?)
frz 8 WO 0 Freeze.

rsv 7:2 RV 0 Reserved (?)
rst_ctrs 1 WO 0 Reset Counters.

rst_ctrl 0 WO 0 Reset Control.

U

HW

Reset

Val

Description

If set to 1 and a freeze signal is received, the counters will be
stopped or ‘frozen’, else the freeze signal will be ignored.

If set to 1 and the .frz_en is 1, the counters in this box will be
frozen.

When set to 1, the Counter Registers will be reset to 0.

When set to 1, the Counter Control Registers will be reset to 0.

2.7.3.2 Intel® QPI PMON state - Counter/Control Pairs

The following table defines the layout of the Intel® QPI performance monitor control registers. The
main task of these configuration registers is to select the event to be monitored by their respective
data counter (.ev_sel, .umask, .ev_sel_ext). Additional control bits are provided to shape the
incoming events (e.g. .invert, .edge_det, .thresh) as well as provide additional functionality for
monitoring software (.rst).

Table 2-86. Q_Py_PCI_PMON_CTL{3-0} Register – Field Definitions (Sheet 1 of 2)

Field Bits Attr

thresh 31:24 RW-V 0 Threshold used in counter comparison.
invert 23 RW-V 0 Invert comparison against Threshold.

en 22 RW-V 0 Local Counter Enable.
ev_sel_ext 21 RW-V 0 Extentsion bit to the Event Select field.
rsv 20 RV 0 Reserved. SW must write to 0 for proper operation.
rsv 19 RV 0 Reserved (?)

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HW

Reset

Val

Description

0 - comparison will be ‘is event increment >= threshold?’.
1 - comparison is inverted - ‘is event increment < threshold?’

NOTE: .invert is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.

Also, if .edge_det is set to 1, the counter will increment when a 1
to 0 transition (i.e. falling edge) is detected.

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-86. Q_Py_PCI_PMON_CTL{3-0} Register – Field Definitions (Sheet 2 of 2)

Field Bits Attr

edge_det 18 RW-V 0 When set to 1, rather than measuring the event in each cycle it

rst 17 WO 0 When set to 1, the corresponding counter will be cleared to 0.
rsv 16 RV 0 Reserved. SW must write to 0 else behavior is undefined.
umask 15:8 RW-V 0 Select subevents to be counted within the selected event.
ev_sel 7:0 RW-V 0 Select event to be counted.

HW

Reset

Val

Description

is active, the corresponding counter will incr ement when a 0 to 1
transition (i.e. rising edge) is detected.

When 0, the counter will increment in each cycle that the event
is asserted.

NOTE: .edge_det is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.

The Intel® QPI performance monitor data registers are 48b wide.Should a counter overflow (a carry
out from bit 47), the counter will wrap and continue to collect events.

If accessible, software can continuously read the data registers without disabling event collection.

Table 2-87. Q_Py_PCI_PMON_CTR{3-0} Register – Field Definitions

Field Bits Attr

rsv 63:48 RV 0 Reserved (?)
event_count 47:0 RW-V 0 48-bit performance event counter

HW

Reset

Val

Description

2.7.3.3 Intel® QPI Registers for Packet Mask/Match Facility

In addition to generic event counting, each port of the Intel® QPI Link Layer provides two pairs of
MAT CH/MASK registers that allow a user to filter packet traffic serviced (crossing from an input port to
an output port) by the Intel® QPI Link Layer. Filtering can be performed according to the packet
Opcode, Message Class, Response, HNID and Physical Address. Program the selected Intel® QPI LL
counter to capture CTO_COUNT in order to capture the filter match as an event.

To use the match/mask facility :
a) Program the match/mask regs (see Table 2-88, “Q_Py_PCI_PMON_PKT_MATCH1 Registers”

through T able 2-91, “Q_Py_PCI_PMON_PKT_MASK0 Registers”).
b) Set the counter’s control register event select to 0x38 (CTO_COUNT) to capture the mask/match

as a performance event.

The following table contains the packet traffic that can be monitored if one of the mask/match
registers was chosen to select the event.

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Table 2-88. Q_Py_PCI_PMON_PKT_MATCH1 Registers

Field Bits

--- 31:20 0x0 Reserved; Must write to 0 else behavior is undefined.
RDS 19:16 0x0 Response Data State (valid when MC == DRS and Opcode == 0x0-

--- 15:4 0x0 Reserved; Must write to 0 else behavior is undefined.
RNID_3_0 3:0 0x0 Remote Node ID(3:0 - Leat Significant Bits)

HW

Reset

Val

2). Bit settings are mutually exclusive.

b1000 - Modified
b0100 - Exclusive
b0010 - Shared
b0001 - Forwarding
b0000 - Invalid (Non-Coherent)

Table 2-89. Q_Py_PCI_PMON_PKT_MATCH0 Registers

Field Bits

RNID_4 31 0x0 Remote Node ID(Bit 4 - Most Significant Bit)

--- 30:18 0x0 Reserved; Must write to 0 else behavior is undefined.
DNID 17:13 0x0 Destination Node ID
MC 12:9 0x0 Message Class

HW

Reset

Val

Description

Description

b0000 HOM - Requests
b0001 HOM - Responses
b0010 NDR
b0011 SNP
b0100 NCS

--­b1100 NCB

--­b1110 DRS

OPC 8:5 0x0 Opcode

DRS,NCB:
[8] Packet Size, 0 == 9 flits, 1 == 11 flits

NCS:
[8] Packet Size, 0 == 1 or 2 flits, 1 == 3 flits

See Section 2.10, “Packet Matching Reference” for a listing of
opcodes that may be filtered per message class.

VNW 4:3 0x0 Virtual Network

b00 - VN0
b01 - VN1
b1x - VNA

--- 2:0 0x0 Reserved; Must write to 0 else behavior is undefined.

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Table 2-90. Q_Py_PCI_PMON_PKT_MASK1 Registers

Field Bits

--- 31:20 0x0 Reserved; Must write to 0 else behavior is undefined.
RDS 19:16 0x0 Response Data State (valid when MC == DRS and Opcode == 0x0-

--- 15:4 0x0 Reserved; Must write to 0 else behavior is undefined.
RNID_3_0 3:0 0x0 Remote Node ID(3:0 - Leat Significant Bits)

HW

Reset

Val

2). Bit settings are mutually exclusive.

b1000 - Modified
b0100 - Exclusive
b0010 - Shared
b0001 - Forwarding
b0000 - Invalid (Non-Coherent)

Table 2-91. Q_Py_PCI_PMON_PKT_MASK0 Registers

Field Bits

RNID_4 31 0x0 Remote Node ID(Bit 4 - Most Significant Bit)

--- 30:18 0x0 Reserved; Must write to 0 else behavior is undefined.
DNID 17:13 0x0 Destination Node ID
MC 12:9 0x0 Message Class
OPC 8:5 0x0 Opcode

HW

Reset

Val

Description

Description

See Section 2.10, “Packet Matching Reference” for a listing of
opcodes that may be filtered per message class.

VNW 4:3 0x0 Virtual Network

--- 2:0 0x0 Reserved; Must write to 0 else behavior is undefined.

2.7.3.3.1 Events Derived from Packet Filters

Following is a selection of common events that may be derived by using the Intel® QPI packet
matching facility . The Match/Mask columns correspond to the Match0/Mask0 registers. For the cases
where additional fields need to be specified, they will be noted.

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Table 2-92. Message Events Derived from the Match/Mask filters (Sheet 1 of 2)

Field

DRS.AnyDataC 0x1C00 0x1F80 Any Data Response message containing a cache line in

DRS.DataC_M 0x1C00

DRS.DataC_E 0x1C00

DRS.DataC_F 0x1C00

DRS.DataC_E_Cmp 0x1C40

DRS.DataC_F_Cmp 0x1C40

DRS.DataC_E_FrcAc
kCnflt

DRS.DataC_F_FrcAc
kCnflt

DRS.WbIData 0x1C80 0x1FE0 Data Response message for Wr ite Back data where cacheline is

DRS.WbSData 0x1CA0 0x1FE0 Data Response message for Write Back data where cacheline is

DRS.WbEData 0x1CC0 0x1FE0 Data R esponse message for Write Back data where cacheline is

DRS.AnyResp 0x1C00 0x1E00 Any Data Response message . A DRS message can be either 9

DRS.AnyResp9flits 0x1C00 0x1F00 Any Data Response message that is 11 flits in length. An 11

DRS.AnyResp11flits 0x1D00 0x1F00 Any Non Data Response completion message. A NDR message

NCB.AnyResp 0x1800 0x1E00 Any Non-Coherent Bypass response message.

Match

[12:0]

&&

Match1

[19:16]

0x8

&&

Match1

[19:16]

0x4

&&

Match1

[19:16]

0x1

&&

Match1

[19:16]

0x4

&&

Match1

[19:16]

0x1

0x1C20

&&

Match1

[19:16]

0x4

0x1C20

&&

Match1

[19:16]

0x1

Mask

[12:0]

0x1FE0

&&

Mask1

[19:16]

0xF

0x1FE0

&&

Mask1

[19:16]

0xF

0x1FE0

&&

Mask1

[19:16]

0xF

0x1FE0

&&

Mask1

[19:16]

0xF

0x1FE0

&&

Mask1

[19:16]

0xF

0x1FE0

&&

Mask1

[19:16]

0xF

0x1FE0

&&

Mask1

[19:16]

0xF

Description

response to a core request. The AnyDataC mes sages are only
sent to an S-Box. The metric DRS.AnyResp - DRS.AnyDataC
will compute the number of DRS writeback and non snoop
write messages.

Data Response message of a cache line in M state that is
response to a core request. The DRS.DataC_M messages are
only sent to Intel® QPI.

Data Response message of a cache line in E state that is
response to a core request. The DRS.DataC_E messages are
only sent to Intel® QPI.

Data Response message of a cache line in F state that is
response to a core request. The DRS.DataC_F messages are
only sent to Intel® QPI.

Complete Data Response message of a cache line in E state
that is response to a core request. The DRS.DataC_E
messages are only sent to Intel® QPI.

Complete Data Response message of a cache line in F state
that is response to a core request. The DRS.DataC_F
messages are only sent to Intel® QPI.

Force Acknowledge Data Response message of a cache line in
E state that is response to a core request. The DRS.DataC_E
messages are only sent to Intel® QPI.

Force Acknowledge Data Response message of a cache line in
F state that is response to a core request. The DRS.DataC_F
messages are only sent to Intel® QPI.

set to the I state.

set to the S state.

set to the E state.

flits for a full cache line or 11 flits for partial data.

flit DRS message contains partial data. Each 8 byte chunk
contains an enable field that specifies if the data is valid.

is 1 on flit.

Reference Number: 327043-001 93

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-92. Message Events Derived from the Match/Mask filters (Sheet 2 of 2)

Field

NCB.AnyMsg9flits 0x1800 0x1F00 Any Non-Coherent Bypass message that is 9 flits in length. A

NCB.AnyMsg11flits 0x1900 0x1F00 Any Non-Coherent Bypass message that is 11 flits in length.

NCB.AnyInt 0x1900 0x1F80 Any Non-Coherent Bypass interrupt message. NCB interrupt

Match

[12:0]

Mask

[12:0]

Description

9 flit NCB message contains a full 64 byte cache line.

An 11 flit NCB message contains either partial data or an
interrupt. For NCB 11 flit data messages, each 8 byte chunk
contains an enable field that specifies if the data is valid.

messages are 11 flits in length.

2.7.3.4 Intel® QPI Extra Registers - Companions to PMON HW

The uncore’s Intel® QPI box includes an extra MSR that provides the current Intel® QPI transfer r ate.

Table 2-93. QPI_RATE_STATUS Register – Field Definitions

Field Bits Attr

rsv 31:5 RV 0 Reserved. SW must write to 0 for proper operation.
slow_mode 4 RO-V 0 Slow Mode

rsv 3 RV 0 Reserved. SW must write to 0 for proper operation.
qpi_rate 2:0 RO-V 11b QPI Rate

HW

Reset

Val

Description

Reflects the current slow mode status being driven to the PLL
This will be set out of reset to bring Intel® QPI in slow mode.

And is only expected to be set when QPI_rate is set to 6.4 GT/s.

This reflects the current QPI rte setting into the PLL
010 - 5.6 GT/s
011 - 6.4 GT/s
100 - 7.2 GT/s
101 - 8 GT/s
110 - 8.8 GT/s
111 - 9.6 GT/s
other - Reserved

2.7.4 Intel® QPI LL Performance Monitoring Events

2.7.4.1 An Overview

The Intel® QPI Link Layer provides events to gather information on topics such as:

• Tracking incoming (ring bound)/outgoing (system bound) transactions,

• Various queue that track those transactions,

• The Link Layer’s power consumption as expressed by the time spent in the Link power states L0p
(half of lanes are disabled).

• A variety of static events such as Direct2Core statistics and when output credit is unavailable.

• Of particular interest, total link utilization may be calculated by capturing and subtracting
transmitted/received idle flits from Intel® QPI clocks.

Many of these events can be further broken down by message class, including link utilization.
Note: In order to measure several of the available events in the Intel® QPI Link Layer, an

extra bit (b16) must be set. These cases will be documented in the full Event List.

94 Reference Number: 327043-001

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

2.7.4.2 Acronyms frequently used in Intel® QPI Events:

RxL (aka IGR) - “Receive from Link” referring to Ingress (requests from the Ring) queues.
TxL (aka EGR) - “Transmit to Link” referring to Egress (requests headed for the Ring) queues.

2.7.5 Intel® QPI LL Box Events Ordered By Code

The following table summarizes the directly measured Intel QPI LL Box events.

Table 2-94. Performance Monitor Events for Intel® QPI LL (Sheet 1 of 2)

Symbol Name

TxL_FLITS_G0 0x00 0 0-3 2 Flits Transferred - Group 0
RxL_FLITS_G0 0x01 0 0-3 2 Flits Received - Group 0
TxL_INSERTS 0x04 0 0-3 1 Tx Flit Buffer Allocations
TxL_BYPASSED 0x05 0 0-3 1 Tx Flit Buffer Bypassed
TxL_CYCLES_NE 0x06 0 0-3 1 Tx Flit Buffer Cycles not Empty
TxL_OCCUPANCY 0x07 0 0-3 1 Tx Flit Buffer Occupancy
RxL_INSERTS 0x08 0 0-3 1 Rx Flit Buffer Allocations
RxL_BYPASSED 0x09 0 0-3 1 Rx Flit Buffer Bypassed
RxL_CYCLES_NE 0x0A 0 0-3 1 RxQ Cycles Not Empty
RxL_OCCUPANCY 0x0B 0 0-3 128 RxQ Occupancy - All Packets
TxL0_POWER_CYCLES 0x0C 0 0-3 1 Cycles in L0
TxL0P_POWER_CYCLES 0x0D 0 0-3 1 Cycles in L0p
RxL0_POWER_CYCLES 0x0F 0 0-3 1 Cycles in L0
RxL0P_POWER_CYCLES 0x10 0 0-3 1 Cycles in L0p
L1_POWER_CYCLES 0x12 0 0-3 1 Cycles in L1
DIRECT2CORE 0x13 0 0-3 1 Direct 2 Core Spawning
CLOCKTICKS 0x14 0 0-3 1 Number of qfclks
TxL_FLITS_G1 0x00 1 0-3 2 Flits Transferred - Group 1
TxL_FLITS_G2 0x01 1 0-3 2 Flits Transferred - Group 2
RxL_FLITS_G1 0x02 1 0-3 2 Flits Received - Group 1
RxL_FLITS_G2 0x03 1 0-3 2 Flits Received - Group 2
RxL_INSERTS_DRS 0x09 1 0-3 1 Rx Flit Buffer Allocations - DRS
RxL_INSERTS_NCB 0x0A 1 0-3 1 Rx Flit Buffer Allocations - NCB
RxL_INSERTS_NCS 0x0B 1 0-3 1 Rx Flit Buffer Allocations - NCS
RxL_INSERTS_HOM 0x0C 1 0-3 1 Rx Flit Buffer Allocations - HOM
RxL_INSERTS_SNP 0x0D 1 0-3 1 Rx Flit Buffer Allocations - SNP
RxL_INSERTS_NDR 0x0E 1 0-3 1 Rx Flit Buffer Allocations - NDR
RxL_OCCUPANCY_DRS 0x15 1 0-3 128 RxQ Occupancy - DRS
RxL_OCCUPANCY_NCB 0x16 1 0-3 128 RxQ Occupancy - NCB
RxL_OCCUPANCY_NCS 0x17 1 0-3 128 RxQ Occupancy - NCS
RxL_OCCUPANCY_HOM 0x18 1 0-3 128 RxQ Occupancy - HOM
RxL_OCCUPANCY_SNP 0x19 1 0-3 128 RxQ Occupancy - SNP
RxL_OCCUPANCY_NDR 0x1A 1 0-3 128 RxQ Occupancy - NDR

Event

Code

Extra

Select

Bit

Ctrs

Max

Inc/

Cyc

Description

Reference Number: 327043-001 95

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-94. Performance Monitor Events for Intel® QPI LL (Sheet 2 of 2)

Symbol Name

VNA_CREDIT_RETURN_OCCUPANCY 0x1B 1 0-3 128 VNA Credits Pending Return -

VNA_CREDIT_RETURNS 0x1C 1 0-3 1 VNA Credits Returned
RxL_CREDITS_CONSUMED_VNA 0x1D 1 0-3 1 VNA Credit Consumed
RxL_CREDITS_CONSUMED_VN0 0x1E 1 0-3 1 VN0 Credit Consumed
CTO_COUNT 0 x38 1 0-3 2 Count of CTO Events

Event

Code

Extra

Select

Bit

Ctrs

Max

Inc/

Cyc

Description

Occupancy

2.7.6 Intel QPI LL Box Common Metrics (Derived Events)

The following table summarizes metrics commonly calculated from Intel QPI LL Box events.

Table 2-95. Metrics Derived from Intel QPI LL Events (Sheet 1 of 3)

Symbol Name:

Definition

DATA_FROM_QPI:
Data received from QPI in bytes ( = DRS +
NCB Data messages received from QPI)

DATA_FROM_QPI_TO_HA_OR_IIO:
Data received from QPI forwarded to HA or
IIO. Expressed in Bytes

DATA_FROM_QPI_TO_LLC:
Data received from QPI forwarded to LLC.
Expressed in Bytes

DATA_FROM_QPI_TO_NODEx:
Data packets received from QPI sent to
Node ID 'x'. Expressed in bytes

DRS_DATA_MSGS_FROM_QPI:
DRS Data Messges From QPI in bytes

DRS_DataC_FROM_QPI_TO_NODEx:
DRS DataC packets received from QPI sent
to Node ID 'x'. Expressed in bytes

DRS_FULL_CACHELINE_MSGS_FROM_QPI:
DRS Full Cacheline Data Messges From QPI
in bytes

DRS_DATA_MSGS_FROM_QPI + NCB_DATA_MSGS_FROM_QPI

DATA_FROM_QPI - DATA_FROM_QPI_TO_LLC

DIRECT2CORE.SUCCESS * 64

DRS_DataC_FROM_QPI_TO_NODEx +
DRS_WRITE_FROM_QPI_TO_NODEx +
NCB_DATA_FROM_QPI_TO_NODEx

(RxL_FLITS_G1.DRS_DATA * 8)

(CTO_COUNT
with:{Q_Py_PCI_PMON_PKT_MATCH0{[12:0],dnid}={0x1C00,
x} Q_Py_PCI_PMON_PKT_MASK0[17:0]=0x3FF80) * 64

(CTO_COUNT
with:{Q_Py_PCI_PMON_PKT_MATCH0[12:0]=0x1C00,Q_Py_PC
I_PMON_PKT_MASK0[12:0]=0x1F00}) * 64)

Equation

96 Reference Number: 327043-001

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-95. Metrics Derived from Intel QPI LL Events (Sheet 2 of 3)

Symbol Name:

Definition

DRS_F_OR_E_FROM_QPI:
DRS response in F or E states received from
QPI in bytes. To calculate the total data
response for each cache line state, it's
necessary to add the contribution from three
flavors {DataC, DataC_FrcAckCnflt,
DataC_Cmp} of data response packets for
each cache line st ate.

DRS_M_FROM_QPI:
DRS response in M state received from QPI
in bytes

DRS_PTL_CACHELINE_MSGS_FROM_QPI:
DRS Partial Cacheline Data Messges From
QPI in bytes

DRS_WB_FROM_QPI:
DRS writeback packets received from QPI in
bytes. This is the sum of Wb{I,S,E} DRS
packets

DRS_WRITE_FROM_QPI_TO_NODEx:
DRS Data packets (Any - DataC) received
from QPI sent to Node ID 'x'. Expressed in
bytes

DRS_WbE_FROM_QPI:
DRS writeback 'change to E state' packets
received from QPI in bytes

DRS_WbI_FROM_QPI:
DRS writeback 'change to I state' packets
received from QPI in bytes

DRS_WbS_FROM_QPI:
DRS writeback 'change to S state' packets
received from QPI in bytes

NCB_DATA_FROM_QPI_TO_NODEx:
NCB Data packets (Any - Interrupts)
received from QPI sent to Node ID 'x'.
Expressed in bytes

NCB_DATA_MSGS_FROM_QPI:
NCB Data Messages From QPI in bytes

PCT_LINK_CRC_RETRY_CYCLES:
Percent of Cycles the QPI link layer is in
retry mode due to CRC errors

Equation

((CTO_COUNT
with:{Q_Py_PCI_PMON_PKT_MATCH0[12:0]=0x1C00,
Q_Py_PCI_PMON_PKT_MASK0[12:0]=0x1FE0,
Q_Py_PCI_PMON_PKT_MATCH1[19:16]=0x4,
Q_Py_PCI_PMON_PKT_MASK0[19:16]=0xF }) + (CTO_COUNT
with:{Q_Py_PCI_PMON_PKT_MATCH0[12:0]=0x1C00,
Q_Py_PCI_PMON_PKT_MASK0[12:0]=0x1FE0,
Q_Py_PCI_PMON_PKT_MATCH1[19:16]=0x1,
Q_Py_PCI_PMON_PKT_MASK0[19:16]=0xF }) + (CTO_COUNT
with:{Q_Py_PCI_PMON_PKT_MATCH0[12:0]=0x1C40,
Q_Py_PCI_PMON_PKT_MASK0[12:0]=0x1FE0,
Q_Py_PCI_PMON_PKT_MATCH1[19:16]=0x4,
Q_Py_PCI_PMON_PKT_MASK0[19:16]=0xF }) + (CTO_COUNT
with:{Q_Py_PCI_PMON_PKT_MATCH0[12:0]=0x1C40,
Q_Py_PCI_PMON_PKT_MASK0[12:0]=0x1FE0,
Q_Py_PCI_PMON_PKT_MATCH1[19:16]=0x1,
Q_Py_PCI_PMON_PKT_MASK0[19:16]=0xF }) + (CTO_COUNT
with:{Q_Py_PCI_PMON_PKT_MATCH0[12:0]=0x1C20,
Q_Py_PCI_PMON_PKT_MASK0[12:0]=0x1FE0,
Q_Py_PCI_PMON_PKT_MATCH1[19:16]=0x4,
Q_Py_PCI_PMON_PKT_MASK0[19:16]=0xF }) + (CTO_COUNT
with:{Q_Py_PCI_PMON_PKT_MATCH0[12:0]=0x1C20,
Q_Py_PCI_PMON_PKT_MASK0[12:0]=0x1FE0,
Q_Py_PCI_PMON_PKT_MATCH1[19:16]=0x1,
Q_Py_PCI_PMON_PKT_MASK0[19:16]=0xF })) * 64

(CTO_COUNT
with:{Q_Py_PCI_PMON_PKT_MATCH0[12:0]=0x1C00,
Q_Py_PCI_PMON_PKT_MASK0[12:0]=0x1FE0,
Q_Py_PCI_PMON_PKT_MATCH1[19:16]=0x8,
Q_Py_PCI_PMON_PKT_MASK0[19:16]=0xF }) * 64

(CTO_COUNT
with:{Q_Py_PCI_PMON_PKT_MATCH0[12:0]=0x1D00,
Q_Py_PCI_PMON_PKT_MASK0[12:0]=0x1F00}) * 64

DRS_WbI_FROM_QPI + DRS_WbS_FROM_QP I +
DRS_WbE_FROM_QPI

((CTO_COUNT
with:{Q_Py_PCI_PMON_PKT_MATCH0{[12:0],dnid}={0x1C00,
x} Q_Py_PCI_PMON_PKT_MASK0[17:0]=0x3FE00) ­(CTO_COUNT
with:{Q_Py_PCI_PMON_PKT_MATCH0{[12:0],dnid}={0x1C00,
x} Q_Py_PCI_PMON_PKT_MASK0[17:0]=0x3FF80)) * 64

(CTO_COUNT
with:{Q_Py_PCI_PMON_PKT_MATCH0[12:0]=0x1CC0,
Q_Py_PCI_PMON_PKT_MASK0[12:0]=0x1FE0) * 64

(CTO_COUNT
with:{Q_Py_PCI_PMON_PKT_MATCH0[12:0]=0x1C80,
Q_Py_PCI_PMON_PKT_MASK0[12:0]=0x1FE0) * 64

(CTO_COUNT
with:{Q_Py_PCI_PMON_PKT_MATCH0[12:0]=0x1CA0,
Q_Py_PCI_PMON_PKT_MASK0[12:0]=0x1FE0) * 64

((CTO_COUNT
with:{Q_Py_PCI_PMON_PKT_MATCH0{[12:0],dnid}={0x1800,
x} Q_Py_PCI_PMON_PKT_MASK0[17:0]=0x3FE00) ­(CTO_COUNT
with:{Q_Py_PCI_PMON_PKT_MATCH0{[12:0],dnid}={0x1900,
x} Q_Py_PCI_PMON_PKT_MASK0[17:0]=0x3FF80)) * 64

(RxL_FLITS_G2.NCB_DATA * 8)

RxL_CRC_CYCLES_IN_LLR / CLOCKTICKS

Reference Number: 327043-001 97

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-95. Metrics Derived from Intel QPI LL Events (Sheet 3 of 3)

Symbol Name:

Definition

PCT_LINK_FULL_POWER_CYCLES:
Percent of Cycles the QPI link is at Full
Power

PCT_LINK_HALF_DISABLED_CYCLES:
Percent of Cycles the QPI link in power
mode where half of the lanes are disabled.

PCT_LINK_SHUTDOWN_CYCLES:
Percent of Cycles the QPI link is Shutdown

QPI_LINK_UTIL:
Percentage of cycles that QPI Link was
utilized. Calculated from 1 - Number of idle
flits - time the link was 'off'

QPI_SPEED:
QPI Speed - In GT/s (GigaTransfers /
Second) - Max QPI Bandwidth is 2 * ROUND
( QPI Speed , 0)

RxL0_POWER_CYCLES / CLOCKTICKS

RxL0p_POWER_CYCLES / CLOCKTICKS

L1_POWER_CYCLES / CLOCKTICKS

(RxL_FLITS_G0.DATA + RxL_FLITS_G0.NON_DATA) / (2 *
CLOCKTICKS)

ROUND ((CLOCKTICKS / (CLOCKTICKS * QPI_VALUES)) *
TSC_SPEED, 0 ) * ( 8 / 1000)

Equation

2.7.7 Intel® QPI LL Box Performance Monitor Event List

The section enumerates the performance monitoring events for the Intel® QPI LL Box.

CLOCKTICKS

• Title: Number of qfclks

• Category: CFCLK Events

• Event Code: 0x14

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of clocks in the Intel® QPI LL. This clock runs at 1/8th the "GT/s"

speed of the Intel® QPI link. For example, a 8GT/s link will have qfclk or 1GHz. JKT does not sup­port dynamic link speeds, so this frequency is fixed.

CTO_COUNT

• Title: Count of CTO Events

• Category: CTO Events

• Event Code: 0x38

• Extra Select Bit: Y

• Max. Inc/Cyc: 2, Register Restrictions: 0-3

• Definition: Counts the number of CTO (cluster trigger outs) events that were asserted across the

two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge
detect to count the number of cases when both events triggered.

DIRECT2CORE

• Title: Direct 2 Core Spawning

• Category: DIRECT2CORE Events

• Event Code: 0x13

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of DRS packets that we attempted to do direct2core on. There are

4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the
different failure cases. Note that this does not count packets that are not candidates for
Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.

98 Reference Number: 327043-001

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

Table 2-96. Unit Masks for DIRECT2CORE

Extension

SUCCESS bxxxxxxx1 Spawn Success:

FAILURE_CREDITS bxxxxxx1x Spawn Failure - Egress Credits:

FAILURE_RBT bxxxxx1xx Spawn Failure - RBT Not Set:

FAILURE_CREDITS_RBT bxxxx1xxx Spawn Failure - Egress and RBT:

umask
[15:8]

Description

The spawn was successful. There were sufficient credits, and the
message was marked to spawn direct2core.

The spawn failed because there were not enough Egress credits. Had
there been enough credits, the spawn would have work ed as the RB T
bit was set.

The spawn failed because the route-back table (RBT) specified that
the transaction should not trigger a direct2core tranaction. This is
common for IO transactions. There were enough Egress credits.

The spawn failed because there were not enough E gress cre dit s AND
the RBT bit was not set.

L1_POWER_CYCLES

• Title: Cycles in L1

• Category: POWER Events

• Event Code: 0x12

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Number of Intel® QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally

shuts down a Intel® QPI link. Use edge detect to count the number of instances when the Intel®
QPI link entered L1. Link power states are per link and per direction, so for example the Tx direc­tion could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a
good amount of time to exit this mode.

RxL0P_POWER_CYCLES

• Title: Cycles in L0p

• Category: POWER_RX Events

• Event Code: 0x10

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Number of Intel® QPI qfclk cycles spent in L0p power mode. L0p is a mode where we

disable 1/2 of the Intel® QPI lanes, decreasing our bandwidth in order to save power. It increases
snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful
in NUMA optimized workloads that largely only utilize Intel® QPI for snoops and their responses.
Use edge detect to count the number of instances when the Intel® QPI link entered L0p. Link
power states are per link and per direction, so for example the Tx direction could be in one state
while Rx was in another.

• NOTE: Using .edge_det to count transitions does not function if L1_POWER_CYCLES

RxL0_POWER_CYCLES

• Title: Cycles in L0

• Category: POWER_RX Events

• Event Code: 0x0F

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Number of Intel® QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the

default mode which provides the highest performance with the most power. Use edge detect to
count the number of instances that the link entered L0. Link power states are per link and per
direction, so for example the Tx direction could be in one state while Rx was in another. The phy
layer sometimes leaves L0 for training, which will not be captured by this event.

Reference Number: 327043-001 99

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring

RxL_BYPASSED

• Title: Rx Flit Buffer Bypassed

• Category: RXQ Events

• Event Code: 0x09

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of times that an incoming flit was able to bypass the flit buffer and

pass directly across the BGF and into the Egress. This is a latency optimization, and should gener­ally be the common case. If this value is less than the number of flits transfered, it implies that
there was queueing getting onto the ring, and thus the transactions saw higher latency.

RxL_CREDITS_CONSUMED_VN0

• Title: VN0 Credit Consumed

• Category: RX_CREDITS_CONSUMED Events

• Event Code: 0x1E

• Extra Select Bit: Y

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses

a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that
were bypasssed.

Table 2-97. Unit Masks for RxL_CREDITS_CONSUMED_VN0

Extension

DRS bxxxxxxx1 DRS:

NCB bxxxxxx1x NCB:

NCS bxxxxx1xx NCS:

HOM bxxxx1xxx HOM:

SNP bxxx1xxxx SNP:

NDR bxx1xxxxx NDR:

umask
[15:8]

VN0 credit for the DRS message class.

VN0 credit for the NCB message class.

VN0 credit for the NCS message class.

VN0 credit for the HOM message class.

VN0 credit for the SNP message class.

VN0 credit for the NDR message class.

Description

RxL_CREDITS_CONSUMED_VNA

• Title: VNA Credit Consumed

• Category: RX_CREDITS_CONSUMED Events

• Event Code: 0x1D

• Extra Select Bit: Y

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

• Definition: Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses

a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that
were bypasssed.

RxL_CYCLES_NE

• Title: RxQ Cycles Not Empty

• Category: RXQ Events

• Event Code: 0x0A

• Max. Inc/Cyc: 1, Register Restrictions: 0-3

100 Reference Number: 327043-001