Intel X38ML - Server Board Motherboard Technical Manual
Intel® Server Board X38ML
Technical Product Specification
Intel order number E15331-006
Revision 1.3
June 2010
Enterprise Platforms and Services Division – Marketing
Revision History Intel® Server Board X38ML
Revision History
Date Revision Number
September 2007 1.0 Initial release.
May 2008 1.1 iBMC fix to Integrated the BMC and fix the FAN sensors.
April 2009 1.2 Corrected the heading typo at the top of some even numbered page.
June 2010 1.3 Updated China CCC/CNCA related information.
Modifications
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Intel® Server Board X38ML Disclaimers
Disclaimers
Information in this document is provided in connection with Intel® products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's
Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any
express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property
right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make
changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or
"undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them.
The Intel® Server Board X38ML may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. Current characterized errata are available on request.
Intel Corporation server baseboards support peripheral components and contain a number of high-density VLSI and
power delivery components that need adequate airflow to cool. Intel’s own chassis are designed and tested to meet
the intended thermal requirements of these components when the fully integrated system is used together. It is the
responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor
datasheets and operating parameters to determine the amount of air flow required for their specific application and
environmental conditions. Intel Corporation can not be held responsible if components fail or the server board does
not operate correctly when used outside any of their published operating or non-operating limits.
Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation.
*Other brands and names may be claimed as the property of others.
Copyright © Intel Corporation 2010. All rights reserved.
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Table of Contents Intel® Server Board X38ML
Table of Contents
1. Introduction ..........................................................................................................................1
1.1 Server Board Use Disclaimer .................................................................................. 1
2. Server Board Overview........................................................................................................2
2.1 Server Board Feature Set........................................................................................ 2
2.2 Server Board Layout................................................................................................ 4
3. Functional Architecture.......................................................................................................7
3.1 Processor Subsystem..............................................................................................8
3.2 Intel® X38 Chipset.................................................................................................... 8
3.2.1 Memory Controller Hub (MCH): Intel® X38 MCH ..................................................... 9
3.2.2 I/O Controller Hub: Intel® ICH9-R ............................................................................9
3.3 Integrated Baseboard Management Controller...................................................... 12
3.3.1 Functionality Overview........................................................................................... 12
3.3.2 Block Diagram ....................................................................................................... 14
3.4 Memory Subsystem ............................................................................................... 15
3.4.1 Memory Support ....................................................................................................15
3.4.2 Memory Population Rules......................................................................................15
3.5 I/O Subsystem ....................................................................................................... 16
3.5.1 PCI Express* x16 Riser Slot .................................................................................. 16
3.5.2 SATA Support........................................................................................................ 16
3.5.3 Video Support ........................................................................................................ 17
3.5.4 Network Interface Controller (NIC) ........................................................................ 17
3.5.5 USB Support.......................................................................................................... 17
3.5.6 Super I/O Chip .......................................................................................................18
3.6 Replacing the Back-Up Battery.............................................................................. 19
4. System BIOS.......................................................................................................................21
4.1 BIOS Identification String....................................................................................... 21
4.2 Logo/Diagnostic Screen......................................................................................... 21
4.3 BIOS Setup Utility .................................................................................................. 22
4.3.1 Operation ............................................................................................................... 22
4.3.2 BIOS Setup Screens.............................................................................................. 25
4.4 Loading BIOS Defaults .......................................................................................... 50
4.5 Multiple Boot Blocks ..............................................................................................50
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4.6 Recovery Mode...................................................................................................... 51
4.7 OEM Logo.............................................................................................................. 51
5. Platform Management........................................................................................................53
5.1 Platform Management Features ............................................................................ 53
5.1.1 IPMI 2.0 Features ..................................................................................................53
5.1.2 Non-IPMI Features ................................................................................................ 54
5.2 Power System........................................................................................................ 54
5.2.1 Power Supply Interface Signals............................................................................. 55
5.2.2 Power-Good Dropout............................................................................................. 55
5.2.3 Power-up Sequence ..............................................................................................56
5.2.4 Power Down Sequence .........................................................................................56
5.2.5 Power Control Sources.......................................................................................... 56
5.2.6 Power State Retention........................................................................................... 57
5.2.7 Power State Restoration........................................................................................ 57
5.2.8 Wake-On-LAN (WOL) ............................................................................................ 58
5.3 Advanced Configuration and Power Interface (ACPI) ........................................... 58
5.3.1 ACPI Power Control...............................................................................................58
5.3.2 ACPI State Synchronization .................................................................................. 59
5.4 System Reset Control............................................................................................ 59
5.4.1 Reset Signal Output............................................................................................... 59
5.4.2 Reset Control Sources........................................................................................... 59
5.4.3 Front Panel System Reset..................................................................................... 59
5.4.4 Soft Reset and Hard Reset.................................................................................... 59
5.4.5 BMC Command Used to Reset System................................................................. 60
5.4.6 Watchdog Timer Expiration ................................................................................... 60
5.5 BMC Reset Control................................................................................................ 60
5.5.1 BMC Exits Firmware Update.................................................................................. 60
5.5.2 Standby Power Comes Up .................................................................................... 60
5.6 System Initialization ............................................................................................... 60
5.6.1 Processor TControl Setting.................................................................................... 60
5.6.2 Fault Resilient Booting (FRB) ................................................................................60
5.6.3 BSP Identification .................................................................................................. 61
5.6.4 Boot Control Support .............................................................................................61
5.6.5 Post Code Display ................................................................................................. 61
5.7 Integrated Front Panel User Interface ...................................................................62
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5.7.1 Power LED............................................................................................................. 62
5.7.2 System Status LED................................................................................................ 62
5.7.3 Front Panel/Chassis Inputs.................................................................................... 63
5.7.4 Front Panel Lock-out Operation............................................................................. 63
5.8 Private Management I2C Buses.............................................................................64
5.9 Watchdog Timer ....................................................................................................64
5.10 BMC Internal Timestamp Clock ............................................................................. 64
5.10.1 BMC Clock Initialization ......................................................................................... 64
5.10.2 System Clock Synchronization .............................................................................. 64
5.11 System Event Log (SEL) ....................................................................................... 65
5.11.1 Servicing Events .................................................................................................... 65
5.11.2 SEL Entry Deletion ................................................................................................65
5.11.3 SEL Erasure ..........................................................................................................65
5.12 Sensor Data Record (SDR) Repository ................................................................. 65
5.12.1 SDR Repository Erasure ....................................................................................... 65
5.12.2 Initialization Agent.................................................................................................. 66
5.13 Field Replaceable Unit (FRU) Inventory Device .................................................... 66
5.13.1 BMC FRU Inventory Area Format..........................................................................66
5.14 Sensor Rearm Behavior ........................................................................................ 67
5.15 Processor Sensors ................................................................................................68
5.15.1 Processor Status Sensors ..................................................................................... 68
5.15.2 Digital Thermal Sensor .......................................................................................... 69
5.16 Standard Fan Management ................................................................................... 69
5.16.1 Fan Domains .........................................................................................................70
5.16.2 Nominal Fan Speed ............................................................................................... 70
5.16.3 Thermal and Acoustic Management ...................................................................... 71
5.17 Power Unit Management ....................................................................................... 71
5.17.1 Power Off............................................................................................................... 71
5.17.2 AC Lost .................................................................................................................. 71
5.17.3 Soft Power Control Fault........................................................................................ 71
5.18 BMC Self Test........................................................................................................ 72
5.19 Messaging Interfaces............................................................................................. 72
5.19.1 Channel Management ...........................................................................................72
5.19.2 User Model ............................................................................................................73
5.19.3 Sessions ................................................................................................................ 73
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5.19.4 Media Bridging.......................................................................................................73
5.19.5 Request/Response Protocol .................................................................................. 73
5.19.6 Host to BMC Communication Interface ................................................................. 73
5.19.7 IPMB Communication Interface ............................................................................. 75
5.19.8 LAN Interface.........................................................................................................75
5.20 Event Filtering and Alerting.................................................................................... 76
5.20.1 Platform Event Filtering (PEF) ............................................................................... 76
5.20.2 Alert-over-LAN ....................................................................................................... 76
5.20.3 Factory Default Event Filters .................................................................................77
5.20.4 Alert Policies .......................................................................................................... 77
5.20.5 MIB File.................................................................................................................. 77
5.21 Sensor Support......................................................................................................77
5.22 BIOS-BMC interactions.......................................................................................... 83
5.23 Platform Management Features Implemented by BIOS ........................................ 83
5.23.1 IPMI .......................................................................................................................84
5.23.2 Console Redirection ..............................................................................................84
5.23.3 IPMI Serial Interface .............................................................................................. 85
5.23.4 Wired For Management (WFM) ............................................................................. 88
5.23.5 System Management BIOS (SMBIOS) .................................................................. 88
5.23.6 Security..................................................................................................................88
6. Error Reporting and Handling...........................................................................................90
6.1 Fault Resilient Booting...........................................................................................90
6.1.1 BSP POST Failures (FRB-2) .................................................................................90
6.1.2 Operating System Load Failures (OS Boot Timer) ................................................ 90
6.2 Error Handling and Logging...................................................................................91
6.2.1 Error Sources and Types....................................................................................... 91
6.2.2 Error Logging via SMI Handler .............................................................................. 91
6.2.3 Logging Format Conventions................................................................................. 92
6.2.4 Timestamp Clock Event......................................................................................... 96
6.3 Error Messages and Error Codes .......................................................................... 97
6.3.1 Diagnostic LEDs .................................................................................................... 97
6.3.2 POST Code Checkpoints....................................................................................... 98
6.3.3 POST Error Messages and Handling .................................................................. 101
6.3.4 POST Error Pause Option ...................................................................................103
7. Connectors and Jumper Blocks .....................................................................................104
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7.1 Power Connectors ............................................................................................... 104
7.1.1 Main Power Connector ........................................................................................104
7.2 PCI Express* x16 Connector ............................................................................... 104
7.3 SMBus Connector................................................................................................ 106
7.4 Front Panel Connector......................................................................................... 106
7.5 I/O Connectors..................................................................................................... 107
7.5.1 VGA Connector.................................................................................................... 107
7.5.2 NIC Connectors ...................................................................................................107
7.5.3 SATA Connectors ................................................................................................108
7.5.4 Serial Port Connectors......................................................................................... 108
7.5.5 USB Connector.................................................................................................... 109
7.5.6 Back Panel I/O Connectors ................................................................................. 110
7.6 Fan Headers ........................................................................................................ 110
7.7 Chassis Intrusion Header ....................................................................................110
7.8 Jumper Blocks ..................................................................................................... 111
8. Design and Environmental Specifications.....................................................................112
8.1 Server Board Design Specification ...................................................................... 112
8.2 Product Regulatory Compliance .......................................................................... 112
8.2.1 Product Safety Compliance .................................................................................112
8.2.2 Product EMC Compliance – Class A Compliance ............................................... 112
8.2.3 Certifications/Registrations/Declarations ............................................................. 113
8.2.4 Product Ecology Requirements ...........................................................................113
Product Regulatory Compliance Markings .......................................................... 113
8.2.5 113
8.3 Electromagnetic Compatibility Notices ................................................................115
8.3.1 FCC (USA)...........................................................................................................115
8.3.2 ICES-003 (Canada) .............................................................................................115
8.3.3 Europe (CE Declaration of Conformity) ...............................................................116
8.3.4 VCCI (Japan) .......................................................................................................116
8.3.5 Taiwan Declaration of Conformity (BSMI)............................................................ 116
8.3.6 Korean Compliance (RRL)...................................................................................116
Glossary...................................................................................................................................117
Reference Documents............................................................................................................120
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Intel® Server Board X38ML List of Figures
List of Figures
Figure 1. Intel
Figure 2. Intel
®
Server Board X38ML Layout ................................................................................ 5
®
Server Board X38ML Mechanical Drawing ..........................................................6
Figure 3. Server Board Block Diagram ......................................................................................... 7
Figure 4. Integrated BMC Block Diagram ................................................................................... 15
Figure 5. Setup Utility — Main Screen Display ........................................................................... 26
Figure 6. Setup Utility — Advanced Screen Display................................................................... 28
Figure 7. Setup Utility — Processor Configuration Screen Display ............................................ 29
Figure 8. Setup Utility — Memory Configuration Screen Display................................................ 31
Figure 9. Setup Utility — ATA Controller Configuration Screen Display..................................... 32
Figure 10. Setup Utility — Serial Port Configuration Screen Display.......................................... 34
Figure 11. Setup Utility — USB Controller Configuration Screen Display .................................. 35
Figure 12. Setup Utility — PCI Configuration Screen Display ....................................................37
Figure 13. Setup Utility — Security Screen Display.................................................................... 38
Figure 14. Setup Utility — Server Management Screen Display ................................................39
Figure 15. Setup Utility — Console Redirection Screen Display ................................................41
Figure 16. Setup Utility —System Information Screen Display................................................... 42
Figure 17. Setup Utility — Boot Options Screen Display ............................................................ 43
Figure 18. Setup Utility — Hard Disk Order Screen Display....................................................... 44
Figure 19. Setup Utility — CDROM Order Screen Display ......................................................... 45
Figure 20. Setup Utility — Floppy Order Screen Display............................................................ 45
Figure 21. Setup Utility — Network Device Order Screen Display.............................................. 46
Figure 22. Setup Utility — BEV Device Order Screen Display.................................................... 46
Figure 23. Setup Utility — Boot Manager Screen Display .......................................................... 47
Figure 24. Setup Utility — Error Manager Screen Display.......................................................... 48
Figure 25. Setup Utility — Exit Screen Display........................................................................... 49
Figure 26. BMC Power/Reset Signals ........................................................................................55
Figure 27. Location of Diagnostic LEDs on the Intel
Figure 28. Intel
®
Server Board X38ML Back Panel I/O connectors .......................................... 110
®
Server Board X38ML............................... 98
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List of Tables Intel® Server Board X38ML
List of Tables
Table 1. Processor Support Matrix ...............................................................................................8
Table 2. Serial A Header Pin-out ................................................................................................18
Table 3. Serial B Header Pin-out ................................................................................................19
Table 4. BIOS Setup Page Layout.............................................................................................. 22
Table 5. BIOS Setup: Keyboard Command Bar.......................................................................... 23
Table 6. Setup Utility — Main Screen Fields ..............................................................................26
Table 7. Setup Utility — Advanced Screen Display Fields .........................................................28
Table 8. Setup Utility — Processor Configuration Screen Fields................................................ 29
Table 9. Setup Utility — Memory Configuration Screen Fields................................................... 31
Table 10. Setup Utility — ATA Controller Configuration Screen Fields ...................................... 33
Table 11. Setup Utility — Serial Ports Configuration Screen Fields ........................................... 34
Table 12. Setup Utility — USB Controller Configuration Screen Fields...................................... 36
Table 13. Setup Utility — PCI Configuration Screen Fields........................................................ 37
Table 14. Setup Utility — Security Screen Fields ....................................................................... 38
Table 15. Setup Utility — Server Management Screen Fields.................................................... 39
Table 16. Setup Utility — Console Redirection Configuration Fields..........................................41
Table 17. Setup Utility —System Information Fields................................................................... 42
Table 18. Setup Utility — Boot Options Screen Fields ...............................................................43
Table 19. Setup Utility — Hard Disk Order Fields....................................................................... 44
Table 20. Setup Utility — CDROM Order Fields......................................................................... 45
Table 21. Setup Utility — Floppy Order Fields............................................................................ 45
Table 22. Setup Utility — Network Device Order Fields ............................................................. 46
Table 23. Setup Utility — BEV Device Order Fields ................................................................... 47
Table 24. Setup Utility — Boot Manager Screen Fields.............................................................. 48
Table 25. Setup Utility — Error Manager Screen Fields ............................................................. 48
Table 26. Setup Utility — Exit Screen Fields .............................................................................. 49
Table 27. Power Control Initiators............................................................................................... 56
Table 28. ACPI Power States .....................................................................................................58
Table 29. System Reset Sources and Actions............................................................................ 59
Table 30. BMC Reset Sources and Actions................................................................................ 60
Table 31. System Status LED Indicator States........................................................................... 62
Table 32. FRU Device ID Map .................................................................................................... 66
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Intel® Server Board X38ML List of Tables
Table 33. Processor Sensors...................................................................................................... 68
Table 34. Processor Status Sensor Implementation................................................................... 68
Table 35. System Fan Domains.................................................................................................. 70
Table 36. BMC Self Test Results................................................................................................72
Table 37. Standard Channel Assignments .................................................................................73
Table 38. Keyboard Controller Style Interfaces .......................................................................... 74
Table 39. Factory Default Event Filters....................................................................................... 77
Table 40. Intel
®
Server Board X38ML Integrated BMC Sensors................................................. 79
Table 41. Console Redirection Escape Sequences for Headless Operation.............................. 85
Table 42. Memory Error Events .................................................................................................. 93
Table 43. Examples of Event Data Field Contents for Memory Errors .......................................94
Table 44. PCI Error Events ......................................................................................................... 94
Table 45. Examples of Event Data Field Contents for PCI Errors ..............................................95
Table 46. FRB-2 Error Events..................................................................................................... 95
Table 47. Timestamp Clock Sync Format................................................................................... 97
Table 48. POST Progress Code LED Example ..........................................................................98
Table 49. POST Code Checkpoints............................................................................................98
Table 50. POST Error Messages and Handling........................................................................ 101
Table 51. Power Connector Pin-out (J4K1) .............................................................................. 104
Table 52. PCI Express* x16 Connector Pin-out (J7B1) ............................................................ 104
Table 53. SMBus Connector Pin-out (J3C1)............................................................................. 106
Table 54. Front Panel 16-Pin Header Pin-out (J5K4) ............................................................... 106
Table 55. VGA Connector Pin-out (J8A1)................................................................................. 107
Table 56. NIC1-Intel
Table 57. NIC2- Intel
®
82575EB (10/100/1000) Connector Pin-out (JA2A1) ............................. 107
®
82575EB (10/100/1000) Connector Pin-out (J3A2) ..............................108
Table 58. SATA Connector Pin-out (J1C1, J1C2, J2C2, J2C1)................................................ 108
Table 59. External DB-9 Serial A Port Pin-out (J5A1) .............................................................. 108
Table 60. Internal 3-pin Serial B Port Pin-out (J4C1)................................................................ 109
Table 61. USB Connectors Pin-out (JA2A1)............................................................................. 109
Table 62. Optional USB Connection Header Pin-out (J1B3) .................................................... 109
Table 63. 8-pin Fan Headers Pin-out (J5K1, J5K2, J5K3)........................................................110
Table 64. Chassis Intrusion Header (J1B2) Pin-out.................................................................. 110
Table 65. Jumper Block Definitions (J1A2, J1A3, J1A4, J3A1, J6B1) ...................................... 111
Table 66. Absolute Maximum Ratings ...................................................................................... 112
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List of Tables Intel® Server Board X38ML
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Intel® Server Board X38ML Introduction
1. Introduction
This Technical Product Specification (TPS) provides a high-level technical description for the
®
Intel
Server Board X38ML. It details the architecture and feature set for all functional
subsystems that make up the server board.
1.1 Server Board Use Disclaimer
Intel® Server Boards support add-in peripherals and contain a number of high-density VLSI and
power delivery components that require adequate airflow to cool. Intel develops and tests
chassis to work with Intel server building blocks so the fully integrated system will meet the
thermal requirements of all components. If Intel server building blocks are not used in the
system, the system integrator must consult vendor datasheets and operating parameters to
determine the air flow requirements for each application and the environmental conditions. Intel
Corporation cannot be held responsible if components fail or the server board does not operate
correctly when it is used outside of the published operating or non-operating limits.
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Server Board Overview Intel® Server Board X38ML
2. Server Board Overview
The Intel® Server Board X38ML is a monolithic printed circuit board with features that support
the entry HPC and high-density 1U server market.
2.1 Server Board Feature Set
Processor and front side bus (FSB) support
- Single LGA775 Processor Socket
- Supports the following processors:
- Quad-Core Intel
- Quad-Core Intel
- Quad-Core Intel
- Quad-Core Intel
- Quad-Core Intel
- Quad-Core Intel
- Dual-Core Intel
- Dual-Core Intel
- Dual-Core Intel
- Dual-Core Intel
- Dual-Core Intel
- Dual-Core Intel
- Dual-Core Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
®
Pentium® Dual-Core Processor E2220
®
Pentium® Dual-Core Processor E2180
®
Pentium® Dual-Core Processor E2160
®
Pentium® Dual-Core Processor E2140
®
Core™2 Quad Processor Q9550
®
Core™2 Quad Processor Q9450
®
Core™2 Quad Processor Q9300
®
Core™2 Quad Processor Q6700
®
Core™2 Quad Processor Q6600
®
Core™2 Extreme Processor X6800
®
Core™2 Extreme Processor QX9770
®
Core™2 Extreme Processor QX9650
®
Core™2 Extreme Processor QX6700
®
Core™2 Extreme Processor X6800
®
Core™2 Duo Processor E8500
®
Core™2 Duo Processor E8400
®
Core™2 Duo Processor E6850
®
Core™2 Duo Processor E8200
®
Xeon® Processor X3360
®
Xeon® Processor X3350
®
Xeon® Processor X3320
®
Xeon® Processor X3230
®
Xeon® Processor X3220
®
Xeon® Processor X3210
®
Xeon® Processor 3085
®
Xeon® Processor 3075
®
Xeon® Processor 3070
®
Xeon® Processor 3065
®
Xeon® Processor 3060
®
Xeon® Processor 3050
®
Xeon® Processor 3040
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Intel® Server Board X38ML Server Board Overview
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
- Intel
®
Core™2 Duo Processor E6750
®
Core™2 Duo Processor E6700
®
Core™2 Duo Processor E6600
®
Core™2 Duo Processor E4600
®
Core™2 Duo Processor E6840
®
Core™2 Duo Processor E4500
®
Core™2 Duo Processor E6420
®
Core™2 Duo Processor E6400
®
Core™2 Duo Processor E4400
®
Core™2 Duo Processor E6320
®
Core™2 Duo Processor E6300
®
Core™2 Duo Processor E4300.
- Supports 800/1066/1333MHz FSB
®
Intel
Intel
Intel
X38 chipset components
®
X38 MCH Memory Controller Hub
®
ICH9R I/O Controller
- Memory subsystem
DDR2 667/800 MHz, unbuffered ECC memory or non-ECC memory.
Two memory channels, two DIMM sockets per channel
8 GB supported
- Video
o 32 MB DDR2 667 MHz video memory
o External VGA connector
- PCI Express* connector
One PCI Express* x16 connector supporting PCI Express* riser card
- HDD Interface
o Four SATA II, 300 Gb/s ports
- USB
o Two external USB 2.0 ports on rear I/O panel
o Two internal USB 2.0 headers
- LAN
o Dual Gigabit Ethernet device connects to PCI Express* x4 interface on the
ICH9R
o Two 10/100/1000 Base-TX Interfaces through RJ45 Connectors
- System management
o Processor on-die temperature monitoring through Platform Environmental
Control Interface (PECI)
o Board temperature measurement
o Fan speed monitoring and control
o Voltage monitoring
o IPMI-based server management
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Server Board Overview Intel® Server Board X38ML
- Power management
o Support for power management of all capable components
o ACPI compliant motherboard and BIOS
- Manufacturing
o Surface mount technology, double-sided assembly
o Eight layer PCB
- Form factor
o 13-inch by 5.9-inch, 1U thermally optimized design
2.2 Server Board Layout
Ref # Description Ref # Description
1 (J1A2) BIOS Recovery Mode jumper
(J1A3) CMOS Clear jumper
(J1A4) Integrated BMC Boot Block Write
Protect jumper
2 (Bottom) USB Port 0
(Middle) USB Port 1
(Top) NIC1 RJ-45 connector
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17 SATA Port 3
18 SATA Port 0
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Intel® Server Board X38ML Server Board Overview
Ref # Description Ref # Description
3 NIC2 RJ-45 connector 19 SATA Port 1
4 (J3A1) Integrated BMC Force Update
Jumper
5 Serial A DB-9 connector 21 1x3 Serial B header
6 VGA connector 22 DIMM socket B2
7 Chassis intrusion header 23 DIMM socket B1
8 ServerEngines* Integrated BMC 24 DIMM socket A2
9 POST LED 25 DIMM socket A1
10 2x5 USB header for USB 2 and 3 26 Intel® X38 MCH
11 Intel® 82575EB LAN controller 27 LGA775 processor socket
12 SMBus connector 28 2x9 main power connector
13 Intel® 82801IR ICH9R 29 System fan 1 (8-pin)
14 (J6B1) Password Clear jumper 30 System fan 2 (8-pin)
15 PCI Express* x16 riser slot 31 System fan 3 (8-pin)
16 SATA Port 2 32 2x8 front panel connector
20 CMOS battery
Figure 1. Intel® Server Board X38ML Layout
The following mechanical drawing shows the physical dimensions of the server board:
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Server Board Overview Intel® Server Board X38ML
Figure 2. Intel® Server Board X38ML Mechanical Drawing
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Intel® Server Board X38ML Functional Architecture
3. Functional Architecture
This chapter provides a high-level description of the functionality associated with the
architectural blocks that make up the server board.
(R)
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Figure 3. Server Board Block Diagram
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Functional Architecture Intel® Server Board X38ML
3.1 Processor Subsystem
The Intel® Server Board X38ML supports one Intel® Xeon® or workstation processor utilizing
Flip-Chip Land Grid Array (LGA) package technology, with an LGA775 socket. The supported
processors are based on the Intel
process technologies. They maintain compatibility with 32-bit software written for the IA-32
instruction set, while supporting 64-bit native mode operation when coupled with supported 64bit operating systems and applications. Previous generations of Intel
supported.
®
Core™ micro-architecture and built on 65 nm and 45 nm
®
processors are not
The processors supported with the Intel
®
Dual-Core Intel
Quad-Core Intel
Quad-Core Intel
®
Intel
Intel
Intel
The Intel
Intel
Intel
Intel
Intel
Core™2 Extreme Processor
®
Core™2 Duo Processor
®
Core™2 Quad Processor
®
Server Board X38ML does not provide support for the following processors:
®
Pentium® 4 Processor Extreme Edition
®
Pentium® D Processor
®
Pentium® 4 Processor
®
Celeron® D Processor
Xeon® Processor 3000 sequence
®
Xeon® Processor 3200 sequence
®
Xeon® Processor 3300 sequence
®
Server Board X38ML are listed below:
Table 1. Processor Support Matrix
Processor Family Processor Number Clock Speed Front Side Bus L2 Cache
Dual-Core Intel® Xeon® Processor 3000
sequence
Quad-Core Intel® Xeon® Processor 3200
sequence
Quad-Core Intel® Xeon® Processor 3300
sequence
Intel® Core™2 Extreme Edition X6800 2.93 GHz 1066 MHz 4 MB
Intel® Core™2 Duo E6300 1.86 GHz 1066 MHz 2 MB
Intel® Core™2 Quad Processor Q6600 2.40 GHz 1066 MHz 8 MB
Note: For a complete list of supported processors, refer to the Intel
3070
X3210
X3360
2.66 GHz 1066 MHz 4 MB
2.13 GHz 1066 MHz 8 MB
2.83 GHz 1333 MHz 12 MB
®
Server Board X38ML
support Web site: http://support.intel.com/support/motherboards/server/X38ML/.
3.2 Intel
®
X38 Chipset
The Intel® Server Board X38ML is designed around the Intel® X38 chipset. The chipset consists
of two components that work together to provide the interface between all major subsystems
found on the server board, including the processor, memory, and I/O subsystems. These
components are:
Memory Controller Hub (Intel
I/O Controller Hub (Intel
Revision 1.3
8
®
X38 MCH)
®
ICH9-R)
Intel order number E15331-006
Intel® Server Board X38ML Functional Architecture
The following sub-sections provide an overview of the primary functions and supported features
of each chipset component as they are used on the Intel
®
Server Board X38ML. Later sections
provide more detail on the implementation of the subsystems.
3.2.1
Memory Controller Hub (MCH): Intel® X38 MCH
The MCH integrates four interfaces:
1. Processor/host interface (FSB)
- Supports LGA775 processors in a UP System configuration
- 200/266/333 MHz FSB clock frequency. Supports FSB transfer rates of
800/1066/1333 MT/s.
- GTL+ bus drivers with integrated GTL termination resistors
2. System memory interface (memory controller)
- Supports 512 Mbit, and 1 Gbit memory technologies
- DDR2 – 667, 800 MHz
- 8 GB addressable memory
- Supports unbuffered, ECC, and non-ECC DIMM
3. Direct media interface (DMI) interface
- Interface to the Intel
®
ICH9R South Bridge
- 100 MHz reference clock shared with PCI Express* interface(s)
4. PCI Express* interface
- Contains two PCI Express* x16 ports. One PCI Express* x16 port is connected to
one PCI Express* X16 connector as shown in the block diagram.
- Compliant with the PCI Express* base specification revision 2.0.
3.2.2
The Intel
I/O Controller Hub: Intel® ICH9-R
®
ICH9-R component integrates bridge functionality for PCI Express*, LPC, USB, SATA
II, IDE and SMBus, and numerous board management functions. The ICH9R is packaged in a
31 mm x 31 mm 676 pin mBGA.
3.2.2.1 Direct Media Interface (DMI)
DMI is the name given to chip-to-chip connection between the Intel
ICH9-R. DMI is an X4 link that mostly adheres to the PCI Express* specification. Deviations of
the DMI from standard PCI Express* specifications are described in the Intel
®
X38 MCH and the Intel®
®
ICH9 component
specification.
3.2.2.2 PCI Express* Interfaces
®
The Intel
ICH9R provides six PCI Express* Root Ports (GEN1), which are compliant with the
PCI Express Base Specification, Revision 1.1. The PCI Express* root ports 1-4 can be statically
configured as four x 1 ports, or ganged together to form two x 2 ports, one x 2 with two x1 ports,
or one x4 port. Ports 5 and 6 can be used as two x1 ports or one x2. The x4 configuration
supports lane reversal. Each Root Port fully supports 2.5 Gb/s bandwidth in each direction.
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Functional Architecture Intel® Server Board X38ML
On the Intel® Server Board XM38ML, Root Ports 1-4 are ganged together to form a single x4
link connecting to an Intel
®
82575EB NIC controller. Port 5 is connected to the Integrated BMC
for 2D video function and Port 6 is not used.
3.2.2.3 Serial ATA II Interface
®
The Intel
ICH9R has an integrated SATA II host controller that supports independent DMA
operation on the six ports and supports data transfer rates of up to 300 MB/Sec. The SATA II
Controller provides two modes of operation – a legacy mode that uses I/O space and an
Advanced Host Controller Interface (AHCI) mode that uses memory space.
3.2.2.4 Low Pin Count Interface (LPC)
The low pin count interface on the Intel
®
ICH9R provides a low system cost design interface
solution for connecting the Super I/O (SIO) for the legacy interfaces such as the parallel port,
serial port, and floppy drive.
3.2.2.5 Compatibility Modules
The Intel
®
ICH9 incorporates compatibility modules such as DMA controller, timer/counters, and
interrupt controller. The DMA controller incorporates the logic of two 8237 DMA controllers, with
seven independently programmable channels. Channels 0 – 3 are hard-wired to 8-bit, count-bybyte transfers and channels 5 to 7 are hardwired to 16-bit, count-by-word transfers. DMA
Channel 4 is used to cascade the two 8327 controllers together. The DMA controller is used to
support the LPC DMA.
The LPC DMA is handled through the LDRQ# lines from peripherals and special encoding on
LAD[3:0] from the host.
The timer/counter block contains three counters that are equivalent in function to those found in
one 8254 programmable internal timer. These three counters are combined to provide the
system timer function and speaker tone. The 14.318 MHz oscillator input provides the clock
source for these three counters.
The Intel
®
ICH9 provides an ISA compatible Programmable Interrupt Controller (PIC) that
incorporates the functionality of two 8259 interrupt controllers. Each 8259 supports eight
interrupts that are cascaded via one master controller interrupt 2 for fifteen programmable
interrupts. The interrupts are for the system timer, keyboard controller, serial ports, parallel
ports, floppy disk, mouse, DMA channels, and mapped PCI-based interrupts.
3.2.2.6 Universal Serial Bus (USB) Controller
The Intel
®
ICH9 contains two EHCI and six UHCI USB Controllers providing support for twelve
USB 2.0 ports. All twelve ports are high speed, full-speed, and low speed capable. The port
routing logic for the ICH9 determines whether a USB port is controlled by one of the UHCI
controllers or by the EHCI controller. USB 2.0 based debug port is also implemented in the
ICH9.
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Intel® Server Board X38ML Functional Architecture
3.2.2.7 Real Time Clock (RTC)
®
The Intel
two 128-byte banks of battery-backed RAM. The RTC performs two key functions on the Intel
ICH9 contains a Motorola MS146818A functionally compatible real-time clock with
®
Server Board XM38ML:
Keeps track of the time of day
Stores system configuration data even when the system is powered down
The RTC operates on a 32.768 KHz crystal and a 3 V lithium battery.
3.2.2.8 GPIO
®
The Intel
ICH9 contains 61 general purpose inputs/outputs. The General Purpose Inputs and
Outputs (GPIO) are provided for custom system design.
3.2.2.9 Enhanced Power Management
®
The Intel
that provides power and thermal management. The Intel
ICH9R supports the Advanced Configuration and Power Interface, Version 2.0 (ACPI)
®
ICH9R also supports the
Manageability Engine Power Management Support for new wake events from the MCH
Management Engine.
3.2.2.10 System Management Interface
The Intel
communicate with SMBus slaves. This interface is compatible with most I
®
ICH9R provides a SMBus 2.0 compliant Host Controller that allows the processor to
2
C devices. The
ICH9R also supports slave functionality. The SMBus logic exists in Device 31: Function 3
configuration space.
3.2.2.11 Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a potentially lower-cost
alternative for the system flash versus the Firmware Hub on the LPC Bus. The Intel
®
ICH9
supports two SPI flash components using two separate chip select pins. Each component may
be up to 16 MB and operate in SPI Fast Read Instructions and frequencies of 20 MHZ or 33
MHz. The SPI Interface has the following features:
Clock (CLK)
Master Out Slave In (MOSI)
Master In Slave Out (MISO)
Chip Select (CS#)
Communication on the SPI is done with a Master – Slave protocol.
The SPI flash can operate in two operational modes: descriptor and non-descriptor. When
operating in non-descriptor mode, the SPI Flash only supports the BIOS through register
access.
When used in descriptor mode, the ICH9 allows a single SPI flash device to store the system
BIOS, Intel
Revision 1.3
®
AMT Firmware, and Gigabit Ethernet EEPROM information.
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Functional Architecture Intel® Server Board X38ML
The SPI Flash Memory device is an Atmel* AT26DF321 - a 32 mbit, 2.7 to 3.6 volt serial
interface FLASH memory, Intel part number D64145-001/D64145-002. This device is installed
directly onto the server board without the use of sockets.
3.2.2.12 Manageability
The Intel
®
ICH9 integrates several functions to manage the system and lower the total cost of
ownership (TCO) of the system. These system management functions report errors, diagnose
the system, and recover from system lockups without the aid of an external microcontroller.
The management engine includes the following features:
TCO timer to detect system locks
Process Present Indicator to determine if the processor fetches the first instruction after
reset
ECC Error reporting from the host controller
Function Disable to prevent a disabled function from generating interrupts and power
management events
Intruder Detect input for system cases
3.3 Integrated Baseboard Management Controller
A ServerEngines* Baseboard Management Controller (Integrated BMC) is integrated onto the
server board. This integrates the baseboard management controller (BMC and KVMS
subsystem), graphics controller (graphics subsystem), and Super I/O interface (Super I/O
subsystem). The Intel
3.3.1
Functionality Overview
Baseboard management controller
- IPMI 2.0 compliant
- Integrated 250 MHz 32-bit ARM9 processor
- Six I
2
- Two independent 10/100 Ethernet controllers with RMII support
- LPC master interface for non-volatile code storage
- SPI Flash interface
- Three UART for ICMB support
- DDR2 16-bit up to 667 MHz memory interface
- Sixteen mailbox registers for communication between the host and the BMC
- Watchdog timer
- Three general purpose timers
- Dedicated real-time clock for BMC
- Up to 16 direct and 64 serial GPIO ports
- Ability to maintain text and graphics controller history
- Twelve 10-bit analog to digital converters
®
Server Board XM38ML does not support remote KVMS features.
C SMBus Modules with master-slave support
Revision 1.3
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Intel order number E15331-006
Intel® Server Board X38ML Functional Architecture
- Three diode inputs for temperature measurements
- Eight fan tachometer inputs
- Four pulse width modulators (PWM)
- Chassis intrusion logic with battery-backed general purpose register
- LED support with programmable blink rate control
- Programmable I/O port snooping, which can be used to snoop on Port 80h
- Unique chip ID for each part, burned at the time production testing
- Hardware 32-bit random number generator
- JTAG master interface
- On-chip test Infrastructure for testing BMC firmware
Remote KVMS features
- USB 2.0 interface for keyboard, mouse, and remote storage such as CD-ROM/DVD-
ROM and floppy
- USB 1.1 interface for PS/2 to USB bridging, remote keyboard and mouse
- Hardware-based video compression and redirection logic
- Supports both text and graphics redirection
- Hardware-assisted video redirection using the frame processing engine
- Direct interface to the Integrated Graphics Controller registers and Frame buffer
- Hardware-based encryption engine
Graphics controller
- Integrated graphics core
- 2D hardware graphics acceleration
- DDR2 memory interface supports up to 128 Mbytes of memory
- Supports all display resolutions up to 1600 x 1200 16 bpp @ 75 Hz
- High speed integrated 24-bit RAMDAC
- Single lane PCI Express* host interface
Server Class Super I/O functionality includes
- Keyboard style/BT interface for BMC support
- Two fully functional serial ports, compatible with the 16C550
- Serial IRQ support
- SMI/SCI/PME support
- ACPI-compliant
- Up to 16 shared GPIO ports
- Programmable wake-up event support
- Plug and play register set
- Power supply control
- Watchdog timer compliant with Microsoft SHDG
- LPC to SPI bridge for system BIOS support
- Real-time clock module with the external RTC interface
Revision 1.3
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Functional Architecture Intel® Server Board X38ML
3.3.2 Block Diagram
The following block diagram shows the three main host interface of the integrated BMC. The
LPC, PCI Express*, and USB interfaces are resourced by the Intel
Board X38ML.
The LPC interface to the host is used for the Super I/O and BMC functionality. The BMC can
communicate with the host through the KCS or BT interfaces. The Super I/O interface also
integrates a LPC to SPI Flash bridge, which can be used to store multiple copies of the system
ROM.
The PCI Express* interface is mainly used for the graphics controller interface to the host. The
graphics controller is a fully compliant VGA controller with 2D hardware acceleration and full
bus master support. The graphics controller can support up to 1600 x1200 resolutions at high
refresh rates.
The USB 1.1 is used for the remote keyboard and mouse support and the USB2.0 is used for
the remote storage support. The Integrated BMC supports various storage devices such as CDROM, DVD-ROM, CD-ROM (ISO image), floppy, and USB flash disk. Any of the storage devices
can be used as a boot device and the host can boot from this remote media.
®
ICH9R on the Intel® Server
Revision 1.3
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Figure 4. Integrated BMC Block Diagram
3.4 Memory Subsystem
3.4.1 Memory Support
The server board supports four DDR2 667/800 MHz unbuffered ECC or non-ECC DIMMs, two
memory channels, two DIMMs per memory channel. The maximum memory capacity supported
is 8 GB using four DIMMs of 2 GB unbuffered, 1 Gbit DDR2 memory.
Only DIMMs tested and qualified by Intel or a designated memory test vendor are supported. A
list of qualified DIMMs is at http://support.intel.com/support/motherboards/server/X38ML/
Note: All DIMMs are supported by design, but only fully qualified DIMMs are supported on the
board.
3.4.2 Memory Population Rules
The X38 MCH supports two DDR2 DIMM sockets for Channel A, and two DDR2 DIMM sockets
for Channel B. The four slots are partitioned with Channel A representing the Channel A DIMMs
Revision 1.3
Intel order number E15331-006
.
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Functional Architecture Intel® Server Board X38ML
(DIMM A1 and DIMM A2) and Channel B representing the Channel B DIMMs (DIMM B1 and
DIMM B2). They are placed in a row and numbered as DIMM A1/DIMM A2/DIMM B1/DIMM B2
with DIMM A1 the closest to the MCH.
Memory population rules:
If dual-channel operation is desired, Channel A and Channel B must be populated
identically (for example, same capacity)
Use DDR2 667/800 only
The speed used on all the channels is the slowest DIMM in the system
Use ECC or non-ECC DIMMs
User can mix different memory technologies (size and density)
For single-channel mode, either channel may be used and DIMM sockets within the
same channel can be populated in any order
For dual-channel interleaved mode, DIMM sockets may be populated in any order as
long as the total memory in each channel is the same.
For dual-channel asymmetric mode, DIMM sockets may be populated in any order.
3.5 I/O Subsystem
3.5.1 PCI Express* x16 Riser Slot
The server board provides a PCI Express* x16 riser slot that is resourced with a PCI Express*
x16 interface from MCH and supports PCI Express* x16 graphics.
3.5.2 SATA Support
The server board provides four SATA II ports by the integrated SATA controller of the Intel®
ICH9-R. The SATA controller supports data transfer rates of up to 300 MB/sec and provides two
modes of operation: a legacy mode using I/O space and an Advanced Host Controller Interface
(AHCI) mode using memory space.
3.5.2.1 SATA RAID
®
Intel
Embedded Server RAID Technology, available with the CH9R, supports four Serial ATA
ports, providing a cost-effective way to achieve higher transfer rates and reliability. Intel
Embedded Server RAID Technology supports:
RAID level 0 data striping for improved performance
RAID level 1 data mirroring for improved data reliability
RAID level 10 data striping and mirroring for high data transfer rates and data
redundancy
®
Revision 1.3
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Intel® Server Board X38ML Functional Architecture
Intel® Embedded Server RAID Technology functionality requires the following items:
Intel
Intel
Most recent version of the Intel
®
ICH9-R
®
RAID Technology option ROM
®
Application Accelerator RAID Edition drivers
Two SATA hard drives
®
RAID Technology is not available in these configurations:
Intel
The SATA controller in compatible mode
Intel
®
RAID Technology disabled
3.5.2.2 Intel
®
The Intel
RAID Technology for SATA Option ROM provides a pre-operating system user
®
RAID Technology Option ROM
interface for the Intel RAID Technology implementation and provides the ability for an Intel RAID
Technology volume to be used as a boot disk as well as to detect any faults in the Intel RAID
Technology volume(s) attached to the Intel RAID controller.
3.5.3 Video Support
The Integrated BMC integrates a fully compliant VGA graphics controller with hardware
acceleration for BLIT and 2D graphics. The graphics controller:
Is resourced with a PCI Express* x1 interface from the ICH9R
Supports 16-bit DDR2 memory running at a configurable frequency of 500 MHz. The
maximum capacity is 128 MB.
Supports all display resolutions up to 1600 x 1200 16bpp @ 75Hz
3.5.4 Network Interface Controller (NIC)
The server board integrates an Intel® 82575EB Gigabit Ethernet Controller to provide two
Gigabit Ethernet Ports. The NIC is resourced with a PCI Express* x4 interface from the ICH9R.
The NIC supports the following features:
PCI Express* x4 interface
IEEE 802.3x compliant flow control support
Integrated PHY for full 10/100/1000 Mbps full and half duplex operation
On-board microcontroller
Wake-On LAN support
3.5.5 USB Support
The server board provides up to four USB 2.0 ports by the USB controller functionality
integrated into the ICH9-R. Two external connectors are located on the back edge of the
Revision 1.3
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Functional Architecture Intel® Server Board X38ML
baseboard. One 10-pin internal on-board header is provided which is capable of supporting two
additional USB 2.0 ports.
3.5.6 Super I/O Chip
The Super I/O chip integrated into the Integrated BMC provides legacy I/O support. The Super
I/O chip contains the necessary circuitry to support two serial ports and hardware
control/monitor functions. The server board implements the following features:
Two fully functional serial ports, compatible with the 16C550
Up to 16 shared GPIO ports
Programmable wake-up event support
Plug and play register set
Power supply control
Watchdog timer compliant with Microsoft SHDG*
LPC to SPI bridge for system BIOS support
Real-time clock module with the external RTC interface
3.5.6.1 Serial Ports
The board provides two serial ports. Serial A is a standard DB-9 interface located at the rear I/O
panel of the server board next to the video connector. The reference designator is J5A1. Serial
B is a 3-pin header interface located near the CMOS battery. The reference designator is J4C1.
Table 2. Serial A Header Pin-out
Pin Signal Name Serial Port A Header Pin-out
1 DCD
2 RXD
3 TXD
4 DTR
5 GND
6 DSR
7 RTS
8 CTS
9 RI
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