Intel SL8J6 - Pentium 4 Processor, Pentium 4 Datasheet

Intel® Pentium® 4 Processor on 90 nm Process

Datasheet

2.80 GHz – 3.40 GHz Frequencies Supporting Hyper-Threading Technology1 for All Frequencies with 800 MHz Front Side Bus

February 2005

Document Number: 300561-003

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PRO PERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEV ER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING T O FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PA TENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “un defined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel from published specifications. Current characterized errata are available on request.

Pentium® 4 processor on 90 nm process may contain design defects or errors known as errata which may cause the product to deviate

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting HT Technology and a Hyper-Threading Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See http://www.intel.com/info/hyperthreading/

Intel, Pentium, Intel NetBurst, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

for more information including details on which processors support HT Technology.

2 Datasheet

Contents

1 Introduction..................................................................................................................9

1.1 Terminology.........................................................................................................10

1.1.1 Processor Packaging Terminology.........................................................10

1.2 References..........................................................................................................11

2 Electrical Specifications........................................................................................13

2.1 Power and Ground Pins......................................................................................13

2.2 Decoupling Guidelines ........................................................................................13

2.2.1 V

2.2.2 FSB GTL+ Decoupling ...........................................................................13

2.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking....................................14

2.3 Voltage Identification........................................................... ... ... .... ... ... ................14

2.3.1 Phase Lock Loop (PLL) Power and Filter...............................................16

2.4 Reserved, Unused, and TESTHI Pins....... ... .... ... ... ... ... .......................................17

2.5 FSB Signal Groups..............................................................................................18

2.6 Asynchronous GTL+ Signals...............................................................................19

2.7 Test Access Port (TAP) Connection....................................................................19

2.8 FSB Frequency Select Signals (BSEL[1:0])........................................................20

2.9 Absolute Maximum and Minimum Ratings..........................................................21

2.10 Processor DC Specifications........................ .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ...21

2.11 V

Overshoot Specification...............................................................................29

2.11.1 Die Voltage Validation...................................................................... ... ...30

Decoupling......................................................................................13

3 Package Mechanical Specifications.................................................................31

3.1 Package Mechanical Specifications....................................................................31

3.1.1 Package Mechanical Drawing................................................................32

3.1.2 Processor Component Keep-out Zones.................................................35

3.1.3 Package Loading Specifications ............................................................35

3.1.4 Package Handling Guidelines ................................................................35

3.1.5 Package Insertion Specifications ...........................................................36

3.1.6 Processor Mass Specification ................................................................36

3.1.7 Processor Materials................................................................................36

3.1.8 Processor Markings................ ... ... ... .... ... ... ... ... .... ...................................36

3.1.9 Processor Pinout Coordinates................................................................37

4 Pin List and Signal Description..........................................................................39

4.1 Processor Pin Assignments ...... ... ... .... ... ... ... .... ... ... ... ... .... ...................................39

4.2 Alphabetical Signals Reference ..........................................................................54

5 Thermal Specifications and Design Considerations.................................63

5.1 Processor Thermal Specifications.......................................................................63

5.1.1 Thermal Specifications.............................................................. ... .... ... ...63

5.1.2 Thermal Metrology .... ... ... ... .... ... ... .......................................... ... ... ..........66

5.2 Processor Thermal Features............................... ... ... ... .... ... ... ... .... ... ... ... ... .... ......67

5.2.1 Thermal Monitor..................................... ... ... ....................................... ...67

Datasheet 3

5.2.2 On-Demand Mode........ ... ... ... .... ... ... .......................................... ... ... .... ...68

5.2.3 PROCHOT# Signal Pin..........................................................................68

5.2.4 THERMTRIP# Signal Pin.......................................................................69

5.2.5 T

5.2.6 Thermal Diode........................................................................................69

and Fan Speed Reduction..........................................................69

control

6Features.......................................................................................................................71

6.1 Power-On Configuration Options ........................................................................71

6.2 Clock Control and Low Power States..................................................................72

6.2.1 Normal State—State 1 ...........................................................................72

6.2.2 AutoHALT Powerdown State—State 2 ..................................................72

6.2.3 Stop-Grant State—State 3 .....................................................................73

6.2.4 HALT/Grant Snoop State—State 4 ........................................................73

6.2.5 Sleep State—State 5..............................................................................74

7 Boxed Processor Specifications.......................................................................75

7.1 Mechanical Specifications...................................................................................76

7.1.1 Boxed Processor Cooling Solution Dimensions.....................................76

7.1.2 Boxed Processor Fan Heatsink Weight..................................................77

7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach

Clip Assembly ........................................................................................78

7.2 Electrical Requirements ......................................................................................78

7.2.1 Fan Heatsink Power Supply...................................................................78

7.3 Thermal Specifications........................................................................................79

7.3.1 Boxed Processor Cooling Requirements ...............................................79

7.3.2 Variable Speed Fan ..................................... ... ... .... ... ... ... .... ... ... ... ... .... ...81

4 Datasheet

Figures

1 Phase Lock Loop (PLL) Filter Requirements ......................................................16

2V 3V 4V

Static and Transient Tolerance for Loadline A... ....................................... ...24

Static and Transient Tolerance for Loadline B... ....................................... ...26

Overshoot Example Waveform....................................................................30

5 Processor Package Assembly................... ... .... ... ... ... ... .... ... ... ... ..........................31

6 Processor Package Drawing (Sheet 1 of 2) ........................................................33

7 Processor Package Drawing (Sheet 2 of 2) ........................................................34

8 Processor Top-Side Markings....................................................................... ... ...36

9 Processor Pinout Coordinates (Top View)..........................................................37

10 Pinout Diagram (Top View—Left Side) ..... ... .... ... ... ... ... .... ... ... .............................40

11 Pinout Diagram (Top View—Right Side).............................................................41

12 Thermal Profile....................................................................... ... ..........................66

13 Case Temperature (TC) Measurement Location.................................................66

14 Stop Clock State Machine............................................................. ... ... ... ... ..........72

15 Mechanical Representation of the Boxed Processor ..........................................75

16 Space Requirements for the Boxed Processor (Side View)................................76

17 Space Requirements for the Boxed Processor (Top View).................................77

18 Boxed Processor Fan Heatsink Power Cable Connector Description.................78

19 Baseboard Power Header Placement Relative to Processor Socket..................79

20 Boxed Processor Fan Heatsink Airspace Keep-out Requirements

(side 1 view)........................................................................................................80

21 Boxed Processor Fan Heatsink Airspace Keep-out Requirements

(side 2 view)........................................................................................................80

22 Boxed Processor Fan Heatsink Set Points .........................................................81

Datasheet 5

Tables

1 References..........................................................................................................11

2 Core Frequency to FSB Multiplier Configuration.................................................14

3 Voltage Identification Definition...........................................................................15

4 FSB Pin Groups ........................ ... ... ....................................... ... ... .... ... ... .............18

5 Signal Characteristics .........................................................................................19

6 Signal Reference Voltages..................................................................................19

7 BSEL[1:0] Frequency Table for BCLK[1:0] .................................. .... ... ... ... ... .... ...20

8 Processor DC Absolute Maximum Ratings.........................................................21

9 Voltage and Current Specifications.....................................................................22

10 V 11 V

Static and Transient Tolerance for Loadline A.............................................23

Static and Transient Tolerance for Loadline B.............................................25

12 GTL+ Signal Group DC Specifications................................................................27

13 Asynchronous GTL+ Signal Group DC Specifications........................................27

14 PWRGOOD and TAP Signal Group DC Specifications ......................................28

15 VCCVID DC Specifications .................................................................................28

16 VIDPWRGD DC Specifications................................................. ... .... ...................28

17 BSEL [1:0] and VID[5:0] DC Specifications.........................................................29

18 BOOTSELECT DC Specifications................................... .... ... ... ... .... ... ... .............29

19 V

Overshoot Specifications.............................................................................29

20 Processor Loading Specifications.......................................................................35

21 Package Handling Guidelines.............................................................................35

22 Processor Materials ............................................................................................36

23 Alphabetical Pin Assignment...............................................................................42

24 Numerical Pin Assignment..................................................................................48

25 Signal Description ...............................................................................................54

26 Processor Thermal Specifications.......................................................................64

27 Thermal Profile....................................................................................................65

28 Thermal Diode Parameters.................................................................................70

29 Thermal Diode Interface......................................................................................70

30 Power-On Configuration Option Pins..................................................................71

31 Fan Heatsink Power and Signal Specifications...................................................79

32 Boxed Processor Fan Heatsink Set Points .........................................................81

6 Datasheet

Revision History

Revision Description Date

-001 • Initial release February 2004

-002 • Added specifications for 3.20 GHz processors with PRB = 1

• Added ISGNT/ISLP specifications

• Updated thermal diode specifications

• Other changes marked with change bars

-003 • Added specifications for 3.40 GHz processors with PRB = 0 February 2005

April 2004

Datasheet 7

Intel® Pentium® 4 Processor on 90 nm Process 2.80A/E GHz, 3E GHz, 3.20E GHz, and 3.40E GHz

• Available at 2.80A/E GHz, 3E GHz,

3.20E GHz, and 3.40E GHz

• Supports Hyper-Threading Technology

(HT Technology) for all frequencies with 800 MHz front side bus (FSB)

• Binary compatible with applications

running on previous members of the Intel microprocessor line

• Intel NetBurst

microarchitecture

• FSB frequencies at 533 MHz, and

800 MHz

• Hyper-Pipelined Technology

—Advance Dynamic Execution —Very deep out-of-order execution

• Enhanced branch prediction

• Optimized for 32-bit applications running

on advanced 32-bit operating systems

• 478-Pin Package

• 16-KB Level 1 data cache

• 1-MB Advanced Transfer Cache (on-die,

full-speed Level 2 (L2) cache) with 8-way associativity and Error Correcting Code (ECC)

• 144 Streaming SIMD Extensions 2

(SSE2) instructions

• 13 Streaming SIMD Extensions 3 (SSE3)

instructions

• Enhanced floating point and multimedia

unit for enhanced video, audio, encryption, and 3D performance

• Power Management capabilities

—System Management mode —Multiple low-power states

• 8-way cache associativity provides

improved cache hit rate on load/store operations

8 Datasheet

1Introduction

Introduction

The Intel® Pentium® 4 processor on 90 nm process is a follow on to the Intel® Pentium® 4 processor in the 478-pin package with enhancements to the Intel NetBurst Pentium 4 processor on 90 nm process uses Flip-Chip Pin Grid Array (FC-mPGA4) package technology, and plugs into a 478-pin surface mount, Zero Insertion Force (ZIF) socket, referred to as the mPGA478B socket. The Pentium 4 processor on 90 nm process, like its predecessor, the Pentium 4 processor in the 478-pin package, is based on the same Intel 32-bit microarchitecture and maintains the tradition of compatibility with IA-32 software.

Note: In this document the Pentium 4 processor on 90 nm process is also referred to as the processor.

The Pentium 4 processor on 90 nm process supports Hyper-Threading Technology Threading Technology allows a single, physical processor to function as two logical processors. While some execution resources (such as caches, execution units, and buses) are shared, each logical processor has its own architecture state with its own set of general-purpose registers, control registers to provide increased system responsiveness in multitasking environments, and headroom for next generation multithreaded applications. Intel recommends enabling HyperThreading Technology with Microsoft Wind ows* XP Profession al or Windows* XP Home, and disabling Hyper-Threading Technology via the BIOS for all previous versions of Windows operating systems. For more information on Hyper-Threading Technology, see www.intel.com/ info/hyperthreading. Refer to Section 6.1, for Hyper-Threading Technology configuration details.

In addition to supporting all the existing Streaming SIMD Extensions 2 (SSE2), there are 13 new instructions that further extend the capabilities of Intel processor technology. These new instructions are called Streaming SIMD Extensions 3 (SSE3).These new instructions enhance the performance of optimized applications for the digital home such as video, image processing and media compression technology. 3D graphics and other entertainment applications (such as gaming) will have the opportunity to take advantage of these new instructions as platforms with the Pentium 4 processor on 90 nm process and SSE3 become available in the market place.

microarchitecture. The

. Hyper-

The processor’s Intel NetBurst microarchitecture front side bus (FSB) uses a split-transaction, deferred reply protocol like the Pentium 4 processor. The Intel NetBurst microarchitecture FSB uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "double-clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 6.4 GB/s.

Intel will enable support components for the processor including heatsink, heatsink retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling.

The processor includes an address bus powerdown capability that removes power from the address and data pins when the FSB is not in use. This feature is always enabled on the processor.

Datasheet 9

Introduction

1.1 Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic lev el, L= Low logic level).

“FSB” refers to the interface between the processor and system core logic (i.e., the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O.

1.1.1 Processor Packaging Terminology

Commonly used terms are explained here for clarification:

• Intel

• Processor — For this document, the term processor is the generic form of the Pentium 4

• Keep-out zone — The area on or near the processor that system design cannot use.

• Intel

• Processor core — Processor core die with integrated L2 cache.

• FC-mPGA4 package — The Pentium 4 processor on 90 nm process is available in a Flip-

Pentium® 4 processor on 90 nm process — Processor in the FC-mPGA4 package

with a 1-MB L2 cache.

processor on 90 nm process.

865G/865GV/865PE/865P chipset — Chipset that supports DDR memory technology

for the Pentium 4 processor on 90 nm process.

875P chipset — Chipset that supports DDR memory technology for the Pentium 4

processor on 90 nm process

Chip Micro Pin Grid Array 4 package, consisting of a processor core mounted on a pinned substrate with an integrated heat spreader (IHS). This packaging technology employs a

1.27 mm [0.05 in] pitch for the substrate pins.

• mPGA478B socket — The Pentium 4 processor on 90 nm process mates with the system

board through a surface mount, 478-pin, zero insertion force (ZIF) socket.

• Integrated heat spreader (IHS) —A component of the processor package used to enhance

the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface.

• Retention mechanism (RM)—Since the mPGA478B socket does not include any mechanical

features for heatsink attach, a retention mechanism is required. Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket.

• Storage conditions — Refers to a non-operational state. The processor may be installed in a

platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor pins should not be connected to any supply voltages, hav e any I/Os biased, or receive any clocks. Upon exposure to “free air”(i.e. unsealed packaging or a device removed from packaging material) the processor must handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.

• Functional operation — Refers to normal operating conditions in which all processor

specifications, including DC, AC, FSB, signal quality, mechanical and thermal, are satisfied.

10 Datasheet

1.2 References

Material and concepts available in the following documents may be beneficial when reading this document.

Table 1. References

Intel® Pentium® 4 Processor Specification Update

Intel® 865G/865GV/865PE/865P Chipset Platform Design Guide

Intel® 875P Chipset Platform Design Guide Intel® Pentium® 4 Processor on 90 nm Process Thermal Design

Guidelines Voltage Regulator-Down (VRD) 10.0: for Desktop Socket 478 Design

Guide

Intel

Pentium®4 Processor 478-Pin Socket (mPGA478B) Socket

Design Guidelines Intel® Architecture Software Developer's Manual

IA-32 Intel Volume 1: Basic Architecture

IA-32 Intel Volume 2A: Instruction Set Reference, A-M

IA-32 Intel Volume 2A: Instruction Set Reference, N-Z

IA-32 Intel Volume 3: System Programming Guide

AP-485 Intel

ITP700 Debug Port Design Guide

Architecture Software Developer’s Manual

Architecture Software Developer’s Manual,

Processor Identification and the CPUID Instruction

Introduction

Document Location

http://developer.intel.com/design/ pentium4/specupdt/249199.htm

http://developer.intel.com/design/ chipsets/designex/252518.htm

http://developer.intel.com/design/ chipsets/designex/252527.htm

http://developer.intel.com/design/ Pentium4/guides/300564.htm

http://developer.intel.com/design/ Pentium4/guides/252885.htm

http://developer.intel.com/design/ pentium4/guides/249890.htm

http://www.intel.com/design/ pentium4/manuals/index_new.htm

http://developer.intel.com/design/ xeon/applnots/241618.htm

http://developer.intel.com/design/ Xeon/guides/249679.htm

Datasheet 11

Introduction

12 Datasheet

2 Electrical Specifications

2.1 Power and Ground Pins

For clean on-chip power distribution, the processor has 85 VCC (power) and 179 VSS (ground) pins. All power pins must be connected to V ground plane.The processor VCC pins must be supplied by the voltage determined by the VID (Voltage identification) pins.

2.2 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 9. Failure to do so can result in timing violations or reduced lifetime of the component. For further information and design guidelin es, refer to the appropriate platform design guide, and the Voltage Regulator-Down (VRD) 10.0 Design Guidelines for Desktop Socket

478.

, while all VSS pins must be connected to a system

Electrical Specifications

2.2.1 V

Decoupling

Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low power states, must be provided by the voltage regulator solution (VR). For more details on this topic, refer to the appropriate platform design guide for Desktop Socket 478.

, and the Voltage Regulator-Down (VRD) 10.0 Design Guidelines

2.2.2 FSB GTL+ Decoupling

The processor integrates signal termination on the die as well as incorporating high frequency decoupling capacitance on the processor package. Decoupling must also be provided by the system baseboard for proper GTL+ bus operation. For more information, refer to the appropriate platform design guide.

Datasheet 13

Electrical Specifications

2.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor . As in previous generation processors, the processor core frequency is a multiple of the BCLK[1:0] frequency. No user intervention is necessary, and the processor will automatically run at the speed indicated on the package. The processor uses a differential clocking implementation.

Table 2. Core Frequency to FSB Multiplier Configuration

Multiplication of System

Core Frequency to FSB

Frequency

1/14 RESERVED 2.80E GHz 1/15 RESERVED 3E GHz 1/16 RESERVED 3.20E GHz 1/17 RESERVED 3.40E GHz 1/18 RESERVED RESERVED 1/19 RESERVED RESERVED 1/20 RESERVED RESERVED 1/21 2.80A GHz RESERVED

NOTES:

1. Individual processors operate only at or below the rated frequency.

Core Frequency

(133 MHz BCLK/533 MHz FSB)

2.3 Voltage Identification

The VID specification for the processor is supported by the Voltage Regulator-Down (VRD) 10.0 Design Guidelines for Desktop Socket 478. The voltage set by the VID pins is the maximum

voltage allowed by the processor. A minimum voltage is provided in Table 9 and changes with frequency. This allows processors running at a higher frequency to have a relaxed minimum voltage specification. The specifications have been set such that one voltage regulator can work with all supported frequencies.

Core Frequency

(200 MHz BCLK/800 MHz FSB)

Notes

1 1 1 1 1 1

Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have different VID settings.

The processor uses six voltage identification pins, VID[5:0], to support automatic selection of power supply voltages. Table 3 specifies the voltage level corresponding to the state of VID[5:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to low voltage level. If the processor socket is empty (VID[5:0] = x11111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. See the Voltage Regulator-Down (VRD) 10.0 Design Guidelines for Desktop Socket 478 for more details.

Power source characteristics must be guaranteed to be stable when the supply to the voltage regulator is stable.

The processor’s Voltage Identification circuit requires an independent 1.2 V supply and some other power sequencing considerations.

14 Datasheet

Electrical Specifications

Table 3. Voltage Identification Definition

VID5 VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VID1 VID0 VID

001010 0.8375 0110101.2125 101001 0.8500 1110011.2250 001001 0.8625 0110011.2375 101000 0.8750 1110001.2500 001000 0.8875 0110001.2625 100111 0.9000 1101111.2750 000111 0.9125 0101111.2875 100110 0.9250 1101101.3000 000110 0.9375 0101101.3125 100101 0.9500 1101011.3250 000101 0.9625 0101011.3375 100100 0.9750 1101001.3500 000100 0.9875 0101001.3625 100011 1.0000 1100111.3750 000011 1.0125 0100111.3875 100010 1.0250 1100101.4000 000010 1.0375 0100101.4125 100001 1.0500 1100011.4250 000001 1.0625 0100011.4375 100000 1.0750 1100001.4500 000000 1.0875 0100001.4625 111111VR output off 1011111.4750 011111VR output off 0011111.4875 111110 1.1000 1011101.5000 011110 1.1125 0011101.5125 111101 1.1250 1011011.5250 011101 1.1375 0011011.5375 111100 1.1500 1011001.5500 011100 1.1625 0011001.5625 111011 1.1750 1010111.5750 011011 1.1875 0010111.5875 111010 1.2000 1010101.6000

Datasheet 15

Electrical Specifications

2.3.1 Phase Lock Loop (PLL) Power and Filter

and V

CCA

CCIOPLL

silicon. Since these PLLs are analog, they require low noise power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this degradation, these supplies must be low pass filtered from V

are power sources required by the PLL clock generators on the processor

The AC low-pass requirements, with input at V

• < 0.2 dB gain in pass band

• < 0.5 dB attenuation in pass band < 1 Hz

• > 34 dB attenuation from 1 MHz to 66 MHz

• > 28 dB attenuation from 66 MHz to core frequency

The filter requirements are illustrated in Figure 1. For recommendations on implementing the filter,

Figure 1. Phase Lock Loop (PLL) Filter Requirements

refer to the appropriate platform design guide.

0.2 dB 0 dB

–0.5 dB

Forbidden

Zone

–28 dB

are as follows:

Forbidden

Zone

–34 dB

1 MHz 66 MH z fcorefpeak1 HzDC

Passband

NOTES:

1. Diagram not to scale.

2. No specification exists for frequencies beyond fcore (core frequency).

3. fpeak, if existent, should be less than 0.05 MHz.

16 Datasheet

High

Frequency

Band

2.4 Reserved, Unused, and TESTHI Pins

All RESERVED pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a pin listing of the processor and the location of all RESERVED pins.

For reliable operation, always connect unused inputs or bidirectional sign als to an appropriate signal level. In a system level design, on-die termination has been included on the processor to allow signals to be terminated within the processor silicon. Most unused GTL+ inputs should be left as no connects since GTL+ termination is provided on the processor silicon. However, see

Table 5 for details on GTL+ signals that do not include on-die termination. Unused active high

inputs should be connected through a resistor to ground (V unconnected; however, this may interfere with some test access port (TAP) functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. For unused GTL+ input or I/O signals, use pull-up resistors of the same value as the on-die termination resistors (R

TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die termination. Inputs and used outputs must be terminated on the system board. Unused outputs may be terminated on the system board or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. Signal termination for these signal types is discussed in the appropriate platform design guide.

). Unused outputs can be left

Electrical Specifications

The TESTHI pins must be tied to the processor V resistor has a resistance value within ±20% of the impedance of the board transmission line traces. For example, if the trace impedance is 60 Ω, then a value between 48 Ω and 72 Ω is required.

The TESTHI pins may use individual pull-up resistors or be grouped together as detailed below . A matched resistor must be used for each group:

using a matched resistor, where a matched

• TESTHI[1:0]

• TESTHI[7:2]

• TESTHI8 – cannot be grouped with other TESTHI signals

• TESTHI9 – cannot be grouped with other TESTHI signals

• TESTHI10 – cannot be grouped with other TESTHI signals

• TESTHI11 – cannot be grouped with other TESTHI signals

• TESTHI12 – cannot be grouped with other TESTHI signals

Datasheet 17

Electrical Specifications

2.5 FSB Signal Groups

The FSB signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers that use GTLREF as a reference level. In this document, the term "GTL+ Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, "GTL+ Output" refers to the GTL+ output group as well as the GTL+ I/O group when driving.

With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals that are dependent on the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals that are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 4 identifies which signals are common clock, source synchronous, and asynchronous.

Table 4. FSB Pin Groups

Signal Group Type Signals

GTL+ Common Clock Input

GTL+ Common Clock I/O

GTL+ Source Synchronous I/O

GTL+ Strobes Asynchronous GTL+

Input Asynchronous GTL+

Output Asynchronous GTL+

Input/Output TAP Input Synchronous to TCK TCK, TDI, TMS, TRST# TAP Output Synchronous to TCK TDO FSB Clock Clock BCLK[1:0], ITP_CLK[1:0]

Power/Other

NOTES:

1. Refer to Section 4.2 for signal descriptions.

2. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 6.1 for details.

3. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.

Synchronous to BCLK[1:0]

Synchronous to associated strobe

Synchronous to BCLK[1:0]

BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY# AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#, DBSY#,

DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR#

SignalsAssociated Strobe

REQ[4:0]#, A[16:3]# A[35:17]# D[15:0]#, DBI0# DSTBP0#, DSTBN0# D[31:16]#, DBI1# DSTBP1#, DSTBN1# D[47:32]#, DBI2# DSTBP2#, DSTBN2# D[63:48]#, DBI3# DSTBP3#, DSTBN3#

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,

SLP#, STPCLK# FERR#/PBE#, IERR#, THERMTRIP#

PROCHOT#

VCC, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA, GTLREF[3:0], COMP[1:0], RESERVED, TESTHI[12:0], THERMDA, THERMDC, VCC_SENSE, VSS_SENSE, VCCVID, VCCVIDLB, BSEL[1:0], SKTOCC#, DBR# VIDPWRGD, BOOTSELECT, OPTIMIZED/COMPAT#, PWRGOOD

ADSTB1#

ADSTB0#

18 Datasheet

Table 5. Signal Characteristics

Electrical Specifications

Signals with R

A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BNR#, BOOTSELECT DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#, OPTIMIZED/COMPAT# RS[2:0]#, RSP#, TRDY#

BSEL[1:0], VID[5:0], THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#, BR0#, TDO

NOTES:

1. The OPTIMIZED/COMP AT# and BOOTSELECT pins have a 500–5000 Ω pull-up to V

2. Signals that do not have RTT, nor are actively driven to their high-voltage level.

, BPRI#, D[63:0]#, DBI[3:0]#,

, PROCHOT#, REQ[4:0]#,

Open Drain Signals

Table 6. Signal Reference Voltages

GTLREF VCC/2 V

BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#, BINIT#, BNR#, HIT#, HITM#, MCERR#, PROCHOT#, BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

NOTES:

1. These signals also have hysteresis added to the reference voltage. See Table 14 for more information.

A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[1:0], COMP[1:0], FERR#/PBE#, IERR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#, SKTOCC#, SLP#, SMI#, STPCLK#, TDO, TESTHI[12:0], THERMDA, THERMDC, THERMTRIP#, VID[5:0], VIDPWRGD, GTLREF[3:0], TCK, TDI, TRST#, TMS

Signals with No R

A20M#, IGNNE#, INIT#, PWRGOOD SMI#, STPCLK#, TCK

TDI

, SLP#,

, TMS1, TRST#

rather than RTT.

CCVID

VIDPWRGD, BOOTSELECT, OPTIMIZED/

COMPAT#

CCVID

2.6 Asynchronous GTL+ Signals

Legacy input signals (such as A20M#, IGNNE#, INIT#, SMI#, SLP#, and STPCLK#) use CMOS input buffers. All of these signals follow the same DC requirements as G TL+ signals; however, the outputs are not actively driven high (during a logical 0-to-1 transition) by the processor. These signals do not have setup or hold time specifications in relation to BCLK[1:0].

2.7 Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the processor be first in the TAP chain and followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage level. Similar considerations must be made for TCK, TMS, TRST#, TDI, and TDO. Tw o copies of each signal may be required, with each driving a different voltage level.

Datasheet 19

Electrical Specifications

2.8 FSB Frequency Select Signals (BSEL[1:0])

The BSEL[1:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]).

Table 7 defines the possible combinations of the signals and the frequency associated with each

combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency.

The processor operates at a 533 MHz or 80 0 MHz FSB frequency (selected by a 133 MHz or 200 MHz BCLK[1:0] frequency). Individual processors will only operate at their specified FSB frequency.

For more information about these pins, refer to Section 4.2 and the appropriate platform design guide.

Table 7. BSEL[1:0] Frequency Table for BCLK[1:0]

BSEL1 BSEL0 Function

L L RESERVED

L H 133 MHz H L 200 MHz H H RESERVED

20 Datasheet

Electrical Specifications

2.9 Absolute Maximum and Minimum Ratings

Table 8 specifies absolut e m aximum and minimum ratings. Within functional operation limits,

functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and

minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute max im u m and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality nor longterm reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded.

Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields.

Table 8. Processo r DC Absolute Maximum Ratings

Symbol Parameter Min Max Unit Notes

TSTORAGE Processor storage temperature –40 +85 °C

NOTES:

1. For functional operation, all processor electrical, signal quality, mechanical, and thermal specifications must be satisfied.

2. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the longterm reliability of the device. For functional operation, refer to the processor case temperature specifications.

3. This rating applies to the processor and does not include any tray or packaging.

Any processor supply voltage with respect to V

Processor case temperature See Section 5 See Section 5 °C

2.10 Processor DC Specifications

The processor DC speci fications in this sectio n ar e de fined at th e pr oc essor co r e sili con and not at the package pins unless noted otherwise. See Chapter 4 for the pin signal definitions and signal

pin assignments. Most of the signals on the processor FSB are in the GTL+ signal group. The DC specifications for these signals are listed in Table 12.

Previously, legacy signals and Test Access Port (TAP) signals to the processor used low-voltage CMOS buffer types. However, these interfaces now follow DC specifications similar to GTL+. The DC specifications for these signal groups are listed in Table 13 and Table 14.

Table 9 through Table 17 list the DC specifications for the processor and are valid only while

meeting specifications for case temperature, clock frequency, and input voltages. Care should be taken to read all notes associated with each parameter.

- 0.3 1.55 V

2, 3 2, 3

MSR_PLATFORM_BRV bit 18 is a Platform Requirement Bit (PRB) that indicates that the processor has specific platform requirements.

Datasheet 21

Electrical Specifications

Table 9. Voltage and Current Specifications

Symbol Parameter Min Typ Max Unit Notes

VID range VID 1.250 1.400 V

VCC Loadline A processors

3.20E GHz (PRB = 1)

3.40E GHz (PRB = 1)

See Table 10 and

Figure 2

VID – I

(max) * 1.45 mΩ V

VCC Loadline B processors

2.80A/E GHz (PRB = 0)

3E GHz (PRB = 0)

3.20E GHz (PRB = 0)

See Table 11 and

Figure 3

VID – I

(max) * 1.45 mΩ V

3.40E GHz (PRB = 0)

for processor with multiple VID:

SGNT

SLP

TCC

CC_VCCA

CC_VCCIOPLL

CC_GTLREF

CC_VCCVID/

VCCVIDLB

2.80A/E GHz (PRB = 0) 3E GHz (PRB = 0)

3.20E GHz (PRB = 0)

3.40E GHz (PRB = 0)

3.20E GHz (PRB = 1)

3.40E GHz (PRB = 1)

Stop-Grant:

2.80A/E GHz (PRB = 0) 3E GHz (PRB = 0)

3.20E GHz (PRB = 0)

3.40E GHz (PRB = 0)

3.20E GHz (PRB = 1)

3.40E GHz (PRB = 1) ICC TCC active I ICC for PLL pins 60 mA ICC for I/O PLL pin 60 mA ICC for GTLREF pins (all pins) 200 µA

ICC for V

CCVID/VCCVIDLB

78 78 78

78 91 91

40 40 40

A 40 50 50

150 mA

NOTES:

1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data.

2. Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may ha ve different VID settings.

3. These voltages are targets only. A variable voltage source shoul d exist on systems in the event that a different voltage is required. See Section 2.3 and Table3 for more information.

4. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE pins at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.

5. Refer to Table 10/Figure 2 or Table 11/Figure 3 for the minimum, typical, and maximum V processor should not be subjected to any V V

should never exceed the VID voltage. Failure to adhere to this specification can shorten the processor lifetime.

6. I

7. The current specified is also for the AutoHALT State.

8. I

9. The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the as-

is specified at V

CC_MAX

Stop-Grant and ICC Sleep are specified at V

CC_MAX

sertion of PROCHOT# is the same as the maximum I

and ICC combination wherein VCC exceeds V

CC_MAX

for the processor.

allowed for a given current. The

for a given current. Moreover,

CC_MAX

3,4,5

7,8,10

9 10 10

22 Datasheet

10. These parameters are based on design characterization and are not tested.

Table 10. VCC Static and Transient Tolerance for Loadline A

Voltage Deviation from VID Setting (V)

Icc (A)

Maximum Voltage Typical Voltage Minimum Voltage

0 0.000 -0.019 -0.038

5 -0.007 -0.027 -0.047 10 -0.015 -0.035 -0.055 15 -0.022 -0.043 -0.064 20 -0.029 -0.051 -0.072 25 -0.036 -0.058 -0.081 30 -0.044 -0.066 -0.089 35 -0.051 -0.074 -0.098 40 -0.058 -0.082 -0.106 45 -0.065 -0.090 -0.115 50 -0.073 -0.098 -0.123 55 -0.080 -0.106 -0.132 60 -0.087 -0.114 -0.140 65 -0.094 -0.121 -0.149 70 -0.102 -0.129 -0.157 75 -0.109 -0.137 -0.166 80 -0.116 -0.145 -0.174 85 -0.123 -0.153 -0.183 90 -0.131 -0.161 -0.191 91 -0.132 -0.162 -0.193

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.11.

2. This table is intended to aid in reading discrete points on Figure 2.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE pins. V oltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Refer to the Voltage Regulator-Down (VRD) 10.0 Design Guide for socket loadline guidelines and VR implementation details for 478_VR_CONFIG_A.

Electrical Specifications

1,2,3

Datasheet 23

Electrical Specifications

Figure 2. VCC Static and Transient Tolerance for Loadline A

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 9

VID - 0.000

Vcc

Icc [A]

VID - 0.038

VID - 0.076

VID - 0.114

Vcc [V]

Maximum

Vcc

VID - 0.152

Typical

Vcc

Minimum

VID - 0.190

VID - 0.228

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.11.

2. This loadline specification shows the deviation from the VID set point.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE pins. V ol t age regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Refer to the Voltage Regulator-Down (VRD) 10.0 Design Guide for socket loadline guidelines and VR implementation details for 478_VR_CONFIG_A.

24 Datasheet

Table 11. VCC Static and Transient Tolerance for Loadline B

Voltage Deviation from VID Setting (V)

Icc (A)

Maximum Voltage Typical Voltage Minimum Voltage

0 0.000 -0.025 -0.050

5 -0.007 -0.033 -0.059 10 -0.015 -0.041 -0.068 15 -0.022 -0.049 -0.077 20 -0.029 -0.058 -0.086 25 -0.036 -0.066 -0.095 30 -0.044 -0.074 -0.104 35 -0.051 -0.082 -0.113 40 -0.058 -0.090 -0.122 45 -0.065 -0.098 -0.131 50 -0.073 -0.106 -0.140 55 -0.080 -0.114 -0.149 60 -0.087 -0.123 -0.158 65 -0.094 -0.131 -0.167 70 -0.102 -0.139 -0.176 75 -0.109 -0.147 -0.185 78 -0.113 -0.152 -0.190

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.11.

2. This table is intended to aid in reading discrete points on Figure 3.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE pins. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Refer to the Voltage Regulator-Down (VRD) 10.0 Design Guide for socket loadline guidelines and VR implementation details for 478_VR_CONFIG_B.

Electrical Specifications

1,2,3

Datasheet 25

+ 56 hidden pages

Intel SL8J6 - Pentium 4 Processor, Pentium 4 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1Introduction

1.1 Terminology

1.1.1 Processor Packaging Terminology

1.2 References

2 Electrical Specifications

2.1 Power and Ground Pins

2.2 Decoupling Guidelines

2.2.2 FSB GTL+ Decoupling

2.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking

2.3 Voltage Identification

2.3.1 Phase Lock Loop (PLL) Power and Filter

2.4 Reserved, Unused, and TESTHI Pins

2.5 FSB Signal Groups

2.6 Asynchronous GTL+ Signals

2.7 Test Access Port (TAP) Connection

2.8 FSB Frequency Select Signals (BSEL[1:0])

2.9 Absolute Maximum and Minimum Ratings

2.10 Processor DC Specifications