Intel SL8K2 - Pentium 4 3.20EGHz 800MHz 1MB Socket 478 CPU, SL79K - Pentium 4 2.80GHz 800MHz 1MB Socket 478 CPU, Pentium 4 Specification

Intel® Pentium® 4 Processor on 90 nm Process

Specification Update

September 2006

Notice: The Intel as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.

Pentium® processor may contain design defects or errors known

Document Number: 302352-031

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See

http:// www.intel.com/info/hyperthreading/

Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations. Intel Virtualization Technology-enabled BIOS and VMM applications are currently in development.

Δ Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See

Φ Intel drivers and applications enabled for Intel EM64T. Processor will not operate (including 32-bit operation) without an Intel EM64T-enabled BIOS. Performance will vary depending on your hardware and software configurations. See details on which processors support EM64T or consult with your system vendor for more information.

Not all specified units of this processor support Enhanced HALT State and Enhanced Intel SpeedStep® Technology. See the Processor Spec Finder at http://processorfinder.intel.com or contact your Intel representative for more information.

Intel, Pentium, Celeron, Xeon, Intel SpeedStep, Intel Core, VTune and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

Pentium® processor may contain design defects or errors known as errata which may cause the product to deviate from published

Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting HT Technology and a Hyper-Threading

for more information including details on which processors support HT Technology.

Extended Memory 64 Technology (Intel® EM64T) requires a computer system with a processor, chipset, BIOS, operating system, device

http://www.intel.com/products/processor_number for details.

www.intel.com/info/em64t for more information including

2 Intel

Pentium® 4 Processor on 90 nm Process Specification Update

Revision History..................................................................................................................4

Preface................................................................................................................................6

Summary Tables of Changes .............................................................................................8

General Information ..........................................................................................................21

Identification Information...................................................................................................23

Errata ................................................................................................................................30

Specification Changes......................................................................................................73

Specification Clarifications................................................................................................74

Documentation Changes ..................................................................................................75

Pentium® 4 Processor on 90 nm Process Specification Update 3

Intel

Revision History

Revision

Number

-001 • Initial Release June 2004

-002 • Added content for Intel® Pentium® 4 processor on 90 nm process

-003 • Repaired drawings in Figures 1 and 2; reformatted document

-004 • Separated the D0 column in Summary Tables of Changes into

-005 • Updated Processor Identification Table, and Summary Table of

-006 • Updated Processor Identification Table, and Summary Table of

-007 • Updated and sorted Processor Identification Table

-008 • Updated Processor Identification Table

-009 • Updated Processor Identification Table

-010 • Updated Processor Identification Table December 2004

-011 • Updated Processor Identification Table and Summary Table of

in 775-land package

• Added 775-land package processor upside marking diagram in Figure 2

• Added processor identification information for 775-land package to Table 1

• Notes added to clarify that C0 errata only apply to 478 pin package

• Modified for Processor Identification information Table Notes

layout

D0 and LD0 (L=LGA775) columns

• Updated errata R23 in summary table of changes

• Added errata R32-R38

Changes

• Added errata R39-R54

Changes

• Added E-stepping information

• Added errata R55-R68

• Added errata R69-R74

• Added errata R75-R77

• Added errata R78, R79

Changes

• Added errata R80, R81, and R82

Description Date

“Out-of-Cycle”

June 21 2004

“Out-of-Cycle” June 22, 2004

Aug 2004

Sept 2004

Out of Cycle

9/23/2004

October 2004

November 2004

December 2004

January 2005

4 Intel

Pentium® 4 Processor on 90 nm Process Specification Update

Revision History

Revision

Number

-012 • Updated Processor Identification Table and its notes and

-013 • Updated Processor Identification Table, and Summary Table of

-014 • Updated Processor Identification Table, and Summary Table of

-015 • Updated Summary Table of Changes, and affected documents

-016 • Updated R32 in Summary Table of Changes May 2005

-017 • Updated affected documents, added/updated 5x1 and 670 part

-018 • Updated errata R36 and R41, and added specification changes

-019 • Added erratum R92 and updated related document July 2005

-020 • Added erratum R93, and updated processor identification table August 2005

-021 • Added errata R94, R95, and updated processor identification

-022 • Added G1-stepping info, updated processor identification table

-023 • Added R0-stepping info, updated affected document, updated

-024 • Updated summary table of changes, updated processor

-025 • Updated erratum R17 and added errata R111-R114, updated

-026 • Updated related documents, updated processor identification

-027 • Added errata R116, R117 March 2006

-028 • Added errata R118, R119, R120 April 2006

-029 • Added erratum R121 May 2006

-030 • Added erratum R122, updated processor identification table June 2006

-031 • Updated R93, added R123, and updated processor identification

updated summary table of changes

• Added errata R83, R84, R85

Changes, and processor upside marking for 660, 650, 640, and

630

processor

• Added N-stepping information

• Added Errata R86

Changes

• Added Errata R87, R88, R89, R90

• Updated R31, R37, and added R91

and processor upside marking, updated processor identification table,

R1, and updated processor identification table

table

and added errata R96, R97, R98

processor identification table and added errata R99-R109

identification table and added erratum R110

processor identification table, updated figure 3 and figure 4 to show Pb-free marking

table, added erratum R115

table

Description Date

February 2005

“Out of Cycle”

February 22, 2005

March 2005

April 2005

“Out of Cycle” May

26, 2005

June 2005

September 2005

October 2005

“Out of Cycle”

November 14, 2005

December 2005

January 2006

February 2006

September 2006

Pentium® 4 Processor on 90 nm Process Specification Update 5

Intel

Preface

This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.

Information types defined in the Nomenclature section of this document are conso lidated into this update document and are no longer published in other documents. This document may also contain information that has not been previously published.

It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. It contains S-Specs, Errata, Documentation Changes, Specification Clarifications and Specification Changes.

Affected Documents

Document Title Document Number

Intel® Pentium® 4 Processor on 90 nm Process Datasheet 300561-003

Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531 and 520/521 Datasheet On 90 nm Process in 775-land LGA Package and supporting Intel

Intel® Pentium® 4 Processor 6xxΔ Sequence and Intel® Pentium® 4

Processor Extreme Edition Datasheet On 90 nm Process in the 775-

land LGA Package and supporting Intel TechnologyΦ , and supporting Intel

Extended Memory 64 TechnologyΦ

Nomenclature

S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics, e.g., core speed, L2 cache size, package type, etc. as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number

Errata are design defects or errors. Errata may cause the Intel deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

Specification Changes are modifications to the current published specifications. These changes will be incorporated in the next release of the specifications.

Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorp orated in the next release of the specifications.

Pentium® processor’s behavior to

Documentation Changes include typos, errors, or omissions from the current published specifications. These changes will be incorporated in the n ext release of the specifications.

Pentium® 4 Processor on 90 nm Process Specification Update 7

Intel

Summary Tables of Changes

The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that apply to Pentium 4 processors on 90 nm process. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or specification changes as noted. This table uses the following notations:

Codes Used in Summary Table

Stepping

X: Erratum, Specification Change or Clarification that applies to

this stepping.

(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification change

does not apply to listed stepping.

Status

Doc: Document change or update that will be implemented. Plan Fix: This erratum may be fixed in a future stepping of the product. Fixed: This erratum has been previously fixed. No Fix: There are no plans to fix this erratum. PKG: This column refers to errata on the Intel

processor on 90 nm process substrate. AP: APIC related erratum. Shaded: This item is either new or modified from the previous version

of the document.

Note: Each Specification Update item is prefixed with a capital letter to distinguish the product. The key

below details the letters that are used in Intel’s microprocessor Specification Updates: A = Intel B = Mob ile Intel C = Intel D = Intel E = Intel F = Intel G = Intel H = Mobile Intel

K = Mobile Intel L = Intel M = Mobile Intel N = Intel

Pentium® II processor

Celeron® processor

Pentium® II Xeon® processor

Pentium® III processor

Pentium® processor Extreme Edition

Pentium® III Xeon® processor

300 MHz, and 266 MHz

Celeron® D processor

Pentium® 4 processor

Pentium® II processor

Celeron® processor at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz,

Pentium® III Processor – M

Celeron® processor

Pentium® 4

8 Intel

Pentium® 4 Processor on 90 nm Process Specification Update

Summary Tables of Changes

O = Intel P = Intel Q = Mobile Intel

R = Intel S = 64-bit Intel T = Mobile Intel U = 64-bit Intel V = Mobile Intel W = Intel X = Intel Y = Intel Z = Mobile Intel AA = Intel

AB = Intel AC = Intel AD = Intel AE = Intel

Xeon® processor MP

Xeon® processor

Pentium® 4 processor supporting Hyper-Threading Technology on 90-nm

process technology

Pentium® 4 processor on 90 nm process

Xeon® Processor with 800 MHz system bus

Pentium® 4 processor – M

Xeon® processor MP with up to 8MB L3 Cache

Celeron® M processor

Pentium® M processor on 90 nm process with 2-MB L2 cache

Pentium® M processor

Pentium® processor Extreme Edition and Intel® Pentium® D processor on 65nm

process

Pentium® 4 processor on 65 nm process

Celeron® Processor in 478 Pin Package

Celeron® D processor on 65 nm process

CoreTM Duo Processor and Intel® CoreTM Solo processor on 65nm process

Celeron® processor on 0.13 Micron Process in Micro-FCPGA Package

Pentium® 4 processor with 533 MHz system bus

NO. C01 D0 LD02 E0 LE02 G11 LG12 LN02 LR02 Plan ERRATA

R1 X X X X X X X X X

R2 X X X X X X X X X

R3 X X X X X X X X X

R4 X X X X X X X X X

R5 X X X X X X X X X

R6 X X X X X X X X X

R7 X X X X X X X X X

R8 X X X X X X X X X

R9 X X X X X X X X X

Transaction Is Not Retried after

Fix

BINIT#

Invalid Opcode 0FFFh Requires a

Fix

ModRM Byte Processor May Hang Due to

Speculative Page Walks to Non-

Fix

Existent System Memory Memory Type of the Load Lock

Different from Its Corresponding

Fix

Store Unlock Machine Check Architecture Error

Reporting and Recovery May Not

Fix

Work As Expected

Debug Mechanisms May Not

Fix

Function as Expected Cascading of Performance

Counters Does Not Work Correctly

Fix

When Forced Overflow Is Enabled

EMON Event Counting of x87

Fix

Loads May Not Work As Expected System Bus Interrupt Messages

without Data Which Receive a

Fix

HardFailure Response May Hang the Processor

Pentium® 4 Processor on 90 nm Process Specification Update 9

Intel

Summary Tables of Changes

NO. C01 D0 LD02 E0 LE02 G11 LG12 LN02 LR02 Plan ERRATA

The Processor Signals Page-Fault Exception (#PF) Instead of

R10 X X X X X X X X X

R11 X X X X X X X X X

R12 X X X X X X X X X

R13 X X X X X X X X X

R14 X X X X X X X X X

R15 X X X X X X X X X

R16 X X X X X X X X X

R17 X X X X X X X X X

R18 X Fixed

R19 X X X X X X X X X

R20 X Fixed

R21 X X X X X Fixed

R22 X X X Fixed

R23 X X X X X X X X X

Alignment Check Exception (#AC)

Fix

on an Unlocked CMPXCHG8B Instruction

FSW May Not Be Completely

Restored after Page Fault on

Fix

FRSTOR or FLDENV Instructions Processor Issues Inconsistent

Transaction Size Attributes for

Fix

Locked Operation When the Processor Is in the

System Management Mode (SMM),

Fix

Debug Registers May Be Fully Writeable

Shutdown and IERR# May Result

Due to a Machine Check Exception

Fix

on a Hyper-Threading Technology Enabled Processor

Processor May Hang under Certain

Frequencies and 12.5% STPCLK#

Fix

Duty Cycle System May Hang if a Fatal Cache

Error Causes Bus Write Line (BWL)

Transaction to Occur to the Same

Fix

Cache Line Address as an Outstanding Bus Read Line (BRL) or Bus Read-Invalidate Line (BRIL}

A Write to an APIC Registers

Sometimes May Appear to Have

Fix

Not Occurred Some Front Side Bus I/O

Specifications are not Met

Parity Error in the L1 Cache May

Fix

Cause the Processor to Hang BPM4# Signal Not Being Asserted

According to Specification Sequence of Locked Operations

Can Cause Two Threads to Receive Stale Data and Cause Application Hang

A 16-bit Address Wrap Resulting from a Near Branch (Jump or Call) May Cause an Incorrect Address to be Reported to the #GP Exception Handler

Bus Locks and SMC Detection May

Cause the Processor to Hang

Fix

Temporarily

10 Intel

Pentium® 4 Processor on 90 nm Process Specification Update

Summary Tables of Changes

NO. C01 D0 LD02 E0 LE02 G11 LG12 LN02 LR02 Plan ERRATA

PWRGOOD and TAP Signals

R24 X Fixed

R25 X X X Fixed

R26 X X X X X X X X X

R27 X X X X X X X X X

R28 X X X X X Fixed

R29 X X X X X X X X X

R30 X X X X X X X X X

R31 X X X X X X X X X

R32 X Fixed

R33 X Fixed

R34 X Fixed

R35 X Fixed

R36 X Fixed

R37 X X X X X X X X X

Maximum Input Hysteresis Higher Than Specified

Incorrect Physical Address Size Returned by CPUID Instruction

Incorrect Debug Exception (#DB)

May Occur When a Data Breakpoint

Fix

is set on an FP Instruction

xAPIC May Not Report Some Illegal

Fix

Vector Errors Enabling No-Eviction Mode (NEM)

May Prevent the Operation of the Second Logical Processor in a Hyper-Threading Technology Enabled Processor

Incorrect Duty Cycle is Chosen when On-Demand Clock

Modulation is Enabled in a

Fix

Processor Supporting HyperThreading Technology

Memory Aliasing of Pages as

Uncacheable Memory Type and

Fix

Write Back (WB) May Hang the System

Interactions Between the Instruction Translation Lookaside Buffer (ITLB)

and the Instruction Streaming Buffer

Fix

May Cause Unpredictable Software Behavior

STPCLK# Signal Assertion under Certain Conditions May Cause a System Hang

Missing Stop Grant Acknowledge Special Bus Cycle May Cause a System Hang

Changes to CR3 Register do not Fence Pending Instruction Page Walks

Simultaneous Page Faults at Similar Page Offsets on Both Logical Processors of a HyperThreading Technology Enabled Processor May Cause Application Failure

The State of the Resume Flag (RF Flag) in a Task-State Segment (TSS) May be Incorrect

Using STPCLK# and Executing

Code From Very Slow Memory

Fix

Could Lead to a System Hang

Pentium® 4 Processor on 90 nm Process Specification Update 11

Intel

Summary Tables of Changes

NO. C01 D0 LD02 E0 LE02 G11 LG12 LN02 LR02 Plan ERRATA

R38 X X X X X X X X X

R39 X X X X X X X X X

R40 X Fixed

R41 X Fixed

R42 X X X X X X X X X

R43 X X X X X X X X X

R44 X X X X X X X X X

R45 X X X X X X X Fixed

R46 X X X Fixed

R47 X X Fixed

R48 X Fixed

R49 X X Fixed

R50 X Fixed

R51 X Fixed

R52 X X X Fixed

R53 X X X X Fixed

Processor Provides a 4-Byte Store

Fix

Unlock After an 8-Byte Load Lock Data Breakpoints on the High Half

of a Floating Point Line Split may

Fix

not be Captured CPUID Instruction May Report

Incorrect L2 Associativity in Leaf 0x80000006

The FP_ASSIST EMON Event May Return an Incorrect Count

Machine Check Exceptions May not

Update Last-Exception Record

Fix

MSRs (LERs) MOV CR3 Performs Incorrect

Reserved Bit Checking When in

Fix

PAE Paging Stores to Page Tables May Not Be

Visible to Pagewalks for

Subsequent Loads Without

Fix

Serializing or Invalidating the Page Table Entry

Execution of IRET or INTn Instructions May Cause Unexpected System Behavior

A Split Store Memory Access May Miss a Data Breakpoint

EFLAGS.RF May be Incorrectly Set After an IRET Instruction

Read for Ownership and Simultaneous Fetch May Cause the Processor to Hang

Writing the Echo TPR Disable Bit in IA32_MISC_ENABLE May Cause a #GP Fault

Cache Lock with Simultaneous Invalidate external snoop and SMC check May Cause the Processor to Hang

IRET Instruction Performing Task Switch May Not Serialize the Processor Execution

Incorrect Access Controls to MSR_LASTBRANCH_0_FROM_LI P MSR Registers

Recursive Page Walks May Cause a System Hang

12 Intel

Pentium® 4 Processor on 90 nm Process Specification Update

Summary Tables of Changes

NO. C01 D0 LD02 E0 LE02 G11 LG12 LN02 LR02 Plan ERRATA

WRMSR to bit[0] of IA32_MISC_ENABLE Register

R54 X5 X X Fixed

R55 X5 X5 X X Fixed

R56 X X Fixed

R57 X X Fixed

R58 X X X X X

R59 X X X X X

R60 X X X X X

R61 X X X X X

R62 X Fixed

R63 X X X X

R64 X Fixed

Changes Only One Logical Processor on a Hyper-Threading Technology Enabled Processor

VERR/VERW Instructions May Cause #GP Fault when Descriptor is in Non-canonical Space

The Base of a Null Segment May be Non-zero on a Processor Supporting Intel® Extended Memory 64 Technology (Intel® EM64T)Φ

Upper 32 Bits of FS/GS with Null Base May not get Cleared in Virtual-8086 Mode on Processors with Intel® Extended Memory 64 Technology (Intel® EM64T) Enabled

Processor May Fault when the Upper 8 Bytes of Segment Selector

is Loaded From a Far Jump

Fix

Through a Call Gate via the Local Descriptor Table

Loading a Stack Segment with a Selector that References a Noncanonical Address can Lead to a

#SS Fault on a Processor

Fix

Supporting Intel® Extended Memory 64 Technology (Intel® EM64T)

FXRSTOR May Not Restore Noncanonical Effective Addresses on

Processors with Intel® Extended

Fix

Memory 64 Technology (Intel® EM64T) Enabled

A Push of ESP that Faults may

Fix

Zero the Upper 32 Bits of RSP Enhanced Halt State (C1E) Voltage

Transition May Affect a System’s Power Management in a HyperThreading Technology Enabled Processor

Enhanced Halt State (C1E) May

Not Be Entered in a Hyper-

Fix

Threading Technology Enabled Processor

When the Execute Disable Bit Function is Enabled a Page-fault in a Mispredicted Branch May Result in a Page-fault Exception

Pentium® 4 Processor on 90 nm Process Specification Update 13

Intel

Summary Tables of Changes

NO. C01 D0 LD02 E0 LE02 G11 LG12 LN02 LR02 Plan ERRATA

R65 X Fixed

R66 X Fixed

R67 X Fixed

R68 X Fixed

R69 X X X X X X X X X

R70 X X X X X X X X X

R71 X Fixed

R72 X X X X X X X X X

R73 X X X Fixed

R74 X X X X X X X X X

R75 X X X X

R76 X X X Fixed

Execute Disable Bit Set with AD Assist Will Cause Livelock

The Execute Disable Bit Fault May be Reported Before Other Types of Page Fault When Both Occur

Writes to IA32_MISC_ENABLE May Not Update Flags for Both Logical Processors Threads

Execute Disable Mode Bit Set with CR4.PAE May Cause Livelock

Checking of Page Table Base

Address May Not Match the

Fix

Address Bit Width Supported by the Platform

The IA32_MCi_STATUS MSR May

Improperly Indicate that Additional

Fix

MCA Information May Have Been Captured

Execution of an Instruction with a Code Breakpoint Inhibited by the RF (Resume Flag) Bit May be Delayed by an RFO (Request For Ownership) from Another Bus Agent

With TF (Trap Flag) Asserted, FP Instruction That Triggers an

Unmasked FP Exception May Take

Fix

Single Step Trap Before Retirement of Instruction

MCA Corrected Memory Hierarchy Error Counter May Not Increment Correctly

BTS(Branch Trace Store) and

PEBS(Precise Event Based

Fix

Sampling) May Update Memory outside the BTS/PEBS Buffer

The Base of an LDT (Local Descriptor Table) Register May be Non-zero on a Processor

Fixed

Supporting Intel® Extended Memory 64 Technology (Intel® EM64T)

L-bit of the CS and LMA bit of the IA32_EFER Register May Have an Erroneous Value For One Instruction Following a Mode Transition in a Hyper-Threading Enabled Processor Supporting Intel® Extended Memory 64 Technology (Intel® EM64T).

14 Intel

Pentium® 4 Processor on 90 nm Process Specification Update

Summary Tables of Changes

NO. C01 D0 LD02 E0 LE02 G11 LG12 LN02 LR02 Plan ERRATA

Memory Ordering Failure May Occur with Snoop Filtering Third

R77 X X X X X X X X X

R78 X X X X X X X X X

R79 X X X X Fixed

R80 X X X X X

R81 X X X X Fixed

R82 X X X X Fixed

R83 X X X X

R84 X X X X X X X X Fixed

R85 X Fixed

R86 X X X X X Fixed

Party Agents after Issuing and

Fix

Completing a BWIL (Bus Write Invalidate Line) or BLW (Bus Locked Write) Transaction

Control Register 2 (CR2) Can be

Updated during a REP

Fix

MOVS/STOS Instruction with Fast Strings Enabled

TPR (Task Priority Register) Updates during Voltage Transitions of Power Management Events May Cause a System Hang

REP STOS/MOVS Instructions with

RCX >=2^32 May Cause a System

Fix

Hang An REP MOVS or an REP STOS

Instruction with RCX >= 2^32 May Fail to Execute to Completion or May Write to Incorrect Memory Locations on Processors Supporting Intel® Extended Memory 64 Technology (Intel® EM64T)

An REP LODSB or an REP LODSD or an REP LODSQ Instruction with RCX >= 2^32 May Cause a System Hang on Processors Supporting Intel® Extended Memory 64 Technology (Intel® EM64T)

A Data Access which Spans Both

the Canonical and the Non-

Fix

Canonical Address Space May Hang the System

Running in SMM (System Management Mode) And L1 Data Cache Adaptive Mode May Cause Unexpected System Behavior when SMRAM is Mapped to Cacheable Memory

CPUID Instruction Incorrectly Reports CMPXCH16B as Supported

Unaligned PDPTR (Page-DirectoryPointer) Base with 32-bit Mode PAE (Page Address Extension) Paging May Cause Processor to Hang

Pentium® 4 Processor on 90 nm Process Specification Update 15

Intel

Summary Tables of Changes

NO. C01 D0 LD02 E0 LE02 G11 LG12 LN02 LR02 Plan ERRATA

FXSAVE Instruction May Result in Incorrect Data on Processors

R87 X Fixed

R88 X Fixed

R89 X Fixed

R90 X Fixed

R91 X X X X X

R92 X X X X X X X X Fixed

R93 X X X X X X X X X

R94 X X X X X X X X X

R95 X X X X X X X X X

R96 X Fixed

R97 X5 X5 X5 X5 X5 X5 X5 X5 X

Supporting Intel® Extended Memory 64 Technology (Intel® EM64T)

Compatibility Mode STOS Instructions May Alter RSI Register Results on a Processor Supporting Intel® Extended Memory 64 Technology (Intel® EM64T)

LDT Descriptor Which Crosses 16 bit Boundary Access Does Not Cause a #GP Fault on a Processor Supporting Intel® Extended Memory 64 Technology (Intel® EM64T)

Upper Reserved Bits are Incorrectly Checked While Loading PDPTR's on a Processor Supporting Intel® Extended Memory 64 Technology (Intel® EM64T)

A 64-Bit Value of Linear Instruction Pointer (LIP) May be Reported

Incorrectly in the Branch Trace

Fix

Store (BTS) Memory Record or in the Precise Event Based Sampling (PEBS) Memory Record

It is Possible That Two specific Invalid Opcodes May Cause Unexpected Memory Accesses

At Core-to-bus Ratios of 16:1 and

Above Defer Reply Transactions

Fix

with Non-zero REQb Values May Cause a Front Side Bus Stall

The Processor May Issue Front

Side Bus Transactions up to 6

Fix

Clocks after RESET# is Asserted Front Side Bus Machine Checks

May be Reported as a Result of On-

Fix

Going Transactions during Warm Reset

CPUID Feature Flag Reports LAHF/SAHF as Unavailable however the Execution of LAHF/SAHF May Not Result in an Invalid Opcode Exception

The Processor May Issue Multiple

Code Fetches to the Same Cache

Fix

Line for Systems with Slow Memory

16 Intel

Pentium® 4 Processor on 90 nm Process Specification Update

Summary Tables of Changes

NO. C01 D0 LD02 E0 LE02 G11 LG12 LN02 LR02 Plan ERRATA

Writing the Local Vector Table

R98 X X X X X X X X X

R99 X

R100 X

R101 X

R102 X

R103 X

R104 X

R105 X

R106 X

R107 X

R108 X

R109 X

R110 X X X X X

(LVT) when an Interrupt is Pending

Fix

May Cause an Unexpected Interrupt

Access to an Unsupported Address Range in Uniprocessor (UP) or

Dual-processor (DP) Systems

Fix

Supporting Intel® Virtualization Technology May Not Trigger Appropriate Actions

VM Exit Due to a MOV from CR8

May Cause an Unexpected Memory

Fix

Access The Processor May Incorrectly

Respond to Machine Checks during

Fix

VM Entry/Exit Transitions INIT during String Operations in the

Virtual-Machine Extension (VMX)

Fix

Guest Mode May Cause Unexpected System Behavior

Power Down Requests May not be Serviced if a Power Down

Transition is Interrupted by an In-

Fix

Target Probe Event in the Presence of a Specific Type of VM Exit

VM EXIT Due to TPR shadow

Below Threshold May Improperly

Fix

Set and Cause "Blocking by STI" actions

VM Entry/Exit Writes to

LSTAR/SYSCALL_FLAG MSR's

Fix

May Cause Incorrect Data to be Written to Bits [63:32]

Machine Check Architecture

Multiple Data Parity Errors May be

Fix

Reported Attempting to Use an LDT Entry

when the LDTR Has Been Loaded

Plan

with an Unusable Segment May

Fix

Cause Unexpected Memory Accesses

The Execution of a VMPTRLD

Instruction May Cause an

Fix

Unexpected Memory Access The Execution of VMPTRLD or

VMREAD May Cause an

Fix

Unexpected Memory Access

IRET under Certain Conditions May

Cause an Unexpected Alignment

Fix

Check Exception

Pentium® 4 Processor on 90 nm Process Specification Update 17

Intel

Summary Tables of Changes

NO. C01 D0 LD02 E0 LE02 G11 LG12 LN02 LR02 Plan ERRATA

FS/GS Base MSRs can be Loaded

R111 X

R112 X

R113 X

R114 X Fixed

R115 X

R116 X X X X X X X X X

R117 X

R118 X

R119 X X X X X X X X X

R120 X X X X X X X X X

R121 X X X X X X X X X

R122 X X X X X X X X X

R123 X X X X X X X X X

from MSR-Load Areas during VM

Fix

Entry or VM Exit NMI-blocking Information Recorded

Plan

in VMCS May be Incorrect after a

Fix

#GP on an IRET Instruction VMLAUNCH/VMRESUME May Not

Plan

Fail when VMCS is Programmed to

Fix

Cause VM Exit to Return to a Different Mode

Upper 32 bits of ‘From’ Address Reported through LBR or LER MSRs, BTMs or BTSs May be Incorrect

VMEntry from 64-bit Host to 32-bit

Plan

Guest may Cause IERR# with

Fix

Hyper-Threading Enabled L2 Cache ECC Machine Check

Errors May be erroneously Reported

Fix

after an Asynchronous RESET# Assertion

VMExit after MOV SS and a Waiting

Plan

x87 Instruction May not Clear the

Fix

Interruptibility State in the VMM’s Working VMCS

VMCALL to Activate Dual-monitor

Plan

Treatment of SMIs and SMM

Fix

Ignores Reserved Bit settings in VM-exit Control Field

Using 2M/4M Pages When A20M#

Is Asserted May Result in Incorrect

Fix

Address Translations Writing Shared Unaligned Data that

Crosses a Cache Line without

Fix

Proper Semaphores or Barriers May Expose a Memory Ordering Issue

The IA32_MC0_STATUS and IA32_MC1_STATUS Overflow Bit is

not set when Multiple Un-

Fix

correctable Machine Check Errors Occur at the Same Time

Debug Status Register (DR6)

Breakpoint Condition Detected

Fix

Flags May be set Incorrectly A Continuous Loop Executing Bus

Lock Transactions on One Logical

Processor may Prevent Another

Fix

Logical Processor from Acquiring Resources

NOTES:

1. Only applies to Pentium

2. Prefix “L” denotes Pentium 4 processor on 90 nm Process in the 775-land LGA package

4 processor on 90 nm Process in the 478-pin package

18 Intel

Pentium® 4 Processor on 90 nm Process Specification Update

Summary Tables of Changes

3. This erratum applies to Pentium 4 processor supporting Intel® Extended Memory 64 Technology (Intel® EM64T) for Single-Processor Server/Workstation Platform configurations only. Non-server/workstation desktop configurations do not support the Intel Extended Memory 64 Technology.

4. This erratum does not apply to Pentium 4 processors for single-processor server/workstation platform configurations.

5. For these steppings, this erratum may be worked around in BIOS.

NO. SPECIFICATION CHANGES

R1 Land Assignment Specification Change

NO. SPECIFICATION CLARIFICATIONS

There are no Specification Clarification in this Specification Update revision

NO. DOCUMENTATION CHANGES

There are no documentation changes in this Specification Update revision

Pentium® 4 Processor on 90 nm Process Specification Update 19

Intel

Summary Tables of Changes

20 Intel

Pentium® 4 Processor on 90 nm Process Specification Update

General Information

Figure 1. Intel® Pentium® 4 Processor on 90 nm Process in the 478-pin Package

SSPEC/Country

Brand

of Assy

2-D Matrix Mark

m c

INTEL PENTIUM® 4 X.XXGHZ / 1M / 800 SLXXX MALAY BBBBBBBB

`03

AAAAAAAA NNNN

FPO

ATPO Serial #

Figure 2. Intel® Pentium® 4 Processors 570, 560, 550, 540, 530 and 520 Δ Supporting Hyper-

Threading Technology on 90 nm Process in the 775-Land LGA Package

Brand

SSPEC /Country of Assy

2-D Matrix Mark

INTEL m ‘04 Pentium 4

3.60GHZ/1M/800 SLxxx [COO] [FPO]

LOT S/N

Frequency/Cache/

Bus

Figure 3. Intel® Pentium® 4 Processors 571, 561, 551, 541, 531 and 521Δ Supporting Hyper-

Threading Technology on 90 nm Process in the 775-Land LGA Package

Pentium® 4 Processor on 90 nm Process Specification Update 21

Intel

General Information

Figure 4. Intel

Pentium® 4 Processor 670, 660, 650, 640, and 630Δ on 90 nm Process in the

775-Land LGA Package

Figure 5. Intel® Pentium® 4 Processor Extreme Edition on 90 nm Process in the 775-Land LGA

Package

22 Intel

Pentium® 4 Processor on 90 nm Process Specification Update

Identification Information

The Pentium 4 processor on 90 nm process can be identified by the following values:

Family1 Model2

1111b 0011b 1111b 0100b

NOTES:

1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.

2. The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan.

Table 1. Intel Information

S-Spec

SL7D7 C0 512K 0F33h 2.26GHz/533MHz

SL7FY C0 1M 0F33h 2.40GHz/800MHz

SL7E8 C0 1M 0F33h 2.40GHz/533MHz

SL7E9 C0 1M 0F33h 2.66GHz/533MHz

SL7D8 C0 1M 0F33h 2.80GHz/533MHz

SL79K C0 1M 0F33h 2.80GHz/800MHz

SL79L C0 1M 0F33h 3.00GHz/800MHz

SL79M C0 1M 0F33h 3.20GHz/800MHz

SL7B8 C0 1M 0F33h 3.20GHz/800MHz

SL7B9 C0 1M 0F33h 3.40GHz/800MHz

SL7AJ C0 1M 0F33h 3.40GHz//800MHz

Pentium® 4 Processor on 90 nm Process Processor Identification

Core

Stepping

L2 Cache

Size (bytes) CPUID Speed Core/Bus Package and Revision Notes

35.0 x 35.0 mm

FC-mPGA4 Rev 2.0

35.0 x 35.0 mm

FC-mPGA4 Rev 2.0

35.0 x 35.0 mm

FC-mPGA4 Rev 2.0

35.0 x 35.0 mm

FC-mPGA4 Rev 2.0

35.0 x 35.0 mm

FC-mPGA4 Rev 2.0

35.0 x 35.0 mm

FC-mPGA4 Rev 2.0

35.0 x 35.0 mm

FC-mPGA4 Rev 2.0

35.0 x 35.0 mm

FC-mPGA4 Rev 2.0

35.0 x 35.0 mm

FC-mPGA4 Rev 2.0

35.0 x 35.0 mm

FC-mPGA4 Rev 2.0

35.0 x 35.0 mm

FC-mPGA4 Rev 2.0

1, 4, 7, 19

2, 4, 7, 11

2, 4, 7

1, 4, 7, 19

2, 4, 7

2, 4, 7, 11

1, 4, 6, 11

2, 4, 6, 11

4, 6, 11

1, 4, 6, 11

Pentium® 4 Processor on 90 nm Process Specification Update 23

Intel

+ 52 hidden pages

Intel SL8K2 - Pentium 4 3.20EGHz 800MHz 1MB Socket 478 CPU, SL79K - Pentium 4 2.80GHz 800MHz 1MB Socket 478 CPU, Pentium 4 Specification

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Revision History

Preface

Affected Documents

Related Documents

Nomenclature

Summary Tables of Changes

Codes Used in Summary Table

Stepping

Status

General Information

Identification Information