Intel SL6NQ - Xeon 2.4 GHz/533MHz/512 KB CPU Processor 2.4GHz, SL6VP - Xeon 3.06 GHz Processor, Xeon Specification

Intel® Xeon® Processor
Specification Update
January 2007
Notice: The Intel may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update.
Xeon® processor may contain design defects or errors known as errata which
Document Number: 249678-057
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRA N TI ES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT.
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future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://deve loper.intel.com/design/litcentr. Intel®, the Intel® logo, Pentium®, Pentium® III Xeon™, Celer on, Intel® NetBurst™ and Intel® Xeon™ are trademarks or registered trademarks of
Intel® Corporation or its subsidiaries in the United S tates and other countries. Copyright © 2001-2005, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others.
2 Intel® Xeon® Processor Specification Update
Contents
Revision History .................................................................................................................5
Preface...............................................................................................................................9
Identification Information..................................................................................................10
Mixed Steppings in DP Systems......................................................................................18
Summary Table of Changes.............................................................................................20
Errata................................................................................................................................27
Specification Changes......................................................................................................51
Specification Clarifications ...............................................................................................53
Documentation Changes..................................................................................................56
Intel® Xeon® Processor Specification Update 3
4 Intel® Xeon® Processor Specification Update
Revision History
Version Description Date
-001 • Initial release. May 2001
-002 • Added errata P27-P28. June 2001
-003 • Updated erratum P25. June 2001
-004 • Added RCPPS, RCPSS, RSQRTPS and RSQRTSS instruction specification clarification.
-005 • Added errata P29-P32.
• Added Unused outputs specification clarifications.
-006 • Added errata P33-34.
• Production mark update to include 2D matrix.
-007 • Added 2 GHz frequency, D0 stepping and FC-BGA package information.
• Added DP Platform Population Matrix.
• Updated Summary of Errata table with applicable “Fixed” & “No Fix” errata plans.
• Updated errata P32.
-008 • Added Erratum P35.
• Updated Summary of Errata Table with latest errata status.
• Added Documentation Changes P1-P5.
-009 • Added errata P36 and P37.
• Added Documentation Change P6.
• Updated Summary Tables with latest errata and documentation changes.
-010 • Added Documentation Changes P7-P11.
• Added errata P38-P44.
• Added new processor with Processor Signature=0F24h B0 Step.
• Added new S-spec processors to Processor ID and DP Matrix tables.
• Added new package markings (Figs 3, 4) for 512KB Cache processor.
-011 • Corrected 3 mislabeled S-Spec Table parts. January 2002
-012 • Added erratum P45 to Processor ID Table. February 2002
-013 • Added errata P46 and P47.
• Added Documentation Changes P1-P6.
• Minor changes to “Fix” descriptions.
-014 • Added PWRGOOD Specification Change.
• Added errata P48.
• Updated errata P11.
• Added Specification Changes P1-P3.
• Added Documentation Changes P1-P3.
• Added new S-specs SL687 and SL65T to Processor ID table.
• Updated datasheet name to 2.40 GHz.
Revision History
July 2001
August 2001
September 2001
October 2001
November 2001
December 2001
January 2002
April 2002
May 2002
Intel® Xeon® Processor Specification Update 5
Revision History
-015 • Added erratum P49.
-016 • Added new erratum P50.
-017 • Edited DP Matrix table.
-018 • Added errata P51, P52. Edited erratum P14.
-019 • Edited erratum P35.
-020 • Added erratum P53.
-021 • Added reference to IA-32 Intel
-022 • Added erratum 054-055. January 2003
-023 • Added new errata P56, P57.
-024 • Added new errata P58 and P59.
-025 • Updated previous errata P55 and P58. April 2003
-026 • Added Specification Clarification P1-P4.
-027 • Added erratum P60.
Version Description Date
June 2002
• Updated errata P24, P40 status.
• Added Document Changes P1-P2. July 2002
• Added new Documentation Changes P3-P12.
• Edited Summary of Errata Table erratum P40 to Plan Fix.
• Minor edits to processor markings. August 2002
• Updated the Summary of Errata table w C1 Step info. September 2002
• Added Documentation Changes P3-P24.
• Added Specification Clarification P1.
• Added new C1 S-specs to Processor ID Info table. October 2002
• Removed erratum previously numbered P52 as not applicable. Added
new erratum P52.
• Added Documentation Changes P25-P32. November 2002
• Added new Specification Change P1.
• Added new Specification Clarification P2.
• Deleted old Documentation Changes.
• Deleted old Specification Changes
®
• Added new Processor (Intel
Xeon® Processor with 533 MHz Front
Side Bus.
• Added new processor with Processor Signature=0F27h C1 Step.
• Added New S-specs to the processor ID table.
• All References to CPUID are now renamed Processor Signature.
®
Architecture Software Developer’s
December 2002
Manual.
February 2003
• Added boxed processors S-Specs for 400 MHz FSB with the
frequencies: 1.80, 2, 2.20 and 2.40 GHz.
March 2003
• Updated previous errata fixing status, P55.
• Updated the name of the datasheet reference.
• Added S-Spec #SL6RR, SL6GH.
May 2003
®
• Added Low Voltage Intel
Xeon® Processor Specifications.
June 2003
®
• Updated Sections with Low Voltage Intel
Xeon® Processor
Datasheets.
• Updated erratum P53.
6 Intel® Xeon® Processor Specification Update
Revision History
Version Description Date
-028 • Added new Processor Intel® Xeon® Processor with 1-MB L3 Cache with Processor Signature=0F25H (M0 Stepping).
• Added New S-specs to the processor ID table for 0F25H (M0 Stepping) and 0F29h (D1 Stepping).
• Added new processor with Processor Signature=0F29H (D1 Stepping).
®
• Updated DP Platform Population Matrix for the Intel
Xeon® Processor
to include 0F25H and 0F29H.
• Removed Specification Clarification P3.
• Updated erratum P30 – Title Correction.
-029 • Updated errata P54 and P56. August 2003
-030 • Added erratum P64.
• Updated erratum P9, P22, P39.
®
-031 • Added new Processor - Intel
Xeon® Processor with 1-MB L3 Cache
at 3.20 GHz with Processor Signature=0F25H (M0 Stepping).
®
• Added New S-specs - Intel
Xeon® Processor with 1-MB L3 Cache at
3.20 GHz.
-032 • Added erratum P65.
• Removed Specification Clarification P4.
• Added S-spec SL74T.
-033 • Added erratum P66.
• Updated erratum P65.
-034 • Added Specification Clarification P3. December 2003
®
-035 • Added new Processor Intel
Xeon® Processor with 2-MB L3 Cache
with Processor Signature=0F25H (M0 Stepping).
-036 • Added errata P67 and P68.
• Added Specification Change P1.
-037 • Updated errata P26 and P66. April 2004
-038 • Updated errata P10 and P48.
• Added erratum P69.
• Added S-spec numbers SL7D5, SL7DG, SL7D4, and SL7DF to Processor ID table.
-039 • Added errata P70, P71, P72. June 2004
-040 • Updated affected documents listed under Preface, Specification Changes, Specification Clarifications, and Documentations Changes.
-041 • Added erratum P73.
• Updated erratum P54.
-042 • Updated erratum 72 in the Errata Summary Table. August 2004
-043 • Added errata P74-P75. September 2004
-044 • Added erratum P76. September 2004
-045 • Added errata P77-P79. October 2004
-046 • Added erratum P80. November 2004
-047 • Added erratum P81. December 2004
-048 • Added Specification Clarification P2. April 2005
-049 • Updated related documents list July 2005
-050 • Added Erattum P82.
• Updated codes used in summary table.
July 2003
September 2003
October 2003
October 2003
November 2003
February 2004
March 2004
May 2004
July 2004
August 2004
October 2005
Intel® Xeon® Processor Specification Update 7
Revision History
-051 • Updated erratum P53 and added erratum P83. January 2006
-052 • Updated links to Software Developers Manuals. Added s-spec SL8TJ. March 2006
-053 • Added S-specs SL8TK, SL8TL, SL8SE and SL8TH. April 2006
-054 • Updated Summary Table of Changes.
-055
Version Description Date
October 2006
• Updated the Software Developer Manual Name.
• Made changes to the DP Platform Population Matrix.
November 2006
-056
-057 • Updated Summary Table of Changes. January 2007
• Updated Summary Table of Changes.
December 2006
8 Intel® Xeon® Processor Specification Update
Preface
This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Information types defined in the Nomenclature section of this document are consolidated into this update document and are no longer published in other documents. This document may also contain information that has not been previously published.
Affected/Related Documents
Document Title Document Number
®
Intel
Xeon® Processor at 1.40 GHz, 1.50 GHz, 1.70 and 2 GHz Datasheet 249665
®
Xeon® Processor with 512 KB L2 Cache at 1.80 GHz to 3.0 GHz Datasheet 298642
Intel
®
Xeon® Processor with 533 MHz Front Side Bus at 2 GHz to 3.20 GHz Datasheet 252135
Intel
®
Low Voltage Intel
®
64 and IA-32 Intel® Architectures Software Developer’s Manual, Volumes 1, 2A,
Intel 2B, 3A, and 3B
Xeon® Processor at 1.60 GHz, 2.0 GHz, and 2.4 GHz Datasheet 273766
Preface
253665, 253666,
253667, 253668 and
253669,
respectively
Nomenclature
S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics, e.g., core speed, L2 cache size, package type, etc., as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number.
Errata are design defects or errors. Errata may cause the Intel deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.
Specification Changes are modifications to the current published specifications. These changes will be incorporated in the next release of the specifications.
Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in the next release of the specifications.
Documentation Changes include typos, errors, or omissions from the current published specifications. These changes will be incorporated in the next release of the specifications.
Intel® Xeon® Processor Specification Update 9
®
Xeon® processor’s behavior to
Identification Information
Identification Information
Intel® Xeon® Processor Markings, 256-KB Cache (603-pin Interposer INT-mPGA Package)
Figure 1. Top Side Processor Marking
2D Matrix
OR
Intel® Xeon™ i(m) ©’01
Dynamic Laser
Mark Area
D0096109 0032
ATPO Mark
(8 Characters)
Serial Number
Mark
(4 digits)
Figure 2. Bottom Side Processor Marking
S-Spec
Country of
Assy
Dynamic Laser
Mark Area
Speed / Cache / Bus / Voltage
1700DP/256/400/1.7V SL56N COSTA RICA
C0096109-0021
FPO – Serial #
(13 Characters)
10 Intel® Xeon® Processor Specification Update
Identification Information
Intel® Xeon® Processor, 512-KB Cache, 400 and 533 MHz FSB Markings, (603-pin Interposer INT-mPGA Package and 604-pin Fc-mPGA2 Package)
Figure 3. Top Side Processor Marking
Intel® Xeon™
i m c ‘02
2D Matrix Includes ATPO and Serial Number (front end mark)
Figure 4. Bottom Side Processor Marking
S-Spec
Country of
Assy
Dynamic Laser
Mark Area
Speed / Cac he / Bus / Voltage
1800DP/512/400/1.5V SL5Z8 COSTA RICA
C0096109-0021
FPO – Serial #
(13 Characters)
Intel® Xeon® Processor Specification Update 11
Identification Information
Figure 5. Example of Production Mark – Top View
Top View
Intel® Xeon™ i m c ‘01
Figure 6. Example of Production Mark – Bottom View
Brand Copyright information
2D Matrix Includes ATPO and Serial Number (front end mark)
Pin A1 Triangle
Bottom View
Product Code with feature infor m ation: Speed/cache/bus/ voltage
S-Spec and Assembly Site
1700DP/256L2/400/1.7V
SL56N COSTA RICA
C0096109-0021
FPO and Serial Number (End of Line M ark)
Pin A1 Triang le
The Intel Xeon processor can be identified by the following values:
1
Family
1111 0000 00001110 1111 0001 00001110 1111 0010 00001011
1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the Processor Signature instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.
2. The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX registe r after the Processor Signature 2 instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Bound ary Scan.
3. The Brand ID corresponds to bits [7:0] of the EBX register after the Processor Signat ure instruct ion is executed with a 1 in the EAX register.
12 Intel® Xeon® Processor Specification Update
Model
2
Brand ID
3
Identification Information
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the Processor Signature instruction is executed with a 2 in the EAX register . Please refer to the Intel Processor Identification and the Processor Signature Instruction Application Note (AP-485 ) for further information on the Processor Signature instruction.
Table 1. Intel
S-Spec
Number
SL4WX C1 0F0Ah 1.40/400 256-KB B0 603-pin micro-PGA
SL56G C1 0F0Ah 1.40/400 256-KB B0 603-pin micro-PGA
SL4WY C1 0F0Ah 1.50/400 256-KB B0 603-pin micro-PGA
SL4ZT C1 0F0Ah 1.50/400 256-KB B0 603-pin micro-PGA
SL56N C1 0F0Ah 1.70/400 256-KB B0 603-pin micro-PGA
SL56H C1 0F0Ah 1.70/400 256-KB B0 603-pin micro-PGA
SL5TD D0 0F12h 1.50/400 256-KB C0 603-pin micro-PGA
SL5U6 D0 0F12h 1.50/400 256-KB C0 603-pin micro-PGA
SL5TE D0 0F12h 1.70/400 256-KB C0 603-pin micro-PGA
SL5U7 D0 0F12h 1.70/400 256-KB C0 603-pin micro-PGA
SL5TH D0 0F12h 2/400 256-KB C0 603-pin micro-PGA
SL5U8 D0 0F12h 2/400 256-KB C0 603-pin micro-PGA
SL5Z8 B0 0F24h 1.80/400 512-KB 01 603-pin micro-PGA
SL622 B0 0F24h 1.80/400 512-KB 01 603-pin micro-PGA
SL5Z9 B0 0F24h 2/400 512-KB 01 603-pin micro-PGA
SL623 B0 0F24h 2/400 512-KB 01 603-pin micro-PGA
®
Xeon® Processor Identification and Package Information (Sheet 1 of 5)
Core
Stepping
Processor
Signature
Speed
Core/Front
Side Bus
(GHz/MHz)
L2 Size
(Kbytes)
L3 Size
(Kbytes)
Processor Interposer
Revision
Package and
Revision
interposer with 31 mm
OLGA rev 2.0
interposer with 31 mm
OLGA rev 2.0
interposer with 31 mm
OLGA rev 2.0
interposer with 31 mm
OLGA rev 2.0
interposer with 31 mm
OLGA rev 2.0
interposer with 31 mm
OLGA rev 2.0
interposer with 31 mm
FC-BGA package
interposer with 31 mm
FC-BGA package
interposer with 31 mm
FC-BGA package.0
interposer with 31 mm
FC-BGA package
interposer with 31 mm
FC-BGA package 0
interposer with 31 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
Notes
1, 4
1, 2, 4
1, 4
1, 2, 4
1, 4
1, 2, 4
1, 4
1, 2, 3,
4
1,4
1, 2, 3,
4
1, 3, 4
1, 2, 3,
4
1
1, 2
1
1, 2
Intel® Xeon® Processor Specification Update 13
Identification Information
Table 1. Intel® Xeon® Processor Identification and Package Information (Sheet 2 of 5)
S-Spec
Number
SL5ZA B0 0F24h 2.20/400 512-KB 01 603-pin micro-PGA
SL624 B0 0F24h 2.20/400 512-KB 01 603-pin micro-PGA
SL687 B0 0F24h 2.40/400 512-KB 01 603-pin micro-PGA
SL65T B0 0F24h 2.40/400 512-KB 01 603-pin micro-PGA
SL6EL C1 0F27H 1.80/400 512-KB 01 603-pin micro-PGA
SL6JX C1 0F27H 1.80/400 512-KB 01 603-pin micro-PGA
SL6EM C1 0F27H 2/400 512-KB 01 603-pin micro-PGA
SL6JY C1 0F27H 2/400 512-KB 01 603-pin micro-PGA
SL6EN C1 0F27H 2.20/400 512-KB 01 603-pin micro-PGA
SL6JZ C1 0F27H 2.20/400 512-KB 01 603-pin micro-PGA
SL6EP C1 0F27H 2.40/400 512-KB 01 603-pin micro-PGA
SL6K2 C1 0F27H 2.40/400 512-KB 01 603-pin micro-PGA
SL6EQ C1 0F27H 2.60/400 512-KB 01 603-pin micro-PGA
SL6K3 C1 0F27H 2.60/400 512-KB 01 603-pin micro-PGA
SL6M7 C1 0F27H 2.80/400 512-KB 01 603-pin micro-PGA
SL6MS C1 0F27H 2.80/400 512-KB 01 603-pin micro-PGA
SL6NP C1 0F27H 2/533 512-KB 01 604-pin micro-PGA
SL6NQ C1 0F27H 2.40/533 512-KB 01 604-pin micro-PGA
Core
Stepping
Processor
Signature
Speed
Core/Front
Side Bus
(GHz/MHz)
L2 Size
(Kbytes)
L3 Size
(Kbytes)
Processor Interposer
Revision
Package and
Revision
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
Notes
1
1, 2
1,2
2
2
2
2
2
2, 5
2, 5
14 Intel® Xeon® Processor Specification Update
Identification Information
Table 1. Intel® Xeon® Processor Identification and Package Information (Sheet 3 of 5)
S-Spec
Number
SL6NR C1 0F27H 2.66/533 512-KB 01 604-pin micro-PGA
SL6NS C1 0F27H 2.8/533 512-KB 01 604-pin micro-PGA
SL6RQ C1 0F27H 2/533 512-KB 01 604-pin micro-PGA
SL6GD C1 0F27H 2.40/533 512-KB 01 604-pin micro-PGA
SL6GF C1 0F27H 2.66/533 512-KB 01 604-pin micro-PGA
SL6GG C1 0F27H 2.8/533 512-KB 01 604-pin micro-PGA
SL6GH SL6RR
SL6GV C1 0F27H 1.60/400 512-KB 01 604-pin micro-PGA
SL6GV C1 0F27H 1.60/400 512-KB 01 604-pin micro-PGA
SL6W3
SL6YS
SL6W6
SL6YT
SL6W7
SL6YU
SL6W8
SL6YV
SL6W9 SL6YW
SL6WA
SL6YX
SL6WB
SL6YY SL6XK D1 0F29H 1.60/400 512-KB 01 604-pin micro-PGA
SL6XL D1 0F29H 2/400 512-KB 01 604-pin micro-PGA
Core
Stepping
C1 0F27H 3.06/533 512-KB 01 604-pin micro-PGA
D1 0F29H 1.80/400 512-KB 01 603-pin micro-PGA
D1 0F29H 2/400 512-KB 01 603-pin micro-PGA
D1 0F29H 2.20/400 512-KB 01 603-pin micro-PGA
D1 0F29H 2.40/400
D1 0F29H 2.60/400
D1 0F29H 2.8/0400
D1 0F29H 3/400
Processor
Signature
Speed
Core/Front
Side Bus
(GHz/MHz)
L2 Size
(Kbytes)
512-KB
512-KB
512-KB
512-KB
L3 Size
(Kbytes)
Processor Interposer
Revision
01 603-pin micro-PGA
01 603-pin micro-PGA
01 603-pin micro-PGA
01 603-pin micro-PGA
Package and
Revision
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 35 mm
FC-BGA package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
Notes
2, 5
2, 5
5
5
5
5
5, 6 2, 6
7
7
3 2
3 2
3 2
3 2
3 2
3 2
3, 6
2 7
7
Intel® Xeon® Processor Specification Update 15
Identification Information
Table 1. Intel® Xeon® Processor Identification and Package Information (Sheet 4 of 5)
S-Spec
Number
SL74T D1 0F29H 2.40/533 512-KB 01 604-pin micro-PGA
SL6VK SL6YM
SL6VL
SL6YN SL6VM
SL6NR SL6VN
SL6YQ SL6VP
SL6YR
SL73K SL72C
SL73L SL72D
SL73M
SL72E SL73N
SL72F SL73P
SL72G SL73Q
SL72Y
SL7AE SL7BW
SL7D5
SL7DG
SL7D4
SL7DF
SL8TJ L0 0F29h 0F29H 2.40/533 512-KB 01 604-pin micro-PGA
SL8TK L0 0F29H 2.80/533 512-KB 01 604-pin micro-PGA
Core
Stepping
D1 0F 29H 2/533 512-KB 01 604-pin micro-PGA
D1 0F 29H 2.40/533 512-KB 01 604-pin micro-PGA
D1 0F 29H 2.66/533 512-KB 01 604-pin micro-PGA
D1 0F29H 2.80/533
D1 0F29H 3.06/533
M0 0F25H 2/533
M0 0F25H 2.40/533
M0 0F25H 2.66/533
M0 0F25H 2.80/533
M0 0F25H 3.06/533
M0 0F25H 3.2/533
M0 0F25H 3.2/533
M0 0F25H 2.80/533
M0 0F25H 2.40/533
Processor
Signature
Speed
Core/Front
Side Bus
(GHz/MHz)
L2 Size
(Kbytes)
512-KB
512-KB
512-KB
512-KB
512-KB
512-KB
512-KB 1-MB
512-KB 1-MB
512-KB 2-MB
512-KB 1-MB
512-KB 1-MB
L3 Size
(Kbytes)
Processor Interposer
Revision
01 604-pin micro-PGA
01 604-pin micro-PGA
01 604-pin micro-PGA
01 604-pin micro-PGA
01 604-pin micro-PGA
01 604-pin micro-PGA
01 604-pin micro-PGA
01 604-pin micro-PGA
01 604-pin micro-PGA
01 604-pin micro-PGA 6
01 604-pin micro-PGA 6
Package and
Revision
interposer with 42.5 mm
FC-PGA2 package
Interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
Notes
7
5 2
5 2
5 2
5 2
5, 6
2 2
2
2
2
2, 6, 8
6, 8
2, 6, 8
6, 8
2, 6, 9
6
2, 6,8
2, 6, 8
7
5 2
16 Intel® Xeon® Processor Specification Update
Identification Information
Table 1. Intel® Xeon® Processor Identification and Package Information (Sheet 5 of 5)
S-Spec
Number
Core
Stepping
Processor
Signature
Core/Front
Side Bus
L2 Size
(Kbytes)
L3 Size
(Kbytes)
(GHz/MHz)
SL8TL L0 0F29H 2.40/533 512-KB 01 604-pin micro-PGA
SL8SE L0 0F29H 2/400 512-KB 01 604-pin micro-PGA
SL8TH L0 0F29H 1.60/400 512-KB 01 604-pin micro-PGA
Speed
Processor Interposer
Revision
Package and
Revision
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
interposer with 42.5 mm
FC-PGA2 package
Notes
5 2
7
7
NOTES:
1. The Intel
®
Xeon® processor listed here is installed onto a micro pin grid array (mPGA) interposer. The overall processor
package is called INT-mPGA.
2. These parts are Intel boxed processors.
3. FC-BGA packaging maintains form, fit, and functionality when compared to OLGA packaging. Users may notice a color change.
4. These parts require the inputs from A20M#, IGNNE#, LINT[1]/NMI and LINT[0]/INTR pins during RESET to set the correct core to bus frequency ratio.
5. These parts are the Intel
6. These parts have a VID of 1.525V.
7. These parts are the Low Voltage Intel
8. These parts are the Intel
9. These parts are the Intel
®
Xeon® Processor with 533 MHz Front Side Bus.
®
®
Xeon® Processor with 1-MB L3 Cache.
®
Xeon® Processor with 2-MB L3 Cache.
Xeon® Processor.
Intel® Xeon® Processor Specification Update 17
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