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SL3VS - Celeron 633 MHz Processor
Specification
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Intel SL3VS - Celeron 633 MHz Processor, Celeron Specification

Intel
®
Celeron
®
Processor
Specification Update
Release Date: August 2007
The Intel product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
®
Celeron® processor may contain design defects or errors known as errata, which may cause the
®
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Mobile Intel® Celeron® Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Pentium, Celeron, Intel Xeon and the Intel logo are trademarks or registered trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries*Other names and brands may be claimed as the property of others.
Copyright © 2007, Intel Corporation. All rights reserved.
PRODUCTS. NO LICENSE,
CONTENTS
REVISION HISTORY....................................................................................................................................... ii
PREFACE ....................................................................................................................................................... vi
®
Specification Update for the Intel
Celeron
GENERAL INFORMATION.............................................................................................................................. 1
Intel® Celeron® Processor and Boxed Intel® Celeron
Intel® Celeron® Processor and Boxed Intel® Celeron
Intel® Celeron® Processor and Boxed Intel® Celeron
IDENTIFICATION INFORMATION .................................................................................................................. 4
SUMMARY OF CHANGES............................................................................................................................ 11
Summary of Errata ..................................................................................................................................... 12
Summary of Documentation Changes .......................................................................................................21
Summary of Specification Clarifications..................................................................................................... 23
Summary of Specification Changes ........................................................................................................... 24
ERRATA ........................................................................................................................................................25
DOCUMENTATION CHANGES .................................................................................................................... 79
SPECIFICATION CHANGES......................................................................................................................... 99
®
Processor................................................................................... 1
®
Processor Markings (S.E.P. Package).................... 1
®
Processor Markings (PPGA Package).................... 2
®
Processor Markings (FC-PGA/FC-PGA2 Package) 3
i
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
REVISION HISTORY
Date of Revision Version Description
April 1998 -001 This document is the first Specification Update for the Intel®
May 1998 -002
June 1998 -003 Updated S-spec Table. Updated Summary Table of Changes.
July 1998 -004 Updated S-spec Table. Added Documentation Changes 13 through
August 1998 -005 Updated Summary Table of Changes. Changed numbering in order
September 1998 -006 Updated S-spec table. Updated Erratum 56. Added Errata 60
October 1998 -007 Implemented new numbering nomenclature. Updated Errata C1 and
November 1998 -008 Updated Erratum C23. Added Erratum C40. Updated Documentation
December 1998 -009 Added the Celeron processor (PPGA) markings. Added the Mb0
December 1998 -010
January 1999 -011 Added Erratum C3AP. Added Documentation Changes C19 and
February 1999 -012
March 1999 -013 Updated Processor Markings, Summary Table of Changes,
May 1999 -014 Updated the Processor Identification Information table. Added
June 1999 -015 Added Erratum C44. Added Documentation Change C1. Added
July 1999 -016
c
Celeron
Added Errata 24 through 28.
Updated Erratum 2 and 26. Added Errata 29 and 30. Added Documentation Changes 7 through 12. Added Specification Clarification 6 and 7.
16. Added Specification Clarifications 7 through 12. Added Specification Change 1.
to maintain consistency with other product Specification Updates. Updated Errata 6 and 38. Added Errata 56 through 59. Updated Specification Clarification 5.
through 62.
C27. Added Errata C37 through C39. Added Specification Clarification C15. Added Specification Change C2.
Change C10. Added Documentation Changes C17 and C18. Added Specification Change C3.
stepping to the Processor Identification Information table and the Table of Changes. Added Errata C41 and C42.
Updated Identification Information table
C20. Updated Processor Identification Information table.
Updated Processor Identification Information table.
Documentation Changes, Specification Clarifications, and Specification Changes sections. Added Specification Change C1.
Erratum C43.
Specification Clarifications C2 and C3. Added Specification Change C1.
Added Erratum C45.
processor.
ii
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
REVISION HISTORY
Date of Revision Version Description
August 1999 -017 Added Documentation Change C2. Updated Preface paragraph.
October 1999 -018 Added ‘Brand Id’ to Identification Information table. Updated
November 1999 -019
December 1999 -020 Added Errata C49. Added Documentation Change C4. Added
January 2000 -021
February 2000 -022 Added Documentation Change C6. Updated Summary of Changes
March 2000 -023 Updated Erratum C47. Updated the CPUID/Stepping information in
May 2000 -024 Updated the Intel® Celeron® Processor Identification Information
June 2000 -025
July 2000 -026
August 2000 -027 Updated Processor Identification Information table. Added Erratum
September 2000 -028 Updated the Intel® Celeron® Processor Identification Information
October 2000 -029 Added Erratum C74. Added Documentation Changes C9 and C10
November 2000 -030 Updated the Intel® Celeron® Processor Identification Information
December 2000 -031 Updated Specification Update product key to include the Intel®
January 2001 -032 Updated the Intel® Celeron® Processor Identification Information
February 2001 -033 Updated Documentation change C17. Added Documentation change
March 2001 -034 Updated Summary of Errata, Summary of Documentation Changes,
Updated Codes Used in Summary Table. Updated column heading in Errata, Documentation Changes, Specification Clarifications and Specification Changes tables.
Processor Identification Information Table. Added Errata C46.
Added Errata C47 and C48. Added Documentation Change C3.
Specification Clarification C4.
Added Errata C50 and C51. Added Documentation Change C5.
product letter codes.
the Summary of Changes section.
table. Added Errata C52 – C69. Updated the Summary of Errata,
Summary of Documentation Changes, Summary of Specification Clarifications and Summary of Changes tables. Added Specification
Change C2.
Added Specification Change C3.
Added Errata C70 and C71.
C72.
table. Added Erratum C73. Updated Errata C33 ,C47 and C51. Added Documentation changes C7 and C8.
table Added Errata C75 and C76.
Pentium® 4 processor, Updated Erratum C2. Added Documentation changes C11, C12, C13, C14, C15 and C16.
table, Updated Erratum C2. Added Documentation changes C17 and C18.
C19.
Summary of Specification Clarifications and Summary of Specification Changes tables. Added Errata C77 and C78.
iii
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
REVISION HISTORY
Date of Revision Version Description
July 2001 -035 Updated the Intel® Celeron® Processor Identification Information
August 2001 -036 Added Errata C79 and C80. Updated the Summary of changes
August 2001 -037 Out of cycle release. Updated the Intel® Celeron® Processor
October 2001 -038 Updated the identification information section with 0.13 micron
December 2001 -039 Added Documentation Changes C1, C2, C3, C4 and C5. Updated
January 2002 -040 Updated Processor Identification Information Table.
January 2002 -041 Added the 1A and 1.10A GHz specifications.
February 2002 -042 Added the 566 MHz at 1.75 VID specifications.
March 2002 -043 Updated Erratum C79. Added Erratum C83. Added Doc change C1.
April 2002 -044 Added Documentation change C1
May 2002 -045 Updated Erratum C67. Added Doc changes C1-C3. Updated
July 2002 -046 Added Erratum C84. Added Documentation Changes C1 - C12.
September 2002 -047 Updated Processor Identification Information Table. Updated
December 2006 -048 Added Erratum C85, C86, C87, C88, C89, C90, C91, C92, C93, C94,
January 2007 -049 Added Erratum C110.
table. Updated the Summary of Errata table.
section.
Identification Information table
Celeron processor details. Updated Processor Identification Information Table. Updated Summary of Errata Table. Updated Summary of Documentation Changes Table. Updated Summary of Specification Clarifications Table. Updated Summary of Specifications Changes Table. Added Errata C81 and C82.
Processor Identification Information Table.
Updated Processor Identification Information table.
Processor Identification Information Table.
Added/updated CPUID 0x6B4 processor.
Summary of Errata Table. Added Documentation Changes C3 – C24.
C95, C96, C97 C98, C99, C100, C101, C102, C103, C104, C105, C106, C107, C108, C109. Update Summary Table of Changes. Updated the names and document numbers of the Software Developers Manual. Updated Processor Identification Table.
May 2007 -050 Updated Summary Table of Changes.
iv
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
REVISION HISTORY
Date of Revision Version Description
August 2007 -051 Updated Summary Table of Changes. Added Erratum C111.
v
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
PREFACE
This document is an update to the specifications contained in the following documents:
®
• Pentium
• P6 Family of Processors Hardware Developer’s Manual (Order Number 244001)
• Intel
• Intel® 64 and Intel IA-32 Architectures Software Developer’s Manual, Volumes 1, 2-A, 2-B, 3-A and 3-B
(Document numbers 253665, 253666, 253667, 253668, and 253669, respectively.)
It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. It contains S-Specs, Errata, Documentation Changes, Specification Clarifications and, Specification Changes.
II Processor Developer’s Manual (Order Number 243502)
®
Celeron® Processor Datasheet (Document Number 243658)
Nomenclature
S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics, e.g., core speed, L2 cache size, package type, etc. as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number.
Errata are design defects or errors. Errata may cause the Celeron processor’s behavior to deviate from published specifications. Hardware and software designed to be used with any given processor must assume that all errata documented for that processor are present on all devices unless otherwise noted.
Documentation Changes include typos, errors, or omissions from the current published specifications. These changes will be incorporated in the next release of the specifications.
Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in the next release of the specifications.
Specification Changes are modifications to the current published specifications for the Celeron processor. These changes will be incorporated in the next release of the specifications.
vi
Specification Update for the Intel® Celeron® Processor
GENERAL INFORMATION
Intel® Celeron® Processor and Boxed Intel® Celeron® Processor Markings (S.E.P. Package)
Static White Silkscreen marks
®
FFFFFFFF SYYYY
266/66 COA
Dynamic laser mark area
NOTES:
• SYYYY = S-spec Number.
FFFFFFFF = FPO # (Test Lot Traceability #).
•
COA = Country of Assembly.
celeron ™
i m ©’98
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
Intel® Celeron® Processor and Boxed Intel® Celeron® Processor Markings (PPGA Package)
Top
Bottom
int l
e
celeron
AAAAAAAZZZ LLL SYYYY
Country of Origin
FFFFFFFF-XXXX
M C
’98
i
®
TM
NOTES:
AAAAAAA = Product Code
ZZZ = Processor Speed (MHz)
LLL = Integrated Level-Two Cache Size (in Kilobytes)
SYYYY = S-Spec Number
FFFFFFFF-XXXX = Assembly Lot Tracking Number
2-D Matrix Mark
Intel UCC# Order Code (Product - speed) S Number Lot Number (date, factory)
•
2
®
INTEL
CELERON® PROCESSOR SPECIFICATION UPDATE
Intel® Celeron® Processor and Boxed Intel® Celeron® Processor Markings (FC-PGA/FC-PGA2 Package)
FC-PGA 370 Pin Package
GRP1LN1: INTEL (m)(c) '01_-_{COO} GRP1LN2: {Core Freq}/{Cache}/{Bus Freq}/{Voltage}
GRP2LN1: {FPO}-{S/N} GRP2LN2: CELERON {S-Spec}
FC-PGA2 370 Pin Package
GRP1LN1 GRP1LN2
GRP2LN1 GRP2LN2
GRP1LN1: INTEL (m)(c) '01_-_{Country of Origin} GRP1LN2: {Core freq}/{Cache}/{Bus Freq}/{Voltage}
GRP2LN1: {FPO}-{S/N} GRP2LN2: CELERON {S-Spec}
3
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
IDENTIFICATION INFORMATION
Complete identification information of the Celeron processor can be found in the Intel Processor Identification
and the CPUID Instruction
The Celeron processor can be identified by the following values:
Family1 Model2 Brand ID3
0110 0101 00h = Not Supported
0110 0110 00h = Not Supported
0110 1000 01h = “Intel® Celeron® Processor”
0110 10114 03h = “Intel® Celeron® Processor”
NOTES:
1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.
2. The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan.
3. The Brand ID corresponds to bits [7:0] of the EBX register after the CPUID instruction is executed with a 1 in the EAX register.
4. This only applies to units with processor signature of 0x6B1.
The Celeron processor’s second level (L2) cache size can be determined by the following register contents:
0-Kbyte Unified L2 Cache1 40h
128-Kbyte Unified L2 Cache1 41h
256-Kbyte 8 way set associative 32byte line
NOTE:
1. When the EAX register contains a value of 2, the CPUID instruction loads the EAX, EBX, ECX and EDX registers with descriptors that indicate the processors cache and TLB characteristics. The lower 8 bits of the EAX register (AL) contain a value that identifies the number of times the CPUID has to be executed to obtain a complete image of the processor’s caching systems. The remainder of the EAX register, the EBX, ECX and EDX registers contain the cache and TLB descriptors. When bit 31 in a given register is zero, that register contains valid 8-bit descriptors. To decode descriptors, move sequentially from the most significant byte of the register down through the least significant byte of the register. Assuming bit 31 is 0, then that register contains valid cache or TLB descriptors in bits 24 through 31, bits 16 through 23, bits 8 through 15 and bits 0 through 7. Software must compare the value contained in each of the descriptor bit fields according to the definition of the CPUID instruction . For more details refer to the AP-485 Intel Processor Identification and the CPUID Instruction Application Note.
application note (Document Number 241618).
1
size, L2 Cache
82h
4
®
INTEL
S-Spec
Core
Stepping
Intel® Celeron® Processor Identification Information
L2 Cache
Size
(Kbytes)
CELERON® PROCESSOR SPECIFICATION UPDATE
Package
and
Revision
Notes
CPUID
Speed (MHz)
Core/Bus
SL2SY A0 0 0650h 266/66 SEPP Rev. 1
SL2YN A0 0 0650h 266/66 SEPP Rev. 1 1
SL2YP A0 0 0650h 300/66 SEPP Rev. 1
SL2Z7 A0 0 0650h 300/66 SEPP Rev. 1 1
SL2TR A1 0 0651h 266/66 SEPP Rev. 1
SL2QG A1 0 0651h 266/66 SEPP Rev. 1 1
SL2X8 A1 0 0651h 300/66 SEPP Rev. 1
SL2Y2 A1 0 0651h 300/66 SEPP Rev. 1 1
SL2Y3 B0 0 0652h 266/66
SL2Y4 B0 0 0652h 300/66
SL2WM A0 128 0660h 300A/66
SL32A A0 128 0660h 300A/66
SL2WN A0 128 0660h 333/66
SL32B A0 128 0660h 333/66
SEPP Rev. 1
SEPP Rev. 1
SEPP Rev. 1
SEPP Rev. 1
SEPP Rev. 1
SEPP Rev. 1
1
1
3
1
3
1
SL376 A0 128 0660h 366/66 SEPP Rev. 1
SL37Q A0 128 0660h 366/66 SEPP Rev. 1 1
SL39Z A0 128 0660h 400/66 SEPP Rev. 1
SL37V A0 128 0660h 400/66 SEPP Rev. 1 1
SL3BC A0 128 0660h 433/66 SEPP Rev. 1
SL39Z A0 128 0660h 400/66
SL37V A0 128 0660h 400/66
SL3BC A0 128 0660h 433/66
SL35Q B0 128 0665h 300A/66
PPGA
PPGA
PPGA
PPGA
SL35Q B0 128 0665h 300A/66 PPGA 2
SL36A B0 128 0665h 300A/66
PPGA
18
SL35R B0 128 0665h 333/66 PPGA 2
SL36B B0 128 0665h 333/66 PPGA
SL36C B0 128 0665h 366/66 PPGA
SL35S B0 128 0665h 366/66 PPGA 2
5
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
Intel® Celeron® Processor Identification Information
S-Spec
Core
Stepping
L2 Cache
Size
(Kbytes)
CPUID
Speed (MHz)
Core/Bus
Package
and
Revision
Notes
SL3A2 B0 128 0665h 400/66 PPGA
SL37X B0 128 0665h 400/66 PPGA 2
SL3BA B0 128 0665h 433/66 PPGA
SL3BS B0 128 0665h 433/66 PPGA 2
SL3EH B0 128 0665h 466/66 PPGA
SL3FL B0 128 0665h 466/66 PPGA 2
SL3FY B0 128 0665h 500/66 PPGA
SL3LQ B0 128 0665h 500/66 PPGA 2
SL3FZ B0 128 0665h 533/66 PPGA
SL3PZ B0 128 0665h 533/66 PPGA 2
SL46S B0 128 0683h 533A/66 FC-PGA
SL3W6 B0 128 0683h 533A/66 FC-PGA 2
SL46T B0 128 0683h 566/66 FC-PGA
SL3W7 B0 128 0683h 566/66 FC-PGA 2
SL4PC C0 128 0686h 566/66 FC-PGA 2, 7, 5
SL4NW
SL5L5
C0 128 0686h 566/66 FC-PGA 2, 7, 5
D0 128 068Ah 566/66 FC-PGA 7, 8
SL46U B0 128 0683h 600/66 FC-PGA
SL3W8 B0 128 0683h 600/66 FC-PGA 2
SL4PB
SL4NX
C0 128 0686h 600/66 FC-PGA 2, 7, 5
C0 128 0686h 600/66 FC-PGA 2, 7, 5
SL3VS B0 128 0683h 633/66 FC-PGA
SL3W9 B0 128 0683h 633/66 FC-PGA 2
SL4PA C0 128 0686h 633/66 FC-PGA 2, 6, 5
SL4NY C0 128 0686h 633/66 FC-PGA 2, 6, 5
SL48E B0 128 0683h 667/66 FC-PGA
SL4AB B0 128 0683h 667/66 FC-PGA 2
SL4P9 C0 128 0686h 667/66 FC-PGA 2, 6, 5
SL4NZ C0 128 0686h 667/66 FC-PGA 2, 6, 5
6
®
INTEL
CELERON® PROCESSOR SPECIFICATION UPDATE
Intel® Celeron® Processor Identification Information
S-Spec
Core
Stepping
L2 Cache
Size
(Kbytes)
CPUID
Speed (MHz)
Core/Bus
Package
and
Revision
Notes
SL48F B0 128 0683h 700/66 FC-PGA
SL4EG B0 128 0683h 700/66 FC-PGA 2
SL4P8 C0 128 0686h 700/66 FC-PGA 2, 4, 5
SL4P2 C0 128 0686h 700/66 FC-PGA 2, 4, 5
SL4P7 C0 128 0686h 733/66 FC-PGA 4, 5
SL4P3 C0 128 0686h 733/66 FC-PGA 2, 4, 5
SL52Y D0 128 068Ah 733/66 FC-PGA 4, 8
SL5E9 D0 128 068Ah 733/66 FC-PGA 2, 4, 8
SL4P6 C0 128 0686h 766/66 FC-PGA 4, 5
SL4QF C0 128 0686h 766/66 FC-PGA 2, 4, 5
SL52X D0 128 068Ah 766/66 FC-PGA 4, 8
SL5EA D0 128 068Ah 766/66 FC-PGA 2, 4, 8
SL4TF C0 128 0686h 800/100 FC-PGA 4, 5
SL45R C0 128 0686h 800/100 FC-PGA 2, 4, 5
SL54P D0 128 068Ah 800/100 FC-PGA 4, 8
SL5WC D0 128 068Ah 800/100 FC-PGA 4, 8
SL5EB D0 128 068Ah 800/100 FC-PGA 2, 4, 8
SL5WW D0 128 068Ah 800/100 FC-PGA 2, 4, 8
SL5GA C0 128 0686h 850/100 FC-PGA 4, 5
SL5GB C0 128 0686h 850/100 FC-PGA 2, 4, 5
SL54Q D0 128 068Ah 850/100 FC-PGA 4, 8
SL5EC D0 128 068Ah 850/100 FC-PGA 2, 4, 8
SL5LX D0 128 068Ah 900/100 FC-PGA 8, 9
SL5WA D0 128 068Ah 900/100 FC-PGA 8, 9
SL5MQ D0 128
SL5WY D0 128
SL633 D0 128 068Ah 900/100 FC-PGA2
SL5UZ D0 128 068Ah 950/100 FC-PGA
068Ah 900/100 FC-PGA 2, 8, 9
068Ah 900/100 FC-PGA 2, 8, 9
2,8,14
8, 10
SL5V2 D0 128 068Ah 950/100 FC-PGA 2, 8, 10
7
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
Intel® Celeron® Processor Identification Information
S-Spec
Core
Stepping
L2 Cache
Size
(Kbytes)
CPUID
Speed (MHz)
Core/Bus
Package
and
Revision
SL634 D0 128 068Ah 950/100 FC-PGA2
Notes
2,8,14
8
®
INTEL
S-Spec
Core
Stepping
Intel® Celeron® Processor Identification Information
L2 Cache
Size
(Kbytes)
CELERON® PROCESSOR SPECIFICATION UPDATE
Package
and
Revision
CPUID
Speed (MHz)
Core/Bus
SL5XT D0 128 068Ah 1 GHz/100 FC-PGA
SL5XQ D0 128 068Ah 1 GHz/100 FC-PGA 2, 8,11
SL5XU D0 128 068Ah 1.10
FC-PGA
GHz/100
SL5XR D0 128 068Ah 1.10
FC-PGA 2, 8,9
GHz/100
SL5VQ A1 256 06B1h 1.10A
FC-PGA2
GHz/100
SL5ZE A1 256 06B1h 1.10A
FC-PGA2
GHz/100
SL6CA B1 256 06B4h 1.10A
FC-PGA2 13, 15
GHz/100
SL6JR B1 256 06B4h 1.10A
FC-PGA2
GHz/100
SL5XS A1 256 06B1h 1.20
FC-PGA2
GHz/100
SL5Y5 A1 256 06B1h 1.20
FC-PGA2
GHz/100
SL656 A1 256 06B1h 1.20
FC-PGA2
GHz/100
SL68P A1 256 06B1h 1.20
FC-PGA2
GHz/100
SL6C8 B1 256 06B4h 1.20
FC-PGA2
GHz/100
SL6JS B1 256 06B4h 1.20
FC-PGA2
GHz/100
SL5VR A1 256 06B1h 1.30
FC-PGA2
GHz/100
SL5ZJ A1 256 06B1h 1.30
FC-PGA2
GHz/100
SL6C7 B1 256 06B4h 1.30
FC-PGA2
GHz/100
SL6JT B1 256 06B4h 1.30
FC-PGA2
GHz/100
SL64V A1 256 06B1h 1.40
FC-PGA2
GHz/100
SL68G A1 256 06B1h 1.40
FC-PGA2 2,14,15
GHz/100
Notes
8,11
8, 9
2,12,13
2,12,13
2,13, 15
12,13
2,12,13
15,17
2, 15, 17
15, 17
2,15, 17
15,16
2,15,16
15, 16
2,15, 16
14,15
9
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
Intel® Celeron® Processor Identification Information
L2 Cache
S-Spec
Core
Stepping
Size
(Kbytes)
CPUID
Speed (MHz)
Core/Bus
SL6C6 B1 256 06B4h 1.40
GHz/100
SL6JU B1 256 06B4h 1.40
GHz/100
SL6C5 B1 256 06B4h 1.50
GHz/100
SL6JV B1 256 06B4h 1.50
GHz/100
NOTES:
1. This is a boxed Celeron processor with an attached fan heatsink.
2. This is a boxed Celeron processor with an unattached fan heatsink.
3. This part also ships as a boxed Celeron processor with an attached fan heatsink.
4.
This part requires Tj of 80° C.
5. This part uses a V
6. This part will require Tj of 82C.
7. This part will require Tj of 90C.
8. This part uses a V
9.
This part has max Tj of 77° C.
10.
This part has max Tj of 79° C.
11.
This part has max Tj of 75° C.
12. This part uses a V
13. This part has max Tcase of 69 Deg C
14. This part has max Tcase of 72 Deg C
15. This part uses a V
16. This part has max Tcase of 71 Deg C
17. This part has max Tcase of 70 Deg C
18. This part has min Tcase of 5 deg C, max Tcase of 85 deg C and TDP of 17.8 W,
19. This part uses a V
CC
CORE
CC
CORE
CC
CORE
CC
CORE
CC
CORE
of 1.7 V.
of 1.75 V.
of 1.475 V.
of 1.5 V.
of 1.5V.
Package
and
Revision
FC-PGA2
FC-PGA2
Notes
14, 15
2,14, 15
FC-PGA2 1,3, 19
FC-PGA2 1,3, 19
10
®
INTEL
CELERON® PROCESSOR SPECIFICATION UPDATE
SUMMARY OF CHANGES
The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that apply to Celeron processors. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or specification changes as noted. This table uses the following notations:
X:
Change applies to the given processor stepping.
(No mark) or (blank box): This item is fixed in or does not apply to the given stepping.
Doc: Document change or update that will be implemented.
PlanFix: This erratum may be fixed in a future stepping of the product.
Fixed: This erratum has been previously fixed.
NoFix: There are no plans to fix this erratum.
Doc: Intel intends to update the appropriate documentation in a future revision.
AP: APIC related erratum.
PKG: This column refers to errata on the Intel® Celeron® processor substrate. Shaded: This item is either new or modified from the previous version of the document.
Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below
Specification Change, Erratum, Specification Clarification, or Documentation
details the letters that are used in Intel’s microprocessor Specification Updates: A = Dual-Core Intel
®
C = Intel D = Dual-Core Intel E = Intel F = Intel
Celeron® processor
®
Pentium® III processor
®
Pentium® processor Extreme Edition and Intel® Pentium® D processor I = Dual-Core Intel J = 64-bit Intel K = Mobile Intel
®
L = Intel M = Mobile Intel N = Intel O = Intel P = Intel
Celeron® D processor
®
Pentium® 4 processor
®
Xeon® processor MP
®
Xeon® processor Q = Mobile Intel
technology
®
R = Intel
Pentium® 4 processor on 90 nm process S = 64-bit Intel T = Mobile Intel U = 64-bit Intel V = Mobile Intel
®
W= Intel X = Intel Y = Intel Z = Mobile Intel AA = Intel AB = Intel
Celeron® M processor
®
Pentium® M processor on 90 nm process with 2 MB L2 Cache
®
Pentium® M processor
®
Pentium® D Processor 900 Sequence and Intel® Pentium® Processor Extreme Edition 955, 965
®
Pentium® 4 Processor 6x1 Sequence
®
Xeon® processor 7000 sequence
®
Xeon® Processor 2.80 GHz
®
Xeon® Processor
®
Xeon® processor MP with 1 MB L2 Cache
®
Pentium® III processor
®
Celeron® processor
®
Pentium® 4 processor supporting Hyper-Threading Technology on 90 nm process
®
Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions)
®
Pentium® 4 processor-M
®
Xeon® processor MP with up to 8 MB L3 Cache
®
Celeron® processor on .13 Micron Process in Micro-FCPGA Package
®
Pentium® 4 processor with 533 MHz system bus
11
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
®
AC = Intel AD = Intel AE = Intel AF = Dual-Core Intel AG = Dual-Core Intel
Celeron® Processor in 478 Pin Package
®
Celeron® D processor on 65 nm process
®
Core™ Duo Processor and Intel® Core™ Solo processor on 65 nm process
®
Xeon® processor LV
®
Xeon® Processor 5100 Series AH = Intel® Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor Technology AI = Intel
AJ = Quad-Core Intel AK = Intel AL = Dual-Core Intel AN = Intel AO = Quad-Core Intel AP = Dual-Core Intel AQ = Intel
®
Core™2 Extreme Processor X6800Δ and Intel® Core™2 Duo Desktop Processor E6000Δ and
Δ
Sequence
E4000
®
Core™2 Extreme quad-core processor QX6700Δ and Intel® Core™2 Quad processor Q6600Δ
®
Pentium® Dual-Core Processor
®
Pentium® Dual-Core Desktop Processor E2000Δ Sequence
®
Xeon® Processor 5300 Series
®
Xeon® Processor 7100 Series
®
Xeon® processor 3200 series
®
Xeon® Processor 3000 Series
AR = Intel® Celeron processor 500 series AS = Intel® Xeon® processor 7200, 7300 series
Summary of Errata
NO. CPUID/Stepping Plans ERRATA
650h
651h
660h
665h
683h
686h
68Ah
6B1h
6B4h
A0
A1
A0
B0
B0
C0
D0
A1
C1 X X X X X X X X X NoFix
B1
FP Data Operand Pointer may be incorrectly calculated after FP access which wraps 64-Kbyte boundary in 16-bit code
C2 X X X X X X X X X NoFix Differences exist in debug
exception reporting
C3 X X X X X X X X X NoFix Code fetch matching
disabled debug register may cause debug exception
C4 X X X X X X X X X NoFix FP inexact-result exception
flag may not be set
C5 X X X X X X X X X NoFix BTM for SMI will contain
incorrect FROM EIP
C6 X X X X X X X X X NoFix I/O restart in SMM may fail
after simultaneous MCE
C7 X X X X X X X X X NoFix Branch traps do not function
if BTMs are also enabled
C8 X X X X X X X X X NoFix Machine check exception
handler may not always execute successfully
C9 X X X X X X X X X NoFix LBER may be corrupted after
some events
C10 X X X X X X X X X NoFix BTMs may be corrupted
during simultaneous L1
12
®
INTEL
CELERON® PROCESSOR SPECIFICATION UPDATE
Summary of Errata
686h
68Ah
6B1h
6B4h
C0
D0
A1
B1
A0
651h
A1
660h
A0
665h
B0
683h
B0
NO. CPUID/Stepping Plans ERRATA
650h
cache line replacement
C11 X X X X Fixed Potential early deassertion of
LOCK# during split-lock cycles
C12 X X X X Fixed A20M# may be inverted after
returning from and Reset SMM
C13 X X Fixed Reporting of floating-point
exception may be delayed
C14 X X X X X X X X X NoFix Near CALL to ESP creates
unexpected EIP address
C15 X X Fixed Built-in self test always gives
nonzero result
C16 X X X X Fixed THERMTRIP# may not be
asserted as specified
C17 X Fixed Cache state corruption in the
presence of page A/D-bit setting and snoop traffic
C18 X Fixed Snoop cycle generates
spurious machine check exception
C19 X X Fixed MOVD/MOVQ instruction
writes to memory prematurely
C20 X X X X X X X X X NoFix Memory type undefined for
nonmemory operations
C21 X X Fixed Bus protocol conflict with
optimized chipsets
C22 X X X X X X X X X NoFix FP Data Operand Pointer
may not be zero after power on or Reset
C23 X X X X X X X X X NoFix MOVD following zeroing
instruction can cause incorrect result
C24 X X X X X X X X X NoFix Premature execution of a
load operation prior to exception handler invocation
C25 X X X X X X X X X NoFix Read portion of RMW
instruction may execute twice
13
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
Summary of Errata
NO. CPUID/Stepping Plans ERRATA
650h
651h
660h
665h
683h
686h
68Ah
6B1h
6B4h
A0
A1
A0
B0
B0
C0
D0
A1
B1
C26 X X X X Fixed Test pin must be high during
power up
C27 X X X X X X X X Fixed Intervening writeback may
occur during locked transaction
C28 X X X X X X X X X NoFix MC2_STATUS MSR has
model-specific error code and machine check architecture error code reversed
C29 X X X X X X X X X NoFix MOV with debug register
causes debug exception
C30 X X X X X X X X X NoFix Upper four PAT entries not
usable with Mode B or Mode C paging
C31 X X Fixed Incorrect memory type may
be used when MTRRs are disabled
C32 X X X Fixed Misprediction in program
flow may cause unexpected instruction execution
C33 X X X X X X X X X NoFix Data Breakpoint Exception in
a displacement relative near call may corrupt EIP
C34 X X X X X X X X X NoFix System bus ECC not
functional with 2:1 ratio
C35 X X X X X X X Fixed Fault on REP CMPS/SCAS
operation may cause incorrect EIP
C36 X X X X X X X NoFix RDMSR and WRMSR to
invalid MSR address may not cause GP fault
C37 X X X X X X X NoFix SYSENTER/SYSEXIT
instructions can implicitly load “null segment selector” to SS and CS registers
C38 X X X X X X X NoFix PRELOAD followed by
EXTEST does not load boundary scan data
C39 X X X X X X Fixed Far jump to new TSS with D-
bit cleared may cause system hang
14
®
INTEL
CELERON® PROCESSOR SPECIFICATION UPDATE
Summary of Errata
NO. CPUID/Stepping Plans ERRATA
650h
651h
660h
665h
683h
686h
68Ah
6B1h
6B4h
A0
A1
A0
B0
B0
C0
D0
A1
B1
C40 X X X X Fixed Incorrect chunk ordering may
prevent execution of the machine check exception handler after BINIT#
C41 X X X X X Fixed UC write may be reordered
around a cacheable write
C42 X X X X X X Fixed Resume Flag may not be
cleared after debug exception
C43 X X X X Fixed Internal cache protocol
violation may cause system hang
C44 X X X X X X X X X NoFix GP# fault on WRMSR to
ROB_CR_BKUPTMPDR6
C45 X X X X X Fixed Machine Check Exception
may occur due to improper line eviction in the IFU
C46 X X X X X X X X X NoFix Lower bits of SMRAM
SMBASE register cannot be written with an ITP
C47 X X X X X X Fixed Task switch may cause
wrong PTE and PDE access bit to be set
C48 X X X X X X X X X NoFix Cross-modifying code
operations on a jump instruction may cause a general protection fault
C49 X X X X X X X Fixed Deadlock may occur due to
illegal-instruction/page-miss combination
C50 X X X X X X X X X NoFix FLUSH# assertion following
STPCLK# may prevent CPU clocks from stopping
C51 X X X X X X Fixed Floating-point exception
condition may be deferred
C52 X X X X X X X Fixed Cache Line Reads May
Result in Eviction of Invalid Data
15
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
Summary of Errata
NO. CPUID/Stepping Plans ERRATA
650h
651h
660h
665h
683h
686h
68Ah
6B1h
6B4h
A0
A1
A0
B0
B0
C0
D0
A1
B1
C53 X X X X X NoFix FLUSH# servicing delayed
while waiting for STARTUP_IPI in 2-way MP systems
C54 X X X X X NoFix Double ECC error on read
may result in BINIT#
C55 X X X X X NoFix MCE due to L2 parity error
gives L1 MCACOD.LL
C56 X X X X X NoFix EFLAGS discrepancy on a
page fault after a multiprocessor TLB shootdown
C57 X X X X X NoFix Mixed cacheability of lock
variables is problematic in MP systems
C58 X X X X X NoFix INT 1 with DR7.GD set does
not clear DR7.GD
C59 X X X X X NoFix Potential loss of data
coherency during MP data ownership transfer
C60 X X X X X NoFix Misaligned Locked access to
APIC space results in a hang
C61 X X X X X NoFix Memory ordering based
synchronization may cause a livelock condition in MP Systems
C62 X X X X X NoFix Processor may assert
DRDY# on a write with no data
C63 X Fixed Machine check exception
may occur due to improper line eviction in the IFU
C65 X X NoFix Snoop request may cause
DBSY# hang
C66 X Fixed MASKMOVQ instruction
interaction with string operation may cause deadlock
C67 X X X X X NoFix MOVD, CVTSI2SS, or
PINSRW Following Zeroing Instruction Can Cause Incorrect Result
16
®
INTEL
CELERON® PROCESSOR SPECIFICATION UPDATE
Summary of Errata
686h
68Ah
6B1h
6B4h
C0
D0
A1
B1
A0
651h
A1
660h
A0
665h
B0
683h
B0
NO. CPUID/Stepping Plans ERRATA
650h
C68 X NoFix Snoop probe during FLUSH#
could cause L2 to be left in shared state
C69 X Fixed Livelock May Occur Due to
IFU Line Eviction
C70 X X X X X Fixed Selector for the LTR/LLDT
register may get corrupted
C71 X X X X X X X X X NoFix
INIT does not clear global entries in the TLB
C72 X X X X X X X X X NoFix
VM bit will be cleared on a double fault handler
C73 X X X X X X X X X NoFix
Memory aliasing with inconsistent A and D bits may cause processor deadlock
C74 X X X X X X X X X
NoFix
Processor may report invalid TSS fault instead of Double fault during mode C paging
C75 X X Fixed APIC failure at CPU
core/system bus frequency of 766/66 MHz
C76 X X X X X X X X X NoFix Machine check exception
may occur when interleaving code between different memory types
C77 X X X X X X X X X NoFix Wrong ESP Register Values
During a Fault in VM86 Mode
C78 X X X X X X X X X NoFix APIC ICR Write May Cause
Interrupt Not to be Sent When ICR Delivery Bit Pending
C79 X X X X X X X X Fixed The instruction fetch unit
(IFU) may fetch instructions based upon stale CR3 data after a write to CR3 Register
C80 X NoFix Processor Might not Exit
Sleep State Properly Upon De-assertion of CPUSLP# Signal
C81 X X NoFix During Boundary Scan, BCLK
not Sampled High When
17
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
Summary of Errata
NO. CPUID/Stepping Plans ERRATA
650h
651h
660h
665h
683h
686h
68Ah
6B1h
6B4h
A0
A1
A0
B0
B0
C0
D0
A1
B1
SLP# is Asserted Low
C82 X X
NoFix Incorrect assertion of
THERMTRIP# Signal
C83 X X X X X X X X X NoFix Under some complex
conditions, the Instructions in the shadow of a JMP FAR may be unintentionally executed and retired
C84 X X X X X X X X X NoFix Processor Does not Flag #GP
on Non-zero Write to Certain MSRs
C85 X X X X X X X X X NoFix
C86 X X X X X X X X X NoFix
IFU/BSU Deadlock May Cause System Hang REP MOVS Operation in Fast string Mode Continues in that Mode When Crossing into a Page with a Different Memory Type
C87 X X X X X X X X X NoFix
POPF and POPFD Instructions that Set the Trap Flag Bit May Cause Unpredictable Processor Behavior
C88 X X X X X X X X X NoFix
The FXSAVE, STOS, or MOVS Instruction May Cause a Store Ordering Violation When Data Crosses a Page with a UC Memory Type
C89 X X X X X X X X X NoFix
Code Segment Limit Violation May Occur on 4 Gigabyte Limit Check
C90 X X X X X X X X X NoFix
FST Instruction with Numeric and Null Segment Exceptions May Cause General Protection Faults to be Missed and FP Linear Address (FLA) Mismatch
C91 X X X X X X X X X NoFix
Code Segment (CS) is Incorrect on SMM Handler when SMBASE is not Aligned
C92 X X X X X X X X X NoFix
Page with PAT (Page Attribute Table) Set to USWC (Uncacheable Speculative Write Combine) While Associated MTRR (Memory Type Range Register) is UC
18
®
INTEL
CELERON® PROCESSOR SPECIFICATION UPDATE
Summary of Errata
686h
68Ah
6B1h
6B4h
C0
D0
A1
B1
A0
651h
A1
660h
A0
665h
B0
683h
B0
NO. CPUID/Stepping Plans ERRATA
650h
(Uncacheable) May Consolidate to UC
C93 X X X X X X X X X NoFix
Under Certain Conditions LTR (Load Task Register) Instruction May Result in System Hang
C93 X X X X X X X X X NoFix
Under Certain Conditions LTR (Load Task Register) Instruction May Result in System Hang
C94 X X X X X X X X X NoFix
Loading from Memory Type USWC (Uncacheable Speculative Write Combine) May Get Its Data Internally Forwarded from a Previous Pending Store
C95 X X X X X X X X X NoFix
FXSAVE after FNINIT Without an Intervening FP (Floating Point) Instruction May Save Uninitialized Values for FDP (x87 FPU Instruction Operand (Data) Pointer Offset) and FDS (x87 FPU Instruction Operand (Data) Pointer Selector)
C96 X X X X X X X X X NoFix
FSTP (Floating Point Store) Instruction Under Certain Conditions May Result In Erroneously Setting a Valid Bit on an FP (Floating Point) Stack Register
C97 X X X X X X X X X NoFix
Invalid Entries in Page­Directory-Pointer-Table Register (PDPTR) May Cause General Protection (#GP) Exception if the Reserved Bits are Set to One
Writing the Local Vector Table (LVT)
C98 X X X X X X X X X NoFix
when an Interrupt is Pending May Cause an Unexpected Interrupt
The Processor May Report
C99 X X X X X X X X X NoFix
an Invalid TSS Fault Instead of a #GP Fault
C100 X X X X X X X X X NoFix
A Write to an APIC Register Sometimes May Appear to
19
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
Summary of Errata
NO. CPUID/Stepping Plans ERRATA
650h
651h
660h
665h
683h
686h
68Ah
6B1h
6B4h
A0
A1
A0
B0
B0
C0
D0
A1
B1
Have Not Occurred
Using 2M/4M Pages When
C101 X X X X X X X X X NoFix
A20M# Is Asserted May Result in Incorrect Address Translations
Values for LBR/BTS/BTM will
C102 X X X X X X X X X NoFix
be Incorrect after an Exit from SMM
C103 X X X X X X X X X NoFix
INIT Does Not Clear Global Entries in the TLB
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
C104 X X X X X X X X X NoFix
Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations
The BS Flag in DR6 May be
C105 X X X X X X X X X NoFix
Set for Non-Single-Step #DB Exception
Fault on ENTER Instruction
C106 X X X X X X X X X NoFix
May Result in Unexpected Values on Stack Frame
Unaligned Accesses to
C107 X X X X X X X X X NoFix
Paging Structures May Cause the Processor to Hang
INVLPG Operation for Large
C108 X X X X X X X X X NoFix
(2M/4M) Pages May be Incomplete under Certain Conditions
Page Access Bit May be Set
C109 X X X X X X X X X NoFix
Prior to Signaling a Code Segment Limit Fault
EFLAGS, CR0, CR4 and the
C110 X X X X X X X X X NoFix
EXF4 Signal May be Incorrect after Shutdown
Performance Monitoring Event
C111 X X X X X X X X X NoFix
FP_MMX_TRANS_TO_MMX May Not Count Some Transitions
20
®
INTEL
CELERON® PROCESSOR SPECIFICATION UPDATE
* Fix will be only on Celeron
processors with CPUID=068xh.
Summary of Documentation Changes
CPUID/Stepping
NO.
650h
A0
651h
A1
660h
A0
665h
B0
683h
B0
686h
C0
68Ah
D0
6B1h
A1
6B4h
B1
Plans
DOCUMENTATION
CHANGES
C1 X X X X X X X X X Doc SSE and SSE2 Instructions
Opcodes
C2
X X X X X X X X X Doc
Executing the SSE2 Variant on a Non-SSE2 Capable Processor
C3 X X X X X X X X X Doc
C4 X X X X X X X X X Doc
C5 X X X X X X X X X Doc
Direction Flag (DF) Mistakenly Denoted as a System Flag
Fopcode Compatibility Mode
FCOS, FPTAN, FSIN, and FSINCOS Trigonometric Domain not correct
C6 X X X X X X X X X Doc
C7 X X X X X X X X X Doc
C8 X X X X X X X X X Doc
C9 X X X X X X X X X Doc
C10 X X X X X X X X X Doc
C11 X X X X X X X X X Doc
C12 X X X X X X X X X Doc
C13 X X X X X X X X X Doc
C14 X X X X X X X X X Doc
C15 X X X X X X X X X Doc
C16 X X X X X X X X X Doc
C17 X X X X X X X X X Doc
C18 X X X X X X X X X Doc
Incorrect Description of stack
EFLAGS Register Correction
PSE-36 Paging Mechanism
0x33 Opcode
Incorrect Information for SLDT
LGDT/LIDT Instruction Information Correction Errors In Instruction Set Reference
RSM Instruction Set Summary
Correct MOVAPS and MOVAPD Operand Section DAA—Decimal Adjust AL after Addition DAS—Decimal Adjust AL after Subtraction Omission of Dependency between BTM and LBR I/O Permissions Bitmap Base Addy > 0xDFFF Does not Cause #GP(0) Fault
C19 X X X X X X X X X Doc
C20 X X X X X X X X X Doc
C21 X X X X X X X X X Doc
Wrong Field Width for MINSS and MAXSS Figure 15-12 PEBS Record Format
I/O Permission Bit Map
21
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
Summary of Documentation Changes
CPUID/Stepping
650h
651h
660h
665h
683h
686h
68Ah
6B1h
NO.
A0
A1
A0
B0
B0
C0
D0
A1
6B4h
B1
Plans
C22 X X X X X X X X X Doc
C23 X X X X X X X X X Doc
C24 X X X X X X X X X Doc
DOCUMENTATION
CHANGES
Cache Description
Instruction Formats and Encoding
Machine-Check Initialization
22
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