Intel SL3QA - Pentium III 550 MHz Processor, SL6BY - Pentium III Processor 1.4GHz Tualatin 512KB/133/370, Pentium III Specification

Intel® Pentium® III Processor

Specification Update

August 2008

Revision 060

Document Number: 244453-060

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,
AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS
INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR
INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use
in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descri ptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.

The Intel® Pentium® III processor may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Intel, Pentium, Intel Xeon, Celeron, MMX and the Intel logo are trademarks or registered trademarks of Intel Corporation or its
subsidi aries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

Copyright © 1999-2008, Intel Corporation.

2 Specification Update

Contents

Preface.............................................................................................................................8

Summary Tables of Changes.............................................................................................. 10

Identification Information.................................................................................................. 20

Errata ............................................................................................................................ 39

Specification Changes....................................................................................................... 88

Specification Clarifications ................................................................................................. 89

Documentation Changes ................................................................................................... 93

Specification Update 3

Revision History

Revision Description Date

-001 This is the first Specification Update for Pentium® III processors. March 1999

-002 Added Erratum E42. Deleted Erratum E16 and renumbered existing
items. Corrected Errata table “Plans” column for E39. Updated the
Pentium III Processor Identification Information tab le.

-003 Updated the Pentium III Processor Identification Information table.
Updated the Errata table by marking Errata E34, E35, and E40 as
Fixed.

-004 Updated the Pentium III Processor Identification and Pack age
Information table. Added Erratum 43. Added Documentation Change
E1. Added Specification Clarifications E1 and E2. Added Specification
Change E3.

-005 Added footnote 4 to the Pentium III Processor Identification and
Package Information table. Added Erratum E44. Added stepping Kc0 in
Summary Table of Changes. Added Mixed Steppings in DP Systems
section. Updated Documentation Changes, Specification Clarifications,
and Specification Changes introduction paragraphs.

-006 Added Errata E45 and E46. Added Documentation Change E2.
Updated Identification Information table. Updated and corrected
Pentium III Processor Identification and Package Information table.
Updated Codes Used in Summary Table. Updated column heading in
Errata, Documentation Changes, Specification Clarifications and
Specification Changes tables.

-007 Revised Errata E45. Updated DP Platform Population Matrix for the
Pentium III Processor with 100 MHz System Bus. Updated datasheet
references to include the latest supported frequency.

-008 Added Errata E47. Updated the Pentium III Processor Identification and
Package Information table. Added the DP Platform Population Matrix
for the Pentium III Processor with 133 MHz System Bus table. Added
Brand ID column to Identification Information. Updated datasheet
references to include the latest supported frequency.

-009 Added Errata E48 and E49. Added Documentation Change E3. Added
new stepping column in the Summary of Changes tables. Updated the
Pentium® III Processor Identification Information tables. Up dated
Mixed Step pings in DP System section. Updated the Pentium® III
Process Identification Information table. Updated references.

-010 Updated document references in Preface to include new Pentium III
processor datasheets. Updated errata E10, E11, E19, and E32 in the
Summary of Errata table. Added Errata E50-E58. Added
Documentation Change E4. Added Specification Clarification E3.
Added Specification Changes E4 and E5.

April 1999

May 1999

June 1999

July 1999

August 1999

September 1999

October 1999

November 1999

December 1999

4 Specification Update

Revision Description Date

-011 Corrected an error in the Summary of Errata table. Erratum E56 was
incorrectly shown as applying to the Ca2 stepping. Erratum E56 does
NOT apply to the Ca2 stepping.

-012 Updated Preface to include new Pentium III processor datasheets.
Added 800-MHz Pentium III processor information to the DP Platform
Population Matrix tables and the Pentium® III Processor Identification
and Packaging Information table. A dded note 10 to the Pentium® III
Processor Identification and Packaging Information table and updated
Notes column and other table data. Updated erratum E51. Added
Errata E59-E62. Added Documentation Change E5. Added
Specification Change E6.

-013 Updated Errata E49 and E61. Added Documentation Change E6.
Updated the Pentium® III Processor Identification Information.
Updated S-Spec SL365. Updated Summary of Changes product letter
codes.

-014 Updated Preface to include new Pentium III processor datasheet.
Updated Pentium® III Processor Identification and Package
Information table. Updated Summary of Errata, Summary of
Documentation Changes, Summary of Specification Clarifications
Summary of Specification Changes tables with Cb0 stepping. Updated
Erratum E48.

-015 Special Launch Edition: Updated the new Cb0 stepping information.
Updated the document references in the Preface. Updated DP
population table.

-016 Updated Processor Identification Information table. Updated DP
Population Tables. Added Errata E63 & E64.

-017 Updated Pentium III Processor Identification and Package Information
table. Updated Errata E64. Added Errata E65 & E66.

-018 Updated Processor Identification, Summary of Errata, and Summary of
Specification Changes tables. Updated Dual Processor Tables. Added
new Specification Change E7.

-019 Added new errata E67 & E68. Updated Processor Identification Table.

Edited erratum E36. Updated Processor Identification, Summary of
Errata, Summary of Documentation Changes, Summary of
Specification Clarifications, Summary of Specification Changes tables
with cC0 Stepping.

-020 Added new Erratum E69. Updated Dual Processor Matrix. Updated Dual
Processor Matrix. Updated Processor Identification Table with new C0
step CPUs.

-021 Added New Errata E70 & E71. Added Re-Writes for Errata E28, E48, &
E62. Added New Documentation Changes E7 & E8. Updated Dual
Processor Matrix, removed TBDs. Updated Processor Identification
Table.

-022 Updated Pentium® III Processor Identification Information table.
Updated Dual Processor Matrix. Added New Errata E72 and E73. Added
New Documentation Changes E9 and E10.

-023 Updated Processor Identification Table. Added New Erratum E73. November 2000

December 1999

January 2000

February 2000

March 2000

March 2000

April 2000

May 2000

June 2000

July 2000

August 2000

September 2000

October 2000

Specification Update 5

Revision Description Date

-024 Updated Specification Update product key to include the Intel®
Pentium® 4 processor, Revised Erratum E2. Added new
Documentation Changes E11 – E16.

-025 Revised Erratum E2. Added new Documentation Changes E17 and E18.
Updated Processor Identification Table.

-026 Added new Documentation Change E19. Revised Documentation
Change E17.

-027 Added new Errata E74 and E75. March 2001

-028 Added erratum E76 March 2001

-029 Revised Erratum E76 to Fixed. Updated processor identification table.
Updated the tables in the Mixed Steppings in DP Systems section.

-030 Updated note 18 in the Pentium® III Processor Identification and
Package Information table. Updated Specification Update product key
to include the Intel® Xeon™ processor

-031 Special Launch Edition: Added package marking information under
General Section. Added new S spec info into processor table. Updated
Dual Processor tables. Updated Summary of Errata, Summary of
Documentation, Summary of Specification Clarifications, and Summary
of Changes tables. Added Errata E77 & E78.

-032 Added new S spec info into processor table. Revised package marking
information under General Section. Updated Dual Processor tables.
Deleted duplicate information in the processor ID table.

-033 Added new errata E79 and E80. Updated DP Matrix Tables August 2001

-034 Changed word “motherboard” to “baseboard” in erratum E78 October 2001

-035 Updated DP population matrix for new tA1 parts. Added Doc Changes
E20, E21, E22, E23, and E24.

-036 Special launch edition. Added part with S-Spec SL5VX at 1.33GHz to
the Pentium® III Processor Identification and Package Information list.

-037 Added: Doc changes E25, E26, E27, E28, E29, Spec Clarification E4, E5
and Spec Change E8. Added part with S-Spec SL657 to the Processor
ID Information Table

-038 Modified Erratum E80 and added Erratum E81. Added Doc Change E1. March 2002

-039 Out of Cycle Special Launch Edition. Added Server LV part with S-Spec
Number SL66D at 800 MHz to the Pentium® III Processor Identification
and Package Information list.

-040 Added Doc Change E1. April 2002

-041 Modified Errata E59. Added Doc Changes E1, E2, and E3. May 2002

-042 Added Erratum E82. Added Doc Changes E1 and E2. Added parts with
S-Spec numbers SL6C2, SL6C3, SL6C4 and SL6BZ with Core Stepping
tB1 to the Processor ID Information Table.

-043 Added Document Changes E3-E12. Added parts with S-Spec numbers
SL6BW, SL6BX, SL6BY and SL6HC with Core Stepping tB1 to the
Processor ID Information Table. Changed status of erratum E78 to
NOFIX.

December 2000

January 2001

February 2001

May 2001

June 2001

June 2001

July 2001

November 2001

November 2001

February 2002

March 2002

June 2002

July 2002

6 Specification Update

Revision Description Date

-044 Added new Doc Changes E3-E24. Removed parts with S-Spec numbers
SL6C2, SL6C3, SL6C4 and SL6BZ with Core Stepping tB1 from the
Processor ID Information Table.

-045 Added Doc Changes E25 to E32. Updated Summary of Changes. October 2002

-046 Updated DP FC-PGA2 Matrix table. Added one S-spec number. December 2002

-047 Added Erratum E83. March 2003

-048 Updated Summary of Errata table E78 and Added one S Spec number. May 2003

-049 Added Errata E84 and E85. November 2003

-050 Updated E85 and added E86 to E89 October 2004

-051 Added Errata E90, E91, E92 November 2004

-052 Added Errata E93, E94 February 2005

-053 Updated Errata E80 March 2005

-054 Added Specification Clarification April 2005

-055 Added Errata E95, E96, E97, E98, E99, E100, E101, E102, E103, E104,
E105, E106, E107. Updated Summary Table of Changes. Updated the
name of the Sofftware Developer Manuals.

-056 Added Erratum E108 January 2007

-057 Updated Summary Table of Changes. May 2007

-058 Added Erratum E109. Updated Summary Table of Changes. August 2007

-059 Updated Summary Table of Changes. April 2008

-060 Updated Summary Table of Changes. August 2008

September 2002

December 2005

§

Specification Update 7

Preface

This document is an update to the specifications contained in the documents listed in
the following Affected Documents/Related Documents table. It is a compilation of
device and document errata and specification clarifications and changes, and is
intended for hardware system manufacturers and for software developers of
applications, operating system, and tools.

Information types defined in the Nomenclature section of this document are
consolidated into this update document and are no longer published in other
documents. This document may also contain information that has not been previously
published.

Affected Documents

Preface

Pentium® III Processor for the SC242 at 450 MHz to 1.13 GHz datasheet

Pentium® III Processor for the PGA370 Socket up to 1.13 GHz
datasheet

Related Documents

Intel Architecture Software Developer’s Manual, Volumes 1, 2a, 2b, 3a
and 3b

Nomenclature

Errata are design defects or errors. Errata may cause the Pentium III behavior to

deviate from published specifications. Hardware and software designed to be used
with any given stepping must assume that all errata documented for that stepping
are present on all devices.

Specification Changes are modifications to the current published specifications.
These changes will be incorporated in the next release of the specifications.

Document Title Document

Document Title Document

Number/Location

244452

245264

Number/Location

253665, 253666,
253667, 253668,

253669

Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications
will be incorporated in the next release of the specifications.

8 Specification Update

Preface

Documentation Changes include typos, errors, or omissions from the current
published specifications. These changes will be incorporated in the next release of the
specifications.

Note: Errata remain in the specification update throughout the product’s lifecycle, or until a

particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon
request. Specification changes, specification clarifications and documentation
changes are removed from the specification update when the appropriate changes
are made to the appropriate product specification or user documentation
(datasheets, manuals, etc.).

§

Specification Update 9

Summary Tables of Changes

Summary Tables of Changes

The following table indicates the Specification Changes, Errata, Specification
Clarifications or Documentation Changes, which apply to the listed MCH steppings.
Intel intends to fix some of the errata in a future stepping of the component, and to
account for the other outstanding issues through documentation or Specification
Changes as noted. This table uses the following notations:

Codes Used in Summary Table

Stepping

X: Erratum, Specification Change or Clarification that applies

to this stepping.

Status

Row

(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification

change does not apply to listed stepping.

Doc: Document change or update that will be implemented.

PlanFix: This erratum may be fixed in a future stepping of the

product.

Fixed: This erratum has been previously fixed.

NoFix: There are no plans to fix this erratum.

Shaded: This item is either new or modified from the previous

version of the document.

Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
Specification Updates:

A = Dual-Core Intel® Xeon® processor 7000 sequence

C = Intel® Celeron® processor

10 Specification Update

Summary Tables of Changes

D = Dual-Core Intel® Xeon® processor 2.80 GHz

E = Intel® Pentium® III processor

F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D

processor

I = Dual-Core Intel® Xeon® processor 5000 series

J = 64-bit Intel® Xeon® processor MP with 1MB L2 cache

K = Mobile Intel® Pentium® III processor

L = Intel® Celeron® D processor

M = Mobile Intel® Celeron® processor

N = Intel® Pentium® 4 processor

O = Intel® Xeon® processor MP

P = Intel ® Xeon® processor

Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology

on 90-nm process technology

R = Intel® Pentium® 4 processor on 90 nm process

S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2

cache versions)

T = Mobile Intel® Pentium® 4 processor-M

U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache

V = Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA

package

W= Intel® Celeron® M processor

X = Intel® Pentium® M processor on 90nm process with 2-MB L2 cache and

Intel® processor A100 and A110 with 512-KB L2 cache

Y = Intel® Pentium® M processor

Z = Mobile Intel® Pentium® 4 processor with 533 MHz system bus

AA = Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor

Extreme Edition 955, 965

AB = Intel® Pentium® 4 processor 6x1 sequence

AC = Intel(R) Celeron(R) processor in 478 pin package

AD = Intel(R) Celeron(R) D processor on 65nm process

AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm

process

AF = Dual-Core Intel® Xeon® processor LV

AG = Dual-Core Intel® Xeon® processor 5100 series

AH = Intel® Core™2 Duo/Solo processor for Intel® Centrino® Duo processor

technology

Specification Update 11

Summary Tables of Changes

AI = Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop

processor E6000 and E4000 sequence

AJ = Quad-Core Intel® Xeon® processor 5300 series

AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel®

Core™2 Quad processor Q6000 sequence

AL = Dual-Core Intel® Xeon® processor 7100 series

AM = Intel® Celeron® processor 400 sequence

AN = Intel® Pentium® dual-core processor

AO = Quad-Core Intel® Xeon® processor 3200 series

AP = Dual-Core Intel® Xeon® processor 3000 series

AQ = Intel® Pentium® dual-core desktop processor E2000 sequence

AR = Intel® Celeron® processor 500 series

AS = Intel® Xeon® processor 7200, 7300 series

AT = Intel® Celeron® processor 200 series

AU = Intel® Celeron® Dual Core processor T1400

AV = Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad

processor Q9000 series

AW = Intel® Core™ 2 Duo processor E8000 series

AX = Quad-Core Intel® Xeon® processor 5400 series

AY= Dual-Core Intel® Xeon® processor 5200 series

AZ = Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-

nm Process

AAA = Quad-Core Intel® Xeon® processor 3300 series

AAB = Dual-Core Intel® Xeon® E3110 Processor

AAC = Intel® Celeron® dual-core processor E1000 series

AAD = Intel® Core™2 Extreme Processor QX9775Δ

AAE = Intel® Atom™ processor Z5xx series

AAF = Intel® Atom™ processor 200 series

AAG = Intel® Atom™ processor N series

The Specification Updates for the Pentium processor, Pentium

®

Pro processor, and

other Intel products do not use this convention.

NO. kB0 kC0 cA2 cB0 cC0 cD0 tA1 tB1 Plans ERRATA

E1 X X X X X X X X NoFix

12 Specification Update

FP data operand pointer may be incorrectly
calculated after FP access which wraps
64-Kbyte boundary in 16-bit code

Summary Tables of Changes

NO. kB0 kC0 cA2 cB0 cC0 cD0 tA1 tB1 Plans ERRATA

E2 X X X X X X X X NoFix

E3 X X X X X X X X NoFix

E4 X X X X X X X X NoFix

E5 X X X X X X X X NoFix

E6 X X X X X X X X NoFix

E7 X X X X X X X X NoFix BTM for SMI will contain incorrect FROM EIP

E8 X X X X X X X X NoFix

E9 X X X X X X X X NoFix

E10 X X Fixed

E11 X X Fixed

E12 X X X X X X X X NoFix

E13 X X X X X X X X NoFix

E14 X X X X X X X X NoFix LBER may be corrupted after some events

E15 X X X X X X X X NoFix

E16 X X X X X X X X NoFix

E17 X X X X X X X X NoFix

E18 X X X X X X X X NoFix

E19 X X Fixed

E20 X X X X X X X X NoFix

E21 X X X X X X X X NoFix

E22 X X X X X X X X NoFix

E23 X X X X X X X X NoFix

Differences exist in debug exception
reporting

FLUSH# servicing delayed while waiting for
STARTUP_IPI in 2-way MP systems

Code fetch matching disabled debug register
may cause debug exception

Double ECC error on read may result in
BINIT#

FP inexact-result exception flag may not be
set

I/O restart in SMM may fail after
simultaneous MCE

Branch traps do not function if BTMs are also
enabled

Checker BIST failure in FRC mode not
signaled

BINIT# assertion causes FRCERR assertion in
FRC mode

Machine check exception handler may not
always execute successfully

MCE due to L2 parity error gives L1
MCACOD.LL

BTMs may be corrupted during simultaneous
L1 cache line replacement

EFLAGS discrepancy on a page fault after a
multiprocessor TLB shootdown

Near CALL to ESP creates unexpected EIP
address

Memory type undefined for nonmemory
operations

Infinite snoop stall during L2 initialization of
MP systems

FP data operand pointer may not be zero
after power on or Reset

MOVD following zeroing instruction can cause
incorrect result

Premature execution of a load operation
prior to exception handler invocation

Read portion of RMW instruction may
execute twice

Specification Update 13

Summary Tables of Changes

NO. kB0 kC0 cA2 cB0 cC0 cD0 tA1 tB1 Plans ERRATA

MC2_STATUS MSR has model-specific error

E24 X X X X X X X X NoFix

E25 X X X X X X X X NoFix

E26 X X X X X X X X NoFix

E27 X X X X X X X X NoFix

E28 X X X X X X X X NoFix

E29 X X X X X X X X NoFix

E30 X X X X X X X X NoFix

E31 X X X X X X X X NoFix

E32 X X Fixed

E33 X X X X X X X X NoFix

E34 X Fixed

E35 X Fixed Transmission error on cache read

E36 X X X X X X X X NoFix

E37 X X X X X X X X NoFix

E38 X X Fixed

E39 X X X X X X X X NoFix

E40 X Fixed

E41 X X X X X X X X NoFix System bus ECC not functional with 2:1 ratio

E42 X X X X X X X X NoFix

E43 X X X X X X X X NoFix

E44 X X X X Fixed

code and machine check architecture error
code reversed

Mixed cacheability of lock variables is
problematic in MP systems

MOV with debug register causes debug
exception

Upper four PAT entries not usable with Mode
B or Mode C paging

Data breakpoint exception in a displacement
relative near call may corrupt EIP

RDMSR and WRMSR to invalid MSR may not
cause GP fault

SYSENTER/SYSEXIT instructions can
implicitly load null segment selector to SS
and CS registers

PRELOAD followed by EXTEST does not load
boundary scan data

Far jump to new TSS with D-bit cleared may
cause system hang

INT 1 instruction handler execution could
generate a debug exception

COMISS/UCOMISS may not update EFLAGS
under certain conditions

Potential loss of data coherency during MP
data ownership transfer

Misaligned Locked access to APIC space
results in hang

Floating-point exception signal may be
deferred

Memory ordering based synchronization may
cause a livelock condition in mp systems

System bus address parity generator may
report false AERR#

Processor may assert DRDY# on a write with
no data

GP# fault on WRMSR to
ROB_CR_BKUPTMPDR6

Machine check exception may occur due to
improper line eviction in the IFU

14 Specification Update

Summary Tables of Changes

NO. kB0 kC0 cA2 cB0 cC0 cD0 tA1 tB1 Plans ERRATA

E45 X X X Fixed

E46 X X X X X Fixed Snoop request may cause DBSY# hang

E47 X X X X X X X X NoFix

E48 X X X Fixed

E49 X X X X X X X X NoFix

E50 X Fixed

E51 X Fixed Noise sensitivity issue on processor SMI# pin

E52 X Fixed

E53 X Fixed

E54 X Fixed IFU/DCU deadlock may cause system hang

E55 X Fixed

E56 X X Fixed

E57 X X X X Fixed

E58 X X X X Fixed

E59 X X X X X X X X NoFix

E60 X X X X X X X X NoFix

E61 X Fixed

E62 X X X X X X Fixed

E63 X Fixed

E64 X X Fixed

E65 X X X X X X X X NoFix

Performance counters include Streaming
SIMD Extensions L1 prefetch

Lower bits of SMRAM SMBASE register
cannot be written with an ITP

Task Switch May Cause Wrong PTE and PDE
Access Bit to be Set

Unsynchronized Cross-Modifying code
operations can cause unexpected instruction
execution results

Processor will erroneously report a BIST
failure

Limitation on cache line ECC detection and
correction

L2_LD and L2_M_LINES_OUTM performance­monitoring counters do not work

L2_DBUS_BUSY performance monitoring
counter will not count writes

Incorrect sign may occur on X87 result due
to indefinite QNaN result from streaming
SIMD extensions multiply

Deadlock may occur due to illegal­instruction/page-miss combination

MASKMOVQ instruction interaction with
string operation may cause deadlock

MOVD, CVTSI2SS, or PINSRW Following
Zeroing Instruction Can Cause Incorrect
Result

FLUSH# assertion following STPCLK# may
prevent CPU clocks from stopping

Intermittent failure to assert ADS# during
processor power-on

Floating-point exception condition may be
deferred

THERMTRIP# may not be asserted as
specified

Cache line reads may result in eviction of
invalid data.

Snoop probe during FLUSH# could cause L2
to be left in shared state

Specification Update 15

Summary Tables of Changes

NO. kB0 kC0 cA2 cB0 cC0 cD0 tA1 tB1 Plans ERRATA

E66 X X X X Fixed Livelock may occur due to IFU line eviction

E67 X X X X Fixed

E68 X X X X X X X X NoFix INIT does not clear global entries in the TLB

E69

E70

E71 X X X X X X X X NoFix

E72 X X X X X X X X NoFix

E73 X X X X X X X X NoFix

E74 X X X X X X X X NoFix

E75 X X X X X X X X NoFix

E76 X Fixed

E77 X X X X X X X X PlanFix

E78 X X X X X X X NoFix Incorrect assertion of THERMTRIP# Signal

E79 X NoFix

E80 X X X X X X X1 Fixed

E81 X X X X X X X X NoFix

E82 X X X X X X X X NoFix

E83 X X X X X X X X NoFix IFU/BSU Deadlock May Cause System Hang

E84

X X X X X X X X NoFix VM bit will be cleared on a double fault

X X X X X X X X NoFix Memory aliasing with inconsistent A and D

X X X X X X X X NoFix REP MOVS Operation in Fast string Mode

Selector for the LTR/LLDT register may get
corrupted

handler

bits may cause processor deadlock

Use of memory aliasing with inconsistent
memory type may cause system hang

Processor may report invalid TSS fault
instead of Double fault during mode C
paging

Machine check exception may occur when
interleaving code between different memory
types

Wrong ESP register values during a fault in
VM86 mode

APIC ICR write may cause interrupt not to be
sent when ICR delivery bit pending

High temperature and low supply voltage
operation may result in incorrect processor
operation

During Boundary Scan, BCLK not Sampled
High When SLP# is Asserted Low

Processor might not exit Sleep State
properly upon de-assertion of CPUSLP#
signal

The Instruction Fetch Unit (IFU) may fetch
instructions based upon stale CR3 data after
a write to CR3 register

Under Some Complex Conditions, the
Instructions in the Shadow of a JMP FAR may
be Unintentionally Executed and Retired

Processor Does not Flag #GP on Non-zero
Write to Certain MSRs

Continues in that Mode When Crossing into a
Page with a Different Memory Type

16 Specification Update

Summary Tables of Changes

NO. kB0 kC0 cA2 cB0 cC0 cD0 tA1 tB1 Plans ERRATA

X X X X X X X X NoFix The FXSAVE, STOS, MOVS Instructions May

E85

E86 X X X X X X X X NoFix

E87 X X X X X X X X NoFix

E88 X X X X X X X X NoFix

E89 X X X X X X X X NoFix

E90 X X X X X X X X NoFix

E91 X X X X X X X X NoFix

E92 X X X X X X X X NoFix

E93 X X X X X X X X NoFix

E94 X X X X X X X X NoFix

E95 X X X X X X X X NoFix

E96 X X X X X X X X NoFix

E97 X X X X X X X X NoFix

E98 X X X X X X X X NoFix

Cause a Store Ordering Violation When Data
Crosses a Page with a UC Memory Type

POPF and POPFD Instructions that Set the
Trap Flag Bit May Cause Unpredictable
Processor Behavior

Code Segment Limit Violation May Occur on
4 Gbyte Limit Check

FST Instruction with Numeric and Null
Segment Exceptions May Cause General
Protection Faults to be Missed and FP Linear
Address (FLA) Mismatch

Code Segment is Wrong on SMM Handler
when SMBASE is not Aligned

Page with PAT (Page Attribute Table) Set to
USWC (Uncacheable Speculative Write
Combine) While Associated MTRR (Memory
Type Range Register) is UC (Uncacheable)
May Consolidate to UC

Under Certain Conditions LTR (Load Task
Register) Instruction May Result in System
Hang

Loading from Memory Type USWC
(Uncacheable Speculative Write Combine)
May Get Its Data Internally Forwarded From
a Previous Pending Store

FXSAVE after FNINIT Without an Intervening
FP (Floating Point) Instruction May Save
Uninitialized Values for FDP (x87 FPU
Instruction Operand (Data) Pointer Offset)
and FDS (x87 FPU Instruction Operand
(Data) Pointer Selector)

FSTP (Floating Point Store) Instruction Under
Certain Conditions May Result In Erroneously
Setting a Valid Bit on an FP (Floating Point)
Stack Register

Invalid Entries in Page-Directory-Pointer­Table-Register (PDPTR) May Cause General
Protection (#GP) Exception if the Reserved
Bits are Set to One

Writing the Local Vector Table (LVT)
when an Interrupt is Pending May Cause an
Unexpected Interrupt

The Processor May Report a #TS Instead of
a #GP Fault

A Write to an APIC Register Sometimes May
Appear to Have Not Occurred

Specification Update 17

Summary Tables of Changes

NO. kB0 kC0 cA2 cB0 cC0 cD0 tA1 tB1 Plans ERRATA

Using 2M/4M Pages When A20M# Is

E99 X X X X X X X X NoFix

Asserted May Result in Incorrect Address
Translations

E100 X X X X X X X X NoFix

E101 X X X X X X X X NoFix INIT Does Not Clear Global Entries in the TLB

E102 X X X X X X X X NoFix

E103 X X X X X X X X NoFix

E104 X X X X X X X X NoFix

E105 X X X X X X X X NoFix

E106 X X X X X X X X NoFix

E107 X X X X X X X X NoFix

E108 X X X X X X X X NoFix

E109 X X X X X X X X NoFix

Values for LBR/BTS/BTM will be Incorrect
after an Exit from SMM

REP MOVS/STOS Executing with Fast Strings
Enabled and Crossing Page Boundaries with
Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory­Ordering Violations

The BS Flag in DR6 May be Set for Non­Single-Step #DB Exception

Fault on ENTER Instruction May Result in
Unexpected Values on Stack Frame

Unaligned Accesses to Paging Structures May
Cause the Processor to Hang

INVLPG Operation for Large (2M/4M) Pages
May be Incomplete under Certain Conditions

Page Access Bit May be Set Prior to
Signaling a Code Segment Limit Fault

EFLAGS, CR0, CR4 and the EXF4 Signal May
be Incorrect after Shutdown

Performance Monitoring Event
FP_MMX_TRANS_TO_MMX May Not Count
Some Transitions

* Fix will be only on Pentium® III processors with CPUID=068xh and not
CPUID=067xh

Notes:

1-

For these steppings, this erratum may be worked around in BIOS.

Number SPECIFICATION CHANGES

There are no Specification Changes in this revision of the Specification Update.

Number SPECIFICATION CLARIFICATIONS

E1 Specification clarification with respect to time stamp counter.

18 Specification Update

Summary Tables of Changes

Number DOCUMENTATION CHANGES

There are no Documentation Chnages in this revision of the Specification Update

§

Specification Update 19

Identification Information

Identification Informati o n

Component Iden tification via Pr ogramming Interface

The Pentium® III processor can be identified by the following values:

Family1 Model2 Brand ID3

0110 0111 00h = Not Supported

0110 1000 02h = "Intel® Pentium® III

Processor"

NOTES:

1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of

the EAX register after the CPUID instruction is executed with a 1 in the EAX register,
and the generation field of the Device ID register accessible through Boundary Scan.

2. The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the

EAX register after the CPUID instruction is executed with a 1 in the EAX register, and
the model field of the Device ID register accessible through Boundary Scan.

3. The Brand ID corresponds to bits [7:0] of the EBX register after the CPUID instruction is

executed with a 1 in the EAX register.

The Pentium III processor’s second level (L2) cache size can be determined by the
following register contents:

512-Kbyte Unified L2 Cache1 43h

256-Kbyte 8 way set associative

32byte line size, L2 Cache

512-Kbyte 8 way set associative

32byte line size, L2 Cache

NOTES:

1. For the Pentium III processor, the unified L2 cache size corresponds to a token in the

EDX register after the CPUID instruction is executed with a 2 in the EAX register. Other
Intel microprocessor models or families may move this information to other bit positions
or otherwise reformat the result returned by this instruction; generic code should parse
the resulting token stream according to the definition of the CPUID instruction.

1

1

82h

83h

20 Specification Update

Identification Information

Mixed Step pings i n DP Systems

Intel Corporation fully supports mixed steppings of Pentium III processors. The following list and
processor matrix describes the requirements to support mixed steppings:

• Mixed steppings are only supported with processors that have identical family and model

number as indicated by the CPUID instruction.

• While Intel has done nothing to specifically prevent processors operating at differing

frequencies from functioning within a multiprocessor system, there may be uncharacterized
errata that exist in such configurations. Intel does not support such configurations. In mixed
stepping systems, all processors must operate at identical frequencies (i.e., the highest
frequency rating commonly supported by all processors).

• While there are no known issues associated with the mixing of processors with differing

cache sizes in a dual processor system, and Intel has done nothing to specifically prevent
such system configurations from operating, Intel does not support such configurations since
there may be uncharacterized errata that exist. In dual processor systems, all processors
must be of the same cache size.

• While Intel believes that certain customers may wish to perform validation of system

configurations with mixed frequency or cache sizes, and that those efforts are an acceptable
option to our customers, customers would be fully responsible for the validation of such
configurations.

• The workarounds identified in this and following specification updates must be properly

applied to each processor in the system. Certain errata are specific to the dual processor
environment and are identified in the Mixed Stepping Processor Matrix found at the end of
this section. Errata for all processor steppings will affect system performance if not properly

worked around. Also see the “Pentium® III Processor Identification and Package
Information” table for additional details on which processors are affected by specific errata.

• In dual processor systems, the processor with the lowest feature-set, as determined by the

CPUID Feature Bytes, must be the Bootstrap Processor (BSP). In the event of a tie in
feature-set, the tie should be resolved by selecting the BSP as the processor with the lowest
stepping as determined by the CPUID instruction.

In the following processor matrix a number indicates that a known issue has been identified as
listed in the table following the matrix. A dual processor system using mixed processor steppings
must assure that errata are addressed appropriately for each processor.

Specification Update 21

MHz

MHz

MHz

MHz

MHz

MHz

600E

MHz

MHz

MHz

MHz

MHz

550E

600E

MHz

MHz

MHz

MHz

MHz

MHz

600E

MHz

MHz

MHz

MHz

MHz

MHz

1 GHz

Identification Information

DP Platform Population Matrix for t he Pentium® III Processor with 100-MHz System Bus in the SECC and SECC2
Packages

Pentium® III

Processor

Stepping

450-MHz kB0 NI X NI X X X X X X X X X X X X X X X X X X X X X X
500-MHz kB0 X NI X NI X X X X X X X X X X X X X X X X X X X X X
450-MHz kC0 NI X NI X X X X X X X X X X X X X X X X X X X X X X
500-MHz kC0 X NI X NI X X X X X X X X X X X X X X X X X X X X X
550-MHz kC0 X X X X NI X X X X X X X X X X X X X X X X X X X X
600-MHz kC0 X X X X X NI X X X X X X X X X X X X X X X X X X X
600E-MHz cA2 X X X X X X NI X X X X X NI X X X X X NI X X X X X X
650-MHz cA2 X X X X X X X NI X X X X X NI X X X X X NI X X X X X
700-MHz cA2 X X X X X X X X NI X X X X X NI X X X X X NI X X X X
750-MHz cA2 X X X X X X X X X NI X X X X X NI X X X X X NI X X X
800 MHz cA2 X X X X X X X X X X NI X X X X X NI X X X X X NI X X
550E MHz cB0 X X X X X X X X X X X NI X X X X X X X X X X X X X
600E MHz cB0 X X X X X X NI X X X X X NI X X X X X NI X X X X X X
650 MHz cB0 X X X X X X X NI X X X X X NI X X X X X NI X X X X X
700 MHz cB0 X X X X X X X X NI X X X X X NI X X X X X NI X X X X
750 MHz cB0 X X X X X X X X X NI X X X X X NI X X X X X NI X X X
800 MHz cB0 X X X X X X X X X X NI X X X X X NI X X X X X NI X X
850 MHz cB0 X X X X X X X X X X X X X X X X X NI X X X X X NI X
600E-MHz cC0 X X X X X X NI X X X X X NI X X X X X NI X X X X X X
650 MHz cC0 X X X X X X X NI X X X X X NI X X X X X NI X X X X X
700 MHz cC0 X X X X X X X X NI X X X X X NI X X X X X NI X X X X
750-MHz cC0 X X X X X X X X X NI X X X X X NI X X X X X NI X X X
800 MHz cC0 X X X X X X X X X X NI X X X X X NI X X X X X NI X X
850 MHz cC0 X X X X X X X X X X X X X X X X X NI X X X X X NI X
1 GHz cC0 X X X X X X X X X X X X X X X X X X X X X X X X NI

450

kB0

500

kB0

450

kC0

500

kC0

550

kC0

600

kC0

cA2

650

cA2

700

cA2

750

cA2

800

cA2

MHz

cB0

cB0

650

cB0

700

cB0

750

cB0

800

cB0

850

cB0

cC0

650

cC0

700

cC0

750

cC0

800

cC0

850

cC0

cC0

NOTES:

1. X = Mixing processors at different frequencies is not supported. This

stepping/frequency not supported in DP.

2. NI = Currently no known issues associated with mixing these steppings.

22 Specification Update

Identification Information

DP Platform Population Matrix for the Pentium® III Processor with 133-MHz
System Bus in the SECC and SECC2 Package from 533MHz to 733MHz

Pentium® III

Processor

Stepping

533B-MHz kB0 NI NI X
533B-MHz kC0 NI NI X
600B-MHz kC0 X X NI
533EB-MHz cA2 X X X
600EB-MHz cA2 X X X
667-MHz cA2 X X X
733-MHz cA2 X X X
533EB MHz cB0 X X X
600EB MHz cB0 X X X
667 MHz cB0 X X X
733 MHz cB0 X X X
600EB-MHz cC0 X X X
667-MHz cC0 X X X
733-MHz cC0 X X X

533B

MHz

kB0

533B

MHz

kC0

533E

600E

667

733

533E

600E

667

600B

B MHz

B MHz

MHz

MHz

B MHz

MHz

cA2

cA2

cA2

kC0

X X X X X X X X X X X

X X X X X X X X X X X

X X X X X X X X X X X

NI X X X NI X X X X X X

X NI X X X NI X X NI X X
X X NI X X
X X X NI

NI X X X NI

X NI
X X NI
X X X NI X X X NI X X NI
X NI X X X NI X X NI X X
X X NI X X X NI X X NI X
X X X NI X X X NI X X NI

cA2

X X

X X

B MHz

cB0

cB0

X

X X

X X X

X NI

X NI X X NI X

733

MHz

MHz

cB0

NI X X NI X

X NI X X NI

X X

B MHz

cB0

600E

667

733

MHz

cC0

MHz

cC0

cC0

X X X

NI X X

NOTES:

1. X = Mixing processors at different frequencies is not supported. This

stepping/frequency is not supported in Dual Processor.

2. NI = Currently no known issues associated with mixing these steppings.

DP Platform Population Matrix for the Pentium® III Processor with 133-MHz
System Bus in the SECC and SECC2 Package from 800MHz to 1.13GHz

Pentium® III Processor

Stepping

800EB-MHz cA2
800EB MHz cB0
866 MHz cB0
933 MHz cB0
1B GHz cB0
800EB MHz cC0
866 MHz cC0
933 MHz cC0
1B GHz cC0

1.13 GHz cC0

800EB

MHz cA2

NI NI X X X NI X X X X
NI NI X X X NI X X X X

NI NI X X X NI X X X X

NOTES:

1. X = Mixing processors at different frequencies is not supported. This

stepping/frequency is not supported in Dual Processor.

2. NI = Currently no known issues associated with mixing these steppings.

800EB

MHz cB0

X X NI X X X NI X X X
X X X NI X X X NI X X

X X X X X X X X X X

X X NI X X X NI X X X
X X X NI X X X NI X X
X X X X X X X X NI X
X X X X X X X X X X

866 MHz

cB0

933
MHz
cB0,

1B GHz

cB0

800EB

MHz cC0

866
MHz
cC0,

933 MHz

cC0,

1B

GHz

cC0

1.13

GHz cC0

Specification Update 23

Identification Information

DP Platform Population Matrix for the Pentium® III Processor with 100­MHz System Bus in the FC-PGA370 Package from 500 MHz to 650 MHz

Pentium® III

Processor

Stepping

500E-MHz cB0 NI X X X

500E MHz

cB0

550E MHz

cB0

600E MHz

cB0

650 MHz

cB0

600E MHz

cC0

650 MHz

cC0

600E MHz

cD0

X X X

550E-MHz cB0 X NI X X

X X X

600E-MHz cB0 X X NI X

X X NI

650-MHz cB0 X X X NI

X X X

600E-MHz cC0 X X X X NI

X NI

650-MHz cC0 X X X X

X

600E-MHz cD0 X X X X

NI

X

NI

NI X

DP Platform Population Matrix for the Pentium® III Processor with 100-MHz System
Bus in the FC-PGA 370 Pin Package from 700 MHz to 1.10 GHz

Pentium® III

Processor

Stepping

700-MHz cB0 NI X X X NI X X X X NI X X X X X X
750-MHz cB0 X NI X X X NI X X X X NI X X X X X
800-MHz cB0 X X NI X X X NI X X X X NI X X X X
850-MHz cB0 X X X NI X X X NI X X X X NI X X X
700-MHz cC0 NI X X X NI X X X X NI X X X X X X
750-MHz cC0 X NI X X X NI X X X X NI X X X X X
800-MHz cC0 X X NI X X X NI X X X X NI X X X X
850-MHz cC0 X X X NI X X X NI X X X X NI X X X
900-MHz cC0 X X X X X X X X NI X X X X NI X X
700-MHz cD0 NI X X X NI X X X X NI X X X X X X
750-MHz cD0 X NI X X X NI X X X X NI X X X X X
800-MHz cD0 X X NI X X X NI X X X X NI X X X X
850-MHz cD0 X X X NI X X X NI X X X X NI X X X
900-MHz cD0 X X X X X X X X NI X X X X NI X X
1 GHz cD0 X X X X X X X X X X X X X X NI X

1.10GHz cD0 X X X X X X X X X X X X X X X NI

700

750

800

850

700

750

800

850

900

700

750

MHz

MHz

MHz

MHz

MHz

MHz

MHz

MHz

MHz

cB0

cB0

cB0

cB0

cC0

cC0

cC0

cC0

NOTES:

1. X = Mixing processors at different frequencies is not supported.

2. NI = Currently no known issues associated with mixing these steppings.

3. TBD = No issues are expected, however further investigation is required to fully

validate this DP solution.

cC0

MHz

cD0

MHz

cD0

800

MHz

cD0

MHz

850

cD0

900

MHz

cD0

1

GHz

cD0

1.10
GHz
cD0

24 Specification Update

800EB

MHz

Identification Information

DP Platform Population Matrix for the Pentium® III Processor with 133­MHz System Bus in the FC - PGA370 Packag e from 533 MHz to 800 MHz

Pentium® III

Processor

Stepping

533EB-MHz cB0 NI X X X X X X X X X X X X
600EB-MHz cB0 X NI X X X X X NI X X X X X
667-MHz cB0 X X NI X X X X X NI X X X X
733-MHz cB0 X X X NI X X X X X NI X NI X
800EB-MHz cB0 X X X X NI X X X X X NI X NI
866-MHz cB0 X X X X X NI X X X X X X X
933-MHz cB0 X X X X X X NI X X X X X X
600EB-MHz cC0 X NI X X X X X NI X X X X X
667-MHz cC0 X X NI X X X X X NI X X X X
733-MHz cC0 X X X NI X X X X X NI X X X
800EB-MHz cC0 X X X X NI X X X X X NI X X
733-MHz cD0 X X X X X X X X NI X NI X

800EB-MHz cD0

667

733

866

933

667

733

533EB

600E

MHz

cB0

X X X X NI X X X X X NI X NI

B

MHz

cB0

MHz

cB0

MHz

cB0

800E

B

MHz

cB0

MHz

cB0

MHz

cB0

600E

B

MHz

cC0

MHz

cC0

MHz

cC0

800E

B
MHz
cC0

733

MHz

cD0

cD0

NOTES:

1. X = Mixing processors at different frequencies is not supported.

2. NI = Currently no known issues associated with mixing these steppings.

3. TBD = No issues are expected, however further investigation is required to fully

validate this DP solution.

DP Platform Population Matrix for the Pentium® III
Processor with 133-MHz System Bus in the FC-PGA370
Package from 866 MHz to 1 GHz

Pentium® III

Processor

Stepping

866-MHz cB0
933-MHz cB0
866-MHz cC0
933-MHz cC0
1B-GHz cC0
866-MHz cD0
933-MHz cD0
1B-GHz cD0

NOTES:

1. X = Mixing processors at different frequencies is not supported.

2. NI = Currently no known issues associated with mixing these steppings.

3. TBD = No issues are expected, however further investigation is required to fully

866 MHz

cB0

NI X NI X X NI X X

NI X NI X X NI X X

NI X NI X X NI X X

validate this DP solution.

933 MHz

cB0

X NI X NI X X NI X

X NI X NI X X NI X
X X X X NI X X NI

X NI X NI X X NI X
X X X X NI X X NI

866 MHz

cC0

933 MHz

cC0

1B GHz

cC0

866 MHz

cD0

933 MHz

cD0

1B GHz

cD0

Specification Update 25

Identification Information

DP Platform Population Matrix for the Pentium®III Processor with 133-MHz System
Bus in the FC-PGA2 Package from 866 MH z t o 1.4 GH z and uF CBGA2 Package for 800
MHz to 933 MHz

Pentium® III

Processor

Stepping

866-MHz
cD0

933-MHz
cD0

1B-GHz cD0 X X NI X X X X X X X X X X X

1.13-GHz
cD0

800-MHz
tA1
(uFCBGA2)

800-MHz
tB1
(uFCBGA2)

933-MHz
tB1
(uFCBGA2)

1-GHz tA1 X X X X X X X NI X X X X X X

1.13-GHz
tA1

1.26-GHz
tA1

1.4-GHz tA1 X X X X X X X X X X X X NI NI

1.13-GHz
tB1

1.26-GHz
tB1

1.4-GHz tB1 X X X X X X X X X X X X NI NI

866

MHz

cD0

933

MHz

cD0

NI X X X X X X X X X X X X X

X NI X X X X X X X X X X X X

X X X NI X X X X X X X X X X

X X X X NI NI X X X X X X X X

X X X X NI NI X X X X X X X X

X X X X X X NI X X X X X X X

X X X X X X X X NI NI X X X X

X X X X X X X X X X NI NI X X

X X X X X X X X NI NI X X X X

X X X X X X X X X X NI NI X X

1B

GHz

cD0

1.13

GHz

cD0

800

MHz

tA1

800

MHz

tB1

933

MHz

tB1

1

GHz

tA1

1.13
GHz

tA1

1.13
GHz

tB1

1.26
GHz

tA1

1.26
GHz

tB1

1.4

GHz

tA1

1.4

GHz

tB1

NOTES:

1. X = Mixing processors at different frequencies is not supported.

2. NI = Currently no known issues associated with mixing these steppings.

3. TBD = No issues are expected, however further investigation is required to fully

validate this DP solution.

26 Specification Update

Identification Information

Pentium® III Processor Identificati on and Package Information

S-Spec

SL364 kB0 0672h 450/100 512 T6P-e/A0 ECC D SECC2† 1, 2, 4

SL365 kB0 0672h 500/100 512 T6P-e/A0 ECC D SECC2† 1, 2, 4, 8

SL3CC kB0 0672h 450/100 512 T6P-e/A0 ECC D SECC2† 1, 2, 3, 4

SL3CD kB0 0672h 500/100 512 T6P-e/A0 ECC D SECC2† 1, 2, 3, 4

SL38E kB0 0672h 450/100 512 T6P-e/A0 ECC D S.E.C.C 1, 2, 4

SL38F kB0 0672h 500/100 512 T6P-e/A0 ECC D S.E.C.C 1, 2, 4

SL35D kC0 0673h 450/100 512 T6P-e/A0 ECC E SECC2† 1, 4

SL37C kC0 0673h 450/100 512 T6P-e/A0 ECC E SECC2† 1, 3, 4

SL35E kC0 0673h 500/100 512 T6P-e/A0 ECC E SECC2† 1, 4

SL37D kC0 0673h 500/100 512 T6P-e/A0 ECC E SECC2† 1, 3, 4

SL3F7 kC0 0673h 550/100 512 T6P-e/A0 ECC E SECC2† 1, 4

SL3FJ kC0 0673h 550/100 512 T6P-e/A0 ECC E SECC2† 1, 3, 4

SL3BN kC0 0673h 533B/133 512 T6P-e/A0 ECC E SECC2† 1, 4, 10

SL3E9 kC0 0673h 533B/133 512 T6P-e/A0 ECC E SECC2† 1, 3, 4, 10

SL3JM kC0 0673h 600/100 512 T6P-e/A0 ECC E SECC2† 1, 4

SL3JT kC0 0673h 600/100 512 T6P-e/A0 ECC E SECC2† 1, 3, 4

SL3JP kC0 0673h 600B/133 512 T6p-e/A0 ECC E SECC2† 1, 4, 10

SL3JU kC0 0673h 600B/133 512 T6P-e/A0 ECC E SECC2† 1, 3, 4, 10

SL3Q9 cA2 0681h 500E/100 256 N/A ECC B FC-PGA

SL3R2 cA2 0681h 500E/100 256 N/A ECC B FC-PGA

SL3VF cA2 0681h 533EB/133 256 N/A ECC B FC-PGA

SL3VA cA2 0681h 533EB/133 256 N/A ECC B FC-PGA

SL3QA cA2 0681h 550E/100 256 N/A ECC B FC-PGA

SL3R3 cA2 0681h 550E/100 256 N/A ECC B FC-PGA

SL3VH cA2 0681h 600E/100 256 N/A ECC B FC-PGA

SL3NL cA2 0681h 600E/100 256 N/A ECC B FC-PGA

Core

Stepping CPUID

Speed

(MHz)

Core/Bus11

L2 Size

(Kbytes)

Tag

RAM/

Stepping

ECC/
Non-

ECC

Processor
Substrate

Revision

Package

and

Revision Notes

9, 10

(370 pin)

7, 9, 10

(370 pin)

9, 10

(370 pin)

7, 9, 10

(370 pin)

9, 10

(370 pin)

7, 9, 10

(370 pin)

9, 10

(370 pin)

7, 9, 10

(370 pin)

Specification Update 27

Identification Information

Pentium® III Processor Identificati on and Package Information

S-Spec

Core

Stepping CPUID

Speed
(MHz)

Core/Bus11

L2 Size

(Kbytes)

Tag

RAM/

Stepping

ECC/
Non-

ECC

Processor
Substrate

Revision

Package

and

Revision Notes

SL3VG cA2 0681h 600EB/133 256 N/A ECC B FC-PGA

(370 pin)

SL3VB cA2 0681h 600EB/133 256 N/A ECC B FC-PGA

(370 pin)

SL3VJ cA2 0681h 650/100 256 N/A ECC B FC-PGA

(370 pin)

SL3NM cA2 0681h 650/100 256 N/A ECC B FC-PGA

(370 pin)

SL3VK cA2 0681h 667/133 256 N/A ECC B FC-PGA

(370 pin)

SL3T2 cA2 0681h 667/133 256 N/A ECC B FC-PGA

(370 pin)

SL3VL cA2 0681h 700/100 256 N/A ECC B FC-PGA

(370 pin)

SL3T3 cA2 0681h 700/100 256 N/A ECC B FC-PGA

(370 pin)

SL3VM cA2 0681h 733/133 256 N/A ECC B FC-PGA

(370 pin)

SL3T4 cA2 0681h 733/133 256 N/A ECC B FC-PGA

(370 pin)

SL3VN cA2 0681h 750/100 256 N/A ECC B FC-PGA

(370 pin)

SL3VC cA2 0681h 750/100 256 N/A ECC B FC-PGA

(370 pin)

SL3WB cA2 0681h 800EB/133 256 N/A ECC B FC-PGA

(370 pin)

SL3VE cA2 0681h 800EB/133 256 N/A ECC B FC-PGA

(370 pin)

SL3X4 cA2 0681h 800/100 256 N/A ECC B FC-PGA

(370 pin)

SL3VD cA2 0681h 800/100 256 N/A ECC B FC-PGA

(370 pin)

SL444 cB0 0683h 500E/100 256 N/A ECC B FC-PGA

(370 pin)

SL446 cB0 0683h 500E/100 256 N/A ECC B FC-PGA

(370 pin)

SL45R cB0 0683h 500E/100 256 N/A ECC B FC-PGA

(370 pin)

SL3XS cB0 0683h 533EB/133 256 N/A ECC B FC-PGA

(370 pin)

9, 10

7, 9, 10

9

7, 9

9

7, 9

9

7, 9

9

7, 9

9

7, 9

9, 10

7, 9, 10

9, 10

7, 9, 10

10

10

10, 7

10

28 Specification Update