Intel SIM4-02 User Manual

®

INTEL

CORP. 3065 Bowers Avenue, Santa Clara, California 95051 • (408) 246-7501

MICRO

SIM4-02

Nine PROMs board, enabling its own program. SIM4

Hardware Assembler and the MCB4-20 System Interface Control debugging.

(A0750

your

Module provides complete program assembly, simulation

COMPUTER

Hardware

to

A0758)

micro computer

The

Simulator

plug

into

prototype

when used

SYSTEMS

Simulator

the SIM4-02

to simulate and debug

in

conjunction

prototyping

with

the and and

©

Intel

Corporation

DECEMBER 1972

1972

1.0

2.0

3.0

4.0

Introduction

Number

Description

Directives

Systems

CONTENTS

............................................

..........................................

...............................................

Page

.

2

5.0

Error Messages

6.0

Operating

6.1

6.2

6.3

6.4

6.5

6.6

6.7

7.0

Jumps

8.0

RAM Usage

9.0

Examples

Instructions

Assemble Program Prepare

Load Program Execute Edit Punch Simulation

to

SI

M4-02 Hardware

Program

New

"BNPF"

of

Page 0

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Simulation

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Tape

................................

Programs

4

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4

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4

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5

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5

.

5

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5

7

1.0 INTRODUCTION

The

SIM4-02 Hardware

will provide interactive The

minimum configuration requited with 16 RAMs, itself occupies nine full ROMs.

The

Hardware Simulation Program has

1.

To

simulate

2.

To

allow

process.

These

two keyboard. or

program modifications, and some

A directive directive quired with

test

the

functions

Some

is

identified

is

associated

the

directive,

user

Simulator

control

programs

execution

to

dynamically interact with

are implemented by means

of

the

directives call for

by

a single letter

with

output

the

2.0 NUMBER SYSTEMS

SIM4-02 HARDWARE SIMULATOR

is

a program

over

the

is a SI

up

to

512 bytes (locations)

two

of a test

simulation program will enable

program, tracing its progress, and apprehending gross errors.

of

the

only,

written

debugging

M4-02

basic functions:

typeouts

directives involve

of

the

alphabet

the

typing (or punching) will

of

other

prototype

and/or

of

a set

by

for

the

in

modify

of

directives

the

simulator program,

(except

MCS-4 ™ series Micro

MCSA ™ programs.

card

with

three

4002

length may be accomodated.

his

test

program,

or

commands

some

both

the

typeouts

the

paper

and

arithmetic conversion directives = and It). If

commence

tape

reader

Computer

RAMs and a Teletype. When fully

in

order

which

of

input

response

immediately. If

control,

System. This program

The

hardware simulation program

to

facilitate

the

user

the

directives signal

or

and

wait

types

data.

input

for valid

the

debugging

in

at the

is

allowed

the

input

stuffed

teletype

of

data

the

or

re-

data.

Two

number

gram

counter ROM in

either radix

the

program. Unless so identified, however, all

To

facilitate working bers coded either the

letter N

All

input leading zeroes are implied as necessary. If significant end of register. This may be used bits

in return, a will give unpredictable results, and should be avoided. ded within

radices are standard with

and

instruction location values, chip numbers, and some pointers are handled in decimal for convenience.

instructions,

numbers

the

receiving field,

comma,

the

by

prefixing it with a suitable indentifier

with

as

strings

is

interpreted as a one.

are right-justified into

the

number. Thus,

a space,

input

number

the

hardware simulation program: binary and decimal. Index register values, pro-

accumulator

program tapes

of

to

then

or

value, and one-bit indicators are handled

in

the

ones and zeroes,

the

receiving register

the

if

it

is

attempted

advantage

re-typing

the

letter

strings with no adverse effects.

in

the

number, all as one string

"F",

or

input

"BNPF"

or

as

strings

number

event

in

the

should be

of

case

3.0 DESCRIPTION

The

hardware simulation program allocates a user-selected block

tions

to

be simulated, assigning

ROM, all 16 RAMs

by

the

test

program. registers (equivalent tive banks (with wraparound)

parameter storage

The

program simulator program adds a bias value increment

Another cause this

to

error

interrupt

must

In

to

three

must

be in

to

be tested may have an address anywhere in

outside

the

interrupt

are:

occurs

two

be used.

addition,

RAM

of

sixteen registers each, so

one

range

of in

11111110,

RAM

locations for each simulated

Any

RAM

locations

the

hardware simulation program uses

chips)

to

hold simulation parameters.

block

of

contiguous

to

all addresses

the

simulated ROM, an error

the

event

of

11111111,

which

an illegal instruction

11100011,

in

binary.

("0"

for decimal,

in

the

format,

is

larger

to

an inadvertant error

Rubouts

not

banks and registers within banks.

the

of

"P"s

or

field.

than

load

an

index register

of

the

= directive, with plus

are

Rubouts

of

allocated for program storage

that

if less

the

4096

reference

interrupt

and

all

"8"

for

binary), regardless

radix used

hardware simulation program will

and

"N"s,

If

the

receiving field,

of

digits. A

the

only non

are ignored

RAM

main

ROM

the

RAM

than

locations

the

simulated ROM. If

occurs.

op

code

instructions

in

the

where

the

number

with

the

typein,

status

16 RAMs are used,

during simulated

by typing

number

"numeric"

in

all cases.

memory

location.

characters

is

assumed

of

addressable, ROM, since

with

aPR = 0000

Any

input

corresponding

letter P is

is smaller

the

or

locations

Thus,

than

excess bits are lost

value 20,

typed

minus sign.

may

to

the

in

as in

characters which

to

simulate

be accessed in twelve consecutive be organized as

those

the

program

execution.

except

number

interpreted as a zero, and

many zeroes as may end

allocated

may

of

the

expectations

typeout.

accept

binary

the

receiving field,

from

result will be 4

with

Any

other

may

hold

the

ROM

512

locations

in

the

four

to

the

hardware

attempts

The

op

for

00000000

be

entered

of

num-

the

most-

in

the

there

are

a carriage

characters

be imbed-

instruc-

of

normal

program and

codes

way

RAM

consecu-

to

jump

which

(NaP).

or

A

breakpoint

register which will cause an some

other

types

During'simulated program,

to

assist in checking

4.0 DIRECTIVES

lin

Binary conversion This directive accepts a bers

to

4095) may be accomodated

=n

Decimal This directive accepts a string sum, may be used

Or,s,e

RAM/ROM This directive the are required. current block allocated tions allocated the ROM in access option

Z Zero

This directive not

In

Input This directive accepts a sequence ning with location n. Spaces, commas, returns, and linefeeds may occur with

individual numbers.

used The

Pn,m Punch

This directive at ter location. If Both

Mn,i Memory

This directive accepts a sequence tions, beginning (i

15, goes into register r + 1, digit

are

Dr, n Dump RAM

This directive beginning with register

adder

modulo

current

values will be unchanged. r

likelihood

segment

an out-of-bounds interrupt. e

to

ROM

word

allocated

to

introduce

program

location n (decimaJ), and ending

are altered by this directive. Four inches

the

breakpoint

input

less

than

filled.

is

associated with

interrupt

of

output.

before execution.

execution, a count

out

the

simulated execution mode

The

BREAK key on

is

kept

of

the

number

programs with critical timing problems.

single (decimal) number, and

at

once.

of

(decimal) numbers separated by plus and minus signs, and

4096.

If

the

to

perform binary

chip

assignment

must

be entered before any

values are

If

of

to

typed

any

of

to

ROM.

to

simulated ROM, so improper access. be simulated.

algebraic sum

to

out.

Then,

the

three parameters

The simulation program has

Any

is

negative, 4095

decimal conversion thus: =Bnnnn

other

letter directive. If

or

immediately after

is

omitted,

is

the

(decimal)

the

user

must

If r is

greater

attempt

the

(decimal) ending address

than

to

execute

locations greater than this address will result

to

zeroes.

simulates

to

counter

will punch

the

BREAK

16),

only

The

sequence ends with a carriage return following

types

the

hardware reset function, and clears

program.

a (decimal)

in

register n (decimal, 0-63) and location i (decimal, 0-19).

The

Input

is

terminated

number

in

the

current

out,

in

key

on

register and

Q directive executes a Z each time

of

(binary) numbers and stores

by

a free-standing letter F in

which, like n, becomes

stack level

"BNPF"

with

the

teletype

the

program

of

(decimal) numbers (0-15) and stores

is

altered

format

with location numbers,

location m.

of

leader and trailer are punched on

is

depressed between locations,

counter

main memory locations are filled.

O.

If

the

starting location

out

in decimal

r.

The

the

typeout

contents

may be

of

each

ended

of

operation, allowing

the

teletype

of

simulated machine cycles (i.e., sync pulses) used

types

out

its equivalent

may also be used

in

binary. A maximum

the

user

to

types

is

logically added

the

Q,

three

or

if a RETURN

RAM

register number (0-63) which

no

way

of

preventing

use care

63,

in

selecting a value

the

previous value

to

it

to

give a positive result. This directive

first character after

the 0 is

parameters separated by commas

is

typed

the

test

for

is

used. s

instead

of

the

is

used as

program from accessing

this parameter which will reduce

is

the

starting address

an instruction with an address less than this

of

the

ROM

segment

in

an out-of-bounds interrupt. This directive clears

to

zero all simulated registers, counters, and all RAMs the

parameters are changed.

them

in

consecutive simulated

the

sequence. An ASCII SOH (control

the

new starting address

by

this directive.

the

contents

The

currently

selected program

the

in

the

current

stack level are altered by this directive.

them

If

The

is

a status character

the

terminal delimiter

RAM

location

after

(both

main

prematurely by depressing

to

be simulated.

any

frequency

for

of

the

counter,

the

tape, with an

typeout

sequentially the

starting location

the

one

which goes into register r, digit

(i

greater

than

of

the

memory

the

BREAK key.

or

subsequent instruction bytes.

simulated

will be aborted, with no trailer.

in

last number.

and status)

to

pre-set a location

interrupt execution and

by

the

test

of

12 bits (num-

out

the

algabraic

a space

first parameter,

the

or

lowest

number

Any

comma,

or

spaces

the

in

the

RAM

of

the

will result

program

loca-

the

ROM

locations, begin-

pattern between

ROM

and

the

breakpoint

"F"

after

consecutive

is

in

main

15), only status characters

of

the

A)

may be

beginning

regis-

the

last

RAM

loca-

memory

n registers,

2

A

Accumulator This directive

ing

the

new value

C

Carry/Link This directive may be used

ive

is

the

Xn

Index This directive a space n

is

followed by a space, index register n comma, 2n

and

S

Stack

pointer This directive may be used tion

counter

by

BBl

l

location This directive may be used the

value

E Examine Everything

This directive stack are displayed.

R RAM/ROM selection

This directive may be used after

the R types selection effected as last used

B

Breakpoint This directive may be used will always be the

second

W When

This directive may be used (decimal)

T Trace

This directive causes in

the

current BREAK key, program was never basic

format

pppp:iiiiiiii c aaaa rr

where

pppp being simulated; c index

or

omitted

N Non-trace

This directive

o

Options This directive may be used following significance;

10

1000

may

A will display

to

be

entered,

same as

or

slash,

2n

instructions.

Counter

of

counter

index pair used

on

1

for

may

comma

follows

or

period, index pair

+ 1 are handled

is

the

stack

combines

out

by

an SRC instruction.

interrupted

byte

of a two-byte

used

location

or

an illegal instruction,

of

the

is

the

decimal location

is

instructions which

is

identical

Input,

Output,

on

the

teletype

No

interrupt

Unconditional jumps and

interpretively, permitting

be used

one

interrupted,

trace listing

to

display

in

binary,

or

by a carriage

to

display

A.

to

display

the

X,

together

to

display

pointed

to

display

pointer

No

an 11-bit binary

the

will cause a

the

display

modification

to

display

last

DCl

to

display

before processing

to

display

to

tally

simulation program

counter.

resultant carry/I ink bit; aaaa

in

the

to

the

to

display

and CPU

the

for

subroutine

and/or

the

contents

and/or

all 16 index registers are displayed (in decimal). Otherwise, if

number n may

as a single 8-bit number.)

and/or

to

by this pointer. This

and/or

functions

is

possible.

and/or

number,

instruction, and

and/or

instruction, no

and/or

the

number

If instruction

the

except

insofar as program parameters

is

counter;

instruction. (value,

do

not

reference

T directive,

and/or

test

port

number

stack overflow subroutine direct

alter

the

contents

of

the

simulated accumulator. This

return

to

end

the

alter

the

contents

alter

the

contents

may

be displayed

be displayed (in decimal)

alter

the

contents

alter

the

contents

different

of

T directive will cause

instructions are

register

of

the

C,

A,

modify

the

alter

to

iiiiiiii

except

alter

and

byte

the

of

which

the

least-significant 8 bits represent

the

instruction

breakpoint

the

contents

instruction cycles used during

begin simulated execution

execution

is

the

is

not

index number)

their

respective registers.

that

the

current

then

typing

or

jumps

I/O during checkout.

of

directive.

of

and/or

of

pointer

simulated the

contents

binary representation

the

execution

to

is

of

to

be

S,

l,

R,

most-significant 3 bits represent

pointed

action

of

simulation

the

resultant

option

executed

or

accepting

underflow will

ROM

the

simulated accumulator. A space

or

the

A may be followed

the

simulated Carry/Link bit.

anyone

altered as in A. If

the

incremented by JMS instructions and

the

current

and X directives.

memory

of

will occur during

the

proceeds

directly

page 0 (chip 0) are

or

and/or

subroutine

current

location

chip/location

the

breakpoint

to

by

the

simulated

instruction

of

is

interrupted

program

accumulator

or

registers

Any

status

occur

to

or

without

bits.

when

the

pair

of

the

altered as a unit.

stack pointer.

location

counter.

All

register.

breakpoint.

instruction

sync

cycle

the

test

program, beginning

by a

resume

were

of

the

(first

value; and rr

all

of

the

tracing.

This

is a 4-bit binary

this

bit

data.

when

this

executed

simulated index registers. If

number n is

counter.

four

the

simulation.

breakpoint, where modified while

last

is

The

the

The

Note

program

seleetion. A space

the

command

contents

The

simulated

If

the

breakpoint

simulation.

counter.

it left off,

byte

of

is

the

three

on,

instead

bit

is

on.

directly instread

or

comma

use

of

(decimal)

followed

(Index

current

decremented

that

counters

of

the

This

at

the

keyboard

just

interrupted.

the)

instruction

resultant

numbers

number

of

typing

either

this direct-

number

by

registers

loca-

altering

in

or

comma

line

index pair

execution

points

is

a 12-bit

the

address

as if

the

(decimal)

may

be

with

out

of

follow-

by a

a

the

to

The

the

3

5.0 ERROR MESSAGES

Most

of

the

errors which can be detected by

by ringing CODE SIGNIFICANCE

? This

the

bell once. Six different types

is

not

a valid directive. Any printed graphic normally generated

evokes this response. A question

the

simulation program are identified by a single character

of

errors are identified this way:

mark-bell combination also calls

# Break condition recognized. This occurs normally, either when

register

> Location

address

Invalid typed the

% Location

tion has been executed or

Cancel. This I, canceled, and If

Test line, it to

in

execution simulation,

counter

out

op

out,

T directive may be entered

counter

retu rned to).

M,

T, and N directives, it cancels

used while

accept

another

out

of

range. This error occurs

of

the

range specified

code. This error occurs and

but

before

the

location

stack overflow

in

simulation. A T

is

the

program response

the

directive

the

simulation program

is

equivalent

to

directive.

or

in

to

examine

or

is

terllJinated

a break

when

the

BREAK key

in

the

most recent Q directive.

is

recognized during execution simulation, after

counter

the

at

is

incremented, so

the

error by trying

underflow. This error

or

an N directive will resume execution with

to

a Cancel (Control

entire directive. If used

at

that

point. Previous values, if any, have already been stored

is

requesting

the

beginning

input

is

depressed

simulation

is

unique

"X"

data from a simulated

of

the

instruction.

typeout,

by

the

ASR33, which

attention

the

location

or

ROM

that

if it occurs under

to

execute it again.

in

or

ESCAPE) typein, during data input. Except

in

the I or

to

a simulated input request.

counter

in

simulation

punching,

that

M directives, only

In

each case

if

the

interruption occurs

ROM

the

is

not

a valid directive,

reaches

or

an

port

the

value

ROM

or

RAM

attempt

the

control

the

simulation program returns

is

made

instruction

of

the

after

the

current

or

the

simulated

followed

in

the

break

dumping.

to

access an

byte

is

N directive,

the

instruc-

datum in

memory.

CPU

for

is

6.0 OPERATING INSTRUCTIONS

6.1 Assemble Program First assemble

Program will and addresses together, block of Control

Prepare SIM4-02 Hardware

6.2 Remove

RESET. ready

to

Determine how much simulated

test

program, using if necessary

testing of this program has been completed and

RESET

destroyed.

6.3

Load Program

the

Place instructions from

terminal F punched

directive will be ignored. Note also

overlap loaded, a simulated RESET may be effected by loaded with data, be loaded up with

the

test

program on the Hardware Assembler (A0740

not

accept

ROM

program tapes created

with

no identifier

ROM

locations, since

"A",

SOH preceding them), and place

ROM

chips

A0740

The

teletype should

accept a directive.

button.

is

If

the

RESET

object

tape

in

the

tape

by

possible. Thus, location 100 would be overwritten by instructions going into location 612. When the program

the

appropriate directives may be used

data

the

through A0743 and plug

type

ROM

the = and"

button

the

teletype

and store

the

assembler. Note

if

desired. If a subroutine or a

for

I directive

out

in

a carriage return-linefeed, and an asterisk

is

needed

directives. Then

is pressed, the simulation parameters

reader, and them

in

the

that

if

the

to

A0743). Important:

by

the

FORTRAN assembler, ASM4, as these tapes have bit patterns

the

addresses. It

the

simulation program

the

instruction patterns into

in

to

test

the

amended program

type

in

proper locations. Reading will be terminated by any error

any

illstructions

Q directive defines

the

Z directive. If starting

part

is

not

necessary

the

Hardware Simulation Program chips, A0750-A0758. Press

program, and which RAMs are least likely

type

in

the

tape

I.

The

simulation program will read

or

data which fall outside

the

ROM

to

set these up. A breakpoint may be set

of

a subroutine

to

assemble

is

able

to

recognize

the

proper simulated

to

show

Q directive for this program. From now until

has been punched

and

any

program in the simulated ROM will

limits

to

be more

at

other

than location zero, or with registers pre-

is

being tested,

the

Hardware Simulation

the

program

the

address fields (by

ROM

that

the

simulation program

out,

DO

both

the

limits defined

than

512

if

the

stack may be loaded with a

in

one

contiguous

the

locations.

to

be accessed by

NOT

touch the

addresses and

or

by

the

in

the

bytes, wraparound

desired, and

RAM

is

the

be

the

Q

is

may

4

return address using

loaded into

be rupt

at

the

first occurrence of a JMS instruction, causes a stack overflow. serted into rupt

6.4 To

start stop BREAK key may be depressed, and

tion

the

occurs, and

Execute Program Simulation

the

execution simulation,

execution simulation, whether because

will resume as

the

L directive.

the

first subroutine level, or

If

it

program

at

the

instruction may be replaced, or

if

uninterrupted,

That

is

desired

desired points. When

type

the

if

the T or

may then be pushed down with

the

process may be repeated up

the

stack pointer may be set

to

achieve more

a T (for Trace mode) or an N (for non-Trace mode). If

of

program errors,

simulation will be interrupted

N directive

than

the

simulation

the

program

one breakpoint, illegal instructions may be assembled

counter

to

examine register contents, or

is

typed

6.5 Edit Program

To

make corrections

the

alters

be incremented first and decremented afterwards - (unless of course,

6.6 After

Four inches of leader and trailer are punched by this directive.

punched while of directive necessary.

contents

Punch New the

program works correctly, an amended

the

program.

if a tape

to

the

program,

of

the

current location

"BNPF"

the

simulation program

The

is

Tape

user should remember

to

be made. If it

the

I directive

counter.

is

waiting for a directive. This will

to

is

desired only

is

used, giving an address, and

Thus, it should either be noted and restored, or

ROM

tape

may be punched

If

turn

on

the

paper tape punch after typing

to

examine

the

more

6.7 Simulation of Segmented Programs

If

a program

in

segments. Suppose

by

the

would be something

is

not

0 directive

very large,

the

program occupies

to

hold

all

like this:

but

is

scattered over a wide range of addresses, it may be possible

the

of this. Suppose

first 32 locations

further

that

in

the

program accesses only bank zero

016,0,127

Then

the

first 32 locations of

deleterious effects, if

Then

the

data.

0 directive

that

the

program

is

convenient,

is

used again,

tape

are read

or

an F may be

to

re-assign

in

using

typed

the

same locations

the

in

manually

099,224,355

Note

that

the

address limits have been offset by 32,

may be read reassigned again:

in

again, or

at

least

that

part

of

it which includes the

to

prevent

the

obliteration of

The process

typed occurs.

to

used program up

is

repeated until

in

again.

If

the

The

0 directive for

relocate a program

one

position

the

whole program

segments are placed correctly, each time a

the

segment jumped

in

ROM:

for example,

in

ROM:

is

loaded.

to

is

the

To

execute,

entered; and

following sequence of commands will effectively move (shift) a

jump

the

00,0,255

10

(program)

00,1,256 P1,256

the

S directive, so

to

three times.

to

3 initially, so

attempts

in

contents

each of four ROMs. 128 locations

I directive.

execution of one of these locations, an inter-

incremented around it

at

the

completion

after a break.

the

simulation

in

is

needed, rubouts

not

of

at

to

the

block

of

the

0 directive for

is

made to

program may proceed. This technique may also be

is

the

"BNPF"

in

any

way

a simulated

The

entire

the

end of

the

data

or

another

that

the

starting address may

If

it

is

desired

that

to

at

any time it

to

of

the

current

value(s)

first 32 locations.

to

be entered.

interrupted

format

or

nulls (shift-control-P) may be

interfere with normal operation

in

the

second address

ROM

to

in

tape

may be read with no

the

first 32 locations'

instructions.

the

starting block

segment, an out-of-range

to

force an

the

first JMS instruction

proceed.

is

desired

make corrections,

instruction. Execu-

The

the

stack

pointer

at

subroutine

using

the

P directive.

in

location, this

accomodate

must

RAM.

Then

is

the

be reserved

The 0 directive

worth

The

object

the

area

of

code

I directive

nest level 3).

the

not

inter~

or

in-

to

the

may

P

program

of

tape

is

interrupt

7.0 JUMPS TO PAGE 0

Because the directly, returning keyboard input, 7 bits wide (the parity

of

the

nuisance of doing serial-to parallel conversion, and properly timing

simulation program

to

simulation mode

is

provided with an

option

upon

return.

bit

is

ignored), teletype

the

bit

frames

to

perform subroutine calls and unconditional jumps

ROM

page 0 contains subroutines

output

8 bits wide, binary

5

to

perform

to

decimal conversion and

in

teletype

input

to

ROM

reader and

and

page 0

output,

the

typing

acter

input

programs,

The

following NAME KEY

TTl

TXX

T6R

T6l

010

Z47 PUN

IPR

RETN

MSG SPACE

DIGIT

PDN

BCD

of

some

specializ~d

with

control

or

the

ROM

may be included

is a summary ADDRESS 120

117

234

205

220

183

6 (4-7) This 80

70

107

66 63 53

40

11

(X) FUNCTION

(11-15) This

in index registers register

character

(11-15) This

reader

(10, 11, 14, 15) This

and

1.

The bit

value,

2.

The space is

taken.

3.

The to

location

4.

The with

(10-15) This

through ' ...

characters

no

echo

is

set

(10-15) This

character contain during simulation.

(4-7, 10-15) This

number called alternate

(11-15)

11

through

(11-15) This

a

15

(11-15)

main

(11-15) (11-15) This (10-15) This

zero, incremented.

(4-7, 10-15) This

4

through

(1-7,10-15)

four

sequences

character

of

the

routine

11

determines

typed

routine

control

the

character

centered

character

and

slash. An indirect

character

256

character

the

accumulator

routine

".

and

occurs. On normal return,

if

the

character

routine

is

left-justified

subroutine

in register 15

repeatedly

exit

routine

This

routine

15 are cleared

routine

ms

delay

This

routine

routine.

This

routine routine routine

and

the

7. This

digits

with

of

characters, partial decimal

checking. A

in

the

subroutines

inputs

14

and

whether

in

is

printable.

inputs

is

enabled), and

routine

in registers 14

is

some

printable graphic

in

the

is a control

is

taken.

is

one

of

those

non-zero.

combines

Characters

delimiters. Note

is

a letter

is

the

calls nested

subroutine

to

input

in

registers

clears registers 4

prints

does

the

occurs

to

allow

types

types types types

register

10

routine

zero suppression.

to

test

program

final program if

and

their

one

7-bit

15. I ndex registers 12 the

one

7-bit

is

examines

and

byte.

The

character

jump

between CAN (Control-X) and

not

TTl and

in

group

that

or

same as

in

registers

three

multiplies

the

product,

and

convert

10

and 11. Register 4

through 7 to

or

punches

to

zero

same as PUN,

the

out

a carriage

out

the

character

one

space.

an ASCII digit contains

will print,

converts

may

use these

teletype

calling parameters:

character

otherwise

the

carry

15

to

determine

between

carry

is

between

to

the

address

generated

TXX

such

(4) above are ignored, and

if

the

address

the

character

higher.

T6R,

except

14

and

deep,

and

the

12-bit

then

goes

to

binary

the

character

on

return.

except

teletype

15, a space

the

printer

return,

in

corresponding

with

zero

12-bit

interface and

from

the

and

is

echoed

from

the

exactly

bit

the

set

"0" and '+".

turned

on

null and ETB (control-Y)

in

by

a KSR33

that

to

is

right-justified in registers 14 and 15, and

that

on

15, leaving

may

binary

to

T6R

a decimal

is

used for scratch.

binary

in

that

to

a null, and a linefeed. It

registers

is

typed

suppression,

binary

number

binary conversion

subroutines

teletype

13 are cleared

back (0 = yes, 1 = no).

teletype

same as KEY.

by

if

one

if

ROM

normal return

which

normal

the

only

to

zero in registers

if register

settle.

14

to

instead. Unless a space

keyboard,

paper

KEY

or

of

the

it

is

a letter. A normal

page 1

US

(Shift-Control-O). An unconditional

teletype,

the

return

lower

be called

number

input

number. A terminal

preparation

14

and 15,

the

BCD

the

four-digit decimal

in

registers 1-3

on

to

facilitate

the

same ancillary

to

zero.

tape

TTl as well as

following

If

so,

the

or

contained

or a rubout.

occurs

alternate

delimiter

the

two

bits zero. Both

from

in

registers 5-7 times

another

and 15

11

is

initially even (echo

may

then

follows it

number

input,

and

6-bit

checkout

routines

and

returns

The

reader

conditions

character

a printable graphic

in

index registers 10 and

only

exits

return

carry

is

the

main program,

digit. This

for

010.

out

on

only

in

the

is

into

it, left-justified,

least significant

The

carry

or

keyboard

the

accumulator

obtains:

is

biased

return

is

A normal

on

characters

are

taken

is

to

be made

always zero, and

T6R

ten,

routine

delimiter

the

teletype.

be

called from

with

a bell.

accumulator.

typed,

register

number

decimal,

teletype

of

complex

are needed.

bit

is

set

if

(the

to

a six-

taken,

acc=O.

between

return

is

"0"

for

control is

odd,

the

carry

and

T6l

except

and adds

may

takes

the

Registers

mode

on

the

If it

10

in registers

and

prints

char-

of

the

value

11

jump

taken,

the

be

input),

is

the

6

8.0 RAM USAGE

The

simulation program,

containing 16 main memory

to

facilitate full usage

locations and

of

the

RAM, has organized it into a nominal block

four

status locations. Directives which reference always address it by a register number, and sometimes by a character position within illustrates this addressing scheme:

DIGIT

Bank RAMO

(Port

Bank 0 RAM

0

0)

1

REGISTER

(selected even in SRC instr.)

by

index

0 1 2 3

4 5 6 7

8 9

(selected

0

1 2

4 5 6

3

by

odd

index

7 8 9

in SRC instr.)

11

10

·

12

the

RAM

register.

14

13

of

64

registers, each as such (i.e., The

following

15

16

0,

M,

chart

[Status]

18

17

and

19

0),

Bank 1 RAMO (Port

Bank RAM (Port

Bank RAMO (Port

Bank RAM (Port

4)

2

3

11)

4

12)

4 3

15)

·

16

17

18 19

20

·

44

45 46 47

48 49 50 51

52

·

60 61 62 63

7

The bank number of

RAMs.

The

positions 16-19 (Le.,

in

the

port

number given corresponds

the

instructions, respectively. The

Q directive

other

registers and parameters. Whole

the

first parameter. locations used represent

formula: n =

the

is

used

is

determined

values

(s

to

The

in

the

+ e}/8 + 1

This value may be more RAM

main

memory address equal first parameter

locations reserved by

to

the

second parameter

of

the

Q directive; subsequent instructions are loaded into

addresses. The

RAM

status

locations reserved by

Relative REGISTER

r + 0 0

lOC'N. 0

1-3

0 1 2 2 3

1-3

0

1-3

0 3 1-3 4 4-7 5

6,7 8-11

0

1-3

0 Simulated Command line selection

0 Simulated

0-3

chart above

status locations) are normally addressed

define and set aside some part

is

RAM

the

value

of

the

to

the

registers are taken by

accumulator during a

number

of

typed

RAM

out

in

the

for use by

the

Q directive, beginning with

during simulation

program by

status locations from exactly 12 registers are used

by

the

second and

or

less than 12,

difference between

third

parameters

the

number

the

Q directive are used solely for program storage.

of

the

Q instruction

the

simulation program are allocated

the

second and third parameters of

of

the

Q directive,

of

registers whose

is

loaded into digits 0 and 1

status

FUNCTIONS

Simulated

low Option High

Accumulator

ROM

address limit

word

ROM

address limit Execution parameters Breakpoint address

Simulated Carry Simulation Simulated Stack

Cycle

counter

pointer

Simulated Stack

ROM

or

RAM

chip selection

Simulated

index registers

DCl

instruction, needed

of

the

WMP

the

RDO/WRO,

the

simulation program

the

by

the

simulator. The number of main memory

the

Q directive. Where

the

number

of

registers used

locations are used, with no

The

instruction with an

of

the

register designated

the

following digit pairs, according

to

the

following functions:

to

address

that

instruction. Register

RD

1 /WR 1, etc.,

as

simulated

ROM

register identified

sand

is

determined by

ill

effects.

by

to

the

bank

and

in

e

the

9.0 EXAMPLES

Figures 9.1, program described entered

9.2

and

via a TTY

in

keyboard.

9.3

are annotated listings generated during actual simulation. Figure 9.1

figures

9.4

and 9.5. Figures

9.2

and 9.3 represent

the

simulator's response

is

a simulation of

to

various directives

the

"ANO"

8

SIMULATOR

IN

ACCORDANCE

DELIMITED CHARACTERS ASSEMBLER)

TRACE AFTER

HAVE

MODE PROGRAM

BEEN SET

RDR

EXECUTED. FOR

TO

WITH

FROM

INSTRUCTION ADDRESS

FIRST

BYTE

OF I NSTR UCT I ON

MEMORY IS

ASSIGNED

INPUT

INITIALIZE

BLOCK

COMMAND

~

/r

SPECIF IES OR IGI N 1

ASSIGNS ADDRESS

WITH

DATA

BY

"CONTROL

A"

(HARDWARE

IS

INITIATED

__

-;::.-=*~T

COUNTERS

INSTRUCTION

IS

----+......:.;R~.,-::-4:,;.;:~;-;;!~!-:-!.~0000

REQUEST

DATA

IS

REPLIED

"0111"

ENTRY

KEYBOARD

_________

TRACE

MODE

+-_~!:-:!~~:!:!!::~!

:-

--------t--T-:~

OUTPUT MEMORY

NON-TRACE IS

TO

PORT

INITIATED

NON-TRACE

~

" M 0

MODE

ASTERISK

~EADY

.L.

*Q0 ., 12!j

.10

16:

1081BNNNNPNNPF

112:BNPNOlPPP~F

I 161BNNNNPNNPF

8P~NpNPNNF

124:aNPNNPpP~F

128:

F

:~

*8

__

::~:!:!::~

3:

6100101001 7111101010

R I

8110110001 0 0000

9101010000 104111110000 0 0000 105:10110010 0 0000 106111010100 0 0100 107110110000 0 0111 108:11110110 I 0011

109110110000 110100011010

112110110001 I 1110 113111110110 0 1111 114110110001 0 0100 115110110010 0 0000

!!~:!!!!:!!: :':~::

I1S111111000 1 0011 119100011100 1 0011 107110110000 1 0011 108111110110 1 1001 109110110000 1 0011

!

:~:~:~:!:!~

113111110110 1 1111

116111110110 117110110010 0 0011 118111111000 1 0010 119100011100 1 0010 107110110000 1 1001

:;;.;~~::-;:~~~:7:~:0;i;1

110:00011010 1 0010 112110110001 1 1111 113111110110 1 1111 114:10110001 1 0010 115110110010 1 1000 116111110110 117:10110010 0 0010 118111111000 1 0001 119:00011100 1 0001 107110110000 1 1100 108111110110 0 1110 109110110000 0 0001 110:0001101000001 122:10110001 0 1111 123:11110110 124110110001 1 0001 125111110001 126:01000000 115:1011001001100 116:1111011000110 117110110010 0 0001 118:11111000 1 0000 119100011100 I 0000 121 :

11:10110010 1 0110 12111100001

13101000000

*L

*5

"

*8

*N

R 0 R 1 M 0

IS

SIMULATOR

OUTPUT

INDICATION

01

0:BPP~PNPPPF

4:8."POl~PPPPF

~::~~~~~~::~:

1041

104IBNN~~PPPPF

121:8NNPPPPPPF

128:

1281

\/~8_0

_____

0

_

11101010

5101101000 0 0000

11110

~~:;...:

11000000

0110

0

10111 11110

0110

I

BPPPPPPPNF

518P.'J:-JPNPPPF 618PPNPNPPNF 71BNNNPNPNPF

1

~:::~:~:~::~

109 1131BNNNNPNNPF 114:BNPNNPPPNF

117:B~PNNPPNPF

125:BNNNOlPPPNF

1051BNPNNPPNPF 1061BNNPNPNPPF 1071BNPNNPPPP

I BNPNNPPPPF I 101BPPPNNPNPF 8PNNNNPNPF

2:BPP~P~PPNF

::~~;~::;:.

1181BNNNNNPPPF 1191BPPPNNNPPF

122:BNPNNPPPNF 1231BNNNNPNNPF

126:BPNPPPPPPF

~

0

0000

17----'"

14

0 0 4

II

00110000/3

4

IS

4

0

3

9

------

:

~~:!

3

! ::!!

1;

1.3

1000

8

2

!!~:

12

2

15

1100

0001

----------

2

12

14

7

6

0

Ii}

10111

Ii}

I

31BNNNPNPNPF

:

~::~:~~;~~~~

115:BNPN~PP~PF

BPNNNPPNNF'

PRE-PUNCHED TAPE

INPUT

LOCATION HAS

128. RESET STACK

BREAKPOINT

CONTENTS

COUNTER

ADVANCED

TO

IS RESET

IS

OF

ACCUMULATOR

CARRY

CONTENTS OPERATED

TO

STOP POINT POINT, NEAR

BREAKPOINT NEXT

TERMINATES

OF ON

TRACE

OTHER

DEPRESS

COMPLETION

AT

LOCATION

TRACE

TO

0

TO

0

LEFT

AT

0

PAIR 4 (DECIMAL)

(BINARY)

REGISTER

(DECIMAL)

MODE

AT

THE

A

BREAK-

KEY

THAN

BREAK

OF A LINE.

Figure 9.1. Trace and Nontrace Modes.

9

FIRST

LINE

DUMP

RAM

COMMAND

*Z

20

*00

2 8 0

11

1 5

0

0 0 0 0

0 0

0

0 0

0

0 0

'"

0

.,

0

'"

(3

0 0 0 0

0 0

0

'"

0

.,

0

"

15

0

11 2

" "

11

1

15 6 11 1 11 2

6 11

12 " 11 1 15

Ii!

0 " 0 0 0 0

"

0

'"

.,

0

" "

5

*M4

55

"

*1'14

5 5 6 7

1

*1'118

1

*D0

20

11)

2 8

1

5 0

11

0 0

0 0 0

11)

0 0

"

0

"

0

"

0 0

0 0 0 0 0

"

0

0 0 0

0 0

0

(3

"

15 0 11

"

1

11

15

6

11

12

0 0 0

0 0

0 0 1 2 0 0

0 0

1 2

0

6 8 11 2

0 0 0

11)

0

"

0

0 0

"

0 0 0 0

.,

"

0

" "

0 0

"

13 4 11

(,)

0

"

0 " 0

6'

8 9

234

1 2 9

6

" 0 "

11)

0 0

"

0 0

"

(3

0

"

0 0

"

2

13

" " "

11

6

0 11 1

" 0 "

4

3

" " "

"

5 6 7 8 9

£

9

14

10

11

0 6

14

0 0

11)

0

"

0 0

"

.,

0

"

0

"

0

"

10

11

14

8

11

0

5 6 7 8 9 10

"

0

"

0

"

0 0 0 0 0

0 0

"

4 11

1

11 2 15 15

0

5 6 7 8 9

"

e

e e

1 4

0 0 0 0 0 0

0 0

"

0 0 0

"

0 0 0 0

0 0

"

0

0 0 0 0

"

0 0

0

"

" "

0

0 0 0

15

6 11 0

"

15 6 11

"

6

11

1

Ii! 0

0 " 0 0 0

0 0

.,

" "

0

0 0

"

12

13

14

10

11

11)

leI

11

2

14

1 4

0 " 0 0 0 0

11) " 11)

0

0 0 0 0 " 0 0 0

0 0

0

"

0 0 0 0 0 0 0 0

"

0 0 0 0

0

"

0 0

"

" "

"

0

15 6 11 0 1 10

" " " " "

6

11

1 0 0 0

"

" "

0 0

"

LOCATION 1110

1010

8 2

0 0 0 0 0 0 0

11

0

0 0 0

15

0 0 " 0

"

15 12

6

"

" "

"

11 15

0 0 0 0 0 0 0 0

10

0

"

" 0 "

I!l

0

'"

" " "

0 0

"

(,)

0 0

0

0 0

" "

0

0 0

"

0 0

"

1

10

2

15

8 1

1

4

"

0

" "

"

" "

14

13

8 2

9

0

;0

0 0 0 0

"

11

12

13

0 0 0 0

"

.,

0

" " "

0

"

2

15

8 1

4

1

0

11

12

13

" "

0

" " " " "

3

= RDR

9

14

0 0

"

0

7

"

7

"

0

14

15

"

0

"

0

"

7

10

"

12

7

3

o "

1~--Y:

14

0_0

0 0 0

" "

"

USED FOR STATUS WORD

SAMPLE AT

ERRONEOUS WITH

MEMORY

LINES 4 AND

RESULT

PROGRAM

000

TO

CONTROL

OF

015

AND

ENTRY

INPUT

18

MEMORY

LOCATED

104

CANCELED

"X"

TO

INPUT

SIMULATION

TO

128

Figure 9.2 Memory

10

Dump/Input.

9

14

10

0 0 0 0

01BPPNPNPPPF 41BNPNNPPPPF

81BNPNNPPPPF

121BPPPPPPPPF

Figure

9.3

Miscellaneous Directives.

11

2 I BPPNPNPPNF

61 BPPNPNPPNF 10 I BPPPPPPPPF 141BPPPPPPPPF

fiH/

0:START.

2:

SRC

3:

RDR

4ft:

XCH

5%

INC 8

6:

SRC

7:

RDR

8:

XCH

9:

JMS

II:

XCH

12:

WMP

13:

JUN

IS:

NOP

16:

=104ft 104:/ 104:

AND.

105: 106:

107:

108: 109: 110:

112:

113: 114:

liS:

116: 117:

118:

I

121:

19:

XCH

l.DM

XCH

RAR

XCH

JCN

XCH

RAR

XCH

ROTR2.

RAR

XCH

DAC

JCN

B8L 0

122:ROTR1,

123:

1-24:

125:

126:

128:CZ

RAR

XCH

CLC

JUN

=10

128:ANZ 128:$

rIM

4P

0

4P

I

AND

2

START

Cl.B

2

4

0

CZ

ROTRI

I

XCH

2

AN Z AN

XCH

I

ROTR2

-=12

4P

2

D+ 3

1

fOUR

0

81 T nAND" ROUTINE

/

LOAD

/

SEND

/

READ

/ A

/

LOAD

/

SEND

/

READ

/ B

EXECUTE

/ /

l.OAD

/

STORE

ROM ROM

INPUT A

TO

REGISTER 0 ROM

ROM

INPUT 8

TO

REGISTER RESUL

/ RESTART

"AND" SUBROUTINE

CLEAR

/ /

CLEAR

/

LOAD

/

LOAD

/

ROTATE

/

RETURN JUMP

/ /

LOAD

/

ROTATE

/

RETURN

/

LOAD

/

ROTATE

/

LOAD

/

DECREMENT

LOOP

/ /

RETURN

/

LOAD

/

ROTATE

/

RETURN

/

CLEAR

/

RETURN

LOOP A,

TO

B.

PARTIAl. RESULT C. l.C.

IF

B.

PORT 0 ADDRESS PORT

ADDRESS

PORT 1 ADDRESS PORT

ADDRESS

"AND··

T C

AT

MEMORY

PORT 0

ACCUMUl.ATOR

REGISTER 2

COUNT

LC

LEAST

TO

(l.C>

REGISTER 0

SIGNIfICANT

ROTATED A TO

ROTRI LC

LEAST

If

TO

ACCUMUl.ATOR

SIGNIfICANT

ROTATED B TO CARRY

INTO PARTIAL RESULT

RETURN C TO

THE

LC LC

8

ACCUMULATOR

NON

ZERO

TO

REGISTER I

ROTATED B TO

CARRY

TO

LOOP

AND

REG

CARRY

REG.

REGISTER 2

REG.

CARRY

BIT

0#

ZERO

BIT

I.

LC

TO

(l.C>

I"

TO

CARRY

LC

TO

ACC.

TO

CARRY

LC

TO

ACC.

REGISTER 2

MSB

LC

TO

ACC.

Figure

01

4:8NPNNPPPPf

8:BNPNNPPPNf 12:BNNNPPPPNf 16:

108aBNNNNPNNPF

0:BPPNPNPPPF

10~:

10~:BNNNNPPPPf

BPPPPPPPNF

5:

BPNNPNPPPF

9:BPNPNPPPPF

13:BPNPPPPPPF

10S:BNPNNPPNPf

109:8NPNNPPPPF 112:BNPNNPPPNF 113tBNNNNPNNPf I I 116:BNNNNPNNPF

BPNNPNPNNF

124:BNPNNPPPNf

128

: 1

F

28 : 128

121aBNNPPPPPPf

tI7:BNPNNPPNPf

125:BNNNNPPPNf

:

122aBNPNNPPPNF 1 23aBNNNNPNNPF

Figure

9.5

9.4.

Pass 1 Listing.

2:

BPPNPNPPNF 31BNNNPNPNPF

6:

BPPNPNPPNF 7:BNNNPNPNPF BPNNPNPPPF 11:BNPNNPPNPF BPPPPPPPPf

1

lOa

BPPPNNPNPf

4ft

I BNPNNPPPNF

LS:BPPPPPPPPf

106:BNNPNPNPPf

BPNNNNPNPF

IIS:BNPNNPPNPF

107lBNPNNPPPP

118:BNNNNNPPPF 119aBPPPNNNPPF 126:BPNPPPPPPf

Programming

Tape

BPNNNPPNNF

Listing.

12

Intel SIM4-02 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual