Intel SAI2 - Ss3/le Dual Fcpga Max-4GB Atx2pci-64 4pci-32 Vid Lan 133mhz, SAI2 Specification

SAI2 Server Board

Technical Product Specification

Revision 1.0

November 2001

Enterprise Platforms and Services Marketing

Revision History SAI2 Server Board TPS

Revision History

Date Revision

Number

November 2001 1.0 Initial Release.

Modifications

ii

Revision 1.0

SAI2 Server Board TPS Disclaimers

Disclaimers

Information in this document is pr ovided in connection with Intel® products. No license, express
or implied, by estoppel or otherwise, to any intellectual propert y rig ht s is granted by this
document. Except as provided in Intel's Terms and Condit ions of Sale for such products, Intel
assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating t o
sale and/or use of Intel products including liability or warranties relating to fit ness for a particular
purpose, merchantability, or inf ringement of any patent, copyright or other intellectual property
right. Intel products ar e not intended for use in medical, life saving, or life sustaining
applications. Intel may make changes t o specifications and product descriptions at any time,
without notice.

Designers must not rely on the absence or characterist ics of any features or instructions
marked "reserved" or "undefined." Intel reserves these for future definition and shall have no
responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The SAI2 Server Board may contain design defects or errors known as errata which may cause
the product to deviate from published specifications. Current characterized errat a ar e available
on request.

Intel, Pentium, Itanium , and Xeon are trademarks or registered trademarks of Intel Corporation.
*Other brands and names may be claimed as the property of ot hers.
Copyright © Intel Corporation 2001.

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iii

Table of Contents SAI2 Server Board TPS

Table of Contents

1. Introduction........................................................................................................................ 1

1.1 Purpose.........................................................................................................................1

1.2 Audience....................................................................................................................... 1

1.3 SAI2 Server Board Feature Overview............................................................................1

1.4 SAI2 Server Board Block Diagram ................................................................................ 2

2. SAI2 Server Board Architecture Overview....................................................................... 3

2.1 Intel® Pentium® III Processor Subsystem..................................................................... 3

2.1.1 Supported Processor Types .................................................................................... 3

2.1.2 Dual Processor Operation........................................................................................ 3

2.1.3 PGA370 Socket....................................................................................................... 4

2.1.4 Processor Bus Termination / Regulation / Power..................................................... 4

2.1.5 APIC Bus................................................................................................................. 4

2.1.6 Boxed Processors.................................................................................................... 4

2.2 ServerWorks ServerSet III LE Chipset.......................................................................... 5

2.3 Memory......................................................................................................................... 5

2.4 PCI I/O Subsystem........................................................................................................ 6

2.4.1 64-bit / 66 MHz PCI Subsystem............................................................................... 6

2.4.2 32-bit/33 MHz PCI Subsystem................................................................................. 6

2.5 Chipset Support Components.....................................................................................12

2.5.1 Legacy I/O (Super I/O) National* PC87417............................................................ 12

2.5.2 BIOS Flash............................................................................................................ 13

2.5.3 External Device Connectors................................................................................... 13

2.6 Interrupt Routing ......................................................................................................... 13

2.6.1 Default I/O APIC.................................................................................................... 14

2.6.2 Extended I/O APIC................................................................................................14

2.6.3 PCI IDs.................................................................................................................. 17

2.6.4 Relationship between PCI IRQ and PCI Device..................................................... 17

2.7 ACPI............................................................................................................................18

2.8 AC Link Mode.............................................................................................................. 18

2.9 Wake On LAN Function .............................................................................................. 18

3. Basic Input Output System (BIOS)................................................................................. 19

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3.1 BIOS Overview............................................................................................................ 19

3.1.1 System BIOS......................................................................................................... 20

3.1.2 Flash Update Utility................................................................................................ 20

3.2 Setup Utility................................................................................................................. 21

3.2.1 Configuration Utilities Overview............................................................................. 21

3.2.2 Setup Utility Operation........................................................................................... 21

3.3 CMOS Memory Definition............................................................................................ 32

3.4 CMOS Default Override...............................................................................................32

3.5 Flash Update Utility..................................................................................................... 33

3.5.1 Loading the System BIOS......................................................................................33

3.5.2 Customization........................................................................................................ 34

3.5.3 Language Area...................................................................................................... 37

3.5.4 Recovery Mode...................................................................................................... 37

3.6 Error Messages and Error Codes................................................................................ 38

3.6.1 POST Codes ......................................................................................................... 38

3.6.2 POST Error Codes and Messages.........................................................................42

3.7 Identifying BIOS Revision Level .................................................................................. 44

3.7.1 BIOS Revision Level Identification......................................................................... 44

4. Jumpers and Connectors................................................................................................ 45

4.1 SAI2 Server Board Jumper and Connector Locations................................................. 45

4.2 Jumper Blocks............................................................................................................. 47

4.2.1 Setting CMOS/Password Clear Jumper Block (JP5) .............................................. 47

4.3 Connectors.................................................................................................................. 49

4.3.1 Main Power Connector (ATX1).............................................................................. 49

4.3.2 I2C Connector (J13)............................................................................................... 49

4.3.3 System Fan Connectors (J8, J11, J7, J14)............................................................ 50

4.3.4 Processor Fan Connectors (J10, J9) ..................................................................... 50

4.3.5 HDD LED (J12)...................................................................................................... 50

4.3.6 Diskette Drive Connector (FDD) ............................................................................ 51

4.3.7 SVGA Video Port (VGA1)...................................................................................... 51

4.3.8 Keyboard (KB) and Mouse (MS) Connectors......................................................... 52

4.3.9 Parallel Port (LPT1)............................................................................................... 52

4.3.10 Serial Ports COM1 and COM2............................................................................. 52

4.3.11 RJ-45 LAN Connector (J2)................................................................................... 53

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4.3.12 USB Connectors (J2)........................................................................................... 53

4.3.13 IDE Connectors (PRI_IDE, SEC_IDE) ................................................................. 53

4.3.14 32-Bit PCI Connectors.........................................................................................54

4.3.15 64-Bit PCI Connectors.........................................................................................55

4.3.16 Front Panel 24-pin Connector Pinout (FRONT_PANEL_HDR)............................. 56

5. Hardware Monitoring....................................................................................................... 57

6. Baseboard Specifications............................................................................................... 59

6.1 Estimated Baseboard MTBF....................................................................................... 59

6.2 Absolute Maximum Ratings......................................................................................... 60

6.3 Calculated Power Consumption .................................................................................. 60

6.4 Measured Power Consumption ................................................................................... 61

7. Regulatory and Integration Information......................................................................... 62

7.1 Regulatory Compliance............................................................................................... 62

7.2 Installation Instructions ................................................................................................ 63

7.2.1 Ensure EMC.......................................................................................................... 63

7.2.2 Ensure Host Computer and Accessory Module Certifications................................ 63

7.2.3 Prevent Power Supply Overload............................................................................ 64

7.2.4 Place Battery Marking on Computer...................................................................... 64

7.2.5 Use Only for Intended Applications........................................................................ 65

7.2.6 Installation Precautions.......................................................................................... 65

Glossary..................................................................................................................................... I

Reference Documents ............................................................................................................ III

Index.........................................................................................................................................IV

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SAI2 Server Board TPS List of Figures

List of Figures

Figure 1. SAI2 Server Board Block Diagram.............................................................................. 2

Figure 2. Embedded NIC PCI Signals........................................................................................ 7

Figure 3. Video Controller PCI Signals....................................................................................... 9

Figure 4. SAI2 Baseboard Interrupt Routing Diagram (PIC Mode)........................................... 15

Figure 5. SAI2 Baseboard Interrupt Routing Diagram (Symmetric Mode) ................................ 16

Figure 6. SAI2 Server Board Jumper and Connector Locations............................................... 45

Figure 7. I/O Back Panel Connectors....................................................................................... 46

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List of Tables SAI2 Server Board TPS

List of Tables

Table 1. SAI2 Server Board Supported Processors ................................................................... 3

Table 2. Video Controller Supported PCI Commands ................................................................ 9

Table 3. Standard VGA Modes.................................................................................................10

Table 4. SAI2 PCI IDs.............................................................................................................. 17

Table 5. SAI2 Relationship between PCI IRQ and PCI Device................................................. 17

Table 6. Setup Utility Screen.................................................................................................... 21

Table 7. Main Menu Selections................................................................................................ 23

Table 8. Primary/Secondary Master and Slave Adapters Submenu Selections........................ 24

Table 9. Advanced Menu Selections........................................................................................ 25

Table 10. Advanced Submenu Selections................................................................................ 25

Table 11. Memory Reconfiguration Submenu Selections......................................................... 26

Table 12. CPU Reconfiguration Submenu Selections .............................................................. 26

Table 13. Peripheral Configuration Submenu Selections ......................................................... 27

Table 14. PCI Device Submenu Selections.............................................................................. 28

Table 15. Option ROM Submenu Selections............................................................................ 28

Table 16. Numlock Submenu Selections.................................................................................. 29

Table 17. Security Menu Selections......................................................................................... 29

Table 18. Secure Mode Submenu Selections........................................................................... 30

Table 19. Server Menu Selections............................................................................................ 30

Table 20. Wake On Events Submenu Selections..................................................................... 31

Table 21. Boot Device Priority Selections................................................................................. 31

Table 22. Hard Drive Selections............................................................................................... 31

Table 23. Removable Devices Selections................................................................................ 32

Table 24. Exit Menu Selections................................................................................................ 32

Table 25. User Binary Area Scan Point Definitions...................................................................36

Table 26. Format of the User Binary Information Structure...................................................... 36

Table 27. Port-80h Code Definition.......................................................................................... 38

Table 28. Standard BIOS Port-80 Codes................................................................................. 38

Table 29. Recovery BIOS Port-80 Codes................................................................................. 41

Table 30. POST Error Messages and Codes........................................................................... 42

Table 31. POST Error Conditions and Beep Codes ................................................................. 43

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SAI2 Server Board TPS List of Tables

Table 32. Jumper Block JP5 Settings....................................................................................... 47

Table 33. Main Power Connector Pinout.................................................................................. 49

Table 34. I2C Connector Pinout................................................................................................ 49

Table 35. Board Fan Connector Pinout.................................................................................... 50

Table 36. Processor Fan Connector Pinout.............................................................................. 50

Table 37. HDD LED Pinout....................................................................................................... 50

Table 38. Diskette Drive Connector Pinout............................................................................... 51

Table 39. Video Port Connector Pinout.................................................................................... 51

Table 40. Keyboard and Mouse Connector Pinout................................................................... 52

Table 41. Parallel Port Connector Pinout ................................................................................. 52

Table 42. Serial Ports COM1 and COM2 Connector Pinouts................................................... 52

Table 43. RJ-45 LAN Connector Signals.................................................................................. 53

Table 44. USB Connectors....................................................................................................... 53

Table 45. IDE Connector Pinout............................................................................................... 53

Table 46. 32-Bit PCI Connector Pinout.....................................................................................54

Table 47. 64-Bit PCI Connctor Pinout.......................................................................................55

Table 48. Front Panel 24-pin Connector Pinout........................................................................56

Table 49. Estimated MTBF Calculated Numbers for SAI2/SC5100.......................................... 59

Table 50. Absolute Maximum Ratings...................................................................................... 60

Table 51. SAI2 Server Board Calculated Power Consumption................................................. 60

Table 52. SAI2 Server Board Measured Power Consumption.................................................. 61

Table 53. Safety Regulations................................................................................................... 62

Table 54. EMC Regulations...................................................................................................... 62

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List of Tables SAI2 Server Board TPS

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SAI2 Server Board TPS Introduction

1. Introduction

1.1 Purpose

This document provides an architectural overview of the SAI2 server boar d, including the board
layout of major components and connectors, and an overview of the server boar d’s feature set.

1.2 Audience

This document for technical per sonnel who want a technical overview of the SAI2 server board.
Familiarity with the personal computer, Intel server ar chitecture and the Peripheral Component
Interconnect (PCI) local bus architecture is assumed.

1.3 SAI2 Server Board Feature Overview

The SAI2 server board provides the following f eat ur es:

• Dual Intel® Pentium® III processor support

- Support for one or two identical Intel Pentium III processors for the PGA370 socket,
which utilizes the Flip Chip Pin Grid Array (FC-PGA) pack age

- Two embedded Voltage Regulating Modules (VRM) for suppor t of both primary and
secondary processors

• ServerWorks* ServerSet* III LE chipset

- 133-MHz Front Side Bus (FSB) Capability

- CNB30LE North Bridge

- CSB5 South Bridge

• Support for four 3.3-V, registered ECC SDRAM DIMMs that are compliant with the

JEDEC PC133 specification

- Support for DIMM sizes 64 MB to 1 GB. Four DIMM slots allow a maxiumum
installed memory of 4 GB

- ECC single-bit correction, and m ultiple-bit detection

• 64-bit, 66-MHz, 3.3-V keyed PCI segment with two expansion connectors

- Two 64-bit, 66-MHz, 3.3-V keyed PCI expansion slots

• 32-bit, 33-MHz, 5-V keyed PCI segment with four expansion connector s and t hr ee

embedded devices

- Four 32-bit, 33-MHz, 5-V keyed PCI expansion slots

- CSB5 South Bridge, which provides Integrated Device Electronics (IDE) and

Universal Serial Bus (USB) controller functions

- Integrated on-board Intel® EtherExpress™ PRO100+ 10/100 meg abit PCI Ethernet
controller (Intel® 82559) with an RJ-45 Ethernet connect or

- Integrated on-board AT I* Rage XL video controller with 8 MB of on-board VRAM
video memory

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Introduction SAI2 Server Board TPS

• Compatibility bus segment with two embedded devices

- Super I/O Controller (PC87417) that provides all PC-compatible I/O (floppy, parallel,
serial, keyboard, mouse, and Real-Tim e Clock)

- 4 megabit Flash device for system BIOS

• Dual Universal Serial Bus (USB) ports

• Two IDE connectors

• Flash BIOS support for all of the above

• ATX board form factor

1.4 SAI2 Server Board Block Diagram

The SAI2 server board off er s a “ flat” design, with the processors and mem or y subsystems
residing on the board. The following figure shows the major funct ional blocks of the SAI2 server
board. The following section describes the major components of the server board.

SAI2 Server Board Block Diagram

SAI2 Server Board Block Diagram

2x 64bit/66MHz PCI Slots

4x 32bi t/33MHz PCI Slot s

8255982559

10/100 NIC

PCI (64/66)

PCI (32/33)

ATI RAGE* XL

ATI RAGE* XL

8MB RAM

8MB RAM

Flash

Flash
BIOS

BIOS

Temp

Voltage

FAN

FCPGA

FCPGA

Tualatin

Tualatin

FCPGA

FCPGA

Tualatin

Tualatin

133MHz System Bus

MCH

LE-T

CSB5

LPC

Super

SM-BUS

HW

HW

Monitor

Monitor

Super

I/O

I/O

X-BUS

Up to 4GB ECC Memory (4 DIMMs)
PC133 Buffered SDRAM

2x IDE (Ultra -ATA/100)
2x USB

Floppy
Keyboard, Mouse

Serial Ports
Parallel Port

NvRAM

NvRAM

(32KB)

(32KB)

Figure 1. SAI2 Server Board Block Diagram

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SAI2 Server Board TPS SAI2 Server Board Architecture Overview

2. SAI2 Server Board Architecture Overview

The architecture of the SAI2 server board is based on a design that supports dual-processor
operation with Intel Pentium III processors and the ServerWorks ServerSet III LE chipset.

The SAI2 server contains embedded devices for video, Network I nt erface Card (NIC), and IDE.
The SAI2 server board also provides support for basic monitoring hardware, and interrupt
control that supports dual-processor and PC/ AT compatible operation.

The section provides an overview of the following SAI2 subsystems:

• Pentium III processor subsystem

• SeverWorks* ServerSet* III LE chipset

• Memory

• PCI subsystem

• Chipset support components

2.1 Intel® Pentium® III Processor Subsystem

The SAI2 server board is designed to accommodate one or two Intel Pentium III processors for
the PGA370 socket. The Pentium III processor for the PGA370 socket uses the same core and
offers the same performance as the Intel Pentium III processor for the SC242 connector, but
utilizes a FC-PGA. This package utilizes the sam e 370- pin zero- inser t ion force socket
(PGA370) used by the Intel® Celeron™ processor.

2.1.1 Supported Processor Types

The table below summarizes the processors that are planned f or the SAI2 server board:

Table 1. SAI2 Server Board Supported Processors

Speed FSB Frequency Cache Size

1.00 GHz 133 MHz 256K

1.13 GHz 133 MHz 512K

1.26 GHz 133 MHz 512K

2.1.2 Dual Processor Operation

The Pentium III processor interface is designed to be multi-processor ready. Each processor
contains a local Intel
handling. W hen two processors are installed, both processors must be of identical revision,
core voltage, and bus/core speeds.

®

Advanced Programmable Interrupt Controller (APIC) section f or interrupt

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SAI2 Server Board Architecture Overview SAI2 Server Board TPS

2.1.3 PGA370 Socket

The SAI2 server board provides two PGA370 sockets. These ar e 370- pin zero- insertion force
(ZIF) sockets into which a FC-PGA package t echnology processor plugs.

2.1.4 Processor Bus Termination / Regulation / Power

The termination circuitry required by the Intel Pentium III processor bus signaling environment,
and the circuitry to set the AGTL/ AGTL+ reference voltage, ar e im plem ented directly on the
processor. The SAI2 server board provides VRM 8.5 compliant DC-t o- DC convert ers to provide
processor power, Voltage Controlled Current Plane ( VCCP) , at each PGA370 socket. The
server board provides embedded VRMs for both the primary and secondary processors.
Additional termination is provided on the SAI2 server board f or terminator-less operation when
only one processor is installed.

2.1.5 APIC Bus

Interrupt notificat ion and generation for the processors is done using an independent path
between local APICs in each processor and the I/O APIC located in the CSB5 South Bridge
component.

2.1.6 Boxed Processors

The Intel Pentium III processor for the PGA370 socket is offered as an Intel boxed processor.
Intel boxed processors are intended for system integrators who build systems from a server
board and standard components.

2.1.6.1 Boxed Processor Fan Heatsinks

The boxed Pentium III processor for the PGA370 socket will be supplied with an unattached fan
heatsink that has an integrat ed clip. Clearance is required around the fan heat sink to ensure
unimpeded airflow for proper cooling . Note that the airflow of t he fan heatsink is into the center
and out of the sides of the fan heatsink. The boxed processor therm al solut ion m ust be installed
by a system integrator to secure the ther mal cooling solution to the processor aft er it is installed
in the 370-pin ZIF socket.

The boxed processor’s fan heatsink req uires a +12-V power supply. A fan power cable is
attached to the fan and connects to pr ocessor fan headers on the SAI2 server board.

The boxed processor fan heatsink will keep the pr ocessor cor e at the recommended junction
temperature, as long as airflow through the fan heatsink is unimpeded. It is recommended that
the air temperature entering the fan inlet be below 45 °C (measured at 0.3 inches above the fan
hub).

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SAI2 Server Board TPS SAI2 Server Board Architecture Overview

2.2 ServerWorks ServerSet III LE Chipset

The ServerWorks ServerSet III LE chipset provides an integrated I/O bridge and memory
controller and a flexible I/O subsystem core (PCI), targeted for multiprocessor systems and
standard high-volume servers that are based on the Intel Pentium III processor. The
ServerWorks ServerSet III LE chipset consists of two components:

• CNB30LE North Bridge

The CNB30LE North Bridge is responsible f or accepting access requests fr om the host
(processor) bus and for directing those accesses to memory or to one of the PCI buses.
The CNB30LE North Bridge monitor s t he host bus, examining addresses for each
request. Accesses may be directed to a memory req uest queue for subsequent
forwarding to the memory subsystem, or t o an outbound request queue for subsequent
forwarding to one of the PCI buses.

The CNB30LE North Bridge is responsible for controlling data transfers to and from the
memory. The CNB30LE North Bridg e pr ovides the int erface for both the 64-b it , 66-MHz,
Revision 2.2-compliant PCI bus and the 32-bit, 33-MHz, Revision 2.2-compliant PCI bus.
The CNB30LE North Bridge is both a mast er and target on both PCI buses.

• CSB5 South Bridge

The CSB5 South Bridge controller has several component s. It can be both a master and
a target on the 32-bit, 33- MHz PCI bus. The CSB5 Sout h Bridge also includes a USB
controller and an IDE controller. T he CSB5 South Bridge is responsible for many of the
power management functions, with Advanced Config ur ation and Power Interface (ACPI)
control registers built in. The CSB5 South Bridge provides a number of In finiband pins.

2.3 Memory

The SAI2 server board contains four 168- pin DI MM sockets. Memory is partitioned as four
banks of registered SDRAM DIMMs, each of which provides 72 bits of single interleaved
memory (64-bit main memory plus ECC).

The SAI2 server board supports up to four 3.3-V, registered ECC SDRAM DIMMs that are
compliant with the JEDEC PC133 specification. A wide range of DIMM sizes are supported,
including 64 MB, 128 MB, 256 MB, 512 MB, and 1-GB DIMMs. The minimum supported
memory configuration is 64 MB using one DIMM. The maximum configurable memory size is
4 GB using four DIMMs.

Note: Neither PC100 DIMMs nor non-ECC DIMMs can be used.

DIMMs may be installed in one, two, three, or four DIMM slots and must be populated starting
with the lowest numbered slot and filling the slots in consecutive order . Em pty memory slots
between DIMMs are not supported. Although the SAI2 server board architect u r e allows the user
to mix various sizes of DIMMS, Intel recommends that module and DRAM vendors not be
mixed in the same server system.

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SAI2 Server Board Architecture Overview SAI2 Server Board TPS

System memory begins at address 0 and is continuous (f lat addressing) up to the maximum
amount of DRAM installed (exception: system memory is noncontiguous in the ranges defined
as memory holes using configuration r egisters). The server board supports bot h base
(conventional) and extended memory.

2.4 PCI I/O Subsystem

The expansion capabilities of the SAI2 server board meet t he needs of file and application
servers for high performance I/O by providing two PCI bus segments in the form of one 64-bit /
66-MHz bus segment and one 32-bit / 33-MHz bus segment. Each of the PCI buses comply
with Revision 2.2 of the PCI Local Bus Specification.

2.4.1 64-bit / 66 MHz PCI Subsystem

The 64-bit, 66-MHz, 3.3-V keyed PCI segm ent includes two 64-bit, 66-MHz, 3.3-V keyed PCI
expansion slots that can support 66-MHz, 64/32-bit cards or 33-MHz, 64/32-bit cards.

64-bit PCI features include:

• Bus speed up to 66 MHz

• 3.3-V signaling environment

• Burst transfers up to a peak of 528 MB per second (MBps)

• 8-, 16-, 32-, or 64-bit dat a t ransfers

• Plug-and-Play ready

• Parity enabled

2.4.2 32-bit/33 MHz PCI Subsystem

The 32-bit, 33-MHz, 5-V keyed PCI includes the following embedded devices and connector s :

• Four 32-bit, 33-MHz, 5-V keyed PCI expansion slots

• Integrated Intel

(Intel® 82559)

• Integrated ATI Rage* XL video controller with 8 MB of on-board SGRAM

• CSB5 South Bridge I/O APIC, PCI-to- Industry Standard Architecture (ISA) bridge, IDE

controller, USB controller, and power management.

32-bit PCI features include:

• Bus speed up to 33 MHz

• 5-V signaling environment

• Burst transfers up to a peak of 132 MBps

• 8-, 16-, or 32-bit data tr ansfers

• Plug-and-Play ready

• Parity enabled

®

EtherExpress™ PRO100+ 10/100 megabit PCI Ethernet controller

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SAI2 Server Board TPS SAI2 Server Board Architecture Overview

2.4.2.1 Network Interface Controll er ( NI C)

The SAI2 server board includes a 10Base-T / 100Base-TX network controller that is based on
the Intel
predecessor (Intel

®

82559 Fast Ethernet PCI Bus Controller. This device is similar in architecture to its

®

82558). No external devices are required to implement an embedded
network subsystem, other than TX / RX magnetics, two status Light Emit ting Diodes (LEDs), and
a connector.

Status LEDs are included on the external NIC connector. The SAI2 server board provides the
ability to disable the embedded NIC in the BIOS Setup opt ion. When disabled it is not visible to
the operating system.

The 82559 is a highly integrated PCI Local Ar ea Net work (LAN) controller for 10 or 100 Mbps
Fast Ethernet networks. As a PCI bus master , the 82559 can burst data at up to 132 MBps.
This high-perform ance bus master interface can eliminate t he int ermediate copy step in RX/TX
frame copies, resulting in faster frame processing.

The network operating system communicates with the 82559 using a memory-mapped I/O
interface, PCI interr upt connected directly to the CSB5, and two large receive and transm it
FIFOs. The receive and transmit FIFO s pr event dat a overr uns or under runs while waiting for
access to the PCI bus, and also enable back-to-back frame transmission within the minimum
960ns inter-frame spacing. The figure below shows the PCI signals supported by the 82559:

AD[31::0]
C/BE[3::0]_L
PAR

FRAME_L
TRDY_L
IRDY_L
STOP_L

i82559 NIC

DEVSEL_L
IDSEL
REQ_L
GNT_L
PCI_CLK

RST_L
PERR_L
SERR_L

PCI_INT_L

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Figure 2. Embedded NIC PCI Signals

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SAI2 Server Board Architecture Overview SAI2 Server Board TPS

2.4.2.1.1 Supported Network Features

The 82559 contains an IEEE MII compliant interf ace t o the components necessary to
implement an IEEE 802.3 100Base TX net work connect ion. The SAI2 supports the following
features of the 82559 cont r oller :

• Glueless 32-bit PCI Bus Master Interf ace ( Dir ect Drive of Bus), compatible with PCI Bus

Specification, revision 2.1 / 2.2

• Chained memory structure, with improved dynamic transmit chaining for enhanced

performance

• Programmable transmit t h r eshold for improved bus utilization

• Early receive interrupt for concurrent processing of receive data

• On-chip counters for network management

• Autodetect and autoswitching for 10 or 100 Mbps network speeds

• Support for both 10 Mbps and 100 Mbps networks, full or half duplex-capable, with

back-to-back transmit at 100 Mbps

• Integrated physical interface to TX magnetics

• The magnetics component term inat es t he 100Base- TX connector interface. A flash

device stores the network ID.

• Support for Wake-on-LAN (WOL)

2.4.2.2 Video Controller

The SAI2 server board includes an ATI Rage XL video controller, 8 MB video SDRAM, and
support circuitry for an embedded SVG A video subsystem. The Rage XL, 64-bit VGA Gr aphics
Accelerator contains a SVGA video controller, clock generator, BitBLT engine, and RAMDAC.
One 2M x 32 SDRAM chip provides 8 MB of 7ns video memory.

The SVGA subsystem supports a variety of modes: up to 1600 X 1200 resolution for CRT
displays and up to 1024 X 768 resolution for TFT displays, and up to 16.7 million colors. It also
supports analog VGA monitors, single- and multi-freq uency, int er laced and non- int er laced, up
to 100 Hz vertical refresh frequency. The SAI2 server board provides a standard 15-pin VGA
connector.

2.4.2.2.1 Video Controller PCI Signals

The Rage XL supports a minimal set of 32-bit PCI signals because it never acts as a PCI
master. As a PCI slave, the device requires no arbitration or interrupts.

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AD[3 1::0 ]
C/BE [ 3::0]_L
PAR
FRAME_L
TRDY_L
IRD Y _ L
STOP_L

Rage XL

DEVSEL_L
IDSEL

Figure 3. Video Controller PCI Signals

2.4.2.2.2 Video Controller PCI Commands

The Rage XL supports the following PCI commands:

Table 2. Video Controller Supported PCI Commands

Rage XL Support
C/BE[3::0]_L Command Type Target Master

0000 Interrupt Acknowledge No No
0001 Special Cycle No No
0010 I/O Read Yes No
0011 I/O Write Yes No
0100 Reserved No No
0101 Reserved No No
0110 Memory Read Yes No
0111 Memory Write Yes No
1000 Reserved No No
1001 Reserved No No
1010 Configuration Read Yes No
1011 Configuration Write Yes No
1100 Memory Read Multiple No No
1101 Dual Address Cycle No No
1110 Memory Read Line No No
1111 Memory Write and Invalidate No No

PCI_CLK

RST_L
PERR_L
SERR_L

PCI_ INT _L

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2.4.2.2.3 Video Modes

The Rage XL supports all standard IBM* VGA modes. The following tables show the standard
resolutions that this implementation suppor ts, including the number of color s and t he refresh rate.

Table 3. Standard VGA Modes

Resolution Refresh Rate (Hz) Colors

640x480 100 256
800x600 100 256
1024x768 100 256
1280x1024 72 256
1600x1200 85 256
640x480 100 65K
800x600 100 65K
1024x768 100 65K
640x480 100 16.7 M
800x600 100 16.7 M

2.4.2.3 CSB5 South Bridge

The CSB5 South Bridge is a PCI device that provides mult iple PCI functions in a single
package: PCI-to- ISA bridge, PCI IDE interface, PCI USB controller, and power managem ent
controller. Each function within the CSB5 South Br idge has its own set of configuration
registers. Once configured, each appears to the system as a distinct hardware controller
sharing the same PCI bus interface.

On the SAI2 baseboard, the primar y role of the CSB5 South Bridge is to provide the g ateway to
all PC-compatible I/O devices and features. The SAI2 server board uses the following CSB5
South Bridge features:

• PCI interface

• IDE interface

• USB interface

• PC-compatible timer/counters and Dir ect Memory Access (DMA) controllers

• Baseboard Plug-and-Play support

• General purpose I/O

• Power management

• APIC and 82C59 interrupt controller

• Host interface for AT compatible signaling

• Internal only ISA bus (no ISA expansion connectors) bridge for communication with

Super I/O, and BIOS flash

The following sections describe each supported f eature as used on the SAI2 server board.

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2.4.2.3.1 PCI Interface

The CSB5 South Bridge fully implements a 32-bit PCI master/slave interface, in accordance
with Revision 2.2 of the PCI Local Bus Specification. On the SAI 2 ser ver boar d, the PCI
interface operates at 33 MHz, using the 5V-signaling environment.

2.4.2.3.2 PCI Bus Master IDE Interface

The CSB5 South Bridge acts as a PCI-based enhanced IDE 32-bit interface controller for
intelligent disk drives that have disk cont r oller electronics on-board. The server board includes
two IDE connectors, each featuring 40 pins ( 2 x 20) t hat suppor t a master and a slave device.
The IDE controller provides support for an internally mounted CD-ROM.

The IDE controller has the following features:

• Programmed Input/Output (PIO) and DMA transfer modes

• Up to PIO Mode 4 , DMA Mode 4, and Ultra DMA Mode 5 timings

• Transfer rates up to 100 MBps

• Buffering for PCI/IDE burst transfers

• Master/slave IDE mode

• Support for up to two devices per channel

2.4.2.3.3 USB Interface

The CSB5 South Bridge contains a USB controller and USB hub. The USB controller moves
data between main memory and the two USB connectors provided.

The SAI2 server board provides a dual external USB connector interface. Both ports function
identically and with the same bandwidth. The external connector is defined by Revision 1.0 of
the USB Specification.

2.4.2.4 Compatibility Interrupt Control

The CSB5 South Bridge provides the functionality of two 82C59 Programmable Interrupt
Controller (PIC) devices, for I SA- compatible interrupt handling.

2.4.2.5 APIC

The CSB5 South Bridge integrates a 16-entry I/O APIC that is used to distribute 16 PCI interrupts.
It also includes an additional 16-entry I/O APIC for distribution of legacy ISA interrupts.

2.4.2.6 Power Management

One of the embedded funct ions of CSB5 South Bridge is a power management contr oller. The
SAI2 server board uses this to implement ACPI-compliant power management feat ur es. SAI2
supports sleep states s0, s1, s4, and s5.

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2.5 Chi pset Suppor t Components

2.5.1 Legacy I/O (Super I/O) National* PC87417

The National* PC87417 Super I/O Plug-and-Play Compatible with ACPI-Compliant
Controller/Extender is used on the SAI2 server board. This device provides the system with:

• Real-time Clock (RTC)

• Two serial ports

• One parallel port

• Floppy disk controller (FDC)

• PS/2-compatible keyboard and mouse controller

• General purpose I/O pins

• Plug-and-Play functions

• A power management controller

The SAI2 server board provides the connector interface for the floppy, dual serial por t s , par allel
port, PS/2 mouse and the PS/2 keyboard. Upon reset, the Super I/O (SIO) reads the values on
strapping pins to determine the boot- up addr ess configuration.

2.5.1.1 Serial Ports

Two 9-pin connectors in D-Sub housing are provided for ser ial por t 1 and serial port 2. Both
ports are compatible with 16550A and 16450 modes, and both are re-locat able. Each serial port
can be set to one of four different COM-x ports, and each can be enabled separately. When
enabled, each port can be programmed t o generate edge- or level-sensitive interrupts. When
disabled, serial port interrupts are available to add-in car ds.

2.5.1.2 Parallel Port

The SAI2 baseboard provides a 25-pin parallel port connector . The SIO provides an IEEE
1284-compliant 25-pin bi-directional parallel port . BIOS programming of the SIO registers
enables the parallel port and determines the port addr ess and int errupt. W hen disabled, the
interrupt is available to add-in cards.

2.5.1.3 Floppy Port

The FDC in the SIO is functionally compat ible with floppy disk controllers CMOS 765B and
82077AA. The baseboard provides the 24-MHz clock, termination resist ors, and chip selects. All
other FDC functions are integrated into the SIO, including analog data separator and 16-byte
FIFO.

2.5.1.4 Keyboard and Mouse Connectors

The keyboard controller is functionally compatible with the 8042A. The keyboard and mouse
connectors are PS/2-compatible.

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2.5.1.5 Real-time Clock

The PC87417 contains an MC146818-compatible real-time clock with external bat t er y back up.
The device also contains 242 bytes of general purpose batt er y-backed CMOS RAM. The real­time clock provides system clock and calendar information stored in non-volatile memory.

2.5.1.6 Plug-and-Play Functions / ISA Data Transfers

The PC87417 contains all signals for I SA com pat ible interrupts and DMA channels. This ISA
subsystem transfers all SIO peripheral control data to the CSB5 South Bridge as well via the
LPC bus interface. The SIO also suppor t s an X-Bus interface that provides control, data and
address signals to and from t he RAS NVRAM device.

2.5.1.7 Power Management Controller

The PC87417 component contains functionality that allows various events to allow the power­on and power-off of the system. This can be from PCI Power Management Events or the front
panel. This circuitry is powered from stand- by voltage, which is present anytime the system is
plugged into the AC outlet.

2.5.2 BIOS Flash

The SAI2 baseboard incorporates an SST39SF040 Flash RO M component. The SST39SF040
is a high-performance 4 m egabit memory organized as 512K x8 bits in128 4-KB blocks.

The 8-bit flash memory provides 512K x 8 of BIOS and nonvolatile storage space. The flash
device is directly addressed as 8-bit ISA memory and accessed through the CSB5 X-Bus
interface.

2.5.3 External Device Connectors

The external I/O connectors provide support for a PS/2 compatible mouse and keyboard, an
SVGA monitor, two serial port connector s, a parallel port connector, a LAN port, and two USB
connections.

2.6 Interrupt Routing

The SAI2 server board interrupt architecture implements two I/O APICs and two PICs through
the use of the integrat ed com ponents in the CSB5 South Bridge component. The SAI2 server
board interrupt architecture allows first and second PCI interrupts to be mapped t o com patible
interrupts through the PCI Interrupt Address Index Register (I/O Address 0C00h) in the CSB5
South Bridge.

The CSB5 South Bridge uses integr at ed logic to map 16 PCI interrupts to EI SA/ISA. In default
or Extended APIC configurations, each PCI interrupt can be independently routed to one of t he
11 EISA interrupts. The interrupt mapping logic for PCI interrupts is disabled when the make bit
in the corresponding I/O APIC redirection table entry is disabled (clear). This interrupt routing
mechanism allows a clean transition from PIC mode to an APIC during operating system boot.

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2.6.1 Default I/O APIC

The CSB5 South Bridge integrates a 16-entry I/O APIC which is used to distribute 16 PCI
interrupts.

2.6.2 Extended I/O APIC

An additional 16-entry I/O APIC is integrated in the CSB5 South Bridge to distribute EISA/ISA
interrupts. This additional I/O APIC is enabled only when the CSB5 South Bridge is configured
to the Extended APIC configuration.

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A

CSB5

PC87417

(Super-I/O)

FERR#
IDE #0
IDE #1

Keyboard
Serial Port2

Serial Port1

FDD
Parallel Port
RTC

Mouse

IRQ 0
IRQ 1
IRQ 2
IRQ 3
IRQ 4
IRQ 5
IRQ 6
IRQ 7
IRQ #8
IRQ 9
IRQ 10
IRQ 11
IRQ 12
IRQ 13 (FERR#)
IRQ 14
IRQ 15

SCAN PIRQ

PCI IRQ to

PIRQ 0

PIRQ 1
LAN
VGA
PCI 3 INT A
PCI 4 INT A

PCI 2 INT A
PCI 5 INT A
PCI 6 INT A

B

PCI 1 INT

C
D

PCI1

PCI3

PCI4

SCI

*1 setting by CSB5 I/O Address C00h Interrupts Address Index Register and I/O
Address C01h Interrupt Redirection

PCI5

PCI6+

PIRQ 2

PIRQ 3

PIRQ 4

PIRQ 5

PIRQ 6

PIRQ 7

PIRQ 8

PIRQ 9

PIRQ 10

PIRQ 11

PIRQ 12

PIRQ 13

PIRQ 14

PIRQ 15

*1

IRQ

Figure 4. SAI2 Baseboard Interrupt Routing Diagram (PIC Mode)

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