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SA-1100
User Manual
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Intel SA-1100 User Manual

Intel® StrongARM® SA-1100 Microprocessor
Developer’s Manual
August 1999
Order Number: 278088-004
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice. This document is an intermediate draft for comment only and is subject to change without notice. Readers should not design products based on this
document.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The SA-1100 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 1999 *Third-party brands and names are the property of their respective owners. ARM and the ARM Powered logo are trademarks and StrongARM is a registered trademark of ARM Limited.

Contents

1 Introduction......................................................................................................................1-1
1.1 Intel® StrongARM® SA-1100 Microprocessor .................................................. 1-1
1.2 Overview............................................................................................................ 1-4
1.3 Example System........................... ...... ....................................... ...... ....... ...... ..... 1-5
1.4 ARM™ Architecture........................................................................................... 1-6
1.4.1 26-Bit Mode .......................................................................................... 1-6
1.4.2 Coprocessors........................................................................................ 1-6
1.4.3 Memory Management........................................................................... 1-6
1.4.4 Instruction Cache.................................................................................. 1-6
1.4.5 Data Cache...................... ...... ....... ...... ....... ...... ..................................... 1-6
1.4.6 Write Buffer........................................................................................... 1-7
1.4.7 Read Buffer........................................................................................... 1-7
2 Functional Description. ....... ...... ....... ...... ....... ...................................... ....... ...... ....... ...... ...2-1
2.1 Block Diagram ................................................................................................... 2-1
2.2 Inputs/Outputs ................................................................................................... 2-3
2.3 Signal Description.............................................................................................. 2-4
2.4 Memory Map...................................................................................................... 2-7
3 ARM™ Implementation Options...... ...... ....... ...... ...... ....................................... ....... ...... ...3-1
3.1 Big and Little Endian.......................................................................................... 3-1
3.2 Exceptions ......................................................................................................... 3-1
3.2.1 Power-Up Reset ................................................................................... 3-2
3.2.2 ROM Size Select .................................................................................. 3-2
3.2.3 Abort..................................................................................................... 3-3
3.2.4 Vector Summary................................................................................... 3-4
3.2.5 Exception Priorities............................................................................... 3-4
3.2.6 Interrupt Latencies and Enable Timing................................................. 3-5
3.3 Coprocessors..................................................................................................... 3-5
4 Instruction Set .................................................... ...... ....... ...... ....... ...... ....... ......................4-1
4.1 Instruction Set.................................................................................................... 4-1
4.2 Instruction Timings............................................................................................. 4-1
5 Coprocessors..................................................................................................................5-1
5.1 Internal Coprocessor Instructions...................................................................... 5-1
5.2 Coprocessor 15 Definition ................................................................................. 5-2
5.2.1 Register 0 – ID...................................................................................... 5-2
5.2.2 Register 1 – Control.............................................................................. 5-3
5.2.3 Register 2 – Translation Table Base ................................................... 5-4
5.2.4 Register 3 – Domain Access Control.................................................... 5-4
5.2.5 Register 4 – RESERVED...................................................................... 5-4
5.2.6 Register 5 – Fault Status ...................................................................... 5-4
5.2.7 Register 6 – Fault Address................................................................... 5-4
5.2.8 Register 7 – Cache Control Operations................................................ 5-5
5.2.9 Register 8 – TLB Operations................................................................ 5-5
5.2.10 Register 9 – Read-Buffer Operations ................................................... 5-6
SA-1100 Developer’s Manual iii
5.2.11 Registers 10 – 12 RESERVED............................................................. 5-6
5.2.12 Register 13 – Process ID Virtual Address Mapping.............................. 5-7
5.2.13 Register 14 – Debug Support (Breakpoints)......................................... 5-8
5.2.14 Register 15 – Test, Clock, and Idle Control.......................................... 5-9
6 Caches, Write Buffer, and Read Buffer...........................................................................6-1
6.1 Instruction Cache (Icache)................................................................................. 6-1
6.1.1 Icache Operation .................................................................................. 6-1
6.1.2 Icache Validity ...................................................................................... 6-1
6.1.2.1 Software Icache Flush ........................................ ...... ............... 6-1
6.1.3 Icache Enable/Disable and Reset ........................................................ 6-2
6.1.3.1 Enabling the Icache ................................................................. 6-2
6.1.3.2 Disabling the Icache ................................................................ 6-2
6.2 Data Caches (Dcaches) .................................................................................... 6-2
6.2.1 Cacheable Bit – C................................................................................. 6-3
6.2.1.1 Cacheable Reads – C = 1 ....................................................... 6-3
6.2.1.2 Noncacheable Reads – C = 0.................................................. 6-3
6.2.2 Bufferable Bit – B.................................................................................. 6-3
6.2.3 Software Dcache Flush ................................ ...................................... .. 6-4
6.2.3.1 Doubly Mapped Space ............................................................ 6-4
6.2.4 Dcaches Enable/Disable and Reset..................................................... 6-4
6.2.4.1 Enabling the Dcaches.............................................................. 6-5
6.2.4.2 Disabling the Dcaches............................................................. 6-5
6.3 Write Buffer (WB) .............................................................................................. 6-5
6.3.1 Bufferable Bit............... ....... ...... ....... ...... ....... ...... .................................. 6-5
6.3.2 Write Buffer Operation.......................................................................... 6-5
6.3.2.1 Writes to a Bufferable and Cacheable Location (B=1,C=1)..... 6-5
6.3.2.2 Writes to a Bufferable and Noncacheable Location (B=1,C=0)6-6
6.3.2.3 Unbufferable Writes (B=0)....................................................... 6-6
6.3.3 Enabling the Write Buffer...................................................................... 6-6
6.3.3.1 Disabling the Write Buffer........................................................ 6-6
6.4 Read Buffer (RB) ............................................................................................... 6-6
7 Memory-Management Unit (MMU)..................................................................................7-1
7.1 Overview............................................................................................................ 7-1
7.1.1 MMU Registers..................................................................................... 7-1
7.2 MMU Faults and CPU Aborts ............................................................................ 7-1
7.3 Data Aborts........................................................................................................ 7-1
7.3.1 Cacheable Reads (Linefetches) ........................................................... 7-2
7.3.2 Buffered Writes..................................................................................... 7-2
7.4 Interaction of the MMU, Icache, Dcache, and Write Buffer ............................... 7-2
7.5 Mini Data Cache.... ...... ....... ...... ....... ...... ....... ...... ....... ...... ...... ............................ 7-3
8 Clocks .. ....... ...... ....... ...... ....... ...... ....... ...... ....... ...................................... ....... ...... ....... . .....8-1
8.1 SA-1100 Crystal Oscillators............................................................................... 8-1
8.2 Core Clock Configuration Register.................................................................... 8-2
8.2.1 Restrictions on Changing the Core Clock Configuration ...................... 8-2
8.3 Driving SA-1100 Crystal Pins from an External Source .................................... 8-3
8.4 Clocking During Test ......................................................................................... 8-4
iv SA-1100 Developer’s Manual
9 System Control Module...................................................................................................9-1
9.1 General-Purpose I/O.......................................................................................... 9-1
9.1.1 GPIO Register Definitions..................................................................... 9-2
9.1.1.1 GPIO Pin-Level Register (GPLR) ............................................ 9-3
9.1.1.2 GPIO Pin Direction Register (GPDR) ...................................... 9-4
9.1.1.3 GPIO Pin Output Set Register (GPSR) and
Pin Output Clear Register (GPCR).......................................... 9-5
9.1.1.4 GPIO Rising-Edge Detect Register (GRER) and
Falling-Edge Detect Register (GFER) ..................................... 9-6
9.1.1.5 GPIO Edge Detect Status Register (GEDR)............................ 9-7
9.1.1.6 GPIO Alternate Function Register (GAFR).............................. 9-8
9.1.2 GPIO Alternate Functions..................................................................... 9-9
9.1.3 GPIO Register Locations.................................................................... 9-10
9.2 Interrupt Controller........................................................................................... 9-11
9.2.1 Interrupt Controller Register Definitions.............................................. 9-11
9.2.1.1 Interrupt Controller Pending Register (ICPR) ........................ 9-12
9.2.1.2 Interrupt Controller IRQ Pending Register (ICIP) and
FIQ Pending Register (ICFP)................................................. 9-13
9.2.1.3 Interrupt Controller Mask Register (ICMR) ............................ 9-14
9.2.1.4 Interrupt Controller Level Register (ICLR) ............................. 9-15
9.2.1.5 Interrupt Controller Control Register (ICCR).......................... 9-16
9.2.2 Interrupt Controller Register Locations............................................... 9-17
9.3 Real-Time Clock.............................................................................................. 9-17
9.3.1 RTC Counter Register (RCNR) .......................................................... 9-17
9.3.2 RTC Alarm Register (RTAR) .............................................................. 9-18
9.3.3 RTC Status Register (RTSR).............................................................. 9-18
9.3.4 RTC Trim Register (RTTR)................................................................. 9-19
9.3.5 Trim Procedure................................................................................... 9-19
9.3.5.1 Oscillator Frequency Calibration............................................ 9-19
9.3.5.2 RTTR Value Calculations ...................................................... 9-20
9.3.6 Real-Time Clock Register Locations .................................................. 9-21
9.4 Operating System Timer.................................................................................. 9-21
9.4.1 OS Timer Count Register (OSCR)...................................................... 9-22
9.4.2 OS Timer Match Registers 0–3
OSMR<0>, OSMR<1>, OSMR<2>, OSMR<3>)................................. 9-22
9.4.3 OS Timer Watchdog Match Enable Register (OWER)....................... 9-22
9.4.4 OS Timer Status Register (OSSR)..................................................... 9-23
9.4.5 OS Timer Interrupt Enable Register (OIER) ....................................... 9-24
9.4.6 Watchdog Timer ................................. ....... ...... ...... ....... ...... ....... ...... ... 9-24
9.4.7 OS Timer Register Locations.............................................................. 9-25
9.5 Power Manager ................................. ....... ...... ....................................... ...... ... 9-26
9.5.1 Run Mode ........................................................................................... 9-26
9.5.2 Idle Mode............................................................................................ 9-26
9.5.2.1 Entering Idle Mode................................................................. 9-26
9.5.2.2 Exiting Idle Mode ................................ ...... ....... ...... ....... ...... ... 9-27
9.5.3 Sleep Mode............... ....... ...... ....................................... ...... ....... ...... ... 9-27
9.5.3.1 CPU Preparation for Sleep Mode .......................................... 9-27
9.5.3.2 Events Causing Entry into Sleep Mode ................................. 9-27
9.5.3.3 The Sleep Shutdown Sequence ............................................ 9-28
9.5.3.4 During Sleep Mode................................................................ 9-28
9.5.3.5 The Sleep Wake-Up Sequence ............................................. 9-28
SA-1100 Developer’s Manual v
9.5.3.6 Booting After Sleep Mode...................................................... 9-29
9.5.3.7 Reviving the DRAMs from Self-Refresh Mode ...................... 9-30
9.5.4 Notes on Power Supply Sequencing.................................................. 9-30
9.5.5 Assumed Behavior of an SA-1100 System in Sleep Mode................. 9-30
9.5.6 Pin Operation in Sleep Mode.............................................................. 9-32
9.5.7 Power Manager Registers.................................................................. 9-33
9.5.7.1 Power Manager Control Register (PMCR) ............................ 9-33
9.5.7.2 Power Manager General Configuration Register (PCFR)...... 9-34
9.5.7.3 Power Manager PLL Configuration Register (PPCR)............ 9-35
9.5.7.4 Power Manager Wake-Up Enable Register (PWER)............. 9-36
9.5.7.5 Power Manager Sleep Status Register (PSSR) .................... 9-37
9.5.7.6 Power Manager Scratch Pad Register (PSPR)..................... 9-39
9.5.7.7 Power Manager GPIO Sleep State Register (PGSR)............ 9-39
9.5.7.8 Power Manager Oscillator Status Register (POSR) .............. 9-40
9.5.8 Power Manager Register Locations ................................................... 9-40
9.6 Reset Controller............................................................................................... 9-41
9.6.1 Reset Controller Registers .................... ....... ...... ...... ....... ................... 9-42
9.6.1.1 Reset Controller Software Reset Register (RSRR) ............... 9-42
9.6.1.2 Reset Controller Status Register (RCSR).............................. 9-43
9.6.2 Reset Controller Register Locations......................... ....... ...... ....... ...... 9-43
10 Memory and PCMCIA Control Module..........................................................................10-1
10.1 Overview of Operation..................................................................................... 10-1
10.1.1 Example Memory System.................................................................. 10-3
10.1.2 Types of Memory Accesses ............................................................... 10-4
10.1.3 Reads ................................................................................................. 10-4
10.1.4 Writes ................................................................................................ 10-4
10.1.5 Transaction Summary ....................................................................... 10-4
10.1.6 Read-Lock-Write................................................................................. 10-5
10.1.7 Aborts and Nonexistent Memory ....................................................... 10-5
10.2 Memory Configuration Registers.................................................................... 10-6
10.2.1 DRAM Configuration Register (MDCNFG) ......................................... 10-7
10.2.2 DRAM CAS Waveform Shift Registers
(MDCAS0, MDCAS1, MDCAS2) ........................................................ 10-9
10.2.3 Static Memory Control Registers (MSC1–0)..................................... 10-10
10.2.4 Expansion Memory (PCMCIA) Configuration Register (MECR)....... 10-12
10.3 Dynamic Interface Operation......................................................................... 10-14
10.3.1 DRAM Overview............................................................................... 10-14
10.3.2 DRAM Timing ................................................................................... 10-15
10.3.3 DRAM Refresh ................................................................................. 10-18
10.3.4 DRAM Self-Refresh in Sleep Mode.................................................. 10-18
10.4 Static Memory Interface................................................................................. 10-18
10.4.1 ROM Interface Overview .................................................................. 10-19
10.4.2 ROM Timing Diagrams and Parameters........................................... 10-19
10.4.3 SRAM Interface Overview ............... ...... ....... ...... ...... ....... ...... ........... 10-22
10.4.4 SRAM Timing Diagrams and Parameters........... ...... ....... ...... ....... .... 10-22
10.4.5 FLASH EPROM Interface Overview................................................ 10-23
10.4.6 FLASH EPROM Timing Diagrams and Parameters ........................ 10-24
10.5 General Memory BUS Timing........................................................................ 10-25
10.5.1 Static Access Followed by a DRAM Access..................................... 10-25
10.5.2 DRAM Access Followed by a Static Access..................................... 10-25
vi SA-1100 Developer’s Manual
10.5.3 DRAM Access Followed by a Refresh Operation............................. 10-25
10.6 PCMCIA Overview............................. ....................................... ...... ....... ...... . 10-26
10.6.1 32-Bit Data Bus Operation............................................................... 10-27
10.6.2 External Logic for PCMCIA Implementation ................................... 10-28
10.6.3 PCMCIA Interface Timing Diagrams and Parameters..................... 10-31
10.7 Initialization of the Memory Interface............................................................. 10-34
10.7.1 Flow of Events After Reset or Exiting Sleep Mode........................... 10-34
10.8 Alternate Memory Bus Master Mode............................................................. 10-35
11 Peripheral Control Module.............................................................................................11-1
11.1 Read/Write Interface........................................................................................ 11-1
11.2 Memory Organization ...................................................................................... 11-2
11.3 Interrupts.......................................................................................................... 11-4
11.4 Peripheral Pins ................................................................................................ 11-5
11.5 Use of the GPIO Pins for Alternate Functions ................................................. 11-6
11.6 DMA Controller ................................................................................................ 11-7
11.6.1 DMA Register Definitions.................................................................... 11-7
11.6.1.1DMA Device Address Register (DDARn)............................... 11-8
11.6.1.2DMA Control/Status Register (DCSRn)............................... 11-11
11.6.1.3DMA Buffer A Start Address Register (DBSAn) ..................11-12
11.6.1.4DMA Buffer A Transfer Count Register (DBTAn) ................ 11-12
11.6.1.5DMA Buffer B Start Address Register (DBSBn) ..................11-13
11.6.1.6DMA Buffer B Transfer Count Register (DBTBn) ................ 11-13
11.6.2 DMA Operation.................................. ....... ...... ...... ....... ...... ....... ...... . 11-13
11.6.3 DMA Register List.............................................................................11-14
11.7 LCD Controller............................................................................................... 11-16
11.7.1 LCD Controller Operation ................................................................. 11-18
11.7.1.1DMA to Memory Interface.................................................... 11-18
11.7.1.2Frame Buffer........................................................................ 11-18
11.7.1.3Input FIFO............................................................................11-23
11.7.1.4Lookup Palette..................................................................... 11-23
11.7.1.5Color/Gray-Scale Dithering.................................................. 11-24
11.7.1.6Output FIFO.........................................................................11-24
11.7.1.7LCD Controller Pins............................................................. 11-25
11.7.2 LCD Controller Register Definitions.................................................. 11-25
11.7.3 LCD Controller Control Register 0.................................................... 11-26
11.7.3.1LCD Enable (LEN)............................................................... 11-26
11.7.3.2Color/Monochrome Select (CMS)........................................11-26
11.7.3.3Single-/Dual-Panel Select (SDS)......................................... 11-26
11.7.3.4LCD Disable Done Interrupt Mask (LDM)............................ 11-29
11.7.3.5Base Address Update Interrupt Mask (BAM).......................11-29
11.7.3.6Error Interrupt Mask (ERM) .................................................11-29
11.7.3.7Passive/Active Display Select (PAS)................................... 11-29
11.7.3.8Big/Little Endian Select (BLE).............................................. 11-31
11.7.3.9Double-Pixel Data (DPD) Pin Mode.....................................11-31
11.7.3.10Palette DMA Request Delay (PDD)................................... 11-31
11.7.4 LCD Controller Control Register 1.................................................... 11-34
11.7.4.1Pixels Per Line (PPL)........................................................... 11-34
11.7.4.2Horizontal Sync Pulse Width (HSW).................................... 11-34
11.7.4.3End-of-Line Pixel Clock Wait Count (ELW) .........................11-34
11.7.4.4Beginning-of-Line Pixel Clock Wait Count (BLW)................ 11-35
11.7.5 LCD Controller Control Register 2.................................................... 11-36
SA-1100 Developer’s Manual vii
11.7.5.1Lines Per Panel (LPP)......................................................... 11-36
11.7.5.2Vertical Sync Pulse Width (VSW)........................................ 11-36
11.7.5.3End-of-Frame Line Clock Wait Count (EFW)....................... 11-37
11.7.5.4Beginning-of-Frame Line Clock Wait Count (BFW)............. 11-37
11.7.6 LCD Controller Control Register 3.................................................... 11-39
11.7.6.1Pixel Clock Divider (PCD).................................................... 11-39
11.7.6.2AC Bias Pin Frequency (ACB)............................................. 11-39
11.7.6.3AC Bias Pin Transitions Per Interrupt (API)......................... 11-40
11.7.6.4Vertical Sync Polarity (VSP)................................................ 11-40
11.7.6.5Horizontal Sync Polarity (HSP)............................................ 11-40
11.7.6.6Pixel Clock Polarity (PCP)................................................... 11-40
11.7.6.7Output Enable Polarity (OEP).............................................. 11-41
11.7.7 LCD Controller DMA Registers......................................................... 11-42
11.7.8 DMA Channel 1 Base Address Register........................................... 11-43
11.7.9 DMA Channel 1 Current Address Register....................................... 11-44
11.7.10 DMA Channel 2 Base and Current Address Registers..................... 11-45
11.7.11 LCD Controller Status Register ........................................................ 11-46
11.7.11.1LCD Disable Done Flag (LDD)
(read/write, maskable interrupt)................... ....... ...... ....... .... 11-46
11.7.11.2Base Address Update Flag (BAU)
(read-only, maskable interrupt)............................................ 11-46
11.7.11.3Bus Error Status (BER)
(read/write, maskable interrupt)................... ....... ...... ....... .... 11-46
11.7.11.4AC Bias Count Status (ABC)
(read/write, nonmaskabl e inter rupt )....... ...... ....... ................. 11-47
11.7.11.5Input FIFO Overrun Lower Panel Status (IOL)
(read/write, maskable interrupt)................... ....... ...... ....... .... 11-47
11.7.11.6Input FIFO Underrun Lower Panel Status (IUL)
(read/write, maskable interrupt)................... ....... ...... ....... .... 11-47
11.7.11.7Input FIFO Overrun Upper Panel Status (IOU)
(read/write, maskable interrupt)................... ....... ...... ....... .... 11-47
11.7.11.8Input FIFO Underrun Upper Panel Status (IUU)
(read/write, maskable interrupt)................... ....... ...... ....... .... 11-47
11.7.11.9Output FIFO Overrun Lower Panel Status (OOL)
(read/write, maskable interrupt)................... ....... ...... ....... .... 11-47
11.7.11.10Output FIFO Underrun Lower Panel Status (OUL)
(read/write, maskable interrupt)................... ....... ...... ....... .... 11-48
11.7.11.11Output FIFO Over run Upper Panel Status (OOU)
(read/write, maskable interrupt)................... ....... ...... ....... .... 11-48
11.7.11.12Output FIFO Underrun Upper Panel Status (OUU)
(read/write, maskable interrupt)................... ....... ...... ....... .... 11-48
11.7.12 LCD Controller Register Locations................................................... 11-50
11.7.13 LCD Controller Pin Timing Diagrams................................................ 11-51
11.8 Serial Port 0 – USB Device Controller........................................................... 11-56
11.8.1 USB Operation ................................................................................. 11-56
11.8.1.1Signalling Levels.................................................................. 11-57
11.8.1.2Bit Encoding ........................................................................ 11-58
11.8.1.3Field Formats....................................................................... 11-59
11.8.1.4Packet Formats .................. ...... ....... ...... ...... ....... ...... ....... .... 11-60
11.8.1.5Transaction Formats............................................................ 11-61
11.8.1.6UDC Device Requests......................................................... 11-62
11.8.2 UDC Register Definitions.................................................................. 11-63
11.8.3 UDC Control Register....................................................................... 11-64
viii SA-1100 Developer’s Manual
11.8.3.1UDC Disable (UDD)............................................................. 11-64
11.8.3.2 UDC Active (UDA) .............................................................. 11-64
11.8.3.3Bit 2 Reserved ..................................................................... 11-64
11.8.3.4Endpoint 0 Interrupt Mask (EIM).......................................... 11-64
11.8.3.5Receive Interrupt Mask (RIM).............................................11-64
11.8.3.6Transmit Interrupt Mask (TIM) ............................................ 11-64
11.8.3.7Suspend/Resume Interrupt Mask (SRM)............................. 11-65
11.8.3.8Reset Interrupt Mask (REM)................................................ 11-65
11.8.4 UDC Address Register .....................................................................11-66
11.8.5 UDC OUT Max Packet Register....................................................... 11-66
11.8.6 UDC IN Max Packet Register........................................................... 11-67
11.8.7 UDC Endpoint 0 Control/Status Register.......................................... 11-68
11.8.7.1OUT Packet Ready (OPR)................................................... 11-68
11.8.7.2IN Packet Ready (IPR) ........................................................ 11-68
11.8.7.3Sent Stall (SST)................................................................... 11-68
11.8.7.4Force Stall (FST) ...................................... ....... ...... ....... ...... . 11-68
11.8.7.5Data End (DE) .... ...... ....... ...... ....... ...... ...... ........................... 11-68
11.8.7.6Setup End (SE).................................................................... 11-68
11.8.7.7Serviced OPR (SO) .. ....... ...... ....................................... ...... . 11-68
11.8.7.8Serviced Setup End (SSE) .................................................. 11-69
11.8.8 UDC Endpoint 1 Control/Status Register.......................................... 11-70
11.8.8.1Receive FIFO Service (RFS)............................................... 11-70
11.8.8.2Receive Packet Complete (RPC) ........................................11-70
11.8.8.3Receive Packet Error (RPE)................................................ 11-70
11.8.8.4Sent Stall (SST)................................................................... 11-70
11.8.8.5Force Stall (FST) ...................................... ....... ...... ....... ...... . 11-70
11.8.8.6Receive FIFO Not Empty (RNE).......................................... 11-70
11.8.8.7Bits 7..6 Reserved ............................................................... 11-71
11.8.9 UDC Endpoint 2 Control/Status Register.......................................... 11-72
11.8.9.1Transmit FIFO Service (TFS) ..............................................11-72
11.8.9.2Transmit Packet Complete (TPC)........................................11-72
11.8.9.3 Transmit Packet Error (TPE) ..............................................11-72
11.8.9.4Transmit Underrun (TUR)............. ...... ................................. 11-72
11.8.9.5Sent STALL (SST)............................................................... 11-72
11.8.9.6Force STALL (FST) .. ....... ...... ....... ...... ...... ....... ...... ....... ...... . 11-72
11.8.9.7Bits 7..6 Reserved ............................................................... 11-73
11.8.10 UDC Endpoint 0 Data Register......................................................... 11-74
11.8.11 UDC Endpoint 0 Write Count Register ............................................. 11-74
11.8.12 UDC Data Register........................................................................... 11-75
11.8.13 UDC Status/Interrupt Register.......................................................... 11-76
11.8.13.1Endpoint 0 Interrupt Request (EIR) ...................................11-76
11.8.13.2Receive Interrupt Request (RIR) ....................................... 11-76
11.8.13.3Transmit Interrupt Request (TIR)....................................... 11-76
11.8.13.4Suspend Interrupt Request (SUSIR) .................................11-76
11.8.13.5Resume Interrupt Request (RESIR) .................................. 11-76
11.8.13.6 Reset Interrupt Request (RSTIR) ..................................... 11-77
11.8.14 UDC Register Locations ................................................................... 11-78
11.9 Serial Port 1 – SDLC/UART........................................................................... 11-78
11.9.1 SDLC Operation ............................................................................... 11-79
11.9.1.1Bit Encoding......................................................................... 11-79
11.9.1.2Frame Format...................................................................... 11-80
11.9.1.3Address Field....................................................................... 11-80
11.9.1.4Control Field ........................................................................ 11-80
SA-1100 Developer’s Manual ix
11.9.1.5Data Field ............................................................................ 11-81
11.9.1.6CRC Field............................................................................ 11-81
11.9.1.7Baud Rate Generation......................................................... 11-81
11.9.1.8Receive Operation............................................................... 11-82
11.9.1.9Transmit Operation.............................................................. 11-83
11.9.1.10Simultaneous Use of the UART and SDLC....................... 11-83
11.9.1.11Transmit and Receive FIFOs............................................. 11-84
11.9.1.12CPU and DMA Register Access Sizes .............................. 11-84
11.9.2 SDLC Register Definitions................................................................ 11-84
11.9.3 SDLC Control Register 0 .................................................................. 11-85
11.9.3.1SDLC/UART Select (SUS)................................................... 11-85
11.9.3.2Single/Double Flag Select (SDF)......................................... 11-85
11.9.3.3Loopback Mode (LBM) ........................................................ 11-85
11.9.3.4Bit Modulation Select (BMS)................................................ 11-86
11.9.3.5Sample Clock Enable (SCE) ............................................... 11-86
11.9.3.6Sample Clock Direction (SCD) ............................................ 11-86
11.9.3.7Receive Clock Edge Select (RCE) ...................................... 11-87
11.9.3.8Transmit Clock Edge Select (TCE)...................................... 11-87
11.9.4 SDLC Control Register 1 .................................................................. 11-88
11.9.4.1Abort After Frame (AAF)...................................................... 11-88
11.9.4.2Transmit Enable (TXE)........................................................ 11-89
11.9.4.3Receive Enable (RXE)......................................................... 11-89
11.9.4.4Receive FIFO Interrupt Enable (RIE)................................... 11-89
11.9.4.5Transmit FIFO Interrupt Enable (TIE).................................. 11-89
11.9.4.6Address Match Enable (AME) ............................................. 11-90
11.9.4.7Transmit FIFO Underrun Select (TUS)................................ 11-90
11.9.4.8Receiver Abort Interrupt Enable(RAE)................................. 11-90
11.9.5 SDLC Control Register 2 .................................................................. 11-92
11.9.5.1Address Match Value (AMV) ............................................... 11-92
11.9.6 SDLC Control Registers 3 and 4 ...................................................... 11-93
11.9.6.1Baud Rate Divisor (BRD)..................................................... 11-93
11.9.7 SDLC Data Register ......................................................................... 11-94
11.9.8 SDLC Status Register 0 ................................................................... 11-96
11.9.8.1End/Error in FIFO Status (EIF)
(read-only, nonmaskable interrupt)...................................... 11-96
11.9.8.2Transmit Underrun Status (TUR)
(read/write, maskable interrupt)................... ....... ...... ....... .... 11-96
11.9.8.3Receiver Abort Status (RAB )
(read/write, maskable interrupt)................... ....... ...... ....... .... 11-96
11.9.8.4Transmit FIFO Service Request Flag (TFS)
(read-only, maskable interrupt)............................................ 11-97
11.9.8.5Receive FIFO Service Request Flag (RFS)
(read-only, maskable interrupt)............................................ 11-97
11.9.9 SDLC Status Register 1 ................................................................... 11-99
11.9.9.1Receiver Synchronized Flag (RSY)
(read-only, noninterruptible)................................................. 11-99
11.9.9.2Transmitter Busy Flag (TBY)
(read-only, noninterruptible)................................................. 11-99
11.9.9.3Receive FIFO Not Empty Flag (RNE)
(read-only, noninterruptible)................................................. 11-99
11.9.9.4Transmit FIFO Not Full Flag (TNF)
(read-only, noninterruptible)................................................. 11-99
x SA-1100 Developer’s Manual
11.9.9.5Receive Transition Detect Status (RTD)
(read/write, noninterruptible)................................................ 11-99
11.9.9.6End of Frame Flag (EOF)
(read-only, noninterruptible)................................................. 11-99
11.9.9.7CRC Error Status (CRE)
(read-only, noninterruptible)............................................... 11-100
11.9.9.8Receiver Overrun Status (ROR)
(read-only, noninterruptible)............................................... 11-100
11.9.10 UART Register Locations ............................................................... 11-102
11.9.11 SDLC Register Locations ............................................................... 11-103
11.10 Serial Port 2 – Infrared Communications Port (ICP).................................... 11-103
11.10.1 Low-Speed ICP Operation.............................................................. 11-104
11.10.1.1HP-SIR* Modulation......................................................... 11 -104
11.10.1.2 UART Frame Format ...................................................... 11-104
11.10.2 High-Speed ICP Operation............................................................. 11-105
11.10.2.14PPM Modulation ............................................................ 11-105
11.10.2.2HSSP Frame Format ....................................................... 11-106
11.10.2.3Address Field................................................................... 11-107
11.10.2.4Control Field .................................................................... 11-107
11.10.2.5Data Field ........................................................................ 11-107
11.10.2.6CRC Field ........................................................................ 11-107
11.10.2.7Baud Rate Generation..................................................... 11-108
11.10.2.8Receive Operation........................................................... 11-108
11.10.2.9Transmit Operation.......................................................... 11-109
11.10.2.10Transmit and Receive FIFOs......................................... 11-110
11.10.2.11CPU and DMA Register Access Sizes .......................... 11-110
11.10.3 UART Register Definition................................................................ 11-111
11.10.4 UART Control Register 4................................................................ 11-111
11.10.4.1HP-SIR Enable (HSE)...................................................... 11-111
11.10.4.2Low-Power Mode (LPM).................................................. 11-111
11.10.5 HSSP Register Definitions.............................................................. 11-112
11.10.6 HSSP Control Register 0................................................................ 11-112
11.10.6.1IrDA Transmission Rate (ITR) ......................................... 11-112
11.10.6.2Loopback Mode (LBM) .................................................... 11-112
11.10.6.3Transmit FIFO Underrun Select (TUS)............................ 11-113
11.10.6.4Transmit Enable (TXE).................................................... 11-113
11.10.6.5Receive Enable (RXE)..................................................... 11-114
11.10.6.6Receive FIFO Interrupt Enable (RIE)............................... 11-114
11.10.6.7Transmit FIFO Interrupt Enable (TIE).............................. 11-114
11.10.6.8Address Match Enable (AME) ......................................... 11-114
11.10.7 HSSP Control Register 1................................................................ 11-116
11.10.7.1Address Match Value (AMV) ........................................... 11-116
11.10.8 HSSP Control Register 2................................................................ 11-117
11.10.8.1Transmit Pin Polarity Select (TXP) .................................. 11-117
11.10.8.2Receive Pin Polarity Select (RXP)................................... 11-117
11.10.9 HSSP Data Register....................................................................... 11-119
11.10.10HSSP Status Register 0 ................................................................ 11-121
11.10.10.1End/Error in FIFO Status (EIF)
(read-only, nonmaskable interrupt).................................... 11-121
11.10.10.2Transmit Underrun Status (TUR)
(read/write, maskable interrupt)......................................... 11-121
11.10.10.3Receiver Abort Status (RAB)
(read/write, nonmaskable interrupt)................................... 11-121
SA-1100 Developer’s Manual xi
11.10.10.4Transmit FIFO Service Request Flag (TFS)
(read-only, maskable interrupt).......................................... 11-122
11.10.10.5Receive FIFO Service Request Flag (RFS)
(read-only, maskable interrupt).......................................... 11-122
11.10.10.6Framing Error Status (FRE)
(read/write, nonmaskabl e inter rupt )....... ...... ....... ............... 11-123
11.10.11HSSP Status Register 1 ................................................................ 11-124
11.10.11.1Receiver Synchronized Flag (RSY)
(read-only, noninterruptible)............................................... 11-124
11.10.11.2Transmitter Busy Flag (TBY)
(read-only, noninterruptible)............................................... 11-124
11.10.11.3Receive FIFO Not Empty Flag (RNE)
(read-only, noninterruptible)............................................... 11-124
11.10.11.4Transmit FIFO Not Full Flag (TNF)
(read-only, noninterruptible)............................................... 11-124
11.10.11.5End-of-Frame Flag (EOF)
(read-only, noninterruptible)............................................... 11-124
11.10.11.6CRC Error Status (CRE)
(read-only, noninterruptible)............................................... 11-125
11.10.11.7Receiver Overrun Status (ROR)
(read-only, noninterruptible)............................................... 11-125
11.10.12UART Register Locations.............................................................. 11-127
11.10.13HSSP Register Locations.............................................................. 11-127
11.11 Serial Port 3 - UART.................................................................................... 11-128
11.11.1 UART Operation............................................................................. 11-128
11.11.1.1Frame Format.................................................................. 11-129
11.11.1.2Baud Rate Generation..................................................... 11-129
11.11.1.3Receive Operation........................................................... 11-129
11.11.1.4Transmit Operation.......................................................... 11-130
11.11.1.5Transmit and Receive FIFOs........................................... 11-130
11.11.1.6CPU and DMA Register Access Sizes ............................ 11-131
11.11.2 UART Register Definitions.............................................................. 11-131
11.11.3 UART Control Register 0................................................................ 11-131
11.11.3.1Parity Enable (PE)........................................................... 11-131
11.11.3.2Odd/Even Parity Select (OES) ........................................ 11-131
11.11.3.3Stop Bit Select (SBS) ............. ....... ...... ...... ....... ............... 11-132
11.11.3.4Data Size Select (DSS) ................................................... 11-132
11.11.3.5Sample Clock Enable (SCE) ........................................... 11-132
11.11.3.6Receive Clock Edge Select (RCE) .................................. 11-132
11.11.3.7Transmit Clock Edge Select (TCE).................................. 11-133
11.11.4 UART Control Registers 1 and 2.................................................... 11-134
11.11.4.1Baud Rate Divisor (BRD)................................................. 11-134
11.11.5 UART Control Register 3................................................................ 11-135
11.11.5.1Receiver Enable (RXE) ................................................... 11-135
11.11.5.2Transmitter Enable (TXE)................................................ 11-135
11.11.5.3Break (BRK) .................................................................... 11-135
11.11.5.4Receive FIFO Interrupt Enable (RIE)............................... 11-135
11.11.5.5Transmit FIFO Interrupt Enable (TIE).............................. 11-136
11.11.5.6Loopback Mode (LBM) .................................................... 11-136
11.11.6 UART Data Register....................................................................... 11-137
11.11.7 UART Status Register 0 ................................................................. 11-139
11.11.7.1Transmit FIFO Service Request Flag (TFS)
(read-only, maskable interrupt).......................................... 11-139
xii SA-1100 Developer’s Manual
11.11.7.2Receive FIFO Service Request Flag (RFS)
(read-only, maskable interrupt).......................................... 11-139
11.11.7.3Receiver Idle Status (RID)
(read/write, maskable interrupt)......................................... 11-140
11.11.7.4Receiver Begin of Break Status (RBB)
(read/write, nonmaskable interrupt)................................... 11-140
11.11.7.5Receiver End of Break Status (REB) (read/write, nonmaskable interrupt)11-140
11.11.7.6Error in FIFO Flag (EIF)
(read-only, nonmaskable interrupt).................................... 11-140
11.11.8 UART Status Register 1 ................................................................. 11-142
11.11.8.1Transmitter Busy Flag (TBY
(read-only, noninterruptible)............................................... 11-142
11.11.8.2Receive FIFO Not Empty Flag (RNE)
(read-only, noninterruptible)............................................... 11-142
11.11.8.3Transmit FIFO Not Full Flag (TNF)
(read-only, noninterruptible)............................................... 11-142
11.11.8.4Parity Error Flag (PRE)
(read-only, noninterruptible)............................................... 11-142
11.11.8.5Framing Error Flag (FRE)
(read-only, noninterruptible)............................................... 11-143
11.11.8.6Receiver Overrun Flag (ROR)
(read-only, noninterruptible)............................................... 11-143
11.11.9 UART Register Locations ............................................................... 11-145
11.12 Serial Port 4 – MCP / SSP........................................................................... 11-145
11.12.1 MCP Operation............................................................................... 11-146
11.12.1.1Frame Format...................... ....... ..................................... 11 -147
11.12.1.2Audio and Telecom Sample Rates and Data Transfer .... 11-148
11.12.1.3MCP Transmit and Receive FIFO Operation................... 11-149
11.12.1.4Codec Control Register Data Transfer ............................ 11-150
11.12.1.5External Clock Operation................................................. 11-151
11.12.1.6Alternate SSP Pin Assignment ........................................ 11-151
11.12.1.7CPU and DMA Register Access Sizes ............................ 11-151
11.12.2 MCP Register Definitions................................................................ 11-152
11.12.3 MCP Control Register..................................................................... 11-152
11.12.3.1Audio Sample Rate Divisor (ASD)................................... 11-152
11.12.3.2Telecom Sample Rate Divisor (TSD)............................... 11-153
11.12.3.3 Multimedia Communications Port Enable (MCE) .......... 11-154
11.12.3.4External Clock Select (ECS)............................................ 11-154
11.12.3.5A/D Sampling Mode (ADM) ............................................. 11-154
11.12.3.6Telecom Transmit FIFO Interrupt Enable (TTE).............. 11-155
11.12.3.7Telecom Receive FIFO Interrupt Enable (TRE)............... 11-155
11.12.3.8Audio Transmit FIFO Interrupt Enable (ATE) .................. 11-155
11.12.3.9Audio Receive FIFO Interrupt Enable (ARE) ................... 11-155
11.12.3.10Loopback Mode (LBM) .................................................. 11-156
11.12.3.11External Clock Prescaler (ECP)..................................... 11-156
11.12.4 MCP Control Register 1.................................................................. 11-158
11.12.4.1Clock Frequency Select (CFS) ........................................ 11-158
11.12.5 MCP Data Registers....................................................................... 11-158
11.12.5.1MCP Data Register 0....................................................... 11-159
11.12.5.2MCP Data Register 1....................................................... 11-160
11.12.5.3MCP Data Register 2....................................................... 11-161
11.12.6 MCP Status Register ...................................................................... 11-163
SA-1100 Developer’s Manual xiii
11.12.6.1Audio Transmit FIFO Service Request Flag (ATS)
(read-only, maskable interrupt).......................................... 11-163
11.12.6.2Audio Receive FIFO Service Request Flag (ARS)
(read-only, maskable interrupt).......................................... 11-163
11.12.6.3Telecom Transmit FIFO Service Request Flag (TTS)
(read-only, maskable interrupt).......................................... 11-164
11.12.6.4Telecom Receive FIFO Service Request Flag (TRS)
(read-only, maskable interrupt).......................................... 11-164
11.12.6.5Audio Transmit FIFO Underrun Status (ATU)
(read/write, nonmaskabl e inter rupt )....... ...... ....... ............... 11-164
11.12.6.6Audio Receive FIFO Overrun Status (ARO)
(read/write, nonmaskabl e inter rupt )....... ...... ....... ............... 11-164
11.12.6.7Telecom Transmit FIFO Underrun Status (TTU)
(read/write, nonmaskabl e inter rupt )....... ...... ....... ............... 11-165
11.12.6.8Telecom Receive FIFO Over run Sta t us (TRO)
(read/write, nonmaskabl e inter rupt )....... ...... ....... ............... 11-165
11.12.6.9Audio Transmit FIFO Not Full Flag (ANF)
(read-only, noninterruptible)............................................... 11-165
11.12.6.10Audio Receive FIFO Not Empty Flag (ANE)
(read-only, noninterruptible)............................................... 11-165
11.12.6.11Telecom Transmit FIFO Not Full Flag (TNF)
(read-only, noninterruptible)............................................... 11-165
11.12.6.12Telecom Receive FIFO Not Empty Flag (TNE)
(read-only, noninterruptible)............................................... 11-166
11.12.6.13Codec Write Completed Flag (CWC)
(read-only, noninterruptible)............................................... 11-166
11.12.6.14Codec Read Completed Flag (CRC)
(read-only, noninterruptible)............................................... 11-166
11.12.6.15Audio Codec Enabled Flag (ACE)
(read-only, noninterruptible)............................................... 11-166
11.12.6.16Telecom Codec Enabled Flag (TCE)
(read-only, noninterruptible)............................................... 11-166
11.12.7 SSP Operation ....... ...... ....... ...... ....... ...... ....................................... .. 11-169
11.12.7.1Frame Format.................................................................. 11-169
11.12.7.2Baud Rate Generation..................................................... 11-173
11.12.7.3 SSP Transmit and Receive FIFOs.................................. 11-173
11.12.7.4CPU and DMA Register Access Sizes ............................ 11-174
11.12.7.5Alternate SSP Pin Assignment ........................................ 11-174
11.12.8 SSP Register Definitions ................. ...... ....... ...... ...... ....... ...... ....... .. 11-174
11.12.9 SSP Control Register 0 .................................................................. 11-174
11.12.9.1Data Size Select (DSS) ................................................... 11-175
11.12.9.2Frame Format (FRF)........................................................ 11-175
11.12.9.3Synchronous Serial Port Enable (SSE)........................... 11-175
11.12.9.4Serial Clock Rate (SCR)............................ ...................... 1 1-176
11.12.10SSP Control Register 1 ................................................................. 11-177
11.12.10.1Receive FIFO Interrupt Enable (RIE)............................. 11-177
11.12.10.2Transmit FIFO Interrupt Enable (TIE)............................ 11-177
11.12.10.3Loopback Mode (LBM) .................................................. 11-177
11.12.10.4Serial Clock Polarity (SPO)............................................ 11-177
11.12.10.5Serial Clock Phase (SPH) ............................................. 11-178
11.12.10.6External Clock Select (ECS).......................................... 11-179
11.12.11SSP Data Register ........................................................................ 11-180
11.12.12SSP Status Register...................................................................... 11-181
xiv SA-1100 Developer’s Manual
11.12.12.1Transmit FIFO Not Full Flag (TNF)
(read-only, noninterruptible)............................................... 11-181
11.12.12.2Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptibl11-181
11.12.12.3SSP Busy Flag (BSY)
(read-only, noninterruptible)............................................... 11-181
11.12.12.4Transmit FIFO Service Request Flag (TFS)
(read-only, maskable interrupt)............................................ 1-181
11.12.12.5Receive FIFO Service Request Flag (RFS)
(read-only, maskable interrupt).......................................... 11-182
11.12.12.6Receiver Overrun Status (ROR)
(read/write, nonmaskable interrupt)................................... 11-182
11.12.13MCP Register Locations................................................................ 11-183
11.12.14SSP Register Locations................................................................. 11-183
11.13 Peripheral Pin Controller (PPC)................................................................... 11-184
11.13.1 PPC Operation................................................................................ 11-184
11.13.2 PPC Register Definitions ................................................................ 11-185
11.13.3 PPC Pin Direction Register............................................................. 11-185
11.13.4 PPC Pin State Register .................................................................. 11-187
11.13.5 PPC Pin Assignment Register........................................................ 11-189
11.13.5.1UART Pin Reassignment (UPR)......................................11-189
11.13.5.2SSP Pin Reassignm ent (SPR)......................................... 11-1 89
11.13.6 PPC Sleep Mode Pin Direction Register ........................................ 11-190
11.13.7 PPC Pin Flag Register.................................................................... 11-192
11.13.8 PPC Register Locations.................................................................. 11-193
12 DC Parameters......................... ....... ...... ....... ...... ...... ....... ...... ....... ...... ...........................12-1
12.1 Absolute Maximum Ratings............................................................................. 12-1
12.2 DC Operating Conditions................................................................................. 12-2
12.3 Power Supply Voltages and Currents.............................................................. 12-3
13 AC Parameters..............................................................................................................13-1
13.1 Test Conditions...................... ....... ...... ....................................... ...... ....... ...... ... 13-1
13.2 Module Considerations.................................................................................... 13-2
13.3 Memory Bus and PCMCIA Signal Timings...................................................... 13-2
13.4 LCD Controller Signals .................................................................................... 13-3
13.5 MCP Signals.................................................................................................... 13-3
13.6 Timing Parameters .......................................................................................... 13-4
13.6.1 Asynchronous Signal Timing Descriptions ......................................... 13-5
14 Package and Pinout ......................................................................................................14-1
14.1 Mechanical Data and Packaging Information .................................................. 14-1
14.2 Mini-Ball Grid Array – (mBGA)......................................................................... 14-3
15 Debug Support..............................................................................................................15-1
15.1 Instruction Breakpoint...................................................................................... 15-1
15.2 Data Breakpoint.................................. ....................................... ...... ....... ...... ... 15-1
16 Boundary-Scan Test Interface.......................................................................................16-1
16.1 Overview.......................................................................................................... 16-1
16.2 Reset ............................................................................................................... 16-2
16.3 Pull-Up Resistors....................................... ...... ....... ...................................... ... 16-2
SA-1100 Developer’s Manual xv
16.4 Instruction Register.......................................................................................... 16-2
16.5 Public Instructions ........................................................................................... 16-2
16.5.1 EXTEST (00000) ................................................................................ 16-3
16.5.2 SAMPLE/PRELOAD (00001) ............................................................. 16-3
16.5.3 CLAMP (00100).................................................................................. 16-3
16.5.4 HIGHZ (00101)................................................................................... 16-4
16.5.5 IDCODE (00110) ................................................................................ 16-4
16.5.6 BYPASS (11111)................................................................................ 16-4
16.6 Test Data Registers......................................................................................... 16-5
16.6.1 Bypass Register ................................................................................. 16-5
16.6.2 SA-1100 Device Identification (ID) Code Register.............................. 16-6
16.6.3 SA-1100 Boundary-Scan (BS) Register ............................................. 16-6
16.7 Boundary-Scan Interface Signals.................................................................... 16-7
A Register Summary ......................................................................................................... A-1
B 3.6864–MHz Oscillator Specifications............................................................................ B-1
B.1 Specifications ....................................................................................................B-1
B.1.1 System Specifications ........ ...... ....... ...... ....... ...... ..................................B-1
B.1.1.1.Parasitic Capacitance Off-chip
Between PXTAL and PEXTAL.................................................B-2
B.1.1.2.Parasitic Capacitance Off-chip
Between PXTAL or PEXTAL and VSS....................................B-2
B.1.1.3.Parasitic Resistance Between PXTAL and PEXTAL...............B-2
B.1.1.4.Parasitic Resistance Between PXTAL or PEXTAL and VSS...B-2
B.1.2 Quartz Crystal Specification .................................................................B-3
C 32.768–kHz Oscillator Specifications.............................................................................C-1
C.1 Specifications ....................................................................................................C-1
C.1.1 System Specifications . ....... ...... ....... ...... ....... ...................................... ..C-1
C.1.1.1.Temperature Range.................................................................C-1
C.1.1.2.Current Consumption...............................................................C-1
C.1.1.3.Startup Time............................................................................C-1
C.1.1.4.Frequency Shift Due to Temperature Effect on the Circuit......C-2
C.1.1.5.Parasitic Capacitance Off-chip
Between TXTAL and TEXTAL.................................................C-2
C.1.1.6.Parasitic Capacitance Off-chip
Between TXTAL or TEXTAL and VSS................ ...... ....... ........C-2
C.1.1.7.Parasitic Resistance Between TXTAL and TEXTAL ...............C-2
C.1.1.8.Parasitic Resistance Between TXTAL or TEXTAL and VSS...C-2
C.1.2 Quartz Crystal Specification .................................................................C-3
D Internal Test................................................................................................................... D-1
D.1 Test Unit Control Register (TUCR)....................................................................D-1
xvi SA-1100 Developer’s Manual

Figures

1-1 SA-1100 Features.............................................................................................. 1-1
1-2 SA-1100 Example System................................................................................. 1-5
2-1 SA-1100 Block Diagram .................................................................................... 2-2
2-2 SA-1100 Functional Diagram............................................................................. 2-3
2-3 SA-1100 Memory Map....................................................................................... 2-8
5-1 Format of Internal Coprocessor Instructions MRC and MCR ............................ 5-1
9-1 General-Purpose I/O Block Diagram................................................................. 9-2
9-2 Interrupt Controller Block Diagram .................................................................. 9-11
9-3 Transitions Between Modes of Operation........................................................ 9-31
10-1 General Memory Interface Configuration........................................................ 10-1
10-2 Example Memory Configuration ............................. ...................................... ... 10-3
10-3 DRAM Single-Beat Transactions................................................................... 10-16
10-4 DRAM Burst-of-Eight Transactions................................................................ 10-17
10-5 DRAM Refresh Cycle..................................................................................... 10-18
10-6 Burst-of-Eight ROM Timing Diagram............................................................. 10-20
10-7 Eight Beat Burst Read from Burst-of-Four ROM ...........................................10-21
10-8 Nonburst ROM, SRAM, or Flash Read Timing Diagram – Four Data Beats . 10-21
10-9 SRAM Write Timing Diagram (4–Beat Burst) ................................................ 10-22
10-10 Flash Write Timing Diagram (2 Writes).......................................................... 10-24
10-11 PCMCIA Memory Map........................ ....... ...................................... ....... ...... . 10-26
10-12 PCMCIA External Logic for a Two-Socket Configuration .............................. 10-29
10-13 PCMCIA External Logic for a One-Socket Configuration ..............................10-30
10-14 PCMCIA Voltage-Control Logic .............................. ...... ...... ....... ...... ....... ....... 10-31
10-15 PCMCIA Memory or I/O 16-Bit Access............................................ ....... ...... . 10-32
10-16 PCMCIA I/O 16-Bit Access to 8-Bit Device.................................................... 10-33
11-1 Peripheral Control Module Block Diagram....................................................... 11-2
11-2 Big and Little Endian DMA Transfers............................................................... 11-9
11-3 Palette Buffer Format..................................................................................... 11-19
11-4 4 Bits Per Pixel Data Memory Organization (Little Endian)........................... 11-20
11-5 8-Bits Per Pixel Data Memory Organization (Little Endian)........................... 11-21
11-6 12-Bits Per Pixel Data Memory Organization (Passive Mode Only).............. 11-21
11-7 16-Bits Per Pixel Data Memory Organization (Active Mode Only)................. 11-21
11-8 LCD Data-Pin Pixel Ordering......................................................................... 11-28
11-9 Frame Buffer/Palette Bits Output to LCD Data Pins in Active Mode ............. 11-30
11-10 Passive Mode Beginning-of-Frame Timing.................................................... 11-51
11-11 Passive Mode End-of-Frame Timing............................................................. 11-52
11-12 Passive Mode Pixel Clock and Data Pin Timing............................................ 11-53
11-13 Active Mode Timing ....................................................................................... 11-54
11-14 Active Mode Pixel Clock and Data Pin Timing............................................... 11-55
11-15 NRZI Bit Encoding Example.......................................................................... 11-58
11-16 IN, OUT, and SETUP Token Packet Format................................................. 11-60
11-17 SOF Token Packet Format............................................................................ 11-60
11-18 Data Packet Format............................ ....... ...... ....... ...... ................................. 11-60
11-19 Handshake Packet Format ............................................................................ 11-60
11-20 Bulk Transaction Formats................................................... ....... ...... ....... ...... . 11-61
11-21 Control Transaction Formats ......................................................................... 11-62
11-22 FM0/NRZ Bit Encoding Example (0100 1011)............................................... 11-80
11-23 SDLC Frame Format ..................................................................................... 11-80
SA-1100 Developer’s Manual xvii
11-24 HP-SIR Modulation Example....................................................................... 11-104
11-25 UART Frame Format for IrDA Transmission (<= 115.2 Kbps) .................... 11-105
11-26 4PPM Modulation Encodings ...................................................................... 11-105
11-27 4PPM Modulation Example ......................................................................... 11-106
11-28 High-Speed Serial Frame Format for IrDA Transmission (4.0 Mbps).......... 11-106
11-29 Example UART Data Frame........................................................................ 11-128
11-30 NRZ Bit Encoding Example – (0100 1011).................................................. 11-129
11-31 MCP Frame Data Format ............................................................................ 11-147
11-32 MCP Frame Pin Timing ............................................................................... 11-147
11-33 MPC/Codec Sampling Counter Synchronization......................................... 11-148
11-34 Audio/Telecom Transmit/Receive FIFO Data Format ................................. 11-150
11-35 Texas Instruments* Synchronous Serial Frame Format.............................. 11-170
11-36 Motorola* SPI Frame Format....................................................................... 11-171
11-37 National Microwire* Frame Format.............................................................. 11-172
11-38 Transmit/Receive FIFO Data Format .......................................................... 11-173
11-39 Motorola* SPI Frame Formats for SPO and SPH Programming ................. 11-178
13-1 Memory Bus AC Timing Definitions................................................................. 13-2
13-2 LCD AC Timing Definitions.............................................................................. 13-3
13-3 MCP AC Timing Definitions............................................................................. 13-3
14-1 Quad Flat Pack – 1.4mm (LQFP) .................................................................... 14-1
14-2 SA-1100 256 Mini-Ball Grid Array Mechanical Drawing.................................. 14-3
16-1 Test Access Port (TAP) Controller State Transitions ...................................... 16-1
16-2 Boundary-Scan Block Diagram ....................................................................... 16-5
16-3 Boundary-Scan General Timing ...................................................................... 16-7
16-4 Boundary-Scan Tristate Timing....................................................................... 16-8
16-5 Boundary-Scan Reset Timing.......................................................................... 16-8

Tables

1-1 Features of the SA-1100 CPU for AA and EA Parts.......................................... 1-2
1-2 Features of the SA-1100 CPU for CA and DA Parts ......................................... 1-2
1-3 Changes to the SA-1100 Core from the SA-110 ............................................... 1-3
1-4 Additional Features Built into SA-1100 Chipset................................................. 1-3
2-1 Signal Descriptions............................................................................................ 2-4
3-1 Vector Summa ry.............................. ...................................... ....... ...... ....... ...... .. 3-4
4-1 Instruction Timings ............................................................................................ 4-1
5-1 Cache and MMU Control Registers (Coprocessor 15)...................................... 5-2
6-1 Effects of the Cacheable and Bufferable Bits on the Data Caches ................... 6-3
7-1 Valid MMU, Dcache, and Write Buffer Combinations........................................ 7-2
8-1 Core Clock Configurations................................................................................. 8-2
9-1 OS Timer Register Locations .......................................................................... 9-25
9-2 SA-1100 Power and Clock Supply Sources and States
During Power-Down Modes............................................................................. 9-31
9-3 Pin State During Step...................................................................................... 9-32
9-4 Power Manager Register Locations ................................................................ 9-40
9-5 Reset Controller Register Locations................................................................ 9-43
10-1 SA-1100 Transactions..................................................................................... 10-5
10-2 Memory Interface Control Registers................................................................ 10-6
10-3 BS_xx Bit Encoding ...................................... ...... ....... ...... .............................. 10-13
10-4 BCLK Speeds for 160-MHz Processor Core Frequency ............................... 10-13
xviii SA-1100 Developer’s Manual
10-5 DRAM Memory Size Options.........................................................................10-14
10-6 DRAM Row/Column Address Multiplexing .................................................... 10-14
11-1 Peripheral Control Modules’ Register Width and DMA Port Size.................... 11-2
11-2 Peripher a l Units’ Base Add ress es .......................... ...... ...... ....... ...... ....... ......... 11-3
11-3 Peripheral Units’ Interrupt Numbers ................................................................ 11-4
11-4 Dedica ted Peri phe ral Pins ......................... ...... ....... ...... ...... ....... ...... ....... ...... ... 11-5
11-5 Peripheral Unit GPIO Pin Assignment............................................................. 11-6
11-6 Valid Settings for the DDARn Register......................................................... 11-10
11-7 Color/Gray-Scale Intensities and Modulation Rates...................................... 11-24
11-8 LCD Controller Data Pin Utilization................................................................ 11-27
11-9 LCD Controller Control, DMA, and Status Register Locations ...................... 11-50
11-10 USB Bus States.............................................................................................11-57
11-11 Endpoint Field Addressing.............................................................................11-59
11-12 Host Device Request Summary..................................................................... 11-63
11-13 UDC Control, Data, and Status Register Locations.......................................11-78
11-14 UART Control, Data, and Status Register Locations................................... 11-102
11-15 SDLC Control, Data, and Status Register Locations................................... 11-103
11-16 UART Control, Data, and Status Register Locations................................... 11-127
11-17 HSSP Control, Data, and Status Register Locations................................... 11-127
11-18 Serial Port 3 Control, Data, and Status Register Locations......................... 11-145
11-19 MCP Control, Data, and Status Register Locations..................................... 11-183
11-20 SSP Control, Data, and Status Register Locations ..................................... 11-183
11-21 PPC Control and Flag Register Locations................................................... 11-193
12-1 SA-1100 DC Maximum Ratings....................................................................... 12-1
12-2 SA-1100 DC Operating Conditions.................................................................. 12-2
12-3 SA-1100 Power Supply Voltages and Currents with TQFP Package.............. 12-3
13-1 SA-1100 Output Derating ................................................................................ 13-1
13-2 SA-1100 AC Timing Table for AA and BA Parts.............................................. 13-4
14-1 SA-1100 Pinout – 208-Pin Quad Flat Pack ..................................................... 14-2
14-2 SA-1100 Pinout – 256-Pin Mini-Ball Grid Array............................................... 14-4
16-1 SA-1100 Boundary-Scan Interface Timing...................................................... 16-9
SA-1100 Developer’s Manual xix
Introduction

1.1 Intel® StrongARM® SA-1100 Microprocessor

1
The Intel® StrongARM® SA-1100 Microprocessor (SA-1100) is the second member of the StrongARM
®
family. It is a highly integrated communications microcontroller that incorporates a 32-bit StrongARM channels, an LCD controller, a PCMCIA controller, and general-purpose I/O ports.
®
As does the Intel
StrongARM® SA-110 Microprocessor (SA-110), the first member of the StrongARM family, the SA-1100 provides power efficiency, low cost, and high performance.
Figure 1-1 shows the features of the SA-1 100. The shaded boxes are featur es that hav e carried ov er
with few or no changes from the SA-1 10 . The nonshaded boxes are new or upda te d featu res for t he SA-1100.
Figure 1-1. SA-1100 Features
Read Buffer
®
RISC processor core, system support logic, multiple communication
16KB
Instruction
Cache
8KB
Data Cache
512-byte
MiniDcache
General-Purpose
I/O
Serial
Controllers
IMMU
DMMU
Write
Buffer
Memory/
Controller
JTAG
®
Intel
StrongARM
CPU
Interrupt
Controller
DMA
Controller
®
*
LCD
Controller
* StrongARM is a registered trademark of ARM Limited.
SA-1100 SA-1100 Developer’s Manual 1-1
Interval
Timer
Real-Time
Clock
A6830-01
Introduction
Table 1-1. Features of the SA-1100 CPU for AA and EA Parts
• High Performance
— 150 Dhrystone 2.1 MIPS @ 133 MHz — 220 Dhrystone 2.1 MIPS @ 190 MHz
• Low power (normal mode)†
— <230 mW @1.5 V/133 MHz — <330 mW @ 1.5 V/200 MHz
• Integrated clock generation
— Internal phase-locked loop (PLL) — 3.686 MHz oscillator — 32.768 kHz oscillator
• Power-management features
— Normal (full-on) mode — Idle (power-down) mode — Sleep (power-down) mode
• Big and little endian operating modes
† Power dissipation, particularly in idle mode, is strongly dependent on the details of the system design. †† Package nomenclature has been modified due to industry standardization of packages. LQFP is 1.4mm
thick, thin quad flat pack. Please note that no modification has been made to the package itself.
• 3.3 V I/O interface
• 208-pin thin quad flat pack (LQFP)††
• 256 mini-ball grid array (mBGA)
• 32-way set-associative caches
— 16 Kbyte instruction cache — 8 Kbyte write-back data cache
• 32-entry memory-management units
— Maps 4 Kbyte, 8 Kbyte, or 1 M byte
• Write buffer
— 8-entry, between 1 and 16 bytes each
• Read buffer
— 4-entry, 1, 4, or 8 words
• Memory bus
— Interfaces to ROM, Flash, SRAM,
and DRAM
— Supports two PCMCIA sockets
Table 1-2. Features of the SA-1100 CPU for CA and DA Parts
• High Performance
— 180 Dhrystone 2.1 MIP S @ 16 0 MHZ — 250 Dhrystone 2.1 MIPS @ 220 MHz
• Low power (normal mode)†
— <430 mW @ 2.0-V/160-MHz — <550 mW @ 2.0-V/220-MHz
• Integrated clock generation
— Internal phase-locked loop (PLL) — 3.686-MHz oscillator — 32.768-kHz oscillator
• Big and little endian operating modes
• 3.3-V I/O interface
• 256 mini-ball grid array (mBGA)
• 32-way set-associative caches
— 16 Kbyte instruction cache — 8 Kbyte write-back data cache
• 32-entry memory-management units
— Maps 4 Kbyte, 8 Kbyte, or 1 M byte
• Write buffer
— 8-entry, between 1 and 16 bytes each
• Read buffer
— 4-entry, 1, 4, or 8 words
• Memory bus
— Interfaces to ROM, Flash, SRAM,
• 208-pin thin quad flat pack (LQFP)††
— Supports two PCMCIA sockets
† Power dissipation, particularly in idle mode, is strongly dependent on the details of the system design. †† Package nomenclature has been modified due to industry standardization of packages. LQFP is 1.4mm
thick, thin quad flat pack. Please note that no modification has been made to the package itself.
and DRAM
1-2 SA-1100 Developer’s Manual
Table 1-3. Changes to the SA-1100 Core from the SA-110
Introduction
• Data cache reduced from 16 Kbyte to
8 Kbyte
• Hardware breakpoints
• Memory-management unit (MMU)
• Interrupt vector address adjust capability
• Read buffer (nonblocking )
• Process ID mapping
• Minicache for alternate data caching
Table 1-4. Additional Features Built into SA-1100 Chipset
• Memory controller supporting R OM,
Flash, EDO, standard DRAM, and SRAM
• LCD controller
— 1-, 2-, or 4-bit gray-scale levels — 8-, 12-, or 16-bit color levels
• Twenty-eight general-purpose I/O ports
• Real-time clock with interrupt capability
• On-chip oscillators for clock sources
• Interrupt control ler
• Power-management features
• Serial communications module supportin g
SDLC
• 230-Kbps UART
• Touch-screen, audio, telecom port
• Infrared data (IrDA) serial port
— 115 Kbps, 4 Mbps
• Six-channel DMA controller
• Four general-purpos e int erruptible timers
• 12-Mbps USB device controller
• Synchronous serial port (UCB1100,
• Integrated two-slot PCMCIA controller
enhancements
— Normal (full-on) mode — Idle (power-down) mode — Sleep (power-down) mode
UCB1200, SPI, TI, Wire)
SA-1100 Developer’s Manual 1-3
Introduction

1.2 Overview

The SA-1100 Microprocessor (SA-1100) is a general-purpose, 32-bit RISC microprocessor with a 16 Kbyte instruction cache, an 8 Kbyte write-back data cache, a minicache, a write buffer, a read buffer, and a memory management unit (MMU) combined in a sing le chip. The SA-1100 is software compatible with the ARM support chips such as I/O, memory, and video. The core of the SA-1100 is derived from the core of the SA-110 Microprocessor (SA-110), with the following changes:
• Reduction in size of the data cache from 16 Kbyte to 8 Kbyte
• Addition of a 512-byte mini data cache that allocates data based on MMU settings
• Addition of debug support in the form of address and data breakpoints
• Addition of a four-entry read buffer to facilitate software-controlled data prefetching
• Addition of vector address adjust capability
• Addition of a process ID register
The logic outside the core and caches is grouped into the following three modules:
• Memory and PCMCIA control module (MPCM)
— Memory interface supporting ROM, Flash, DRAM, SRAM and PCMCIA control signals
™
V4 architecture processor family and can be used with ARM
• System control module (SCM)
— Twenty-eight general-purpose interruptible I/O ports — Real-time clock, watchdog, and interval timers — Power management controller — Interrupt controller — Reset controller — Two on-chip oscillators for connection to 3.686 MHz and 32.768 kHz crystals
• Peripheral control module (PCM)
— Six-channel DMA controller — Gray/color, active/passive LCD controller — 230 Kbps SDLC controller — 16550-compatible UART — IrDA serial port (115 Kbps, 4 Mbps) — Synchronous serial port (UCB1100, UCB1200, SPI, TI, µWire) — Universal serial bus (USB) device controller
1-4 SA-1100 Developer’s Manual
Introduction
The instruction set comprises eight basic instruction types:
• Two make use of on-chip arithmetic logic unit, barrel shifter, and multiplier to perform
high-speed operations on data in a bank of 16 logical registers (31 physical registers), each 32 bits wide.
• Three classes of instructions control data transfer between memory and the registers: one
optimized for flexibility of addressing, one for rapid context switching, and one for swapping data.
• Two instructions control the flow and privilege level of execution.
• One class is used to access the privileged state of the CPU.
The ARM instruction set is a good target for compilers of many different high-level languages. Where required for critical code segments, assembly code programming is also straightforward, unlike some RISC processors that need sophisticated compiler technology to manage complicated instruction interdependencies.
The SA-1100 is a static part and has been desi gned t o ru n at a reduced v olt age to mi nimize i ts power requirements. This makes it a good choice for portable applications where both of t hese features are essential.

1.3 Example System

Figure 1-2 shows how the SA-1100 can be used in a hand-held computing device.
Figure 1-2. SA-1100 Example System
Gray Scale
or
Color LCD
Display
3.686 MHz
32.768 KHz
Glue Logic
PCMCIA Interface
(Flash, Modem)
Intel® StrongARM
SA-1100
Portable
Communications
Microcontroller
®*
UART or LocalTalk
Communications
Tablet / Serial
Keyboard
Codec
Infrared
Communications
USB Synchronization
Port
DRAM
ROM
Flash
* StrongARM is a registered trademark of ARM Limited.
A6870-01
SA-1100 Developer’s Manual 1-5
Introduction

1.4 ARM™ Architecture

The SA-1100 implements th e ARM V4 architecture as defined in the ARM Architectur e Reference, 28-July-1995, with the foll owing options:

1.4.1 26-Bit Mode

The SA-1100 supports 26-bit mode but all exceptions are initiated in 32-bit mode. The P and D bits do not affect the operation of SA-1100; they are always read as ones and writes to them are ignored.

1.4.2 Coprocessors

The SA-1100 supports MCR and MRC access to coprocessor number 15. These instructions are used to access the memory-management, configuration, and cache control registers. In addition, coprocessor 15 provides control for read buffer fills and flushes, and hardware breakpoints. All other coprocessor instructions cause an undefined instruction exception. No support for external coprocessors is provide d.

1.4.3 Memory Management

Memory management exceptions preserve the base address registers so that no code is required to restore state. Separate translation lookaside buffers (TLBs) are implemented for the instruction and data streams. Each TLB has 32 entries that can each map a segment, a large page, or a small page. The TLB replacement algorithm is round robin. Th e data TLBs support both the flush-all and flush-single-entry operations, while the instruction TLBs support only the flush-all operation.

1.4.4 Instruction Cache

The SA-1100 has a 16 Kbyte instruction cache (Icache) with 32-byte blocks and 32-way associativity. The cache supports the flush-all function. Replacement is round robin within a set. The Icache can be enabled while memory management is disabled. When memory management is disabled, all memory is considered cacheable by the Icache.

1.4.5 Data Cache

The SA-1100 has an 8 Kbyte data cache (Dcache) with 32-byte blocks and 32-way associativity. The cache supports the flush-all, flush-entry, and copyback-entry functions. The copyback-all function is not supported in hardware. This function can be provided by software. The cache is read allocate with round-robin replacement.
The Dcache has been augmented with a 16-entry, two-way set associative minicache that allocates when the MMU b and c bits are 0 and 1, respectively. This cache is accessed in parallel with the main Dcache. Replacement victims in this cache are replaced based on a least-recently-used (LRU) algorithm. This cache is useful for applications that access large data structures and would normally thrash the main Dcache. Instead, these data structur es can be mapp ed so that they allocate into the minicache and only replace data from the same structure.
1-6 SA-1100 Developer’s Manual

1.4.6 Write Buffer

The SA-1100 has an eight-entry write buffer with each entry able to contain 1 to 16 bytes. A drain write buffer operation is supported.

1.4.7 Read Buffer

The SA-110 0 has a four-entry read buffer capable of loadin g 1, 4, or 8 word s of d ata per entr y. This facility permits software to preload data into the buffer for use at a later time without block ing the operation of the processor. Software can flush either a single entry or the entire buffer (four entries). The read buffer is controlled through system control coprocessor 15 and can be enabled for use in user mode.
Introduction
SA-1100 Developer’s Manual 1-7
Functional Description
This chapter provides a functional description of the Intel® StrongARM® SA-1100 Micropro cessor (SA-1100). It describes the basic building blocks within the processor, lists and describes the pins, and explains the memory map.

2.1 Block Diagram

The SA-1100 consists of the following functional blocks:
• Processor
The processor is the ARM™ (Dcache). The instruction (I) and data (D) streams are translated through independent memory-management units (MMUs). Stores are made using a four-line write buffer. The performance of specialized load routines is enhanced with the four-entry read buffer that can be used to prefetch data for use at a later time. A 16-entry minicache provides a smaller and logically separate data cache that can be used to enhance caching performance when dealing with large data structures.
• Memory and PCMCIA controller
The memory and PCMCIA control module (MPCM) supports four banks of standard or EDO DRAM on a 32-bit data width. ROM (standard and burst), Flash memory, and SRAM are also supported. ROM and Flash can be either 16 or 32 bits wide. SRAM width is limited to 32 bits. Expansion devices are supported through PCMCIA control signals that share the memory bus data and address lines to complete the card i nter f ace. So me ex ter nal g l ue lo gic ( bu ffers and transceivers) is necessary to implement the interface. Control is provided to permit two card slots with hot-swap capability.
• Peripherals
SA-1 core with a 16 Kbyte instruction and 8 Kbyte data cache
2
The peripheral control module (PCM) contains a number of serial control devices, an LCD controller as well as a six-channel DMA controller to provide service to these devices:
– An LCD controller with support for passive or active displays – A universal serial bus (USB) endpoint controller – An SDLC communications controller – A serial controller with supporting 115 Kbps and 4 Mbps IrDA protocols – A 16550-like UART supporting 230 Kbps – A CODEC interface supporting SPI, µWire, TI, UCB1100, and UCB12 00
• General system control functions
The system control module (SCM) is also connected to the peripheral bus. It contains five blocks used for general system functions:
– A real-time clock (RTC) clocked from an independent 32.768 kHz oscillator – An operating system timer (OST) for general system timer functions as well as a watchdog mode – Twenty-eight general-purpose I/Os (GPIO) – An interrupt controller – A power-manag em en t co n tro ller th at handles the transitions in and out of slee p an d idle modes – A reset controller that handles the various reset sources on the processor
SA-1100 Developer’s Manual 2-1
Functional Description
Figure 2-1 shows the functional blocks contained in the SA-1100 integrated proces sor. Figure 2-2
is a functional diagram of the SA-1100.
Figure 2-1. SA-1100 Block Diagram
3.686 MHz
32.768 KHz
OSC
OSC
PLL
RTC
OS Timer
General-
Purpose I/O
Interrupt
Controller
Power
Management
Reset
Controller
IMMU
DMMU
Processing Core
System
System Bus
Control Module
(SCM)
Peripheral Control
Module (PCM)
Peripheral Bus
Instruction
Icache
(16 Kbytes)
Dcache
(8 Kbytes)
Minicache
Load/Store Data
Write
Buffer
Bridge
PC
Addr
DMA
Controller
ARM™*
SA-1 Core
Read
Buffer
LCD
Controller
®
Intel
StrongARM
SA-1100
JTAG
and Misc Test
Memory
and
PCMCIA
Control Module
(MPCM)
®
*
Serial
Channel 0
UjSB
Serial
Channel 1
SDLC
Serial
Channel 2
IrDA
Serial
Channel 3
UART
* ARM is a trademark and StrongARM is a registered trademark of ARM Limited.
Serial
Channel 4
CODEC
A6832-01
2-2 SA-1100 Developer’s Manual
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