Intel® Server Board S1200BT
Revision 2.4
May, 2013
Enterprise Platforms and Services Division
Technical Product Specification
Intel order number G13326-007
Revision History Intel® Server Board S1200BT TPS
ii
Date
Revision
Number
Modifications
July 2010
0.3
Initial release.
November 2010
0.5
Updated the hardware info and SE SKU.
January 2011
0.7
Updated S1200BTS info and BIOS setup page.
January 2011
0.9
Updated S1200BT video mode.
March 2011
1.0
Corrected typos.
September 2011
1.1
Corrected typos.
February 2012
2.0
Updated the E3-1200 v2 processors support.
Added a note in chapter 1.
June 2012
2.1
Add S1200BTLRM SKU in S1200BT family.
Add Intel® ROC module support on S1200BTLRM.
Add BIOS new feature.
February 2013
2.2
Updated Disclaimers.
SAS Mezzanine connectors.
March 2013
2.3
Updated section 3.8 title and section 3.8.1
May 2013
2.4
Updated MTBF value
Revision History
Intel order number G13326-007 Revision 2.4
Intel® Server Board S1200BT TPS Disclaimers
iii
Disclaimers
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE,
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INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
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THE INTEL PRODUCT OR ANY OF ITS PARTS.
Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not
rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves
these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them. The information here is subject to change without notice. Do not finalize a design with this
information.
The products described in this document may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your
product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may
be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.
Revision 2.4 Intel order number G13326-007
Table of Contents Intel® Server Board S1200BT TPS
iv
Table of Contents
1. Introduction ........................................................................................................................ 1
1.1 Chapter Outline ...................................................................................................... 1
1.2 Server Board Use Disclaimer ................................................................................. 2
2. Overview ................................ ................................................................ ............................. 3
2.1 Intel® Server Board S1200BT Feature Set.............................................................. 3
2.2 Server Board Layout .............................................................................................. 6
2.2.1 Server Board Connector and Component Layout ................................................... 7
2.2.2 Intel® Server Board S1200BTL/S1200BTLRM Mechanical Drawings ................... 10
2.2.3 Server Board Rear I/O Layout .............................................................................. 14
3. Functional Architecture ................................................................................................... 15
3.1 Processor Sub-System ......................................................................................... 16
3.1.1 Intel® Xeon® Processor E3-1200 Processors and Intel® Xeon® E3-1200 V2
Processors ......................................................................................................................... 17
3.1.2 The 2nd Generation Intel® Core™ i3 Processors and the 3rd Generation Intel®
Core™ i3 Processors ......................................................................................................... 17
3.1.3 Intel® Turbo Boost Technology ............................................................................. 17
3.2 Memory Subsystem.............................................................................................. 18
3.2.1 Memory Supported ............................................................................................... 18
3.2.2 Post Error Codes .................................................................................................. 19
3.2.3 Memory Map and Population Rules ...................................................................... 20
3.2.4 Publishing System Memory .................................................................................. 22
3.2.5 Memory RAS Support .......................................................................................... 22
3.3 Intel® Chipset PCH ............................................................................................... 23
3.4 I/O Sub-system .................................................................................................... 23
3.4.1 Digital Media Interface (DMI) ................................................................................ 23
3.4.2 PCI Express* Interface ......................................................................................... 23
3.4.3 Serial ATA Support .............................................................................................. 24
3.4.4 Low Pin Count (LPC) Interface ............................................................................. 25
3.4.5 USB 2.0 Support .................................................................................................. 25
3.5 Optional Intel® SAS RAID Module ........................................................................ 26
3.6 Optional Intel® ROC Module ................................................................................. 26
3.7 Integrated Baseboard Management Controller ..................................................... 26
3.7.1 Integrated BMC LAN Channels ............................................................................ 28
3.7.2 Optional RMM4 Advanced Management Board .................................................... 29
3.7.3 Serial Ports .......................................................................................................... 29
3.7.4 Floppy Disk Controller .......................................................................................... 29
3.7.5 Keyboard and Mouse Support .............................................................................. 30
3.7.6 Wake-up Control .................................................................................................. 30
3.8 Graphic Support ................................................................................................... 30
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Intel® Server Board S1200BT TPS Table of Contents
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3.8.1 Intel® Server Board S1200BTL/S1200BTLRM ...................................................... 30
3.8.2 Video for Intel® Server Board S1200BTS ............................................................. 31
3.9 Network Interface Controller (NIC) ....................................................................... 31
3.9.1 Gigabit Ethernet Controller 82574L ...................................................................... 31
3.9.2 Gigabit Ethernet PHY 82579 ................................................................................ 31
3.9.3 MAC Address Definition ....................................................................................... 32
3.10 Intel® I/O Acceleration Technolgy 2 (Intel® I/OAT2) .............................................. 32
3.10.1 Direct Cache Access (DCA) ................................................................................. 32
3.11 Intel® Virtualization Technology for Directed I/O (Intel® VT-d) ............................... 32
3.12 TPM (Trusted Platform Module) ........................................................................... 32
4. Platform Management ...................................................................................................... 34
4.1 Feature Support ................................................................................................... 35
4.1.1 IPMI 2.0 Features ................................................................................................. 35
4.1.2 Non-IPMI Features ............................................................................................... 35
4.1.3 New Manageability Features ................................................................................ 36
4.2 Basic and Optional Advanced Management Features .......................................... 37
4.2.1 Enabling Advanced Management Features .......................................................... 38
4.2.2 Keyboard, Video, and Mouse (KVM) Redirection ................................................. 38
4.2.3 Media Redirection ................................................................................................ 40
4.2.4 Embedded Web server ......................................................................................... 41
4.2.5 Embedded Platform Debug .................................................................................. 42
4.2.6 Data Center Management Interface (DCMI) ......................................................... 43
4.2.7 Local Directory Authentication Protocol (LDAP) ................................................... 43
4.3 Thermal Control ................................................................................................... 43
4.3.1 Memory Thermal Throttling .................................................................................. 43
4.3.2 Fan Speed Control ............................................................................................... 44
4.4 Intel® Intelligent Power Node Manager ................................................................. 44
4.4.1 Overview .............................................................................................................. 44
4.4.2 Features ............................................................................................................... 45
4.4.3 Role of Integrated BMC in NM .............................................................................. 46
5. Server Management Capability for Intel® Server Board S1200BTS ............................... 47
5.1 Supper I/O ............................................................................................................ 47
5.1.1 Key Features of supper I/O .................................................................................. 47
6. BIOS User Interface .......................................................................................................... 48
6.1 BIOS POST Initialization ...................................................................................... 48
6.1.1 BIOS Revision Identification ................................................................................. 48
6.2 HotKeys Supported During POST ........................................................................ 49
6.3 POST Logo Screen/Diagnostic Screen................................................................. 50
6.4 BIOS Boot Pop-up Menu ...................................................................................... 50
6.5 BIOS Setup Utility ................................................................................................ 51
6.5.1 BIOS Setup Operation .......................................................................................... 51
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Table of Contents Intel® Server Board S1200BT TPS
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6.5.2 BIOS Setup Utility Screens................................................................................... 54
7. Connector/Header Locations and Pin-outs .................................................................... 95
7.1 Board Connector Information ............................................................................... 95
7.2 Power Connectors ................................................................................................ 96
7.3 System Management Headers ............................................................................. 97
7.3.1 Intel® Remote Management Module 4 (Intel® RMM4) Lite connetor and Dedicated
NIC connector .................................................................................................................... 97
7.3.2 LPC/IPMB Header ................................................................................................ 98
7.3.3 HSBP Header....................................................................................................... 98
7.3.4 SGPIO Header ..................................................................................................... 98
7.4 Front Control Panel Connector ............................................................................. 98
7.4.1 Power Button........................................................................................................ 99
7.4.2 Reset Button ........................................................................................................ 99
7.4.3 System Status Indicator LED .............................................................................. 100
7.5 I/O Connectors ................................................................................................... 101
7.5.1 VGA Connector .................................................................................................. 101
7.5.2 Rear NIC and USB connector ............................................................................ 101
7.5.3 SATA ................................................................................................................. 102
7.5.4 SAS Mezzanine Connectors ............................................................................... 102
7.5.5 Serial Port Connectors ....................................................................................... 103
7.5.6 USB Connector .................................................................................................. 103
7.6 PCI Express* Slot/PCI Slot/Riser Card Slot ........................................................ 104
7.7 Fan Headers ...................................................................................................... 108
8. Jumper Blocks ................................................................................................................ 109
8.1 CMOS Clear and Password Reset Usage Procedure ......................................... 111
8.1.1 Clearing the CMOS ............................................................................................ 111
8.1.2 Clearing the Password ....................................................................................... 111
8.2 Integrated BMC Force Update Procedure (for The Intel® Server Board
S1200BTL/S1200BTLRM) ................................................................................................... 112
8.3 ME Force Update Jumper .................................................................................. 112
8.4 BIOS Recovery Jumper ...................................................................................... 113
9. Intel® Light Guided Diagnostics .................................................................................... 114
9.1 System Status LED (For S1200BTL/S1200BTLRM) ........................................... 114
9.2 Post Code Diagnostic LEDs ............................................................................... 114
10. Design and Environmental Specifications .................................................................... 116
10.1 Intel® Server Board S1200BT/S1200BTLRM Design Specifications ................... 116
10.2 Board-level Calculated MTBF ............................................................................. 116
10.2.1 Processor Power Support................................................................................... 117
10.3 Power Supply Output Requirements ................................ .................................. 117
10.3.1 Grounding .......................................................................................................... 118
10.3.2 Standby Outputs ................................................................................................ 118
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Intel® Server Board S1200BT TPS Table of Contents
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10.3.3 Remote Sense ................................................................................................... 118
10.3.4 Voltage Regulation ............................................................................................. 118
10.3.5 Dynamic Loading ............................................................................................... 118
10.3.6 Capacitive Loading ............................................................................................. 119
10.3.7 Closed-loop Stability........................................................................................... 119
10.3.8 Common Mode Noise ......................................................................................... 119
10.3.9 Ripple/Noise ....................................................................................................... 119
10.3.10 Timing Requirements ......................................................................................... 119
10.3.11 Residual Voltage Immunity in Standby Mode ..................................................... 121
10.3.12 Protection Circuits ................................ .............................................................. 122
Appendix A: Integration and Usage Tips ............................................................................ 123
Appendix B: Integrated BMC Sensor Tables ....................................................................... 124
Appendix C: POST Code Diagnostic LED Decoder ............................................................ 134
Appendix D: POST Code Errors ........................................................................................... 138
Appendix E: Supported Intel® Server Chassis .................................................................... 141
Glossary ................................................................................................................................ 142
Reference Documents .......................................................................................................... 146
Revision 2.4 Intel order number G13326-007
List of Figures Intel® Server Board S1200BT TPS
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List of Figures
Figure 1. Intel® Server Board S1200BTL/S1200BTLRM .............................................................. 6
Figure 2. Intel® Server Board S1200BTS .................................................................................... 7
Figure 3. Intel® Server Board S1200BTL/S1200BTLRM Layout .................................................. 8
Figure 4. Intel® Server Board S1200BTS Layout ......................................................................... 9
Figure 5. Intel® Server Board S1200BTL/S1200BTLRM – Hole and Component Positions ....... 10
Figure 6. Intel® Server Board S1200BTL/S1200BTLRM – Major Connector Pin Location (1 of 2)11
Figure 7. Intel® Server Board S1200BTL/S1200BTLRM – Major Connector Pin Location (2 of 2)12
Figure 8. Intel® Server Board S1200BTL/S1200BTLRM – Primary Side Keepout Zone ............ 13
Figure 9. Intel® Server Board S1200BTL/S1200BTLRM – Secondary Side Keepout Zone ........ 13
Figure 10. Intel® Server Board S1200BT Rear I/O Layout ......................................................... 14
Figure 11. Intel® Server Board S1200BTL/S1200BTLRM Functional Block Diagram ................. 15
Figure 12. Intel® Server Board S1200BTS Functional Block Diagram ....................................... 16
Figure 13. Integrated BMC Hardware ........................................................................................ 27
Figure 14. Server Management Bus (SMBUS*) Block Diagram ................................................ 34
Figure 15. Main Screen ............................................................................................................. 57
Figure 16. Advanced Screen ..................................................................................................... 60
Figure 17. Processor Configuration Screen (S1200BT) ............................................................. 62
Figure 18. Memory Configuration Screen .................................................................................. 69
Figure 19. Mass Storage Controller Configuration Screen ........................................................ 71
Figure 20. Serial Port Configuration Screen .............................................................................. 74
Figure 21. USB Configuration Screen ....................................................................................... 74
Figure 22. PCI Configuration Screen ......................................................................................... 75
Figure 23. System Acoustic and Performance Configuration ..................................................... 76
Figure 24. Security Screen ........................................................................................................ 78
Figure 25. Server Management Screen (S1200BTL/S1200BTLRM) ......................................... 81
Figure 26. Server Management Screen (S1200BTS) ................................................................ 82
Figure 27. Console Redirection Screen ..................................................................................... 82
Figure 28. System Information Screen (S1200BTL/S1200BTLRM) ........................................... 83
Figure 29.System Information Screen (S1200BTS) ................................................................... 84
Figure 30. BMC LAN Configuration Screen (S1200BTL/S1200BTLRM) .................................... 85
Figure 31. Hardware Monitor Screen, Auto Fan Control (S1200BTS) ....................................... 86
Figure 32. Hardware Monitor Screen, Manual Fan Control (S1200BTS) ................................... 86
Figure 33. Real-time Teperature and Voltage Status Screen (S1200BTS) ................................ 87
Figure 34. Boot Options Screen ................................................................................................ 88
Figure 35. Hard Disk Order Screen ........................................................................................... 89
Figure 36. CDROM Order Screen ............................................................................................. 89
Figure 37. Floppy Order Screen ................................................................................................ 90
Figure 38. Network Device Order Screen .................................................................................. 90
Figure 39. BEV Device Order Screen ........................................................................................ 91
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Intel® Server Board S1200BT TPS List of Figures
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Figure 40. Add EFI Boot Option Screen .................................................................................... 91
Figure 41. Delete EFI Boot Option Screen ................................................................................ 92
Figure 42. Boot Manager Screen .............................................................................................. 92
Figure 43. Error Manager Screen .............................................................................................. 93
Figure 44. System Event Log Screen (S1200BTS) ................................................................... 93
Figure 45. Exit Screen ............................................................................................................... 94
Figure 46. Jumper Blocks (J4A2, J1F1, J1F3, J1F2, and J1E2) on S1200BTL/S1200BTLRM 109
Figure 47. Jumper Blocks (J2G1, J1G1, J1H3, and J2J1) on S1200BTS ................................ 110
Figure 48. POST Code Diagnostic LED Location .................................................................... 115
Figure 49. Output Voltage Timing ........................................................................................... 120
Figure 50. Turn On/Off Timing (Power Supply Signals) ........................................................... 121
Revision 2.4 Intel order number G13326-007
List of Tables Intel® Server Board S1200BT TPS
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List of Tables
Table 1. Intel® Server Board S1200BT Feature Set ..................................................................... 3
Table 2. Major Board Components.............................................................................................. 8
Table 3. Major Board Components.............................................................................................. 9
Table 4. Memory Configuration Table ....................................................................................... 21
Table 5. UDIMM memory configuration rule for Intel® Xeon® E3-1200 Processors or the 2nd
Generation Intel® Core™ i3 Processors .............................................................................. 21
Table 6. UDIMM memory configuration rule for Intel® Xeon® E3-1200 V2 Processors or the 3rd
Generation Intel® Core™ i3 Processors .............................................................................. 22
Table 7. UDIMM Maximum configuration .................................................................................. 22
Table 8. Optional RMM4 Advanced Management Board Features ............................................ 29
Table 9. Serial B Header (J1B2 on S1200BTL/S1200BTLRM or J8A1 on S1200BTS) Pin-out .. 29
Table 10. Video Modes ............................................................................................................. 30
Table 11. Dual Video Modes ..................................................................................................... 31
Table 12. Basic and Advanced Management Features ............................................................. 37
Table 13. NM Features ............................................................................................................. 45
Table 14. POST HotKeys Recognized ...................................................................................... 49
Table 15. BIOS Setup Page Layout .......................................................................................... 52
Table 16. BIOS Setup: Keyboard Command Bar ...................................................................... 52
Table 17. Screen Map ............................................................................................................... 55
Table 18. Board Connector Matrix on S1200BTL/S1200BTLRM ............................................... 95
Table 19. Board Connector Matrix on S1200BTS ...................................................................... 96
Table 20. Baseboard Power Connector Pin-out (J9G1) ............................................................. 96
Table 21. SSI Processor 8-PIN Power Connector Pin-out (J9A1) ............................................. 97
Table 22. Intel® RMM4 lite Connector Pin-out (J4B1) ................................................................ 97
Table 23. Dedicated NIC connector for RMM4 .......................................................................... 97
Table 24. LPC/IPMB Header Pin-out (J1H5) ............................................................................. 98
Table 25. HSBP Header Pin-out (J1J2) ..................................................................................... 98
Table 26. SGPIO Header Pin-out (J1J3 on S1200BTL/S1200BTLRM and J2J2 on S1200BTS)98
Table 27. Front Panel SSI Standard 24-pin Connector Pin-out (J1C1 on
S1200BTL/S1200BTLRM or J1C2 on S1200BTS) .............................................................. 98
Table 28. System Status LED Indicator States ................................................................ ........ 100
Table 29. VGA Connector Pin-out ........................................................................................... 101
Table 30. RJ-45 10/100/1000 NIC Connector Pin-out ............................................................. 101
Table 31. RJ-45 10/100/1000 NIC Connector Pin-out (J6A1) .................................................. 101
Table 32. 6Gb/s SATA Connector Pin-Out .............................................................................. 102
Table 33. 3Gb/s SATA Connector Pin-out ............................................................................... 102
Table 34. SAS Connector Pin-out (J2H1) ................................................................................ 102
Table 35. External Serial A Port Pin-out (J8A1)....................................................................... 103
Table 36. Internal 9-pin Serial B Header Pin-out (J1B2) .......................................................... 103
Intel order number G13326-007 Revision 2.4
Intel® Server Board S1200BT TPS List of Tables
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Table 37. Internal USB Connector Pin-out ( J1E1 and J1D1) .................................................. 104
Table 38. Pin-out of Internal USB Connector for low-profile Smart module (J3F2) .................. 104
Table 39. Pin-out of adaptive riser slot/PCI Express slot 6 ...................................................... 104
Table 40. Three PCI Express* x8 connectors (J2B2, J3B1, and J4B2) ................................... 106
Table 41. One PCI X32 connector (J1B1) ............................................................................... 107
Table 42. SSI 4-pin Fan Header Pin-out ................................................................................. 108
Table 43. Server Board Jumpers (J1F1, J1F2, J1F3, J1E2, and J4A2) on
S1200BTL/S1200BTLRM ................................................................................................. 109
Table 44. Server Board Jumpers (J2G1, J1G1, J1H3, and J2J1) on S1200BTS ..................... 110
Table 45. Front Panel LED Behavior Summary ....................................................................... 114
Table 46. Server Board Design Specifications ........................................................................ 116
Table 47. Intel® Xeon® Processor TDP Guidelines .................................................................. 117
Table 48. 350-W Load Ratings ................................................................................................ 117
Table 49. Voltage Regulation Limits ........................................................................................ 118
Table 50. Transient Load Requirements ................................................................................. 118
Table 51. Capacitve Loading Conditions ................................ ................................................. 119
Table 52. Ripple and Noise ..................................................................................................... 119
Table 53. Output Voltage Timing ............................................................................................. 120
Table 54. Turn On/Off Timing .................................................................................................. 120
Table 55. Over-Current Protection (OCP) ............................................................................... 122
Table 56. Over-voltage Protection (OVP) Limits ...................................................................... 122
Table 57. BMC Core Sensors ................................................................ ................................. 126
Table 58. POST Progress Code LED Example ....................................................................... 134
Table 59. POST Progress Codes ............................................................................................ 134
Table 60. POST Error Codes and Messages .......................................................................... 138
Table 61. POST Error Beep Codes ......................................................................................... 140
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List of Tables Intel® Server Board S1200BT TPS
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Intel order number G13326-007 Revision 2.4
Intel® Server Board S1200BT TPS Introduction
1
1. Introduction
This Technical Product Specification (TPS) provides board specific information detailing the
features, functionality, and high-level architecture of the Intel® Server Board S1200BT.
In addition, you can obtain design-level information for specific subsystems by ordering the
External Product Specifications (EPS) or External Design Specifications (EDS) for a given
subsystem. EPS and EDS documents are not publicly available and must be ordered through
your local Intel® representative.
Note: The product codes of S1200BTL and S1200BTS can only support Intel® Xeon® E3-1200
Processors or the 2nd Generation Intel® Core™ i3 Processors. The product codes of
S1200BTLR, S1200BTSR, and S1200BTLRM can support Intel® Xeon® E3-1200Processors,
the 2nd Generation Intel® Core™ i3 Processors, Intel® Xeon® E3-1200 V2 processors or the 3rd
Generation Intel® Core™ i3.
1.1 Chapter Outline
This document is divided into the following chapters:
Chapter 1 – Introduction
Chapter 2 – Server Board Overview
Chapter 3 – Functional Architecture
Chapter 4 – Platform Management
Chapter 5 – Server Management Capability for Intel
Chapter 6 – BIOS User Interface
Chapter 7 – Connector/Header Locations and Pin-outs
Chapter 8 – Jumpers Blocks
Chapter 9 – Intel
Chapter 10 – Design and Environmental Specifications
Appendix A – Integration and Usage Tips
Appendix B – Integrated BMC Sensor Tables
Appendix C – POST Code Diagnostic LED Decoder
Appendix D – POST Code Errors
Appendix E – Supported Intel
Glossary
Reference Documents
®
Light-Guided Diagnostics
®
Server Chassis
®
Server Board S1200BTS
Revision 2.4 Intel order number G13326-007
Introduction Intel® Server Board S1200BT TPS
2
1.2 Server Board Use Disclaimer
Intel Corporation server boards contain a number of high-density Very Large Scale Integration
(VLSI) and power delivery components that need adequate airflow to cool. Intel® ensures
through its own chassis development and testing that when Intel® server building blocks are
used together, the fully integrated system meets the intended thermal requirements of these
components. It is the responsibility of the system integrator who chooses not to use Intel®
developed server building blocks to consult vendor datasheets and operating parameters to
determine the amount of airflow required for their specific application and environmental
conditions. Intel Corporation cannot be held responsible if components fail or the server board
does not operate correctly when used outside any of their published operating or non-operating
limits.
Intel order number G13326-007 Revision 2.4
Intel® Server Board S1200BT TPS Overview
3
Feature
Description of S1200BTL/S1200BTLRM
Description of S1200BTS
Processor
Supports for one Intel® Xeon® E3-1200
Processors or the 2nd Generation Intel® Core™
i3 Processors in FC-LGA 1155 socket package
5 GT/s point-to-point DMI interface to PCH
LGA 1155 pin socket
Supports for Intel® Xeon® E3-1200 V2
processors or the 3rd Generation Intel® Core™
i3 processors in FC-LGA 1155 socket package
5 GT/s point-to-point DMI interface to PCH
LGA 1155 pin socket
Supports for one Intel® Xeon® E3-1200
Processors or the 2nd Generation Intel®
Core™ i3 Processors in FC-LGA 1155 socket
package
5 GT/s point-to-point DMI interface to PCH
LGA 1155 pin socket
Supports for Intel® Xeon® E3-1200 V2
processors or the 3rd Generation Intel® Core™
i3 processors in FC-LGA 1155 socket
package
5 GT/s point-to-point DMI interface to PCH
LGA 1155 pin socket
Memory
Two memory channels with support for
1066/1333 MHz (with Intel® Xeon® E3-1200
Processors or the 2nd Generation Intel® Core™
i3 Processors) or 1333/1600 MHz (with Intel®
Xeon® E3-1200 V2 Processors or the 3rd
Generation Intel® Core™ i3 Processors) ECC
Unbuffered (UDIMM) DDR3
Up to two UDIMMs per channel
32 GB max with x8 ECC UDIMM (2-Gb
DRAM)
64-bit wide channels
DDR3 I/O Voltage of 1.5 V
Two memory channels with support for
1066/1333 MHz (with Intel® Xeon® E3-1200
Processors or the 2nd Generation Intel®
Core™ i3 Processors) or 1333/1600 MHz
(with Intel® Xeon® E3-1200 V2 Processors or
the 3rd Generation Intel® Core™ i3
Processors) ECC Unbuffered (UDIMM) DDR3
Up to two UDIMMs per channel
32 GB max with x8 ECC UDIMM (2-Gb
DRAM)
64-bit wide channels
DDR3 I/O Voltage of 1.5 V
Chipset
Support for Intel® C204 Platform Controller Hub
(PCH) chipset
ServerEngines* LLC Pilot III BMC controller
(Integrated BMC)
Support for Intel® C202 Platform Controller
Hub (PCH) chipset
2. Overview
The Intel® Server Board S1200BT is a monolithic Printed Circuit Board (PCB) with features
designed to support entry-level severs. It has three board SKUs, namely S1200BTL,
S1200BTLRM, and S1200BTS.
2.1 Intel
®
Server Board S1200BT Feature Set
Table 1. Intel® Server Board S1200BT Feature Set
Revision 2.4 Intel order number G13326-007
Overview Intel® Server Board S1200BT TPS
4
Feature
Description of S1200BTL/S1200BTLRM
Description of S1200BTS
I/O
External connections:
DB-15 video connectors
DB-9 serial Port A connector
Four ports on two USB/LAN combo
connectors at rear of board
Internal connections:
Two USB 2x5 pin headers, each supporting
two USB 2.0 ports
One 2x5 Serial Port B headers
Two 6Gb/s SATA ports and four 3Gb/s
SATA ports
One SAS mezzanine slot for optional SAS
module
External connections:
DB-15 video connectors
DB-9 serial Port A connector
Four ports on two USB/LAN combo
connectors at rear of board
Internal connections:
Two USB 2x5 pin headers, each supporting
two USB 2.0 ports
Six 3Gb/s SATA ports
Add-in PCI Card,
PCI Express* Card
With Intel® Xeon® E3-1200 processors or the
2nd Generation Intel® Core™ i3 Processors:
Slot1: One 5V PCI 32 bit/33 MHz connector
Slot3: One PCI Express* Gen2 x8 (x4
throughput) connector
Slot4: One PCI Express* Gen2 x8 (x4
throughput) connector
Slot5: One PCI Express* Gen2 x8 (x4
throughput) connector
Slot6: One PCI Express* Gen2 x16 (x8
throughput) connector
With Intel® Xeon® E3-1200 V2 processors or
the 3rd Generation Intel® Core™ i3 Processors:
Slot1: One 5V PCI 32 bit/33 MHz connector
Slot3: One PCI Express* Gen2 x8 (x4
throughput) Gen2 connector
Slot4: One PCI Express* Gen3 x8 (x4
throughput) connector
Slot5: One PCI Express* Gen3 x8 (x4
throughput) connector
Slot6: One PCI Express* Gen3 x16 (x8
throughput) connector
With Intel® Xeon® E3-1200 processors or the
2nd Generation Intel® Core™ i3 Processors:
Slot4: One 5V PCI 32 bit/33 MHz connector
Slot5: One PCI Express* Gen2 x8 (x4
throughput) connector
Slot6: One PCI Express* Gen2 x8 (x8
throughput) connector
Slot7: One PCI Express* Gen2 x16 (x8
throughput) connector
With Intel® Xeon® E3-1200 V2 processors or
the 3rd Generation Intel® Core™ i3
Processors:
Slot4: One 5V PCI 32 bit/33 MHz connector
Slot5: One PCI Express* Gen2 x8 (x4
throughput) connector
Slot6: One PCI Express* Gen3 x8 (x8
throughput) connector
Slot7: One PCI Express* Gen3 x16 (x8
throughput) connector
System Fan
Support
Five 4-pin fan headers supporting four system
fans and one processor
Four 4-pin fan headers supporting four system
fans and one processor
Video
Onboard ServerEngines* LLC Pilot III BMC
Controller
External 32MB (or above) DDR3 800MHz
memory
Silicon Motion SM712GX04LF02-BA
Onboard Hard
Drive
Support for six Serial ATA II hard drives
through six onboard SATA II connectors with
SW RAID 0, 1, 5, and 10
Up to four SAS hard drives through optional
Intel® SAS Entry RAID Module card
Two 6Gb/s SATA ports and four 3Gb/s SATA
ports
Support for six Serial ATA II hard drives
through six onboard SATA II connectors with
SW RAID 0, 1, 5, and 10.
Six 3Gb/s SATA ports
Intel order number G13326-007 Revision 2.4
Intel® Server Board S1200BT TPS Overview
5
Feature
Description of S1200BTL/S1200BTLRM
Description of S1200BTS
RAID Support
Intel
®
Embedded Server RAID Technology II
through onboard SATA connectors provides
SATA RAID 0, 1, and 10 and optional RAID
5 support provided by the Intel® RAID
Activation Key AXXRAKSW5
Intel
®
Rapid Storage RAID through onboard
SATA connectors provides SATA RAID 0, 1,
5, and 10
One optional internal SAS module connector
which supports AXXRMS2AF040,
AXXRMS2LL040, and AXX4SASMOD
Optional ROC module support on all PCI –e
slots [Only for S1200BTLRM]
Intel
®
Embedded Server RAID Technology
II through onboard SATA connectors
provides SATA RAID 0, 1, and 10 and
optional RAID 5 support provided by the
Intel® RAID Activation Key AXXRAKSW5
Intel
®
Rapid Storage RAID through
onboard SATA connectors provides SATA
RAID 0, 1, 5, and 10
LAN
One Gigabit Ethernet device 82574L connect to
PCI-E x1 interfaces on the PCH
One Gigabit Ethernet PHY 82579 connected to
PCH through PCI-E x1 interface
One Gigabit Ethernet device 82574L connect
to PCI-E x1 interfaces on the PCH
One Gigabit Ethernet PHY 82579 connected
to PCH through PCI-E x1 interface
Server
Management
Onboard LLC Pilot III Controller (Integrated
BMC)
Integrated Baseboard Management
Controller (Integrated BMC), IPMI 2.0
compliant
Integrated 2D video controller on PCI-E x1
Optional Intel® Remote Management Module 4
(RMM4) Lite only or Intel® Remote
Management Module 4 (RMM4)
—
Security
TPM module connector
TPM module connector
Revision 2.4 Intel order number G13326-007
Overview Intel® Server Board S1200BT TPS
6
2.2 Server Board Layout
Figure 1. Intel® Server Board S1200BTL/S1200BTLRM
Intel order number G13326-007 Revision 2.4
Intel® Server Board S1200BT TPS Overview
7
Figure 2. Intel® Server Board S1200BTS
2.2.1 Server Board Connector and Component Layout
The following figure shows the board layout of the server board. Each connector and major
component is identified by a number or letter, and Table 2 provides the description:
Revision 2.4 Intel order number G13326-007
Overview Intel® Server Board S1200BT TPS
8
Description
Description
A
Slot 1, 32 Mbit/33 MHz PCI
R
System FAN2 and System FAN3 Connector
B
TPM
S
CPU connector
C
Slot 3/4, PCI Express* Gen2 x4 (x8 connector)
T
CPU Fan connector
D
Slot 5, PCI Express* Gen2 x4 (x8 connector)
U
USB connector for smart module
E
Slot 6, PCI Express* Gen2 x8 (x16 connector)
V
SAS Module connector
F
Chassis Intrusion
W
IPMB
G
SATA_KEY
X
SYS_FAN_1
H
Two Ethernet and Dual USB COMBO
Y
HSBP
I
Video port
Z
SATA_SGPIO
J
External Serial port
AA
Internal Serial Connector
K
RMM4 Lite Connector
BB
Front Panel Connector
Figure 3. Intel® Server Board S1200BTL/S1200BTLRM Layout
Table 2. Major Board Components
Intel order number G13326-007 Revision 2.4
Intel® Server Board S1200BT TPS Overview
9
Description
Description
L
CPU Power Connector
CC
HDD LED
M
SYS_FAN_4
DD
Internal USB Connector
N
RMM4 Dedicated NIC connector
EE
CMOS battery
O
Four DIMM Slots
FF
Four 3Gb/s SATA ports
P
P/S AUX
GG
Two 6Gb/s SATA ports
Q
MAIN POWER
HH
Smart module
Description
Description
A
Slot 4, 32 Mbit/33 MHz PCI
N
SYS FAN 1
B
Slot 5. PCI Express* Gen2 x8 (x8 connector);
Slot 6, PCI Express* Gen2x4 (x8 connector).
O
CPU connector
C
SATA_KEY
P
CPU Fan connector
Revision 2.4 Intel order number G13326-007
Figure 4. Intel® Server Board S1200BTS Layout
Table 3. Major Board Components
Overview Intel® Server Board S1200BT TPS
10
Description
Description
D
Slot 7, PCI Express* Gen2 x8 (x16 connector)
Q
Chassis Intrusion
E
Ethernet and Dual USB COMBO
R
SATA_SGPIO
F
Ethernet and Dual USB COMBO
S
SYS_FAN_3
G
Video port
T
Six 3Gb/s SATA ports
H
External Serial port
U
Low profile USB connector
I
CPU Power connector
V
Internal USB
J
SYS_FAN_2
W
CMOS battery
K
DIMM slots
X
Front Panel
L
MAIN power connector
Y
HDD LED
M
TPM connector
2.2.2 Intel
®
Server Board S1200BTL/S1200BTLRM Mechanical Drawings
Figure 5. Intel® Server Board S1200BTL/S1200BTLRM – Hole and Component Positions
Intel order number G13326-007 Revision 2.4
Intel® Server Board S1200BT TPS Overview
11
Figure 6. Intel® Server Board S1200BTL/S1200BTLRM – Major Connector Pin Location (1 of 2)
Revision 2.4 Intel order number G13326-007
Overview Intel® Server Board S1200BT TPS
12
Figure 7. Intel® Server Board S1200BTL/S1200BTLRM – Major Connector Pin Location (2 of 2)
Intel order number G13326-007 Revision 2.4
Intel® Server Board S1200BT TPS Overview
13
Figure 8. Intel® Server Board S1200BTL/S1200BTLRM – Primary Side Keepout Zone
Figure 9. Intel® Server Board S1200BTL/S1200BTLRM – Secondary Side Keepout Zone
Revision 2.4 Intel order number G13326-007
Overview Intel® Server Board S1200BT TPS
14
A
Serial Port A
C
NIC Port 1 (1 Gb) and Dual USB Port
Connector
B
Video
D
NIC port 2 (1 Gb) and Dual USB Port
Connector
2.2.3 Server Board Rear I/O Layout
The following figure shows the layout of the rear I/O components for the server board:
Figure 10. Intel® Server Board S1200BT Rear I/O Layout
Intel order number G13326-007 Revision 2.4
Intel® Server Board S1200BT TPS Functional Architecture
15
PCIe Gen2 x4
x4 DMI Gen2
4
12
FLASHFLASH
LPC
Notes:
Dual GbE
RMII
SATA 3G
FLASHFLASH
BMC Boot
Flash
Intel® C204
Ch A Ch B
DDR3 (Channel B)
PCIe x8
XDP
PCIe Gen1 x1
PCIe Gen2 x4
SPI
GLCI
USB 2.0
Slot 6
(PCIe Gen1 x1 in physical)
optional
on-board
4 Unbuffered
DIMMs
GbE
GbE
USB
1.1
USB
2.0
22
DDR3 (Channel A)
Lewisville
GbE
PHY
USB
RGMII
(x16 connector)
SERIAL 2
RMM4 Dedicated
NIC Module
2
2
SATA 6G
Mezzanine Module
GbE
Hartwell
2
USB
TP
M
BIOS Flash
PCIe Gen1 x1
DDR3
PCIe x4
PCIe x4
Slot 5
Knoxvill
Socket H2
Intel® Xeon®
Processor
Slot 4
(x8 connector)
(x8 connector)
Slot 3
PCI 32/33
(x8 connector)
Slot 1
Intel® Server Board S1200BTL/S1200BTLRM Block
Diagram
ATX - 12" x 9.6"
PCI
Internal USB
Header x2
I/O Module
Rear I/O USB
Ports x2
Type-A
Header
Zoar
SERIAL 1VIDEO
Rear I/O
VGA Port
Rear I/O
COM Port
Internal
Header
SATA-III
0
1
4
5
2
3
SATA-II
BMC
1. Video integrated into BMC.
A1 A0 B1 B0
SPI
SPI
RMM4 LITE
Module
3. Functional Architecture
The architecture and design of the Intel® Server Board S1200BT is based on the Intel
®
C200
Chipset. The chipset is designed for systems based on the Intel® Xeon® processor in the FCLGA 1155 socket package.
The Intel® Server Board S1200BTL/S1200BTLRM use Intel® C204 Chipset and the Intel® Server
Board S1200BTS uses Intel® C202 Chipset.
The Intel® Xeon® Processor E3-1200 Processors are made up of multi-core processors based
on the 32nm processor technology. The Intel® Xeon® Processor E3-1200 V2 Processors are
made up of multi-core processors based on the 22nm processor technology. The 2nd Generation
Intel® Core™ i3 Processors are made up of dual-core processors based on the 32nm processor
technology. The 3rd Generation Intel® Core™ i3 Processors are made up of dual-core
processors based on the 22nm processor technology.
This chapter provides a high-level description of the functionality associated with each chipset
component and the architectural blocks that make up the server board.
Revision 2.4 Intel order number G13326-007
Figure 11. Intel® Server Board S1200BTL/S1200BTLRM Functional Block Diagram
Functional Architecture Intel® Server Board S1200BT TPS
16
PCIe Gen2 x4
x4 DMI Gen2
12
FLASHFLASH
LPC
Dual GbE
Intel® C202
Ch A Ch B
DDR3 (Channel B)
PCIe X8
XDP
PCIe Gen1 x1
SPI
GLCI
USB 2.0
Slot 7
(PCIe Gen1 x1 in physical)
TPM
Header
4 Unbuffered
DIMMs
GbE
GbE
22
DDR3 (Channel A)
Lewisville
GbE
PHY
USB
(x16 connector)
6
SATA 3G
GbE
Hartwell
2
USB
TPM
MEM
VTT
MEM VRD 12.0
BIOS Flash
Misc
VR s
PCIe X8
Slot 6
Knoxvill
Socket H2
Intel® Xeon®
Processor
(x8 connector)
Slot 5
(x8 connector)
Slot 4
Intel® Server Board S1200BTS Block
Diagram
ATX – 9.6" x 9.6"
PCI
Internal USB
Header x2
Rear I/O USB
Ports x2
Type-A
Header
SERIAL 1
VIDEO
Rear I/O
VGA Port
Rear I/O
COM Port
SATA-II
0
1
4
5
2
3
A1 A0 B1 B0
VTT
VPLL
VSA
VRD 12.0
VCORE
SERIAL 2
Internal
Header
SM712
PCI 32/33
SIO
W83627DHGP
Figure 12. Intel® Server Board S1200BTS Functional Block Diagram
3.1 Processor Sub-System
The Intel® Server Board S1200BT supports the following processors:
The Intel® Xeon® E3-1200 Processors are made up of multi-core processors based on the 32nm
processor technology. The 2nd Generation Intel® Core™ i3 Processors are made up of dual-core
processors based on the 32nm processor technology.
The Intel® Server Board S1200BTR also supports the following processors:
The Intel® Xeon® E3-1200 V2 Processors are made up of multi-core processors based on the
22 nm processor technology. The 3rd Generation Intel® Core™ i3 Processors are made up of
dual-core processors based on the 22nm processor technology.
Intel order number G13326-007 Revision 2.4
Intel
The 2
Intel
The 3
®
Xeon® E3-1200 Processors.
nd
Generation Intel® Core™ i3 Processors.
®
Xeon® E3-1200 V2 Processors.
rd
Generation Intel® Core™ i3 Processors.
Intel® Server Board S1200BT TPS Functional Architecture
17
3.1.1 Intel
®
Xeon® Processor E3-1200 Processors and Intel® Xeon® E3-1200 V2
Processors
The Intel® Xeon® E3-1200 Processors highly integrated solution variant is composed of quad
processor cores.
FC-LGA 1155 socket package with five GT/s.
Up to 95 W Thermal Design Power (TDP); processors with higher TDP are not
supported.
The Intel® Xeon® E3-1200 V2 Processors highly integrated solution variant is composed of quad
processor cores.
FC-LGA 1155 socket package with five GT/s.
Up to 95 W Thermal Design Power (TDP); processors with higher TDP are not
supported.
The list of supported processors may be found at http://serverconfigurator.intel.com.
Note: The workstation processor is not supported in this platform.
3.1.2 The 2nd Generation Intel
®
Core™ i3 Processors and the 3rd Generation Intel®
Core™ i3 Processors
The 2nd Generation Intel® Core™ i3 Processors highly integrated solution variant is composed of
Dual cores.
FC-LGA 1155 socket package with five GT/s.
Up to 65 W Thermal Design Power (TDP); processors with higher TDP are not
supported.
The 3rd Generation Intel® Core™ i3 Processors highly integrated solution variant is composed of
Duo cores.
FC-LGA 1155 socket package with five GT/s.
Up to 65 W Thermal Design Power (TDP); processors with higher TDP are not
supported.
The list of supported processors may be found at http://serverconfigurator.intel.com.
3.1.3 Intel
®
Turbo Boost Technology
Intel® Turbo Boost Technology is featured on certain processors in the Intel® Xeon® Processor
1200 Series. Intel® Turbo Boost Technology opportunistically and automatically allows the
processor to run faster than the marked frequency if the processor is operating below power,
temperature, and current limits. This results in increased performance for both multi-threaded
and single-threaded workloads.
Intel® Turbo Boost Technology operation:
Operates under Operating System control – It is only entered when the operating system
requests the highest (P0) performance state.
Operation can be enabled or disabled in BIOS Setup.
Revision 2.4 Intel order number G13326-007
Functional Architecture Intel® Server Board S1200BT TPS
18
Converts any available power and thermal headroom into a higher frequency on active
cores.
At nominal marked processor frequency, many applications consume less than the rated
processor power draw.
Availability is independent of the number of active cores.
Maximum Turbo Boost frequency depends on the number of active cores and varies by
processor configuration.
The amount of time the system spends in Intel
®
Turbo Boost operation depends on
workload, operating environment, and platform design.
If the processor supports the Intel® Turbo Boost Technology feature, the BIOS Setup provides
an option to enable or disable this feature. The default state is “enabled”.
3.2 Memory Subsystem
The Intel® Xeon® Processor E3-1200 series or Intel® Core™ Processor i3 series have an
Integrated Memory Controller (IMC) in its package. Each processor produces up to two DDR3
channels of memory. Each DDR3 channel in the IMC supports up to two UDIMM slots. The
DDR3 UDIMM frequency can be 1066/1333 (for Intel® Xeon® E3-1200 Processors or the 2nd
Generation Intel® Core™ i3 Processors) and 1333/1600 (for Intel® Xeon® E3-1200 V2
Processors or the 3nd Generation Intel® Core™ i3 Processors) MHz. Only ECC memory is
supported on this platform.
The memory channels are named as “Channel A” and “Channel B”.
The memory slots are named as “Slot1” and “Slot2” on each channel. Slot1will be the
farthest from the processor socket.
DIMMs are named to reflect the channel and slot in which they are installed:
o Channel A, Slot1 is “DIMM_A1”.
o Channel A, Slot2 is “DIMM_A2”.
o Channel B, Slot1 is “DIMM_B1”.
o Channel B, Slot2 is “DIMM_B2”.
3.2.1 Memory Supported
The Intel® Server Board S1200BT family supports various DDR3 DIMM modules of different
types and sizes and speeds.
In this section, the statements of support are subject to qualification in two ways:
For S1200 Server Boards with an SNB-DT processor, the Server Board and the BIOS may
support:
DIMMs composed of Dynamic Random Access Memory (DRAM) chips using 1 Gb, 2 Gb,
or 4 Gb technology.
DIMMs using x8 DRAM technology only.
DIMMs organized as Single Rank (SR) or Dual Rank (DR).
DIMM sizes of 1 GB, 2 GB, 4 GB, or 8 GB.
For Intel® Xeon® E3-1200 Processors or the 2nd Generation Intel® Core™ i3 Processors,
the DIMM speeds of 1066 or 1333 MT/s (megatransfers/second).
Intel order number G13326-007 Revision 2.4
Intel® Server Board S1200BT TPS Functional Architecture
19
For Intel® Xeon® E3-1200 V2 Processors or the 3rd Generation Intel® Core™ i3
Processors, the DIMM speeds of 1333/1600 MT/s (megatransfers/second).
Only Unregistered (Unbuffered) DIMMs (UDIMMs) are supported.
Only Error Correction Code (ECC) enabled DIMMs are supported.
UDIMMs may or may not have thermal sensors.
Note: UDIMMs must be ECC, and may or may not have thermal sensors.
S1200BT BIOS has the following limitations:
No support for LV DIMMs
No support for RDIMMs
All channels in a system will run at the fastest common frequency
Mixing ECC and non-ECC UDIMMs anywhere on the platform is not supported
Static Closed Loop Thermal Throttling (CLTT) supported through BMC (requires ECC
DIMMs with thermal sensor)
3.2.2 Post Error Codes
The range {0xE0 - 0xEF} of POST codes is used for memory errors in early POST. In late POST,
this same range of POST code values is used for reporting other system errors.
0xE8 - No Usable Memory Error: If no usable memory is available, the BIOS emits a
beep code and displays POST Diagnostic LED code 0xE8 and halts the system.
This can also occur if all memory in the system fails and/or has become disabled during
memory initialization. For example, if a DDR3 DIMM has no SPD information, the BIOS
treats the DIMM slot as if no DDR3 DIMM is present on it. Therefore, if this is the only
DDR3 DIMM installed in the system, there is no usable memory, and the BIOS goes to a
memory error code 0xE8 as described above.
0x53/0x55/0XE8 – DIMM SPD does not respond or DIMM SPD Read Error, the DIMM
will not be detected, if the SPD does not respond, which could result in “No memory
Installed” or “No Usable Memory” Memory Error Halt 0X53, 0x55, or 0xE8, or could
result later in an invalid configuration if the “no SPD” DIMM is in Slot 1 on the channel..
0x51 – Memory SPD Error: If the DIMM does respond but the SPD cannot be
successfully read, that would cause a “Memory SPD Error”, memory error halt 0X51. For
each memory channel, once the DIMM SPD parameters have been read, they are
checked to verify that the DIMMs on the channel are a valid configuration, DIMM speed
and size, ECC capability, and in which memory slots the DIMMs are installed. An invalid
configuration will cause the system to halt.
0xEA - Channel Training Error: If the memory initialization process is unable to
properly perform the Data/Data Strobe timing training on a memory channel, the BIOS
emits a beep code and displays POST Diagnostic LED code 0xEA momentarily during
the beeping. If there is usable memory in the system on other channels, POST memory
initialization continues. Otherwise, the system beeps and halts with POST Diagnostic
LED code 0xEA staying displayed.
0x54/0xEB - Memory Test Error: If a DDR3 DIMM or a set of DDR3 DIMMs on the
same memory channel fails memory testing but usable memory remains available, the
BIOS emits a beep code and displays POST Diagnostic LED code 0xEB momentarily
Revision 2.4 Intel order number G13326-007
Functional Architecture Intel® Server Board S1200BT TPS
20
during the beeping, then continues POST. If all of the memory fails memory testing, then
system memory error code 0xE8 (No Usable Memory) as described above.
0xED - Population Error or Invalid DIMM: If the installed memory contains an invalid
DIMM configuration on any channel in the system, the system beeps and halts with
POST Diagnostic LED code 0xED. The DIMM are installed incorrectly, not following the
“Fill Farthest First” rule (Slot 1 must be filled before Slot 2). This will result in a DIMM
Population Error, with a Memory Error Halt 0xED
Note: Mixed DIMM configurations are not supported and not validated by Intel®.
3.2.3 Memory Map and Population Rules
The overall configuration is a single processor with two channels, and two DIMM slots on each
channel on the Intel® Server Board S1200BT. All memory DIMMs are ECC UDIMMs only, with a
maximum size of 8 GB.
Slot1 must be populated first before Slot2, on either channel.
Channel A and Channel B are independent and are not required to have the same
number of DIMMs installed. Either channel may be used for a single-DIMM configuration.
o When only one memory channel is populated, the memory runs in Single
Channel mode, with no interleaving.
o When both channels are populated identically, the memory runs in Dual Channel
Symmetric mode. The memory is interleaved by full 64-byte cache lines
alternating between channels, that is the first entire cache line resides in
DIMM_A1, the second in DIMM_B1, and so on. This allows Adjacent Cache Line
Prefetch to fetch cache lines from both channels simultaneously, approximately
doubling the potential memory bandwidth.
o When both channels are populated, but with different numbers of DIMMs, Intel®
Flex Memory Technology divides the installed memory into two zones, using
interleaved Dual Channel Symmetric mode as far as the highest address on the
less-populated channel, then using uninterleaved Dual Channel Asymmetric
mode for the remaining memory on the more-populated channel.
The maximum total installed memory size supported is 32 GB, using four 8 GB DIMMs.
The maximum memory bandwidth is 10.6 GB/s in Single-Channel mode or 21 GB/s in DualChannel Symmetric mode, assuming DDR3 running at 1333 MT/s.
Intel order number G13326-007 Revision 2.4
Intel® Server Board S1200BT TPS Functional Architecture
21
Configuration
DIMM_A1
DIMM_A2
DIMM_B1
DIMM_B2
One DIMM
Single Channel
A1 only
Single Channel
One DIMM
Single Channel
B1 only
Single Channel
Two DIMMs
Single Channel
A1
Single Channel
A2
Single Channel
Two DIMMs
Single Channel
B1
Single Channel
B2
Single Channel
Two DIMMs
Dual Channel
Symmetric
A1
Dual Channel
Symmetric
B1
Dual Channel
Symmetric
Three DIMMs
Intel® Flex
Memory
A1
Dual Channel
Symmetric
A2
Dual Channel
Asymmetric
B1
Dual Channel
Symmetric
Three DIMMs
Intel® Flex
Memory
A1
Dual Channel
Symmetric
B1
Dual Channel
Symmetric
B2
Dual Channel
Asymmetric
Four DIMMs
Dual Channel
Symmetric
A1
Dual Channel
Symmetric
A2
Dual Channel
Symmetric
B1
Dual Channel
Symmetric
B2
Dual Channel
Symmetric
DIMM slots per channel
DIMMs populated per channel
Speed
Ranks per channel
2 1 1066 and 1333
Single Rank and Dual Rank
2 2 1066 and 1333
Single Rank and Dual Rank
3.2.3.1 Memory Configuration Table
Table 4. Memory Configuration Table
3.2.3.2 DIMM Configuration rules
Table 5. UDIMM memory configuration rule for Intel® Xeon® E3-1200 Processors or the 2nd
Revision 2.4 Intel order number G13326-007
Generation Intel® Core™ i3 Processors
Functional Architecture Intel® Server Board S1200BT TPS
22
DIMM slots per channel
DIMMs populated per channel
Speed
Ranks per channel
2 1 1333 and1600
Single Rank and Dual Rank
2 2 1333 and1600
Single Rank and Dual Rank
Max Memory Possible
1Gb DRAM Technology
2Gb DRAM Technology
4Gb DRAM Technology
Single Rank UDIMM
4GB
(4x 1GB DIMMs)
8GB
(4x 2GB DIMMs)
16GB
(4x 4GB DIMMs)
Dual Rank UDIMMs
8GB
(4x 2GB DIMMs)
16GB
(4x 4GB DIMMs)
32GB
(4x 8GB DIMMs)
To get the maximum memory size on UDIMM, you get the detailed information from following
table:
Table 6. UDIMM memory configuration rule for Intel® Xeon® E3-1200 V2 Processors or the 3rd
Generation Intel® Core™ i3 Processors
To get the maximum memory size on UDIMM, you get the detailed information from following
table:
Table 7. UDIMM Maximum configuration
3.2.4 Publishing System Memory
For S1200 Server Boards with an SNB-DT processor, the memory configurations and
population rules are relatively simple. The overall configuration is a single processor/IMC, with
two channels, and two DIMM slots on each channel. All memory DIMMs are ECC UDIMMs only,
with a maximum size of 8 GB.
Slot1 must be populated first before Slot2, on either channel.
Channel A and Channel B are independent and are not required to have the same
number of DIMMs installed. Either channel may be used for a single-DIMM configuration.
o When only one memory channel is populated, the memory runs in Single
Channel mode, with no interleaving.
3.2.5 Memory RAS Support
For Intel® Server Board S1200BT, the form of Memory RAS provided is Error Correction Code
(ECC). ECC uses “extra bits” – 64-bit data in a 72-bit DRAM array – to add an 8-bit calculated
“Hamming Code” to each 64 bits of data. This additional encoding enables the memory
controller to detect and report single or double bit errors, and to correct single-bit errors.
There is a specific step in memory initialization in which all of memory is cleared to zeroes
before the ECC function is enabled, in order to bring the ECC codes into agreement with
memory contents.
During operation, in the process of every fetch from memory, the data and ECC bits are
examined for each 64-bit data + 8-bit ECC group. If the ECC computation indicates that a single
bit Correctable Error has occurred, it is corrected and the corrected data is passed on to the
processor. If a double-bit Uncorrectable Error is detected, it cannot be corrected. In each case,
a Correctable or Uncorrectable ECC Error event is generated.
For Correctable Errors, there is a certain tolerance observed, since a Correctable Error can be
generated by something as random as a stray Cosmic Ray impacting the DIMM. Correctable
Errors are counted on a per-DIMM basis, but are just silently recorded until the tolerance
Intel order number G13326-007 Revision 2.4
Intel® Server Board S1200BT TPS Functional Architecture
23
threshold is crossed. The Correctable Error Threshold for Intel® Server Board S1200BT board is
set at 10 events. When the 10th CE occurs, a single Correctable Error event is logged.
3.3 Intel
®
Chipset PCH
The Intel® C200 Series Chipset is designed for use with Intel® Xeon® E3-1200 Processors, Intel®
Xeon® E3-1200 V2 Processors, the 2nd Generation Intel® Core™ i3 Processors or the 3rd
Generation Intel® Core™ i3 Processors in a UP server platform. The role of the PCH in the
Intel® Server Board S1200BT is to manage the flow of information between its eleven interfaces,
described below:
DMI interface to Processor
PCI Express* Interface
PCI Interface
Serial ATA Interface
LPC Interface to INTEGRATED BMC and TPM
USB host interface
SMBus* Host interface
Serial Peripheral interface
LAN interface
ACPI interface
3.4 I/O Sub-system
Intel® C200 Series PCH provides extensive I/O support.
3.4.1 Digital Media Interface (DMI)
Direct Media Interface (DMI) is the chip-to-chip connection between the processor and C202
chipset. This high-speed interface integrates advanced priority-based servicing allowing for
concurrent traffic and true isochronous transfer capabilities. Base functionality is completely
software-transparent, permitting current, and legacy software to operate normally.
3.4.2 PCI Express* Interface
The PCI-E configurations for each SKU are defined below:
With Intel
S1200BTL/S1200BTLRM
One PCI-E x16 Gen2 connector to be used as a x8 link, two PCI-E x8 Gen2 connectors to
be used as a x4 link and one SAS module Gen2 connector to be used as a x4 link
connected to the PCI-E ports of the processor. One PCI-E x8 Gen2 connector to be used
as x4 link connected to the PC-E ports of PCH.
With Intel
on S1200BTL/S1200BTLRM
One PCI-E x16 Gen3 connector to be used as a x8 link, two PCI-E x8 Gen3 connectors to
be used as a x4 link and one SAS module Gen3 connector to be used as a x4 link
connected to the PCI-E ports of the processor. One PCI-E x8 Gen2 connector to be used
as x4 link connected to the PC-E ports of PCH.
With Intel
S1200BTS
®
Xeon® E3-1200 Processors or the 2nd Generation Intel® Core™ i3 Processors on
®
Xeon® E3-1200 V2 Processors or the 3rd Generation Intel® Core™ i3 Processors
®
Xeon® E3-1200 Processors or the 2nd Generation Intel® Core™ i3 Processors on
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o One PCI-E x16 Gen2 connector to be used as x8 link, one PCI-E x8 Gen2
connectors to be used as a x8 link connected to the PCI-E ports of the processor.
One PCI-E x8 Gen2 connector to be used as x4 link connected to the PCI-E
ports of PCH.
With Intel
®
Xeon® E3-1200 V2 Processors or the 3rd Generation Intel® Core™ i3 Processors
on S1200BTS
o One PCI-E x16 Gen3 connector to be used as x8 link, one PCI-E x8 Gen3
connectors to be used as a x8 link connected to the PCI-E ports of the processor.
One PCI-E x8 Gen2 connector to be used as x4 link connected to the PCI-E
ports of PCH.
There is one 32-bit, 33-MHz 5-V PCI slot, common on both SKUs.
Compatibility with the PCI addressing model is maintained to ensure all existing applications
and drivers operate unchanged.
The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-andPlay specification. The initial recovered clock speed of 1.25 GHz results in 2.5 Gb/s each
direction, which provides a 250-MB/s communications channel in each direction (500 MB/s total).
This is close to twice the data rate of classic PCI. It is a fact that 8b/10b encoding is used
accounts for the 250 MB/s where quick calculations would imply 300 MB/s. The external
graphics ports support 5.0 GT/s speed as well. Operating at 5.0 GT/s results in twice as much
bandwidth per lane as compared to 2.5 GT/s operation.
When operating with two PCI Express* controllers, each controller can operate at either 2.5
GT/s or 5.0 GT/s. The PCI Express* architecture is specified in three layers: Transaction Layer,
Data Link Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries.
3.4.3 Serial ATA Support
The Intel® C200 Series chipset has two integrated SATA host controllers that support
independent DMA operation on up to six ports and supports data transfer rates of up to 6.0 Gb/s
on up to two ports (Port 0 and 1 Only on S1200BTL/S1200BTLRM) while all ports support rates
up to 3.0 Gb/s. The SATA controller contains two modes of operation – a legacy mode using I/O
space, and an AHCI mode using memory space. Software that uses legacy mode will not have
AHCI capabilities.
Software that uses legacy mode does not have Advanced Host Configuration Interface (AHCI)
capabilities. The Intel® C202 PCH Chipset supports the Serial ATA Specification, Revision 1.0a.
The PCH also supports several optional sections of the Serial ATA II: Extensions to Serial ATA
1.0 Specification, Revision 1.0 (AHCI support is required for some elements).
The Intel® C200 Series chipset PCH provides hardware support for AHCI, a standardized
programming interface for SATA host controllers. Platforms supporting AHCI may take
advantage of performance features such as no master/slave designation for SATA devices each device is treated as a master – and hardware assisted native command queuing. AHCI
also provides usability enhancements such as Hot-Plug. AHCI requires appropriate software
support (for example, an AHCI driver) and for some features, hardware support in the SATA
device or additional platform hardware.
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3.4.3.1 Intel
®
Matrix Storage Technology
The Intel® C200 Series chipset provides support for Intel® Rapid Storage Technology 11.0,
providing both AHCI (see above for details on AHCI) and integrated RAID functionality. The
RAID capability provides high-performance RAID 0, 1, 5, and 10 functionality up to 6 SATA
ports of the PCH. Matrix RAID support is provided to allow multiple RAID levels to be combined
on a single set of hard drives, such as RAID 0 and RAID 1 on two disks. Other RAID features
include hot spare support, SMART alerting, and RAID 0 auto replace. Software components
include an Option ROM for pre-boot configuration and boot functionality, a Microsoft Windows*
compatible driver, and a user interface for configuration and management of the RAID capability
of PCH.
3.4.4 Low Pin Count (LPC) Interface
The Intel® C200 Series chipset implements an LPC Interface as described in the LPC 1.1
Specification. The Low Pin Count (LPC) bridge function of the C202 resides in PCI Device 31:
Function 0. In addition to the LPC bridge interface function, D31:F0 contains other functional
units including DMA, interrupt controllers, timers, power management, system management,
GPIO, and RTC.
3.4.5 USB 2.0 Support
On the Intel® C200 series PCH Chipset, the USB controller functionality is provided by the dual
EHCI controllers with an interface for up to ten USB 2.0 ports. All ports are high-speed, fullspeed, and low-speed capable.
Four external connectors are located on the back edge of the server board.
Two internal 2x5 headers (J1E1 and J1D1) are provided, each supporting two optional
USB 2.0 ports.
One port on internal smart module connector (J1J2) on Intel
®
Server Board
S1200BTL/S1200BTLRM.
3.4.5.1 Native USB Support
During the power-on self-test (POST), the BIOS initializes and configures the USB subsystem.
The BIOS is capable of initializing and using the following types of USB devices:
USB Specification-compliant keyboards.
USB Specification-compliant mouse.
USB Specification-compliant storage devices that utilize bulk-only transport mechanism.
USB devices are scanned to determine if they are required for booting.
The BIOS supports USB 2.0 mode of operation, and as such supports USB 1.1 and USB 2.0
compliant devices and host controllers.
During the pre-boot phase, the BIOS automatically support the hot addition and hot removal of
USB devices and a short beep is emitted to indicate such an action. For example, if a USB
device is hot plugged, the BIOS detects the device insertion, initializes the device, and makes it
available to the user. During POST, when the USB controller is initialized, it emits a short beep
for each USB device in the system as if they were all just “hot added”.
Only on-board USB controllers are initialized by BIOS. This does not prevent the operating
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system from supporting any available USB controllers including add-in cards.
3.4.5.2 Legacy USB Support
The BIOS supports PS/2 emulation of USB keyboards and mouse. During POST, the BIOS
initializes and configures the root hub ports and searches for a keyboard and/or a mouse on the
USB hub and then enables the devices that are recognized.
3.5 Optional Intel
The Intel® Server Board S1200BTL/S1200BTLRM provides a SAS Mezzanine slot (J2H1) for
the installation of an optional Intel® SAS RAID Module. Once the optional Intel® SAS Entry RAID
Module is detected, the x4 PCI Express* links from the chipset to the SAS Mezzanine slot.
Three modules are supported in these two platforms: AXXRMS2AF040, AXXRMS2LL040, and
AXX4SASMOD.
3.6 Optional Intel
The Intel® Server Board S1200BTLRM provides Intel® ROC Module support on all PCI-e slots.
The list of supported ROC modules may be found at
http://www.intel.com/support/motherboards/server/sb/CS-033596.htm.
Note: Intel® Server Board S1200BTL and S1200BTS do not support PCI-e ROC modules.
®
SAS RAID Module
®
ROC Module
3.7 Integrated Baseboard Management Controller
The Intel® Server Board S1200BTL/S1200BTLRM have the highly integrated single-chip
baseboard management controller based on ServerEngines* Pilot III, but Intel® Server Board
S1200BTS does not have the integrated baseboard management control.
This Intel® Integrated BMC contains the following integrated subsystems and features.
The following is a summary of the BMC management hardware features used by the BMC:
400MHz 32-bit ARM9 processor with memory management unit (MMU)
Two independent10/100/1000 Ethernet Controllers with RMII (Reduced Media
Independent Interface)/RGMII(Reduced Gigabit Media-Independent Interface)
support
DDR2/3 16-bit interface with up to 800 MHz operation
12 10-bit Analog to Digital Converters
16 fan tachometers
Eight Pulse Width Modulators (PWM)
Chassis intrusion logic
JTAG Master
Eight I2C interfaces with master-slave and SMBus* timeout support. All interfaces
are SMBus* 2.0 compliant.
Parallel general-purpose I/O Ports (16 direct and 32 shared)
Serial general-purpose I/O Ports (80 in and 80 out)
Three UARTs
Platform Environmental Control Interface (PECI)
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Six general-purpose timers
Interrupt controller
Multiple SPI flash interfaces
NAND/Memory interface
16 mailbox registers for communication between the Integrated BMC and host
LPC ROM interface
Integrated BMC watchdog timer capability
SD/MMC card controller with DMA support
LED support with programmable blink rate controls on GPIOs
Port 80h snooping capability
Secondary Service Processor (SSP), which provides the HW capability of offloading
time critical processing tasks from the main ARM core.
Figure 13. Integrated BMC Hardware
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3.7.1 Integrated BMC LAN Channels
The Integrated BMC supports two RMII/RGMII ports that can be used for communicating with
Ethernet devices. One port is used for communication with the on-board NICs and the other one
is used for communication with an Ethernet PHY located on an optional add-in card (or
equivalent on-board circuitry).
3.7.1.1 Baseboard NICs
The baseboard NIC is connected to a single Integrated BMC RMII/RGMII port that is configured
for RMII operation. The NC-SI protocol is used for this connection and provides a 100 Mb/s fullduplex multi-drop interface which allows multiple NICs to be connected to the Integrated BMC.
The physical layer is based upon RMII, however RMII is a point-to-point bus whereas NC-SI
allows one master and up to four slaves. The logical layer (configuration commands) is
incompatible with RMII.
3.7.1.2 Dedicated Management Channel
An additional LAN channel dedicated to Integrated BMC usage and not available to host SW is
supported through an optional add-in card. There is only a PHY device present on the add-in
card. The Integrated BMC has a built-in MAC module that uses the RGMII interface to link with
the card’s PHY. Therefore, for this dedicated management interface, the PHY and MAC are
located in different devices.
The PHY on the card connects to the Integrated BMC’s other RMII/RGMII interface (that is the
one that is not connected to the baseboard NICs). This Integrated BMC port is configured for
RGMII usage.
In addition to the use of an add-in card for a dedicated management channel, on systems that
support multiple Ethernet ports on the baseboard, the system BIOS provides a setup option to
allow one of these baseboard ports to be dedicated to the Integrated BMC for manageability
purposes. When this is enabled, that port is hidden from the OS.
3.7.1.3 Concurrent Server Management Use of Multiple Ethernet Controllers
Provided the HW supports a management link between the Integrated BMC and a NIC port, the
Integrated BMC FW supports concurrent OOB LAN management sessions for one on-board
NIC and the optional dedicated add-in management NIC combinations.
All NIC ports must be on different subnets for the above concurrent usage models.
MAC addresses are assigned for management NICs from a pool of up to three MAC addresses
allocated specifically for manageability. The total number of MAC addresses in the pool is
dependent on the product HW constraints (for example, a board with two NIC ports available for
manageability would have a MAC allocation pool of two addresses).
For these channels, support can be enabled for IPMI-over-LAN and DHCP.
For security reasons, embedded LAN channels have the following default settings:
IP Address: Static
All users disabled
IPMI-enabled network interfaces may not be placed on the same subnet. This includes the
Intel® Dedicated Management NIC and either of the BMC’s embedded network interfaces.
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Feature
Description
KVM Redirection
Remote console access through keyboard, video, and mouse redirection over LAN.
USB Media Redirection
Remote USB media access over LAN.
WS-MAN
Full SMASH profiles for WS-MAN based consoles.
Pin
Signal Name
Serial Port B Header Pin-out
1
DCD
2
DSR
3
RX
4
RTS
5
TX 6 CTS
7
DTR
8
RI
9
GND
Host-BMC communication over the same physical LAN connection – also known as “loopback”
– is not supported. This includes “ping” operations.
3.7.2 Optional RMM4 Advanced Management Board
On the Intel
®
Server Board S1200BTL/S1200BTLRM provides RMM4 module.
Give the customer the option to add a dedicated management 100 Mbit LAN
interface to the product.
Provide additional flash space, enabling the Advanced Management functions to
support WS-MAN and CIMON.
Table 8. Optional RMM4 Advanced Management Board Features
3.7.3 Serial Ports
The server board provides two serial ports: an external DB9 serial port connector and an
internal DH-10 serial header.
The rear DB9 Serial A port is a fully functional serial port that can support any standard serial
device.
The Serial B port is an optional port accessed through a nine-pin internal DH-10 header (J1B1
on S1200BTL/S1200BTLRM; J8A1 on S1200BTS). You can use a standard DH-10 to DB9
cable to direct serial A port to the rear of a chassis. The serial B interface follows the standard
RS-232 pin-out as defined in the following table:
Table 9. Serial B Header (J1B2 on S1200BTL/S1200BTLRM or J8A1 on S1200BTS) Pin-out
3.7.4 Floppy Disk Controller
The server board does not support a floppy disk controller interface. However, the system BIOS
recognizes USB floppy devices.
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2D Mode
Refresh rate
8bpp
16bpp
32bpp
640 x 480
60, 70, 72, 75,
85, 90, 100, and
200
Supported
Supported
Supported
800 x 600
60, 70, 72, 75,
85, 90, 100,120,
and 160
Supported
Supported
Supported
1024 x 768
60, 70, 72, 75,
85, 90, and 100
Supported
Supported
Supported
1152 x 852
43, 47, 60, 70,
75, 80, and 85
Supported
Supported
Supported
1280 x
1024
60, 70, 74, and
75
Supported
Supported
Supported
1600 x
1200
52
Supported
Supported
Supported
3.7.5 Keyboard and Mouse Support
The server board does not support PS/2 interface keyboards and mouse. However, the system
BIOS recognizes USB specification-compliant keyboard and mouse.
3.7.6 Wake-up Control
The super I/O contains functionality that allows various events to power on and power off the
system.
3.8 Graphic Support
3.8.1 Intel
®
Server Board S1200BTL/S1200BTLRM
The server board includes on-board Emulex* LLC Pilot III* controller with 128MB DDR3 memory
in which 8MB is usable\accessible memory for graphic display functions.
3.8.1.1 Video Modes
The integrated video controller supports all standard IBM VGA modes. The following table
shows the 2D modes supported for both CRT and LCD:
Table 10. Video Modes
3.8.1.2 Dual Video
The BIOS supports both single-video and dual-video modes. The dual-video mode is disabled
by default.
In the single mode (dual monitor video = disabled), the on-board video controller is
disabled when an add-in video card is detected.
In single mode, the onboard video controller is disabled when an add-in video card is
detected.
In dual mode, the onboard video controller is enabled and is the primary video device.
The external video card is allocated resources and is considered the secondary video
device.
When KVM is enabled in Integrated BMC FW, dual video is enabled.
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Onboard Video
Enabled
Disabled
Onboard video controller.
Warning: System video is completely disabled if
this option is disabled and an add-in video
adapter is not installed.
Dual Monitor Video
Enabled
Disabled
If enabled, both the onboard video controller and
an add-in video adapter are enabled for system
video. The onboard video controller becomes
the primary video device.
Table 11. Dual Video Modes
3.8.2 Video for Intel
®
Server Board S1200BTS
SM712 is a video chip from Silicon Motion, Inc*. (SMI). It is one in SMI’s LynxEM* family. It is
PCI 2.1 compliant with the standard PCI 33MHz and 66 MHz PCI Master/Slave interface.
33 MHz and 66 MHz PCI Master/Slave interface
PCI 2.1 compliant
Memory control is provided for the 4MB internal memory
Support 640x480, 800x600, 1024x768 resolution, and up to 85Hz
Dual Video mode is supported.
3.9 Network Interface Controller (NIC)
The Intel
onboard Intel® 82574L GbE PCI Express* network controller; the other is the onboard Intel®
82579 Gigabit Network controller.
3.9.1 Gigabit Ethernet Controller 82574L
The 82574 family (82574L and 82574IT) are single, compact, low-power components that offer
a fully-integrated Gigabit Ethernet Media Access Control (MAC) and Physical Layer (PHY) port.
The 82574 uses the PCI Express* architecture and provides a single-port implementation in a
relatively small area so it can be used for server and client configurations as a LAN on
Motherboard (LOM) design.
®
Server Board S1200BT supports two network interfaces; One is provided from the
External interfaces provided on the 82574:
PCIe Rev. 2.0 (2.5 GHz) x1
MDI (Copper) standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASETX,
and 10BASE-T applications (802.3, 802.3u, and 802.3ab)
NC-SI or SMBus* connection to a Manageability Controller (MC)
EEE 1149.1 JTAG (note that BSDL testing is NOT supported)
3.9.2 Gigabit Ethernet PHY 82579
The 82579 is a single port Gigabit Ethernet Physical Layer Transceiver (PHY). It connects to the
Intel® C200 series Chipset’s integrated Media Access Controller (MAC) through a dedicated
interconnect. The 82579 supports operation at 1000/100/10 Mb/s data rates. The PHY circuitry
provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and
10BASE-T applications (802.3, 802.3u, and 802.3ab). The 82579 also supports the Energy
Efficient Ethernet (EEE) 802.az specification.
The 82579 operates with the Platform Controller Hub (PCH) chipset that incorporates the MAC
and interfaces with its integrated LAN controller through two interfaces: PCIe-based and
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SMBus*. The PCIe (main) interface is used for all link speeds when the system is in an active
state (S0) while the SMBus* is used only when the system is in a low power state (Sx). In
SMBus* mode, the link speed is reduced to 10 Mb/s (dependent on low power options). The
PCIe interface incorporates two aspects: a PCIe SerDes (electrically) and a custom logic
protocol.
3.9.3 MAC Address Definition
Each Intel® Server Board S1200BTL/S1200BTLRM have the following four MAC addresses
assigned to it at the Intel® factory:
NIC 1 MAC address
NIC 2 MAC address – Assigned the NIC 1 MAC address +1
Integrated BMC LAN Channel MAC address – Assigned the NIC 1 MAC address +2
Intel
Each Intel® Server Board S1200BTS has the following two MAC addresses assigned to it at the
Intel® factory:
NIC 1 MAC address
NIC 2 MAC address – Assigned the NIC 1 MAC address +1
®
Remote Management Module 4 dedicated NIC MAC address – Assigned the NIC
1 MAC address +3
3.10 Intel
®
I/O Acceleration Technolgy 2 (Intel® I/OAT2)
Intel® I/O AT2 is not supported.
3.10.1 Direct Cache Access (DCA)
Direct Cache Access (DCA) is not supported on Intel® Xeon® Processor E3-1200 Series.
3.11 Intel
®
Virtualization Technology for Directed I/O (Intel® VT-d)
The Intel® C202 chipset provides hardware support for implementation of Intel® Virtualization
Technology with Directed I/O (Intel® VT-d). Intel® VT-d Technology consists of technology
components that support the virtualization of platforms based on Intel® Architecture Processors.
Intel® VT-d technology enables multiple operating systems and applications to run in
independent partitions. A partition behaves like a virtual machine (VM) and provides isolation
and protection across partitions. Each partition is allocated its own subset of host physical
memory.
Note: If the setup options are changed to enable or disable the Virtualization Technology setting
in the processor, the user must perform an AC power cycle for the changes to take effect.
3.12 TPM (Trusted Platform Module)
There is one TPM module connector. The detail information is listed below:
Embedded TPM 1.2 firmware
33-MHz Low Pin Count (LPC) interface V1.1
Compliant with TCG PC client specific TPM
Implementation Specification (TIS) V1.2
For the detail Intel® TPM module, please refer to TPM Module User Guide.
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BB Sensor4
Temp: 0x96
PATSBURG -A/D
IBMC
SMLink1 @ 100kHz (3.3V STBY)
MM/S[7]
SMLink0 @ 400kHz (3.3V STBY)
MM[1]
MM[4]
PMBus PS 0
FRU: 0xA0 / Device:
0xB0
S
PMBus (3.3V STBY)
MM[5]
HSBP (3.3V STBY)
MM[2]
PCI (3.3V STBY)
ME
PCH
0x88
(0x88 is default for SSB)
M/S
MM[0]
0xTBD
MM/S[1]
0xTBD
PMBus PS 1
FRU: 0xA2 / Device:
0xB2
S
PCI/PCIe Slots
S
CK-MNG
0xD0
S
CK420BQ
0xD2
S
DB1900Z
0xD8
S
Host (3.3V Main)Host (3.3V STBY)
MM[3]
MM[6]
XDP 0
N/A
MM
XDP 1
N/A
MM
S SMBus Slave (Main)
M/S
MM
MM/S
SMBus Multi-Master (Main)
SMBus Multi-Master (Standby)
SMBus Master (Main)
S SMBus Slave (Standby)
MM[0]
IPMB (3.3V STBY)
Voltage
Translation
LCP
0x22
S
IPMB Connector
M/S
IPMB (5V STBY)
BB sensor2
Temp: 0x98
S
ISOLATION
0-Ω
STUFFED
Sensor (3.3V STBY)
Front-Panel
FRU: 0xAE
S
BB Sensor1
Temp: 0x9A
S
BB Sensor3
Temp: 0x9C
S
Riser1
FRU: 0xA0
Temp: 0x90
S
Riser2
FRU: 0xA2
Temp: 0x92
S
rIOM
FRU: 0xA4
Temp: 0x94
S
SAS Module
FRU: 0xA6
Temp: 0x96
S
S
Front-Panel
Temp: 0x9E
S
ISOLATION
HSBP1
PSOC 0xD0
Temp: 0x90
FRU: 0xA0
HSBP2
PSOC 0xD6
Temp: 0x96
FRU: 0xA6
HSBP3
PSOC 0xD4
Temp: 0x94
FRU: 0xA4
S
S
S
Lewsville
0xC8 (Bromollow)
S
Nuvoton LOT6
0x6C
BB Optional
sensor 5
Temp: 0x94
S
Note: This sensor5 address is optional
only reserved for possible Thermal
management on certain board such as
IronPass
Note: The SMBus to PCIE slot connection is
reserved for certain cased which will use it for
GPU management.
4. Platform Management
This chapter is only for The Intel® Server Board S1200BTL/S1200BTLRM.
The platform management subsystem is based on the Integrated BMC features of the
ServerEngines* Pilot III. The onboard platform management subsystem consists of
communication buses, sensors, system BIOS, and server management firmware. The following
diagram provides an overview of the Server Management Bus (SMBUS*) architecture used on
this server board.
Figure 14. Server Management Bus (SMBUS*) Block Diagram
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4.1 Feature Support
4.1.1 IPMI 2.0 Features
Baseboard management controller (BMC)
IPMI Watchdog timer
Messaging support, including command bridging and user/session support
Chassis device functionality, including power/reset control and BIOS boot flags support
Event receiver device: The BMC receives and processes events from other platform
subsystems
Field replaceable unit (FRU) inventory device functionality: The BMC supports access to
system FRU devices using IPMI FRU commands
System event log (SEL) device functionality: The BMC supports and provides access to
a SEL
Sensor data record (SDR) repository device functionality: The BMC supports storage
and access of system SDRs
Sensor device and sensor scanning/monitoring: The BMC provides IPMI management of
sensors. It polls sensors to monitor and report system health
IPMI interfaces
o Host interfaces include system management software (SMS) with receive
message queue support, and server management mode (SMM)
o IPMB interface
o LAN interface that supports the IPMI-over-LAN protocol (RMCP and RMCP+)
Serial-over-LAN (SOL)
ACPI state synchronization: The BMC tracks ACPI state changes that are provided by
the BIOS
BMC self-test: The BMC performs initialization and run-time self-tests and makes results
available to external entities
Please see the Intelligent Platform Management Interface Specification Second Generation v2.0
for detail information.
4.1.2 Non-IPMI Features
The BMC supports the following non-IPMI features. This list does not preclude support for future
enhancements or additions.
In-circuit BMC firmware update
Fault resilient booting (FRB): FRB2 is supported by the watchdog timer functionality
Chassis intrusion detection
Basic fan control using TControl version 2 SDRs
Power supply redundancy monitoring and support
Hot-swap fan support
Acoustic management: Support for multiple fan profiles
Signal testing support: The BMC provides test commands for setting and getting
platform signal states
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The BMC generates diagnostic beep codes for fault conditions
System GUID storage and retrieval
Front panel management: The BMC controls the system status LED and chassis ID LED.
It supports secure lockout of certain front panel functionality and monitors button presses.
The chassis ID LED is turned on using a front panel button or a command.
Power state retention
Power fault analysis
Intel® Light-Guided Diagnostics
Power unit management: Support for power unit sensor. The BMC handles power-good
dropout conditions
DIMM temperature monitoring: New sensors and improved acoustic management using
closed-loop fan control algorithm taking into account DIMM temperature readings
Address Resolution Protocol (ARP): The BMC sends and responds to ARPs (supported
on embedded NICs)
Dynamic Host Configuration Protocol (DHCP): The BMC performs DHCP (supported on
embedded NICs)
Platform environment control interface (PECI) thermal management support
E-mail alerting
Embedded web server
Integrated KVM
Integrated Remote Media Redirection
Local Directory Access Protocol (LDAP) support
Intel® Intelligent Power Node Manager support
4.1.3 New Manageability Features
This generation server products offer a number of changes and additions to the manageability
features that are supported on the previous generation of servers. The following is a list of the
more significant changes that are common to this generation servers:
Sensor and SEL logging additions/enhancements (for example, additional thermal
monitoring capability, better isolation of faults to the FRU level)
Embedded platform debug feature which allows capture of detailed data for later
analysis by Intel® engineering
Provisioning and inventory enhancements:
o Signed Firmware (improved security)
o Inventory data/system information export (partial SMBIOS table)
Enhancements to fan speed control
DCMI 1.0 compliance
Support for embedded web server UI in Basic Manageability feature set
Enhancements to embedded web server
o Human-readable SEL
o Additional system configurability
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Feature
Basic*
Advanced**
IPMI 2.0 Feature Support
X X In-circuit BMC Firmware Update
X X FRB 2
X X Chassis Intrusion Detection
X X Fan Redundancy Monitoring
X X Hot-Swap Fan Support
X X Acoustic Management
X X Diagnostic Beep Code Support
X X Power State Retention
X X ARP/DHCP Support
X X PECI Thermal Management Support
X X E-mail Alerting
X X Embedded Web Server
X X SSH Support
X X Integrated KVM
X
Integrated Remote Media Redirection
X
Local Directory Access Protocol (LDAP)
X
X
Intel® Intelligent Power Node Manager
Support***
X
X
SMASH CLP
X
X
o Additional system monitoring capability
o Enhanced on-line help
Enhancements to KVM redirection
o Support for higher resolution
Management support for PMBus* rev1.2 compliant power supplies
Integrated BMC firmware reliability enhancements:
o Redundant Integrated BMC boot blocks to avoid possibility of a corrupted boot
block resulting in a scenario that prevents a user from updating the Integrated
BMC
4.2 Basic and Optional Advanced Management Features
This section explains the advanced management features supported by the Integrated
Baseboard Management Controller (Integrated BMC) firmware.
This section explains the advanced management features supported by the BMC firmware.
Table 12 lists basic and advanced feature support. Individual features may vary by platform. For
more information, refer to Appendix D.
Table 12. Basic and Advanced Management Features
* Basic management features provided by Integrated BMC
**Advanced management features available with optional Intel® Remote Management Module 4
***Intel® Intelligent Power Node Manager Support requires PMBus*-compliant power supply
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4.2.1 Enabling Advanced Management Features
The Advanced management features are to be delivered as part of the Integrated BMC firmware
image. The Integrated BMC’s baseboard SPI flash contains code/data for both the Basic and
Advanced features. An optional add-in card Intel® RMM4-lite is used as the activation
mechanism. When the Integrated BMC firmware initializes, it attempts to access the Intel®
RMM4-lite. If the attempt to access Intel® RMM4-lite is successful, then the Integrated BMC
activates the advanced features.
Advanced manageability features are supported over all NIC ports enabled for server
manageability. This includes baseboard NICs as well as the LAN channel provided by the
optional Dedicated NIC add-in card.
There are two RMM4 SKUs:
Intel® RMM4-lite – Advance features enabled but no dedicated management NIC.
Intel® RMM4 – Advance features enabled with a dedicated management NIC. It is a
package that contains two modules: Intel® Dedicated Server Management NIC and Intel®
RMM4-lite.
4.2.2 Keyboard, Video, and Mouse (KVM) Redirection
The BMC firmware supports keyboard, video, and mouse redirection (KVM) over LAN. This
feature is available remotely from the embedded web server as a Java* applet. This feature is
enabled when the Intel® RMM4 is present. The client system must have a Java* Runtime
Environment (JRE) version 5.0 or later to run the KVM or media redirection applets.
The Integrated BMC supports an embedded KVM application (Remote Console) that can be
launched from the embedded web server from a remote console. USB1.1 or USB 2.0 based
mouse and keyboard redirection are supported. It is also possible to use the KVM-redirection
(KVM-r) session concurrently with media-redirection (media-r). This feature allows a user to
interactively use the keyboard, video, and mouse (KVM) functions of the remote server as if the
user were physically at the managed server.
The KVM-redirection feature automatically senses video resolution for best possible screen
capture and provides high-performance mouse tracking and synchronization. It allows remote
viewing and configuration in pre-boot POST and BIOS setup, once BIOS has initialized video.
Other attributes of this feature include:
Encryption of the redirected screen, keyboard, and mouse
Compression of the redirected screen
4.2.2.1 Remote Console
The Remote Console is the redirected screen, keyboard and mouse of the remote host system.
To use the Remote Console window of your managed host system, the browser must include a
Java* Runtime Environment plug-in. If the browser has no Java* support, such as with a small
handheld device, the user can maintain the remote host system using the administration forms
displayed by the browser.
The Remote Console window is a Java* Applet that establishes TCP connections to the
Integrated BMC. The protocol that is run over these connections is a unique KVM protocol and
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not HTTP or HTTPS. This protocol uses ports #7578 for KVM, #5120 for CDROM media
redirection, and #5123 for Floppy/USB media redirection (both supporting encryption).
4.2.2.2 Performance
The remote display accurately represents the local display. The feature adapts to changes to the
video resolution of the local display and continues to work smoothly when the system transitions
from graphics to text or vice-versa. The responsiveness may be slightly delayed depending on
the bandwidth and latency of the network.
Enabling KVM and/or media encryption will degrade performance. Enabling video compression
provides the fastest response while disabling compression provides better video quality.
For the best possible KVM performance, a 2Mb/sec link or higher is recommended.
The redirection of KVM over IP is performed in parallel with the local KVM without affecting the
local KVM operation.
4.2.2.3 Security
The KVM redirection feature supports multiple encryption algorithms, including RC4 and AES.
The actual algorithm that is used is negotiated with the client based on the client’s capabilities.
4.2.2.4 Availability
The remote KVM session is available even when the server is powered-off (in stand-by mode).
No re-start of the remote KVM session shall be required during a server reset or power on/off.
An Integrated BMC reset (for example, due to an Integrated BMC Watchdog initiated reset or
Integrated BMC reset after Integrated BMC firmware update) will require the session to be reestablished.
KVM sessions persist across system reset, but not across an AC power loss.
4.2.2.5 Timeout
The remote KVM session will automatically timeout after a configurable amount of time (30
minutes is the default).
The default inactivity timeout is 30 minutes, but may be changed through the embedded web
server. Remote KVM activation does not disable the local system keyboard, video, or mouse.
Remote KVM is not deactivated by local system input, unless the feature is disabled locally.
4.2.2.6 Usage
As the server is powered up, the remote KVM session displays the complete BIOS boot process.
The user is able interact with BIOS setup, change and save settings as well as enter and
interact with option ROM configuration screens.
At least two concurrent remote KVM sessions are supported. It is possible for at least two
different users to connect to same server and start remote KVM sessions
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4.2.3 Media Redirection
The embedded web server provides a Java* applet to enable remote media redirection. This
may be used in conjunction with the remote KVM feature, or as a standalone applet.
The media redirection feature is intended to allow system administrators or users to mount a
remote IDE or USB CD-ROM, floppy drive, or a USB flash disk as a remote device to the server.
Once mounted, the remote device appears just like a local device to the server, allowing system
administrators or users to install software (including operating systems), copy files, update BIOS,
and so on, or boot the server from this device.
The following capabilities are supported:
The operation of remotely mounted devices is independent of the local devices on the
server. Both remote and local devices are useable in parallel.
Either IDE (CD-ROM, floppy) or USB devices can be mounted as a remote device to the
server.
It is possible to boot all supported operating systems from the remotely mounted device
and to boot from disk IMAGE (*.IMG) and CD-ROM or DVD-ROM ISO files. See the
Tested/supported Operating System List for more information.
Media redirection shall support redirection for a minimum of two virtual devices
concurrently with any combination of devices. As an example, a user could redirect two
CD or two USB devices.
The media redirection feature supports multiple encryption algorithms, including RC4
and AES. The actual algorithm that is used is negotiated with the client based on the
client’s capabilities.
A remote media session is maintained even when the server is powered-off (in standby
mode). No restart of the remote media session is required during a server reset or power
on/off. An Integrated BMC reset (for example, due to an Integrated BMC reset after
Integrated BMC firmware update) will require the session to be re-established
The mounted device is visible to (and useable by) managed system’s OS and BIOS in
both pre-boot and post-boot states.
The mounted device shows up in the BIOS boot order and it is possible to change the
BIOS boot order to boot from this remote device.
It is possible to install an operating system on a bare metal server (no OS present) using
the remotely mounted device. This may also require the use of KVM-r to configure the
OS during install.
USB storage devices will appear as floppy disks over media redirection. This allows for
the installation of device drivers during OS installation.
If either a virtual IDE or virtual floppy device is remotely attached during system boot,
both the virtual IDE and virtual floppy are presented as bootable devices. It is not
possible to present only a single-mounted device type to the system BIOS.
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4.2.3.1 Availability
The default inactivity timeout is 30 minutes and is not user-configurable.
Media redirection sessions persist across system reset but not across an AC power loss or
BMC reset.
4.2.3.2 Network Port Usage
The KVM and media redirection features use the following ports:
5120 – CD Redirection
5123 – FD Redirection
5124 – CD Redirection (Secure)
5127 – FD Redirection (Secure)
7578 – Video Redirection
7582 – Video Redirection (Secure)
4.2.4 Embedded Web server
Integrated BMC Base manageability provides an embedded web server and an OEMcustomizable web GUI which exposes the manageability features of the Integrated BMC base
feature set. It is supported over all on-board NICs that have management connectivity to the
Integrated BMC as well as an optional dedicated add-in management NIC. At least two
concurrent web sessions from up to two different users is supported. The embedded web user
interface shall support the following client web browsers:
Microsoft Internet Explorer 7.0*
Microsoft Internet Explorer 8.0*
Microsoft Internet Explorer 9.0*
Mozilla Firefox 3.0*
Mozilla Firefox 3.5*
Mozilla Firefox 3.6*
The embedded web user interface supports strong security (authentication, encryption, and
firewall support) since it enables remote server configuration and control. The user interface
presented by the embedded web user interface shall authenticate the user before allowing a
web session to be initiated. Encryption using 128-bit SSL is supported. User authentication is
based on user id and password.
The GUI presented by the embedded web server authenticates the user before allowing a web
session to be initiated. It presents all functions to all users but grays-out those functions that the
user does not have privilege to execute. (For example, if a user does not have privilege to
power control, then the item shall be displayed in grey-out font in that user’s UI display). The
web GUI also provides a launch point for some of the advanced features, such as KVM and
media redirection. These features are grayed out in the GUI unless the system has been
updated to support these advanced features.
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A partial list of additional features supported by the web GUI includes:
Presents all the Basic features to the users.
Power on/off/reset the server and view current power state.
Virtual front panel display and overall system health.
Provides embedded firmware version information.
Configuration of various IPMI parameters (LAN parameters, users, passwords, and so
on).
Configuration of alerting (SNMP and SMTP).
Display system asset information for the product, board, and chassis.
Display of BMC-owned sensors (name, status, current reading, and enabled thresholds),
including color-code status of sensors.
Automatic refresh of sensor data with a configurable refresh rate.
On-line help.
Display/clear SEL (display is in easily understandable human readable format).
Supports major industry-standard browsers (Internet Explorer and Mozilla Firefox*).
Automatically logs out after user-configurable inactivity period.
The GUI session automatically times-out after a user-configurable inactivity period. By
default, this inactivity period is 30 minutes.
Embedded Platform Debug feature - Allow the user to initiate a “diagnostic dump” to a
file that can be sent to Intel® for debug purposes.
Display of power statistics (current, average, minimum, and maximum) consumed by the
server.
4.2.5 Embedded Platform Debug
The Embedded Platform Debug feature supports capturing low-level diagnostic data (applicable
MSRs, PCI configuration-space registers, and so on). This feature allows a user to export this
data into a file that is retrievable through the embedded web GUI, as well as through host and
remote IPMI methods, for the purpose of sending to an Intel® engineer for an enhanced
debugging capability. The files are compressed, encrypted, and password protected. The file is
not meant to be viewable by the end user but rather to provide additional debugging capability
to an Intel® support engineer.
A list of data that may be captured using this feature includes but is not limited to:
1. Platform sensor readings – This includes all “readable” sensors that can be accessed
by the Integrated BMC firmware and have associated SDRs populated in the SDR
repository. This does not include any “event-only” sensors. (All BIOS sensors and some
Integrated BMC and ME sensors are “event-only”; meaning that they are not readable
using an IPMI Get Sensor Reading command but rather are used just for event logging
purposes).
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2. SEL – The current SEL contents are saved in both hexadecimal and text format.
3. CPU/memory register data useful for diagnosing the cause of the following
system errors: CATERR, ERR[2], SMI timeout, PERR, and SERR. The debug data is
saved and time-stamped for the last three occurrences of the error conditions.
a. PCI error registers
b. MSR registers
c. MCH registers
4. Integrated BMC configuration data
5. Integrated BMC firmware debug log (also known as SysLog) – Captures firmware
debug messages.
4.2.6 Data Center Management Interface (DCMI)
DCMI is an IPMI-based standard that builds upon a set of required IPMI standard commands by
adding a set of DCMI-specific IPMI OEM commands. BTP1200-LC platform will support DCMI
1.0 specification.
4.2.7 Local Directory Authentication Protocol (LDAP)
The Lightweight Directory Access Protocol (LDAP) is an application protocol supported by the
Integrated BMC for the purpose of authentication and authorization. The Integrated BMC user
connects with an LDAP server for login authentication. This is only supported for non-IPMI
logins including the embedded web UI and SM-CLP. IPMI users/passwords and sessions are
not supported over LDAP.
LDAP can be configured (IP address of LDAP server, port, and so on) through the Integrated
BMC’s Embedded Web UI. LDAP authentication and authorization is supported over the any
NIC configured for system management. The BMC uses a standard Open LDAP implementation
for Linux*.
4.3 Thermal Control
4.3.1 Memory Thermal Throttling
The system shall support thermal management through open loop throttling (OLTT) or static
closed loop throttling (CLTT) of system memory based on availability of valid temperature
sensors on the installed memory DIMMs. The Integrated Memory Controller (IMC) dynamically
changes throttling levels to cap throttling based on memory and system thermal conditions as
determined by the system and DIMM power and thermal parameters. Support for CLTT on
mixed-mode DIMM populations (that is, some installed DIMMs have valid temp sensors and
some do not) is not supported. The Integrated BMC fan speed control functionality is related to
the memory throttling mechanism used.
The following terminology is used for the various memory throttling options:
Static Open Loop Thermal Throttling (Static-OLTT): OLTT control registers are
configured by BIOS MRC remain fixed after post. The system does not change any of
the throttling control registers in the embedded memory controller during runtime.
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Static Closed Loop Thermal Throttling (Static-CLTT): CLTT control registers are
configured by BIOS MRC during POST. The memory throttling is run as a closed-loop
system with the DIMM temperature sensors as the control input. Otherwise, the system
does not change any of the throttling control registers in the embedded memory
controller during runtime.
4.3.2 Fan Speed Control
BIOS and BMC software work cooperatively to implement system thermal management support.
During normal system operation, the BMC will retrieve information from the BIOS and monitor
several platform thermal sensors to determine the required fan speeds.
In order to provide the proper fan speed control for a given system configuration, the BMC must
have the appropriate platform data programmed. Platform configuration data is programmed
using the FRUSDR utility during the system integration process and by System BIOS during run
time.
4.3.2.1 System Configuration Using the FRUSDR Utility
The Field Replaceable Unit and Sensor Data Record Update Utility (FRUSDR utility) is a
program used to write platform-specific configuration data to NVRAM on the server board. It
allows the user to select which supported chassis (Intel® or non-Intel®) and platform chassis
configuration is used. Based on the input provided, the FRUSDR writes sensor data specific to
the configuration to NVRAM for the BMC controller to read each time the system is powered on.
4.4 Intel
®
Intelligent Power Node Manager
4.4.1 Overview
Power management deals with requirements to manage processor power consumption and
manage power at the platform level to meet critical business needs. Node Manager (NM) is a
platform resident technology that enforces power capping and thermal-triggered power capping
policies for the platform. These policies are applied by exploiting subsystem knobs (such as
processor P and T states) that can be used to control power consumption. NM enables data
center power management by exposing an external interface to management software through
which platform policies can be specified. It also implements specific data center power
management usage models such as power limiting, and thermal monitoring.
The NM feature is implemented by a complementary architecture utilizing the ME, Integrated
BMC, BIOS, and an ACPI-compliant OS. The ME provides the NM policy engine and power
control/limiting functions (referred to as Node Manager or NM) while the Integrated BMC
provides the external LAN link by which external management software can interact with the
feature. The BIOS provides system power information utilized by the NM algorithms and also
exports ASL code used by OSPM for negotiating processor P and T state changes for power
limiting. PMBus*-compliant power supplies provide the capability to monitoring input power
consumption, which is necessary to support NM.
The NM architecture applicable to this generation of servers is defined by the NPTM
Architecture Specification v2.0. NPTM is an evolving technology that is expected to continue to
add new capabilities that will be defined in subsequent versions of the specification. The ME NM
implements the NPTM policy engine and control/monitoring algorithms defined in the NPTM
specification.
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Task
Capabilities and Features
2.0
Monitor Power
and Thermal
Platform power monitoring
Thermal monitoring and thermal policy support
Processor package power monitoring
Memory power monitoring
Control Power
Utilization
Power limiting policy support
Platform
Processor power limiting
Memory power limiting
Dynamic core allocation (runtime core-idling)
Configure core power off at boot time
Configure power-optimized boot at boot time
Delegate Power
and Thermal
Policy
Concurrent policies
Limit power upon power excursion (OS operational)
Reduce power upon temperature excursion
Limit power even when OS is not operational (OS failure)
Avoid Triggering
HW Protection
Reduce power consumption to prevent tripping DC circuit breaker
Power supply optimization technologies (SmaRT and CLST) used
to limit power consumption to reduce demand on power supplies in
specific scenarios.
Interfaces
IPMI-based commands over SMBus* (monitoring, control and
alert)
PECI Proxy and Pass-Through (this feature is also available on the
ME Si-Enabling firmware)
Power telemetry from Integrated BMC or from PMBus*-compliant
power supplies
Note: EPSD systems have ME get power data directly from power
supplies
4.4.2 Features
NM provides feature support for policy management, monitoring, and querying, alerts and
notifications, and an external interface protocol. The policy management features implement
specific IT goals that can be specified as policy directives for NM. Monitoring and querying
features enable tracking of power consumption. Alerts and notifications provide the foundation
for automation of power management in the data center management stack. The external
interface specifies the protocols that must be supported in this version of NM.
The table below summarizes the feature support for NM 2.0:
Table 13. NM Features
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4.4.3 Role of Integrated BMC in NM
This section summarizes the Integrated BMC role in the NM feature implementation.
4.4.3.1 External Communications Link
The Integrated BMC provides the access point for remote commands from external
management software and generates alerts to that software. The ME plays the role of an IPMI
satellite controller that communicates to the Integrated BMC over a secondary IPMB. There are
mechanisms to forward commands to ME and send response back to originator. Similarly
events generated by ME to the Integrated BMC (through IPMB) have to be sent by the
Integrated BMC to the external software over the LAN link. It is the responsibility of Integrated
BMC to implement these mechanisms for communication with Node Manager (NM).
4.4.3.1.1 Command Passing Through Integrated BMC
External software wishing to communicate with the NM will send ‘bridged’ IPMI commands to
Integrated BMC. This will be in the form an IPMI packet encapsulated in another packet,
following standard IPMI bridging as described in the IPMI 2.0 Specification. Integrated BMC
forwards the encapsulated command it to NM engine on the ME and returns the response to the
sender.
Due to the fact that some of the NM commands have potential for performance limiting and
system shut-down, the Integrated BMC firmware enforce an administrator privilege for any
commands bridged to the ME.
4.4.3.1.2 Alerting
Alerts may be sent from the NM in the ME to the external software by one of two different
methods depending on the nature of the alert.
Alerts that signify fault conditions that should be recorded in the system SEL will be sent to the
Integrated BMC by the ME using the IPMI Platform Event Message command. The Integrated
BMC deposits such events into the SEL. The external software must configure the Integrated
BMC’s PEF and alerting features to then send that event out as an IPMI LAN alert, directed to
the software application over the LAN link.
Alerts that provide useful notification to the external software for NM management, but do not
represent significant fault conditions that need to be put into the SEL, will be sent to the
Integrated BMC using the IPMI Alert Immediate command. This requires that the external
software application provide the NM on the ME with the alert destination and alert string
information needed to properly form and send the alert. The external software must first properly
configure the alert destination and string in the Integrated BMC LAN configuration using
standard IPMI commands, then provide the associated selectors to the Integrated BMC using
the Set Node Manager Alert Destination OEM command.
4.4.3.2 BIOS-Integreated BMC-ME Communication
In this generation of platforms, the BIOS communicates directly with the ME through HECI.
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5. Server Management Capability for Intel
®
Server Board
S1200BTS
5.1 Supper I/O
5.1.1 Key Features of supper I/O
The W83627DHG-P is from the Nuvoton*’s Super I/O product line. This family features the LPC
(Low Pin Count) interface. This interface is more economical than its ISA counterpart. It has
approximately 40 pins less, yet it provides as great performance. In addition, the improvement
allows even more efficient operation of software, BIOS, and device drivers.
The W83627DHG-P provides the following key features:
Meet LPC Spec. 1.01
Integrated hardware monitor functions
Support ACPI (Advanced Configuration and Power Interface)
Support up to 2 16550-compatible UARTs ports
8042-based keyboard controller
Smart Fan control system
Five fan-speed monitoring inputs
Four fan-speed controls
GPIO
Support PECI 1.0 and 1.1a Specifications
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6. BIOS User Interface
6.1 BIOS POST Initialization
6.1.1 BIOS Revision Identification
6.1.1.1 BIOS ID String
The BIOS Identification string is used to uniquely identify the revision of the BIOS being used on
the server. The BIOS ID string is displayed on the Power On Self-Test (POST) diagnostic
screen and in Setup and System Management BIOS (SMBIOS) structures.
The BIOS ID string is formatted as follows:
6.1.1.2 BoardFamilyID.OEMID.MajorVer.RelRev.RelNum.BuildDateTime
Where:
BoardFamilyID = String name for to identify board family.
- S1200BT is used to identify BIOS builds for S1200BT server boards.
OEMID = Three-character OEM BIOS Identifier, to identify the board BIOS owner.
Changed only if and when BIOS Development management authorizes a BIOS program
for a specific OEM customer.
- 86B is used for BIOS Releases.
MajorVer = Major Version, two decimal digits 01-99 which are changed only to identify
major hardware or functionality changes that affect BIOS compatibility between boards.
- 01 is the starting BIOS Major Version for all platforms. This designation can change only
at the discretion of BIOS Development management.
RelRev = Release Revision, two decimal digits 00-99 which are changed to identify
specific point releases or branches based on a given BIOS Release but with targeted
minor fixes or special-purpose differences in functionality from the primary BIOS
Release. The Release Revision first digit is incremented for each initial revision of a
BIOS Release. The second digit will increment only if a revision itself needs to be
revised with a change or fix. The Release Number will not change when a BIOS is built
as a Release Revision and will reset to “00” with each new Release Number.
- 00 is the starting Release Revision for all platform BIOS Releases. Release Revisions
are not Standard Operating Procedure, but may be produced if authorized BIOS
management.
The sequence will be as in the following examples for Release Revision and Release Number:
Release 2 (that is, 2.0) = RelRev/RelNum “.00.0002”
Release 2 Revision 1(that is, 2.1) = RelRev/RelNum “.10.0002”
Release 2 Revision 1 fix 1 (that is, 2.11) = RelRev/RelNum “.11.0002”
Release 3 (that is, 3.0) = reverts to RelRev/RelNum “.00.0003”
RelNum = Release Number, four decimal digits which are changed to identify distinct
BIOS Releases. BIOS Releases are major collections of fixes and changes in
functionality
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HotKey Combination
Function
<F2>
Enter Setup
<F6>
Pop up BIOS Boot Menu
<F12>
Network boot
- 0001 is the starting Release Number for all platform BIOS releases, for each distinct
BoardFamilyID and OEMID. This number increases by 1 for each BIOS release. It
does not increment for a Release Revision. It resets to 0001 when the Major Version
changes, or for a different BoardFamilyID or OEMID.
BuildDateTime = Build timestamp – date and time in MMDDYYYYHHMM format:
- MM = Two-digit month.
- DD = Two-digit day of month.
- YYYY = Four-digit year.
- HH = Two-digit hour using 24-hour clock.
- MM = Two-digit minute.
For example, the following BIOS ID string is displayed on the POST diagnostic screen for BIOS
Release 3 that is generated on August 13, 2010 at 11:56 AM:
S1200BT.86B.01.00.0003.081320101156
The BIOS version in the Setup Utility is displayed without the time/date timestamp, which is
displayed separately as “Build Date”:
S1200BT.86B.01.00.0003
For the SMBIOS Type 0 BIOS Version field, the full BIOS ID string is used, including the
complete timestamp.
6.1.1.3 OEM BIOS Differentiation Support
There is an optional “OEM Extension” segment which can be added by an OEM customer to
distinguish an OEM-specific edited version of the BIOS from a standard Intel® version. This
“OEM Extension” will never be present in a standard BIOS supplied directly by Intel®. This can
only be done using a restricted-distribution BIOS utility available through Technical Marketing
OEM support channels.
6.2 HotKeys Supported During POST
Certain “HotKeys” are recognized during POST. A HotKey a key or key combination that is
recognized as an unprompted command input, that is, the operator is not prompted to press the
HotKey and typically the HotKey will be recognized even while other processing is in progress.
The Server Board BIOS recognizes a number of HotKeys during POST. After the OS is booted,
HotKeys are the responsibility of the OS and the OS defines its own set of recognized HotKeys.
Following are the POST HotKeys, with the functions they cause to be performed.
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6.3 POST Logo Screen/Diagnostic Screen
The Logo Screen/Diagnostic Screen appears in one of two forms:
If Quiet Boot is enabled in the BIOS setup, a splash screen is displayed with a logo
image, which is the standard Intel® Logo Screen or a customized OEM Logo Screen. By
default, Quiet Boot is enabled in the BIOS setup, so the Logo Screen will be the default
POST display. However, if the logo is displayed during POST, the user can press <Esc>
to hide the logo and display the Diagnostic Screen instead.
If a logo is not present in the BIOS Flash Memory space, or if Quiet Boot is disabled in
the system configuration, the POST Diagnostic Screen is displayed with a summary of
system configuration information.
The diagnostic screen displays the following information:
Copyright <year> Intel Corporation
AMI Copyright statement
BIOS version (ID)
BMC firmware version
SDR version
ME firmware version
Platform ID (identifies the board on which the BIOS is running
System memory detected (total size of all installed DDR3 DIMMs)
Current memory speed (currently configured memory operating frequency)
Processor information (Intel® Brand String identifying type of processor and nominal
operating frequency, and number of physical processors identified)
Keyboards detected, if any attached
Mouse devices detected, if any attached
Instructions showing hotkeys for going to Setup, going to popup Boot Menu, starting
Network Boot
6.4 BIOS Boot Pop-up Menu
The BIOS Boot Specification (BBS) provides a Boot Pop-up menu that can be invoked by
pressing the <F6> key during POST. The BBS Pop-up menu displays all available boot devices.
The boot order in the pop-up menu is not the same as the boot order in the BIOS setup. The
pop-up menu simply lists all of the available devices from which the system can be booted, and
allows a manual selection of the desired boot device.
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When an Administrator password is installed in Setup, the Administrator password will be
required in order to access the Boot Pop-up menu using the <F6> key. If a User password is
entered, the Boot Pop-up menu will not even appear – the user will be taken directly to the Boot
Manager in the Setup, where a User password allows only booting in the order previously
defined by the Administrator.
6.5 BIOS Setup Utility
The BIOS Setup utility is a text-based utility that allows the user to configure the system and
view current settings and environment information for the platform devices. The Setup utility
controls the platform's built-in devices, the boot manager, and error manager.
The BIOS Setup interface consists of a number of pages or screens. Each page contains
information or links to other pages. The advanced tab in Setup displays a list of general
categories as links. These links lead to pages containing a specific category’s configuration.
The following sections describe the look and behavior for the platform setup.
6.5.1 BIOS Setup Operation
The BIOS Setup Utility has the following features:
Localization – The Intel® Server Board BIOS is only available in English. However, BIOS
Setup uses the Unicode standard and is capable of displaying data and input in Setup
fields in all languages currently included in the Unicode standard.
Console Redirection –BIOS Setup is functional through Console Redirection over
various terminal emulation standards.
Setup screens are designed to be displayable in an 80-character x 24-line format in
order to work with Console Redirection, although that screen layout should display
correctly on any format with longer lines or more lines on the screen.
Password protection – BIOS Setup may be protected from unauthorized changes by
setting an Administrative Password in the Security screen. When an Administrative
Password has been set, all selection and data entry fields in Setup (except System Time
and Date) are grayed out and cannot be changed unless the Administrative Password
has been entered.
Note: If an Administrative Password has not been set, anyone who boots the system to Setup
has access to all selection and data entry fields in Setup and can change any of them.
6.5.1.1 Setup Page Layout
The Setup page layout is sectioned into functional areas. Each occupies a specific area of the
screen and has dedicated functionality. The following table lists and describes each functional
area.
The Setup page is designed to a format of 80 x 24 (24 lines of 80 characters each). The typical
display screen in a Legacy mode or in a terminal emulator mode is actually 80 characters by 25
lines, but with line wrap enabled (which it usually is) the 25th line cannot be used with the Setup
page.
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Functional Area
Description
Title Bar
The title bar is located at the top of the screen and displays the title of the form
(page) the user is currently viewing. It may also display navigational information.
Setup Item List
The Setup Item List is a set of control entries and informational items. The list is
displayed in two columns. For each item in the list, a prompt string (or label string)
occupies the left column of the list, and the right column contains either a data
display, a data input field, or a multiple choice field. The operator navigates up and
down the right hand column through the available input or choice fields.
A Setup Item may also represent a selection to open a new screen with a further
group of options for specific functionality. In this case, the operator navigates to the
desired selection and presses <Enter> to go to the new screen.
Item-Specific Help Area
The Item-specific Help area is located on the right side of the screen and contains
help text for the highlighted Setup Item. Help information may include the meaning
and usage of the item, allowable values, effects of the options, and so on.
Keyboard Command Bar
The Keyboard Command Bar is located at the bottom right of the screen and
continuously displays help for keyboard special keys and navigation keys.
Key
Option
Description
<Enter>
Execute
Command
The <Enter> key is used to activate submenus when the selected feature is a
submenu, or to display a pick list if a selected option has a value field, or to select a
subfield for multi-valued features like time and date. If a pick list is displayed, the
<Enter> key selects the currently highlighted item, undoes the pick list, and returns
the focus to the parent menu.
Table 15. BIOS Setup Page Layout
6.5.1.2 Entering BIOS Setup
To enter the BIOS Setup using a keyboard (or emulated keyboard); press the <F2> function key
during boot time when the OEM or Intel® logo is displayed. The following message is displayed
on the diagnostics screen and under the Quiet Boot logo screen:
Press <F2> to enter setup
When the Setup Utility is entered, the Main screen is displayed. However, serious errors cause
the system to display the Error Manager screen instead of the Main screen.
6.5.1.3 Setup Navigation Keyboard Commands
The bottom right portion of the Setup screen provides a list of commands that are used to
navigate through the Setup utility. These commands are displayed at all times.
Each Setup menu page contains a number of features. Each feature is associated with a value
field, except those used for informative purposes. Each value field contains configurable
parameters. Depending on the security option chosen and in effect by the password, a menu
feature’s value may or may not be changed. If a value cannot be changed, its field is made
inaccessible and appears grayed out.
Table 16. BIOS Setup: Keyboard Command Bar
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Key
Option
Description
<Esc>
Exit
The <Esc> key provides a mechanism for backing out of any field. When the <Esc>
key is pressed while editing any field or selecting features of a menu, the parent
menu is re-entered.
When the <Esc> key is pressed in any submenu, the parent menu is re-entered.
When the <Esc> key is pressed in any major menu, the exit confirmation window is
displayed and the user is asked whether changes can be discarded. If “No” is
selected and the <Enter> key is pressed, or if the <Esc> key is pressed, the user is
returned to where they were before <Esc> was pressed, without affecting any
existing settings. If “Yes” is selected and the <Enter> key is pressed, the setup is
exited and the BIOS returns to the main System Options Menu screen.
Select Item
The up arrow is used to select the previous value in a pick list, or the previous
option in a menu item's option list. The selected item must then be activated by
pressing the <Enter> key.
Select Item
The down arrow is used to select the next value in a menu item’s option list, or a
value field’s pick list. The selected item must then be activated by pressing the
<Enter> key.
Select Menu
The left and right arrow keys are used to move between the major menu pages.
The keys have no effect if a sub-menu or pick list is displayed.
<Tab>
Select Field
The <Tab> key is used to move between fields. For example, <Tab> can be used
to move from hours to minutes in the time item in the main menu.
-
Change Value
The minus key on the keypad is used to change the value of the current item to the
previous value. This key scrolls through the values in the associated pick list
without displaying the full list.
+
Change Value
The plus key on the keypad is used to change the value of the current menu item
to the next value. This key scrolls through the values in the associated pick list
without displaying the full list. On 106-key Japanese keyboards, the plus key has a
different scan code than the plus key on the other keyboards, but will have the
same effect.
<F9>
Setup Defaults
Pressing the <F9> key causes the following to display:
Load Optimized Defaults?
Yes No
If “Yes” is highlighted and <Enter> is pressed, all Setup fields are set to their
default values. If “No” is highlighted and <Enter> is pressed, or if the <Esc> key is
pressed, the user is returned to where they were before <F9> was pressed without
affecting any existing field values.
<F10>
Save and Exit
Pressing the <F10> key causes the following message to display:
Save configuration and reset?
Yes No
If “Yes” is highlighted and <Enter> is pressed, all changes are saved and the Setup
is exited. If “No” is highlighted and <Enter> is pressed, or the <Esc> key is
pressed, the user is returned to where they were before <F10> was pressed
without affecting any existing values.
6.5.1.4 Setup Screen Menu Selection Bar
The Setup Screen Menu selection bar is located at the top of the BIOS Setup Utility screen. It
displays tabs showing the major screen selections available to the user. By using the left and
right arrow keys, the user can select the listed screens. Some screen selections are out of the
visible menu space, and become available by scrolling to the left or right of the current
selections displayed.
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6.5.2 BIOS Setup Utility Screens
The following sections describe the screens available in the BIOS Setup utility for the
configuration of the server platform.
For each of these screens, there is an image of the screen with a list of Field Descriptions which
describe the contents of each item on the screen. Each item on the screen is hyperlinked to the
relevant Field Description. Each Field Description is hyperlinked back to the screen image.
These lists follow the following guidelines:
The text heading for each Field Description is the actual text as displayed on the BIOS
Setup screen. This screen text is a hyperlink to its corresponding Field Description.
The text shown in the Option Values and Help Text entries in each Field Description are
the actual text and values are displayed on the BIOS Setup screens.
In the Option Values entries, the text for default values is shown with an underline.
These values do not appear underline on the BIOS Setup screen. The underlined text in
this document is to serve as a reference to which value is the default value.
The Help Text entry is the actual text which appears on the screen to accompany the
item when the item is the one in focus (active on the screen).
The Comments entry provides additional information where it may be helpful. This
information does not appear on the BIOS Setup screens.
Information enclosed in angular brackets (< >) in the screen shots identifies text that can
vary, depending on the option(s) installed. For example, <Amount of memory installed>
is replaced by the actual value for “Total Memory”.
Information enclosed in square brackets ([ ]) in the tables identifies areas where the user
must type in text instead of selecting from a provided option.
Whenever information is changed (except Date and Time), the systems requires a save
and reboot to take place in order for the changes to take effect. Alternatively, pressing
<ESC> discards the changes and resumes POST to continue to boot the system
according to the boot order set from the last boot.
6.5.2.1 Map of Screens and Functionality
There are a number of screens in the entire Setup collection. They are organized into major
categories. Each category has a hierarchy beginning with a top-level screen from which lowerlevel screens may be selected. Each top-level screen appears as a tab, arranged across the top
of the Setup screen image of all top-level screens.
There are more categories than will fit across the top of the screen, so at any given time there
will be some categories which will not appear until the user has scrolled across the tabs which
are present.
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Categories (Top Tabs)
Second Level Screens
Third Level Screens
Main Screen (Tab) — —
Advanced Screen (Tab)
—
—
Processor Configuration
—
Memory Configuration
—
Mass Storage Controller
Configuration
—
Serial Port Configuration
—
USB Configuration
—
PCI Configuration
—
System Acoustic and
Performance Configuration
—
Security Screen (Tab)
—
—
Server Management Screen
(Tab)
—
—
Console Redirection
— System Information
—
[With BMC Only]
BMC LAN Configuration
—
[Non-BMC Only]
Hardware Monitor
—
—
[Non-BMC Only]
Real-time Temperature and
Voltage Status
The categories and the screens included in each category are listed below, with links to each of
the screens named.
Table 17. Screen Map
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Categories (Top Tabs)
Second Level Screens
Third Level Screens
Boot Options Screen (Tab)
—
Hard Disk Order
—
CDROM Order
—
Floppy Order
—
Network Device Order
—
BEV Device Order
—
Add EFI Boot Option
—
Delete EFI Boot Option
—
Boot Manager Screen (Tab)
—
—
Error Manager Screen (Tab)
—
—
System Event Log Screen (Tab)
[Non-BMC Only]
—
—
Exit Screen (Tab)
—
—
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Main
Advanced
Security
Server Management
Boot Options
Boot Manager
Logged in as:
Administrator/User
Platform ID
<Platform Identification String>
System BIOS
BIOS Version
<Platform.86B.xx.yy.zzzz>
Build Date
<MM/DD/YYYY>
Memory
Total Memory
<Amount of memory installed>
Quiet Boot
Enabled/Disabled
POST Error Pause
Enabled/Disabled
System Date
[Day MM/DD/YYYY]
System Time
[HH:MM:SS]
6.5.2.2 Main Screen (Tab)
The Main Screen is the first screen that appears when the BIOS Setup configuration utility is
entered, unless an error has occurred. If an error has occurred, the Error Manager Screen
appears instead.
Figure 15. Main Screen
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Screen Field Descriptions:
1. Logged in as:
Option Values: <Administrator/User>
Help Text: <None>
Comments: Information only. Displays password level that setup is running in:
Administrator or User. With no passwords set, Administrator is the default mode.
2. Platform ID
Option Values: < Platform ID>
Help Text: <None>
Comments: Information only. Displays the Platform ID for the board on which the
BIOS is executing POST.
3. BIOS Version
Option Values: <Current BIOS version ID>
Help Text: <None>
Comments: Information only. The version information displayed is taken from the
BIOS ID String, with the timestamp segment dropped off. The segments displayed are:
Platform: Identifies whether this is a platform BIOS
86B: Identifies this BIOS as being an EPSD Server BIOS
xx: Major Revision level of the BIOS
yy: Release Revision level for this BIOS
zzzz: Release Number for this BIOS
4. Build Date
Option Values: <Date and time when the currently installed BIOS was created
(built)>
Help Text: <None>
Comments: Information only. The time and date displayed are taken from the
timestamp segment of the BIOS ID String.
5. Total Memory
Option Values: <Amount of memory installed in the system>
Help Text: <None>
Comments: Information only. Displays the total physical memory installed in the
system, in MB or GB. The term physical memory indicates the total memory discovered
in the form of installed DDR3 DIMMs.
6. Quiet Boot
Option Values: Enabled
Disabled
Help Text:
[Enabled] – Display the logo screen during POST.
[Disabled] – Display the diagnostic screen during POST.
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7. POST Error Pause
Option Values: Enabled
Disabled
Help Text:
[Enabled] – Go to the Error Manager for critical POST errors.
[Disabled] – Attempt to boot and do not go to the Error Manager for critical POST
errors.
Comments: If enabled, the POST Error Pause option takes the system to the error
manager to review the errors when major errors occur. Minor and fatal error displays are
not affected by this setting.
8. System Date
Option Values: <System Date initially displays the current system calendar date,
including the day of the week>
Help Text:
System Date has configurable fields for the current Month, Day, and Year.
The year must be between 2005 and 2099.
Use [Enter] or [Tab] key to select the next field.
Use [+] or [-] key to modify the selected field.
Comments: This field will initially display the current system day of week and date. It
may be edited to change the system date.
9. System Time
Option Values: <System Time initially displays the current system time of day, in
24-hour format>
Help Text:
System Time has configurable fields for Hours, Minutes, and Seconds.
Hours are in 24-hour format.
Use the [Enter] or [Tab] key to select the next field.
Use the [+] or [-] key to modify the selected field.
Comments: This field will initially display the current system time (24 hour time). It
may be edited to change the system time.
6.5.2.3 Advanced Screen (Tab)
The Advanced screen provides an access point to configure several groups of options. On this
screen, the user can select the option group to be configured. Configuration actions are
performed on the selected screen, and not directly on the Advanced screen.
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Main
Advanced
Security
Server Management
Boot Options
Boot Manager
► Processor Configuration
► Memory Configuration
► PCI Configuration
► Mass Storage Controller Configuration
► Serial Port Configuration
► USB Configuration
► System Acoustic and Performance Configuration
► Hardware Monitor
To access this screen from the Main screen or other top-level “Tab” screen, press the right or
left arrow keys to traverse the tabs at the top of the Setup screen until the Advanced screen is
selected.
Figure 16. Advanced Screen
Screen Field Descriptions:
1. Processor Configuration
Option Values: <None>
Help Text: View/Configure processor information and settings.
Comments: Selection only. Position to this line and press the <Enter> key to go to the
Processor Configuration group of configuration settings.
2. Memory Configuration
Option Values: <None>
Help Text:
View/Configure memory information and settings.
Comments: Selection only. Position to this line and press the <Enter> key to go to the
Memory Configuration group of configuration settings.
3. Mass Storage Controller Configuration
Option Values: <None>
Help Text:
View/Configure mass storage controller information and settings.
Comments: Selection only. Position to this line and press the <Enter> key to go to the
Mass Storage Controller Configuration group of configuration settings.
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4. Serial Port Configuration
Option Values: <None>
Help Text:
View/Configure serial port information and settings.
Comments: Selection only. Position to this line and press the <Enter> key to go to the
Serial Port Configuration group of configuration settings.
5. USB Configuration
Option Values: <None>
Help Text:
View/Configure USB information and settings.
Comments: Selection only. Position to this line and press the <Enter> key to go to the
USB Configuration group of configuration settings.
6. PCI Configuration
Option Values: <None>
Help Text:
View/Configure PCI information and settings.
Comments: Selection only. Position to this line and press the <Enter> key to
go to the PCI Configuration group of configuration settings.
7. System Acoustic and Performance Configuration
Option Values: <None>
Help Text:
View/Configure system acoustic and performance information and settings.
Comments: Selection only. Position to this line and press the <Enter> key to
go to the System Acoustic and Performance Configuration group of configuration
settings.
8. Hardware Monitor
Help Text:
The Hardware Monitor screen allows the user to configure Fan Speed Control
and to view displays of temperature and voltage status.
This screen is present only for boards without a BMC. There are two screen layouts,
depending on whether Auto or Manual Fan Control is selected on the screen. “Auto” Fan
Control is intended to support standard EPSD chassis options. “Manual” Fan Control is
intended to support third-party chassis installations.
To access this screen from the Main screen, select Server Management > Hardware
Monitor. To move to another screen, press the <Esc> key to return to the Server
Management screen, then select the desired screen.
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Advanced
Processor Configuration
Processor ID
<CPUID>
stepping Processor Frequency
<Proc Freq>
Microcode Revision
<Rev data>
L1 Cache RAM
<L1 Cache Size>
L2 Cache RAM
<L2 Cache Size>
L3 Cache RAM
<L3 Cache Size>
Processor Version
<ID string from processor>
CPU Core Ratio Settings
Show CPU Core Ratio
<63>
Enabled/Disabled
Intel® Turbo Boost Technology
Enabled/Disabled
Enhanced Intel® SpeedStep® Tech
Enabled/Disabled
Turbo Boost Performance/Watt Mode
Power Optimized/Traditional
Processor C3
Enabled/Disabled
Processor C6
Enabled/Disabled
Intel® Hyper-Threading Tech
Enabled/Disabled
Core Multi-Processing
All/1/2/3
Execute Disable Bit
Enabled/Disabled
Intel® Virtualization Technology
Enabled/Disabled
Intel® VT for Directed I/O
Enabled/Disabled
Interrupt Remapping
Enabled/Disabled
Pass-through DMA Support
Intel® TXT
Enabled/Disabled
Enabled/Disabled
MLC Streamer
Enabled/Disabled
MLC Spatial Prefetcher
Enabled/Disabled
DCU Data Prefetcher
Enabled/Disabled
DCU Instruction Prefetcher
Enabled/Disabled
Intel® (SMX) Safer Mode Extensions
Enabled/Disabled
6.5.2.4 Processor Configuration
The Processor Configuration screen displays the processor identification and microcode level,
core frequency, cache sizes, Intel® QuickPath Interconnect information for all processors
currently installed. It also allows the user to enable or disable a number of processor options.
To access this screen from the Main screen, select Advanced > Processor Configuration. To
move to another screen, press the <Esc> key to return to the Advanced screen, then select the
desired screen.
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Screen Field Descriptions:
1. Processor ID
Option Values: <CPUID>
Help Text: <None>
Comments: Information only. Displays the Processor Signature value (from the
CPUID instruction) identifying the type of processor and the stepping Processor
Frequency.
Option Values: <Current Processor Operating Frequency>
Help Text: <None>
Comments: Information only. Displays current operating frequency of the processor.
2. Microcode Revision
Option Values: <Microcode Revision Number>
Help Text: <None>
Comments: Information only. Displays Revision Level of the currently loaded
processor microcode.
3. L1 Cache RAM
Option Values: <L1 cache size>
Help Text: <None>
Comments: Information only. Displays size in KB of the processor L1 Cache. Since L1
cache is not shared between cores, this is shown as the amount of L1 cache per core.
There are two types of L1 cache., This amount is the total of L1 Instruction Cache plus
L1Data Cache for each core.
4. L2 Cache RAM
Option Values: <L2 cache size>
Help Text: <None>
Comments: Information only. Displays size in KB of the processor L2 Cache. Since L2
cache is not shared between cores, this is shown as the amount of L2 cache per core.
5. L3 Cache RAM
Option Values: <L3 cache size>
Help Text: <None>
Comments: Information only. Displays size in MB of the processor L3 Cache. Since
L3 cache is shared between all cores in a processor package, this is shown as the total
amount of L3 cache per processor package. S1200BT boards have a single processor
display. Romley boards have “N/A” for the second processor if not installed.
6. Processor Version
Option Values: <ID string from processor>
Help Text: <None>
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Comments: Information only. Displays Brand ID string read from processor with
CPUID instruction.
7. Show CPU Core Ratio
Option Values: Enabled
Disabled
Help Text:
Enable/Disable CPU Core Ratio Settings
Comments: If this option is enabling, CPU core ratio will be limited to the value in the CPU
Core Ratio Settings.
8. CPU Core Ratio Settings
Option Values: 0-63, default is 63
Help Text:
This value must between Maximum Efficiency Ratio (LFM) and Maximum non-turbo ratio
set by Hardware (HFM).
Comments: This option is only visible if Show CPU Core Ratio is Enabled.
9. Intel® Turbo Boost Technology
Option Values: Enabled
Disabled
Help Text:
Intel® Turbo Boost Technology allows the processor to automatically increase its
frequency if it is running below power, temperature, and current specifications.
Comments: This option is only visible if all processors installed in the system support
Intel® Turbo Boost Technology. In order for this option to be available, Enhanced Intel®
SpeedStep® Technology must be Enabled.
10. Enhanced Intel® SpeedStep® Tech
Option Values: Enabled
Disabled
Help Text:
Enhanced Intel® SpeedStep® Technology allows the system to dynamically
adjust processor voltage and core frequency, which can result in decreased
average power consumption and decreased average heat production.
Contact your OS vendor regarding OS support of this feature.
Comments: When Disabled, the processor setting reverts to running at Max TDP Core
Frequency (rated frequency).
This option is only visible if all processors installed in the system support Enhanced
Intel® SpeedStep® Technology. In order for the Intel® Turbo Boost option to be available,
Enhanced Intel® SpeedStep® Technology must be Enabled.
11. Turbo Boost Performance/Watt Mode
Option Values: Power Optimized
Traditional
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Help Text:
When Power Optimized is selected, Intel® Turbo Boost Technology engages after
performance state P0 is sustained for more than two seconds. When Traditional
is selected, Intel® Turbo Boost Technology is engaged even for P0 requests less
than two seconds.
Comments: Turbo Boost Power Optimization is not available on all processors, and is
available only when Intel® Turbo Boost Technology and Enhanced Intel® SpeedStep®
Technology are Enabled.
12. Processor C3
Option Values: Enabled
Disabled
Help Text:
Enable/Disable Processor C3 (ACPI C2/C3) report to OS
Comments: This is normally Disabled, but can be Enabled for improved performance
on certain benchmarks and in certain situations.
13. Processor C6
Option Values: Enabled
Disabled
Help Text:
Enable/Disable Processor C6 (ACPI C3) report to OS
Comments: This is normally Enabled but can be Disabled for improved performance
on certain benchmarks and in certain situations.
14. Intel® Hyper-Threading Tech
Option Values: Enabled
Disabled
Help Text:
Intel® Hyper-Threading Technology allows multithreaded software applications to
execute threads in parallel within each processor.
Contact your OS vendor regarding OS support of this feature.
Comments: This option is only visible if all processors installed in the system support
Intel® Hyper-Threading Technology.
15. Core Multi-Processing
Option Values: All
2
4
Help Text:
Enable 1, 2, 3, 4, 5, 6, 7 or all cores of installed processor packages.
Comments: The number of cores that appear as selections and in the Help text
depends on the number of cores in the processors installed.
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16. Execute Disable Bit
Option Values: Enabled
Disabled
Help Text:
Execute Disable Bit can help prevent certain classes of malicious buffer overflow
attacks.
Contact your OS vendor regarding OS support of this feature.
Comments: This option is only visible if all processors installed in the system
support the Execute Disable Bit. The OS and applications installed must support this
feature in order for it to be enabled.
17. Intel® Virtualization Technology
Option Values: Enabled
Disabled
Help Text:
Intel® Virtualization Technology allows a platform to run multiple operating
systems and applications in independent partitions.
Note: A change to this option requires the system to be powered off and then back on before
the setting takes effect.
Comments: This option is only visible if all processors installed in the system support
Intel® VT. The software configuration installed on the system must support this feature in
order for it to be enabled.
18. Intel® VT for Directed I/O
Option Values: Enabled
Disabled
Help Text:
Enable/Disable Intel® Virtualization Technology for Directed I/O (Intel® VT-d).
Report the I/O device assignment to VMM through DMAR ACPI Tables.
Comments: This option is only visible if all processors installed in the system support
Intel® VT-d. The software configuration installed on the system must support this feature
in order for it to be enabled.
19. Interrupt Remapping
Option Values: Enabled
Disabled
Help Text:
Enable/Disable Intel® VT-d Interrupt Remapping support.
Comments: This option only appears when Intel® Virtualization Technology for
Directed I/O is Enabled.
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20. ATS Support
Option Values: Enabled
Disabled
Help Text:
Enable/Disable Intel® VT-d Address Translation Services (ATS) support.
Comments: This option only appears when Intel® Virtualization Technology for
Directed I/O is Enabled. Appears only on Romley boards.
21. Pass-through DMA Support
Option Values: Enabled
Disabled
Help Text:
Enable/Disable Intel® VT-d Pass-through DMA support.
Comments: This option only appears when Intel® Virtualization Technology for
Directed I/O is Enabled.
22. MLC Streamer
Option Values: Enabled
Disabled
Help Text:
MLC Streamer is a speculative prefetch unit within the processor(s).
Note: Modifying this setting may affect performance.
Comments: MLC Streamer is normally Enabled for the best efficiency in L2 Cache
and Memory Channel use, but disabling it may improve performance for some
processing loads and on certain benchmarks.
23. MLC Spatial Prefetcher
Option Values: Enabled
Disabled
Help Text:
[Enabled] – Fetches adjacent cache line (128 bytes) when required data is not
currently in cache.
[Disabled] - Only fetches cache line with data required by the processor (64
bytes).
Comments: MLC Spatial Prefetcher is normally Enabled, for best efficiency in L2
Cache and Memory Channel use, but disabling it may improve performance for some
processing loads and on certain benchmarks.
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24. DCU Data Prefetcher
Option Values: Enabled
Disabled
Help Text:
The next cache line will be prefetched into L1 data cache from L2 or system
memory during unused cycles if it sees that the processor core has accessed
several bytes sequentially in a cache line as data.
[Disabled] – Only fetches cache line with data required by the processor (64
bytes).
Comments: DCU Data Prefetcher is normally Enabled, for best efficiency in L1 Data
Cache and Memory Channel use, but disabling it may improve performance for some
processing loads and on certain benchmarks.
25. DCU Instruction Prefetcher
Option Values: Enabled
Disabled
Help Text:
The next cache line will be prefetched into L1 instruction cache from L2 or
system memory during unused cycles if it sees that the processor core has
accessed several bytes sequentially in a cache line as data. [Disabled] – Only
fetches cache line with data required by the processor (64 bytes).
Comments: DCU Data Prefetcher is normally Enabled, for best efficiency in L1 I
Cache and Memory Channel use, but disabling it may improve performance for some
processing loads and on certain benchmarks.
26. Intel® (SMX) Safer Mode Extensions
Option Values: Enabled
Disabled
Help Text:
When enabled, a SMX can utilize the additonal hardware capabilities provided by
Safer Mode Extensions.
Comments: Intel® (SMX) Safer Mode Extensions is set of CPU instructions used by
Intel® TXT software.
6.5.2.5 Memory Configuration
The Memory Configuration screen allows the user to view details about the DDR3 DIMMs that
are installed as system memory.
To access this screen from the Main screen, select Advanced > Memory Configuration. To
move to another screen, press the <Esc> key to return to the Advanced screen, then select the
desired screen.
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Advanced
Memory Configuration
Screen Field Descriptions:
Total Memory
<Total Physical Memory Installed in System>
Effective Memory
<Total Effective Memory>
Current Configuration
Single Channel/Dual Channel Symmetric/Intel® Flex
Current Memory Speed
<Operational Memory Speed in MT/s>
DIMM Information
DIMM_A1
Installed/Not Installed/Failed/Disabled
DIMM_A2
Installed/Not Installed/Failed/Disabled
DIMM_B1
Installed/Not Installed/Failed/Disabled
DIMM_B2
Installed/Not Installed/Failed/Disabled
Screen Field Descriptions:
1. Total Memory
Option Values: <Total Physical Memory Installed in System>
Help Text: <None>
Comments: Information only. Displays the amount of memory available in the
system in the form of installed DDR3 DIMMs, in units of GB.
2. Effective Memory
Option Values: <Total Effective Memory>
Help Text: <None>
Comments: Information only. Displays the amount of memory available to the
OS in MB or GB.
The Effective Memory is the difference between Total Physical Memory and the sum of
all memory reserved for internal usage, RAS redundancy and SMRAM. This difference
includes the sum of all DDR3 DIMMs that failed Memory BIST during POST or were
disabled by the BIOS during the memory discovery phase in order to optimize memory
configuration.
Figure 18. Memory Configuration Screen
Note: Some server operating systems do not display the total physical memory installed.
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3. Current Configuration
Option Values: Single Channel
Dual Channel Symmetric
Intel® Flex
Help Text: <None>
Comments: Displays one of the following:
Single Channel – DIMMs are operating in Single Channel mode. This is the
configuration when only one channel is populated with DIMMs.
Dual Channel Symmetric – DIMMs are operating in Dual Channel
Symmetric mode. This is the configuration when both channels are identically
populated with DIMMs.
Intel® Flex – DIMMs are configured according to Intel® Flex Memory
Technology, where part of the memory is in Dual Channel Symmetric mode
and part in Dual Channel Asymmetric mode. This is the configuration when
both channels are populated, but with unequal amounts of memory.
4. Current Memory Speed
Option Values: <Operational Memory Speed in MT/s>
Help Text: <None>
Comments: Information only. Displays the speed in MT/s at which the memory is
currently running.
For Intel® Xeon Processor E3-1200 Processors – supports memory speeds are 1066
MT/s and 1333 MT/s.
For Intel® Xeon Processor E3-1200 V2 Processors – supports memory speeds are 1333
MT/s and 1600 MT/s.
5. DIMM_A1
6. DIMM_A2
7. DIMM_B1
8. DIMM_B2
Option Values: Installed
Not Installed
Help Text: <None>
Comments: Information only, for S1200 boards: Displays the state of each
DIMM socket present on the board. Each DIMM socket field reflects one of the following
possible states:
Installed – There is a DDR3 DIMM installed in this slot.
Not Installed – There is no DDR3 DIMM installed in this slot.
Note: In “DIMM_XY”, X denotes the Channel Identifier A or-B, and Y denotes the DIMM Slot
identifier 1 or 2 within the Channel. DIMM_A2 is the DIMM socket on Channel A, Slot 2.
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Advanced
Mass Storage Controller Configuration
AHCI Capable SATA Controller
Enabled/Disabled
Configure SATA Mode
COMPATIBILITY/ENHANCED/AHCI/RAID Mode
RAID Mode Options
Intel
®
ESRT2 (LSI(TM)) / Intel
®
RST (Matrix)
Intel® Storage Module
None / <Name of Storage Module detected>
Configure AXX4SASMOD RAID Module
IT/IR / Intel® ESRT2 (LSI(TM))
SATA Port 0
Not Installed/<Drive Info.>
SATA Port 1
Not Installed/<Drive Info.>
SATA Port 2
Not Installed/<Drive Info.>
SATA Port 3
Not Installed/<Drive Info.>
SATA Port 4
Not Installed/<Drive Info.>
SATA Port 5
Not Installed/<Drive Info.>
6.5.2.6 Mass Storage Controller Configuration
The Mass Storage Configuration screen allows the user to configure the SATA or SAS controller
when it is present on the server board, midplane or backplane of an Intel® system.
To access this screen from the Main screen, select Advanced > Mass Storage Controller
Configuration. To move to another screen, press the <Esc> key to return to the Advanced
screen, then select the desired screen.
Figure 19. Mass Storage Controller Configuration Screen
1. AHCI Capable SATA Controller
Option Values: Enabled
Disabled
Help Text: AHCI capable SATA controller (also known as Onboard SATA Controller)
refers to the Advanced Host Controller Interface SATA device integrated into the chipset.
In order to utilize the AHCI capacities, the AHCI option needs to be enabled in the SATA
Mode menu.
Comments: If the SATA Controller is Enabled, then the mode of operation can be set
using following options. If it is Disabled, the SATA Ports will not operate and any
installed SATA devices will be unavailable.
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2. Configure SATA Mode
Option Values: Compatibility
Enhanced
AHCI
RAID Mode
Help Text:
[Compatibility] provides PATA emulation on the SATA device, allowing the use of
legacy IDE/PATA drivers.
[Enhanced] provides Native SATA support, using native SATA drivers included
with the vast majority of current operating systems.
[AHCI] enables the Advanced Host Controller Interface, which provides Enhanced
SATA functionality plus additional functionality such as Native Command Queuing.
Uses AHCI drivers available for the majority of current operating systems.
[RAID Mode] provides host based RAID support on the onboard SATA ports.
Comments: This option setting only appears when the SATA Controller is Enabled. In
order to use the AHCI setting, any OS being booted must have AHCI drivers available. If
the RAID Mode setting is chosen, then the following setting for RAID Mode Options will
appear.
Note: When the SATA Mode setting is changed, before attempting to set the Boot Order it is
necessary to do a Save and Exit, and reboot to properly recognize any SATA hard drives.
3. RAID Mode Options
Option Values: Intel® ESRT2 (LSI(TM))
Intel® RST (Matrix)
Help Text:
- Intel® ESRT2 (Powered By LSI*): Supports RAID 0/1/10 and optional RAID 5
with Intel® Embedded Server RAID Technology 2 (ESRT2). Uses Intel® ESRT2
drivers (based on LSI* MegaSR).
- Intel® RST (formerly known as Matrix RAID): Provides pass-through drive
support with Intel® Rapid Storage Technology(RST). Also provides host based
RAID 0/1/10/5 support. Uses Intel® RST iaStor drivers
Comments: This option setting only appears when the SATA Controller is enabled,
and RAID Mode has been selected as the operational SATA Mode. If a RAID Volume
has not previously been created, it will be necessary to Save and Exit and reboot in order
to create a RAID Volume.
4. Intel® Storage Module
Option Values: None
<Name of Storage Module detected>
Help Text: Shows the name of the Storage Module detected, if one is
installed.
Comments: Information only. If no Storage module is detected, then “None” is
displayed. '- This shows the customer the product name of the module installed, which
helps in identifying drivers, support, documentation, and so on by listing this on the BIOS
screen.
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When an AXX4SASMOD Storage Module is detected, then (and only then) a following
option will be available for switching between IT/IR and ESRT2 RAID settings.
5. Configure AXX4SASMOD RAID Module
Option Values: IT/IR
Intel® ESRT2 (LSI(TM))
Help Text:
- IT/IR: Provides pass-through drive support as well as HW RAID 0/1/1e support.
Uses LSI* mpt drivers.
- Intel® ESRT2 (Powered by LSI*): Supports RAID 0/1/10 and optional RAID 5
with Intel® Embedded Server RAID Technology 2 (ESRT2). Uses Intel® ESRT2
drivers (based on LSI* MegaSR).
Comments: This option setting only appears when an AXX4SASMOD Storage Module
is installed. If a RAID Volume has not previously been created, it will be necessary to
Save and Exit and reboot in order to create a RAID Volume.
6. SATA Port
Option Values: Not Installed
<Drive Information>
Help Text:
(Ports 0-1): 6Gb SATA capable port
(Ports 2-5): 3Gb SATA capable port
Comments: Information only. This is repeated for all six SATA Port for the Onboard
SATA Controller. This section for SATA Drive Information does not appear when the
SATA Mode is RAID Mode.
6.5.2.7 Serial Port Configuration
The Serial Port Configuration screen allows the user to configure the Serial A [COM 1] and
Serial B [COM2] ports.
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Advanced
Serial Port Configuration
Serial A Enable
Enabled/Disabled
Address
3F8h/2F8h/3E8h/2E8h
IRQ
3 or 4
Serial B Enable
Enabled/Disabled
Address
3F8h/2F8h/3E8h/2E8h
IRQ
3 or 4
Advanced
USB Configuration
Detected USB Devices
<Total USB Devices in System>
USB Controller
Enabled/Disabled
Legacy USB Support
Enabled/Disabled/Auto
Port 60/64 Emulation
Enabled/Disabled
Make USB Devices Non-Bootable
Enabled/Disabled
USB Mass Storage Device Configuration
Device Reset timeout
10 seconds/20 seconds/30 seconds/40 seconds
Mass Storage Devices:
<Mass storage devices one line/device>
Auto/Floppy/Forced FDD/Hard Disk/CD-ROM
To access this screen from the Main screen, select Advanced > Serial Port Configuration. To
move to another screen, press the <Esc> key to return to the Advanced screen, then select the
desired screen.
Figure 20. Serial Port Configuration Screen
6.5.2.8 USB Configuration
The USB Configuration screen allows the user to configure the USB controller options.
To access this screen from the Main screen, select Advanced > USB Configuration. To move
to another screen, press the <Esc> key to return to the Advanced screen, then select the
desired screen.
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Figure 21. USB Configuration Screen
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Advanced
PCI Configuration
Maximize Memory below 4GB
Enabled / Disabled
Memory Mapped I/O above 4GB
Enabled / Disabled
Onboard Video
Enabled / Disabled
Dual Monitor Video
Enabled / Disabled
Wake on LAN (PME)
Enabled / Disabled
Onboard NIC1 ROM
Enabled / Disabled
Onboard NIC2 ROM
Enabled / Disabled
Onboard NIC3 ROM
Enabled / Disabled
Onboard NIC4 ROM
Enabled / Disabled
Onboard NIC5 ROM
Enabled / Disabled
Onboard NIC iSCSI ROM
Enabled / Disabled
NIC 1 MAC Address
<MAC #>
NIC 2 MAC Address
<MAC #>
NIC 3 MAC Address
<MAC #>
NIC 4 MAC Address
<MAC #>
NIC 5 MAC Address
<MAC #>
6.5.2.9 PCI Configuration
The PCI Configuration screen allows the user to configure the PCI memory space used for
onboard and add-in adapters, configure video options, and configure onboard adapter options. It
also displays the NIC MAC Addresses in use.
To access this screen from the Main screen, select Advanced > PCI Configuration. To move
to another screen, press the <Esc> key to return to the Advanced screen, then select the
desired screen.
7. Wake on LAN (PME)
Option Values: Enabled
Disabled
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Help Text:
Figure 22. PCI Configuration Screen
Enables or disables PCI PME function for Wake on LAN capability from LAN
adapters.
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Advanced
System Acoustic and Performance Configuration
Set Throttling Mode
Auto/CLTT/OLTT
Altitude
300m or less/301m-900m/901m – 1500m/Higher than
1500m
Set Fan Profile
Acoustic
Comments: Enables/disables PCI/PCIe PME# signal to generate Power Management
Events (PME) and ACPI Table entries required for Wake on LAN (WOL). However, note
that this will enable WOL only with an ACPI-capable Operating System which has the
WOL function enabled.
6.5.2.10 System Acoustic and Performance Configuration
The System Acoustic and Performance Configuration screen allows the user to configure the
thermal control behavior of the system in order to balance performance and acoustics with
power consumption and heat generation.
To access this screen from the Main screen, select Advanced > System Acoustic and
Performance Configuration. To move to another screen, press the <Esc> key to return to the
Advanced screen, then select the desired screen.
Figure 23. System Acoustic and Performance Configuration
1. Set Throttling Mode
Option Values: Auto
Help Text:
[Auto] – Auto Throttling mode.
[CLTT] – Closed Loop Thermal Throttling Mode.
[OLTT] – Open Loop Thermal Throttling Mode.
Closed Loop Throttling Mode is supported only when ECC DIMM plugged. Open Loop
Throttling Mode is not supported.
Comments: Information only, for S1200BT boards with BMC: CLTT Mode is the only
mode supported. This will always be Auto, since there is no choice. If CLTT Mode
cannot be established, then the fallback mode is no memory thermal-based throttling.
2. Altitude
Option Values: 300m or less
301m-900m
901m-1500m
Higher than 1500m
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Help Text:
[300m or less] (980ft or less)
Optimal performance setting near sea level.
[301m - 900m] (980ft - 2950ft)
Optimal performance setting at moderate elevation.
[901m - 1500m] (2950ft - 4920ft)
Optimal performance setting at high elevation.
[Higher than 1500m] (4920ft or greater)
Optimal performance setting at the highest elevations.
Comments: This option sets an altitude value in order to choose a Fan Profile that is
optimized for the air density at the current altitude at which the system is installed.
3. Set Fan Profile
Option Values: Acoustic
Help Text:
[Acoustic] - The system will favor using throttling of memory over boosting
fans to cool the system if thermal thresholds are met.
Comments: Information only, for S1200BT boards with BMC: Acoustic Mode is the
only Fan Profile supported. This will always be Acoustic, since there is no other choice.
6.5.2.11 Security Screen (Tab)
The Security screen allows the user to enable and set the user and administrative password
and to lock out the front panel buttons so they cannot be used. This screen also allows the user
to enable and activate the Trusted Platform Module (TPM) security settings on those boards
that support TPM.
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Main
Advanced
Security
Server Management
Boot Options
Boot Manager
Administrator Password Status
<Installed/Not Installed>
User Password Status
<Installed/Not Installed>
Set Administrator Password
[1234aBcD]
Set User Password
Power ON Password
[1234aBcD]
Enabled/Disabled
Front Panel Lockout
Enabled/Disabled
TPM State
<Displays current TPM Device State>
TPM Administrative Control
No Operation/Turn On/Turn Off/Clear Ownership
To access this screen from the Main screen or other top-level Tab screen, press the right or left
arrow keys to traverse the tabs at the top of the Setup screen until the Security screen is
selected.
1. Administrator Password Status
Option Values: Installed
Not Installed
Help Text: <None>
Comments: Information only. Indicates the status of the User Password.
2. User Password Status
Option Values: Installed
Not Installed
Help Text: <None>
Comments: Information only. Indicates the status of the User Password.
3. Set Administrator Password
Option Values: [Entry Field]
Help Text:
Administrator password is used to control change access in the BIOS Setup
utility.
Only alphanumeric characters can be used. Maximum length is seven
characters and it is case sensitive.
Figure 24. Security Screen
Note: Administrator password must be set in order to use the user account.
Comments: This option is only to control access to Setup. Administrator has full
access to all Setup options. Clearing the Administrator Password also clears the User
Password.
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4. Set User Password
Option Values: [Entry Field]
Help Text:
User password is used to control entry access to the BIOS Setup utility.
Only alphanumeric characters can be used. Maximum length is seven
characters and it is case sensitive.
Note: Removing the administrator password also automatically removes the user password.
Comments: Available only if the Administrator Password is installed. This option
protects Setup settings as well as boot choices. The User Password only allows limited
access to the Setup options, and no choice of boot devices.
5. Power ON Password
Option Values: Enabled
Disabled
Help Text:
If enabled, password entry is required in order to boot the system.
Comments: Only when setting Administrator Password, this option is available for
operation.
6. Front Panel Lockout
Option Values: Enabled
Disabled
Help Text:
If enabled, locks the power button and reset button on the system's front panel.
If [Enabled] is selected, power and reset must be controlled through a system
management interface.
Comments:
Note: This option does not appear on all boards.
7. TPM State
Option Values: <Displays current TPM Device State>
May be:
Enabled and Activated
Enabled and Deactivated
Disabled and Activated
Disabled and Deactivated
Help Text: <None>
Comments: Information only. Shows the current TPM device state.
A Disabled TPM device does not execute commands that use the TPM functions
and TPM security operations are not available.
An Enabled and Deactivated TPM is in the same state as a disabled TPM,
except that setting of the TPM ownership is allowed if it is not present already.
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An Enabled and Activated TPM executes all commands that use the TPM
functions and TPM security operations are also available.
Note: This option appears only on boards equipped with a TPM.
8. TPM Administrative Control
Option Values: No Operation
Turn On
Turn Off
Clear Ownership
Help Text:
[No Operation] - No changes to current state.
[Turn On] - Enables and activates TPM.
[Turn Off] - Disables and deactivates TPM.
[Clear Ownership] - Removes the TPM ownership authentication and returns the TPM to
factory default state.
Note: BIOS setting will return to [No Operation] on every boot cycle by default.
Comments: Any Administrative Control operation selected will require the system to
perform a Hard Reset in order to become effective.
Note: This option appears only on boards equipped with a TPM.
6.5.2.12 Server Management Screen (Tab)
The Server Management screen allows the user to configure several server management
features. This screen also provides an access point to the screens for configuring console
redirection, displaying system information, and controlling the BMC LAN configuration.
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Main
Advanced
Security
Server Management
Boot Options
Boot Manager
Assert NMI on SERR
Enabled / Disabled
Assert NMI on PERR
Enabled / Disabled
Resume on AC Power Loss
Stay Off / Last state / Power On
Clear System Event Log
Enabled / Disabled
FRB-2 Enable
Enabled / Disabled
O/S Boot Watchdog Timer
Enabled / Disabled
O/S Boot Watchdog Timer Policy
Power off / Reset
O/S Boot Watchdog Timer Timeout
5 minutes / 10 minutes / 15 minutes / 20 minutes
Plug & Play BMC Detection
Enabled / Disabled
► Console Redirection
► System Information
► BMC LAN Configuration
To access this screen from the Main screen or other top-level Tab screen, press the right or left
arrow keys to traverse the tabs at the top of the Setup screen until the Server Management
screen is selected.
Figure 25. Server Management Screen (S1200BTL/S1200BTLRM)
1. EuP LOT6 Off-Mode
Option Values: Enabled
Disabled
Help Text:
Enable/disable Ecodesign EuP LOT6 “Deep Sleep” Off-Mode for near-zero
energy use when powered off.
Comments: This option controls whether the system goes into “Deep Sleep” or more
conventional S5 “Soft-Off” when powered off. S5 can wake up faster and can Wake on
LAN, but Deep Sleep uses less energy.
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Main
Advanced
Security
Server Management
Boot Options
Boot Manager
Assert NMI on SERR
Enabled / Disabled
Assert NMI on PERR
Enabled / Disabled
Resume on AC Power Loss
Stay Off / Last state / Power On
Clear System Event Log
Enabled / Disabled
FRB-2 Enable
Enabled / Disabled
O/S Boot Watchdog Timer
Enabled / Disabled
O/S Boot Watchdog Timer Policy
Power off / Reset
O/S Boot Watchdog Timer Timeout
5 minutes / 10 minutes / 15 minutes / 20 minutes
► Console Redirection
► System Information
► Hardware Monitor
Server Management
Console Redirection
Console Redirection
Disabled / Serial Port A / Serial Port B
Flow Control
None / RTS/CTS
Baud Rate
9.6k / 19.2k / 38.4k / 57.6k / 115.2k
Terminal Type
PC-ANSI / VT100 / VT100+ / VT-UTF8
Legacy OS Redirection
Disabled / Enabled
This option will not appear on platforms which do not support EuP LOT6 Off-Mode. For
details on any platform
Figure 26. Server Management Screen (S1200BTS)
6.5.2.13 Console Redirection
The Console Redirection screen allows the user to enable or disable console redirection and to
configure the connection options for this feature.
To access this screen from the Main screen, select Server Management > Console
Redirection. To move to another screen, press the <Esc> key to return to the Server
Management screen, then select the desired screen.
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Figure 27. Console Redirection Screen
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Server Management
System Information
Board Part Number
<Part Number display>
Board Serial Number
<Serial Number display>
System Part Number
<Part Number display>
System Serial Number
<Serial Number display>
Chassis Part Number
<Part Number display>
Chassis Serial Number
<Serial Number display>
Asset Tag
<Asset Tag-display>
BMC Firmware Revision
<BMC FW Rev display>
HSC Firmware Revision
<HSC FW Rev display>
ME Firmware Revision
<ME FW Rev display>
SDR Revision
<SDR Rev display>
UUID
<UUID display>
6.5.2.14 System Information
The System Information screen allows the user to view part numbers, serial numbers, and
firmware revisions. This is an Information Only screen.
This screen may have fewer or more items displayed on it, depending on the system hardware
configuration. For example, when the board does not include a BMC, this display does not
include BMC Firmware Revision or SDR Version. Similarly, there is no HSC Firmware Revision
displayed for systems which do not include an HSC.
To access this screen from the Main screen, select Server Management > System
Information. To move to another screen, press the <Esc> key to return to the Server
Management screen, then select the desired screen.
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Figure 28. System Information Screen (S1200BTL/S1200BTLRM)
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Server Management
System Information
Board Part Number
<Part Number display>
Board Serial Number
<Serial Number display>
System Part Number
<Part Number display>
System Serial Number
<Serial Number display>
Chassis Part Number
<Part Number display>
Chassis Serial Number
<Serial Number display>
Asset Tag
<Asset Tag-display>
HSC Firmware Revision
<HSC FW Rev display>
ME Firmware Revision
<ME FW Rev display>
UUID
<UUID display>
Figure 29.System Information Screen (S1200BTS)
6.5.2.15 BMC LAN Configuration
The BMC configuration screen allows the Setup user to configure the BMC Baseboard LAN
channel and the RMM4 LAN channel, and to manage BMC User settings for up to five BMC
Users.
To access this screen from the Main screen, select Server Management > System
Information. To move to another screen, press the <Esc> key to return to the Server
Management screen, then select the desired screen.
Intel order number G13326-007 Revision 2.4
Intel® Server Board S1200BT TPS BIOS User Interface
85
Server Management
BMC LAN Configuration
Baseboard LAN configuration
IP Source
Static/Dynamic
IP Address
[0.0.0.0 IP display/edit]
Subnet Mask
[0.0.0.0 IP display/edit]
Gateway IP
[0.0.0.0 IP display/edit]
[0.0.0.0 IP display/edit]
Intel® RMM4 LAN configuration
Intel® RMM4
<Present/Not Present>
IP Source
Static/Dynamic
IP Address
[0.0.0.0 IP display/edit]
Subnet Mask
[0.0.0.0 IP display/edit]
Gateway IP[
[0.0.0.0 IP display/edit]
BMC DHCP Host Name
[DHCP Host Name display/edit]
User Configuration
User ID
anonymous/root/User3/User4/User5
Privilege
Callback/ User/Operator/Administrator
User status
Disable/Enable
User Name
[User Name display/edit]
User Password.
The BMC LAN Configuration screen is unusual in that the LAN Configuration parameters are
maintained by the BMC itself, so this screen is just a User Interface to the BMC configuration.
As such, the initial values of the LAN options shown on the screen are acquired from the BMC
when this screen is initially accessed by a user. Any values changed by the user are
communicated back to the BMC when a “Save Changes” or “Save Changes and Exit” action is
performed. If a “Discard Changes” or “Discard Changes and Exit” action is performed instead,
any accumulated changes from this screen will be disregarded and lost.
Figure 30. BMC LAN Configuration Screen (S1200BTL/S1200BTLRM)
6.5.2.16 Hardware Monitor
The Hardware Monitor screen allows the user to configure Fan Speed Control and to view
displays of temperature and voltage status.
Revision 2.4 Intel order number G13326-007
BIOS User Interface Intel® Server Board S1200BT TPS
86
Server Management
Hardware Monitor
► Real-time Temperature and Voltage Status
Fan Controller
Auto / Manual
CPU Fan Altitude
300m/900m/1500m/3000m
System Fan Altitude
300m/900m/1500m/3000m
Server Management
Hardware Monitor
► Real-time Temperature and Voltage Status
Fan Controller
Manual
CPU Fan
Hysteresis
Default Fan PWM
[2 Degree Celsius/3 Degree Celsius/4 Degree Celsius
[40%/60%/80%/100%]
System Fan
Hysteresis
Default Fan PWM
[2 Degree Celsius/3 Degree Celsius/4 Degree Celsius
[40%/60%/80%/100%]
Auxiliary Fan 1
Hysteresis
Default Fan PWM
[2 Degree Celsius/3 Degree Celsius/4 Degree Celsius
[40%/60%/80%/100%]
Auxiliary Fan 2
Hysteresis
Default Fan PWM
[2 Degree Celsius/3 Degree Celsius/4 Degree Celsius
[40%/60%/80%/100%]
To access this screen from the Main screen, select Server Management > Hardware Monitor.
To move to another screen, press the <Esc> key to return to the Server Management screen,
then select the desired screen.
Figure 31. Hardware Monitor Screen, Auto Fan Control (S1200BTS)
Figure 32. Hardware Monitor Screen, Manual Fan Control (S1200BTS)
Intel order number G13326-007 Revision 2.4
Intel® Server Board S1200BT TPS BIOS User Interface
87
Server Management
Real time Temperature :
CPU Fan PWM
System Fan PWM
System temperature
Voltage status:
+Vccp
+12V
+3.3V
+5.0V
+1.5V
+1.05V
+3.3V(standby)
6.5.2.17 Real-time Temperature and Voltage Status
The Real-time Temperature and Voltage Status screen allows the user to view displays of
current processor and system fan speeds, current system temperature, and the status of
various voltages which are monitored on the board.
This screen is present only for boards without a BMC.
To access this screen from the Main screen, select Server Management > Hardware Monitor >
Real-time Temperature and Voltage Status. To move to another screen, press the <Esc> key
to return to the Hardware Monitor screen, if necessary press the <Esc> key again to return to
the Server Management screen, then select the desired screen.
6.5.2.18 Boot Options Screen (Tab)
The Boot Options screen displays any bootable media encountered during POST, and allows
the user to configure the desired order in which boot devices are to be tried.
The first boot device in the specified Boot Order which is present and is bootable during POST
will be used to boot the system, and will continue to be used to reboot the system until the boot
device configuration has changed (that is, which boot devices are present), or until the system
has been powered down and booted in a cold power-on boot.
Revision 2.4 Intel order number G13326-007
Figure 33. Real-time Teperature and Voltage Status Screen (S1200BTS)
BIOS User Interface Intel® Server Board S1200BT TPS
88
Main
Advanced
Security
Server Management
Boot Options
Boot Manager
System Boot Timeout
<0 - 65535>
Boot Option #1
<Available Boot devices>
Boot Option #2
<Available Boot devices>
Boot Option #n
<Available Boot devices>
► Hard Disk Order
► CDROM Order
► Floppy Order
► Network Device Order
► BEV Device Order
► Add EFI Boot Option
► Delete EFI Boot Option
EFI Optimized Boot
Enabled/Disabled
Use Legacy Video for EFI OS
Enabled/Disabled
Boot Option Retry
Enabled/Disabled
USB Boot Priority
Enabled/Disabled
If all types of bootable devices are installed in the system, then the default boot order is as
follows:
CD/DVD-ROM
Floppy Disk Drive
Hard Disk Drive
PXE Network Device
BEV (Boot Entry Vector) Device
EFI Shell and EFI Boot paths
To access this screen from the Main screen or other top-level Tab screen, press the right or left
arrow keys to traverse the tabs at the top of the Setup screen until the Boot Options screen
is selected.
Intel order number G13326-007 Revision 2.4
Figure 34. Boot Options Screen
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