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Intel may make changes to specifications and product descriptions at any time, without notice.
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights
that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any
license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property
rights.
The Quad-Core Intel® Xeon® Processor 3300 Series may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
∆
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor
family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time
processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not
intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number
progression is not necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details.
Intel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled
for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary
depending on your hardware and software configurations. See http://www.intel.com/info/em64t for more information including
details on which processors support Intel 64, or consult with your system vendor for more information.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting
operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
±
Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor
(VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary
depending on hardware and software configur ations and may re quire a BIOS update. S oftware applicatio ns may not be compatible
with all operating systems. Please check with your application vendor.
Not all specified units of this processor support Thermal Monitor 2, Enhanced HALT State and Enhanced Intel SpeedStep®
Technology. See the Processor Spec Finder at http://processorfinder.intel.com or contact your Intel representative for more
information.
Intel, Pentium, Xeon, Intel Core, Intel SpeedStep, and the Intel logo are trademarks of Intel Corporation in the U.S. and other
countries.
• Enhanced floating point and multimedia unit
for enhanced video, audio, encryption, and
3D performance
• Power Management capabilities
• System Management mode
®
®
• Multiple low-power states
• 8-way cache associativity provides improved
cache hit rate on load/store operations
• 775-land Package
The Quad-Core Intel® Xeon® Processor 3300 Series deliver Intel's advanced, powerful processors for
desktop PCs. The processor is designed to deliver performance across applications and usages where
end-users can truly appreciate and experience the performance. These applications include Internet
audio and streaming video, image processing, video content creation, speech, 3D, CAD, games,
multimedia, and multitasking user environments.
Intel® 64 architecture enables the processor to execute operating systems and applications written to
take advantage of the Intel 64 architecture. The processor, supporting Enhanced Intel Speedstep
®
technology, allows tradeoffs to be made between performance and power consumption.
®
The Quad-Core Intel
Xeon® Processor 3300 Series also includes the Execute Disable Bit capability.
This feature, combined with a supported operating system, allows memory to be marked as
executable or non-executable.
®
The Quad-Core Intel
Xeon® Processor 3300 Series support Intel® Virtualization Technology.
Virtualization Technology provides silicon-based functionality that works together with compatible
Virtual Machine Monitor (VMM) software to improve on software-only solutions.
Datasheet7
§
8Datasheet
Introduction
1Introduction
The Quad-Core Intel® Xeon® Processor 3300 Series, like the Quad-Core Intel® Xeon®
Processor 3200 Series, is a based on the Intel® CoreTM microarchitecture. The Intel
Core microarchitecture combines the performance of previous generation Desktop
products with the power efficiencies of a low-power microarchitecture to enable
smaller, quieter systems.The Quad-Core Intel® Xeon® Processor 3300 Series are 64bit processors that maintain compatibility with IA-32 software.
The processor utilizes Flip-Chip Land Grid Array (FC-LGA6) package technology, and
plug into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the
LGA775 socket.
Note:In this document the Quad-Core Intel® Xeon® Processor 3300 Series may be referred
to simply as "the processor."
Note:The Quad-Core Intel® Xeon® Processor 3300 Series refers to X3380, X3360, X3350,
X3330, X3320, L3360.
The processor is a quad-core processor, based on 45 nm process technology. The
processor features the Intel
cache that significantly reduces latency to frequently used data. The processors feature
a 1333 MHz front side bus (FSB) and either two independent but shared 6 MB of L2
cache (2x6M) or two independent but shared 3 MB of L2 cache (2x3M).The processor
supports all the existing Streaming SIMD Extensions 2 (SSE2), Streaming SIMD
Extensions 3 (SSE3), Supplemental Streaming SIMD Extension 3 (SSSE3), and the
Streaming SIMD Extensions 4.1 (SSE4.1). The processor supports several Advanced
Technologies: Execute Disable (XD) Bit, Intel
Intel SpeedStep
The processor's front side bus (FSB) utilizes a split-transaction, deferred reply protocol.
The FSB uses Source-Synchronous Transfer of address and data to improve
performance by transferring data four times per bus clock (4X data transfer rate).
Along with the 4X data bus, the address bus can deliver addresses two times per bus
clock and is referred to as a "double-clocked" or 2X address bus. Working together, the
4X data bus and 2X address bus provide a data bus bandwidth of up to 10.7 GB/s.
The processor use some of the infrastructure already enabled by 2005 FMB platforms
including heatsink, heatsink retention mechanism, and socket. Manufacturability is a
high priority; hence, mechanical assembly may be completed from the top of the
baseboard and should not require any special tooling.
®
Technology, and Intel® Virtualization Technology (Intel® VT).
1.1Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
®
Advanced Smart Cache, a shared multi-core optimized
®
64 architecture (Intel® 64), Enhanced
“Front Side Bus” refers to the interface between the processor and system core logic
(a.k.a. the chipset components). The FSB is a multiprocessing interface to processors,
memory, and I/O.
Datasheet
9
1.1.1Processor Terminology Definitions
Commonly used terms are explained here for clarification:
• Quad-Core Intel® Xeon® Processor 3300 Series — Quad core processor in the
FC-LGA6 package with two 6 MB L2 cache or two 3 B L2 cache.
• Processor — For this document, the term processor is the generic form of the
Quad-Core Intel® Xeon® Processor 3300 Series.
• Intel
• Keep-out zone — The area on or near the processor that system design can not
• Processor core — Processor die with integrated L2 cache.
• LGA775 socket — The processor mates with the system board through a surface
• Integrated heat spreader (IHS) —A component of the processor package used
• Retention mechanism (RM) — Since the LGA775 socket does not include any
• FSB (Front Side Bus) — The electrical interface that connects the processor to
• Storage conditions — Refers to a non-operational state. The processor may be
• Functional operation — Refers to normal operating conditions in which all
• Execute Disable (XD) Bit — XD allows memory to be marked as executable or
• Intel
• Enhanced Intel SpeedStep
• Intel® Virtualization Technology (Intel® VT) — A set of hardware
®
CoreTM microarchitecture — A new foundation for Intel® architecture-
based desktop, mobile and mainstream server multi-core processors. For additional
information refer to: http://www.intel.com/technology/architecture/coremicro/
utilize.
mount, 775-land, LGA socket.
to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.
mechanical features for heatsink attach, a retention mechanism is required.
Component thermal solutions should attach to the processor via a retention
mechanism that is independent of the socket.
the chipset. Also referred to as the processor system bus or the system bus. All
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.
installed in a platform, in a tray , or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased, or receive any clocks.
Upon exposure to “free air”(i.e., unsealed packaging or a device removed from
packaging material) the processor must be handled in accordance with moisture
sensitivity labeling (MSL) as indicated on the packaging material.
processor specifications, including DC, AC, system bus, signal quality, mechanical
and thermal are satisfied.
non-executable, when combined with a supporting operating system. If code
attempts to run in non-executable memory the processor raises an error to the
operating system. This feature can prevent some classes of viruses or worms that
exploit buffer over run vulnerabilities and can thus help improve the overall security
of the system. See the Intel® Architecture Software Developer's Manual for more
detailed information.
®
64 Architecture — An enhancement to Intel's IA-32 architec ture, allowing
the processor to execute operating systems and applications written to take
advantage of Intel 64 architecture. Further details on Intel 64 architecture and
programming model can be found in the Software Developer Guide at http://
developer.intel.com/technology/64bitextensions/.
®
Technology — Enhanced Intel SpeedStep
Te chnology allows trade-offs to be made between performance and power
consumptions, based on processor utilization. This may lower average power
consumption (in conjunction with OS support).
enhancements to Intel server and client platforms that can improve virtualization
solutions. Intel VT will provide a foundation for widely-deployed virtualization
Introduction
10Datasheet
Introduction
solutions and enables more robust hardware assisted virtualization solutions. More
information can be found at: http://www.intel.com/technology/virtualization/
• Platform Environment Control Interface (PECI) — A proprietary one-wire bus
interface that provides a communication channel between the processor and
chipset components to external monitoring devices.
1.2References
Material and concepts available in the following documents may be beneficial when
reading this document:
Table 1-1.References
Quad-Core Intel® Xeon® Processor 3300 Series
Thermal and Mechanical Design Guidelines Addendum
Quad-Core Intel® Xeon® Processor 3300 Series
Specification Update
Voltage Regulator-Down (VRD) 11.0 Processor Power
Delivery Design Guidelines For Desktop LGA775 Socket
Volume 1: Basic Architecture
Volume 2A: Instruction Set Reference, A-M
Volume 2B: Instruction Set Reference, N-Z
Volume 3A: System Programming Guide, Part 1
Volume 3B: System Programming Guide, Part 2
DocumentLocation
http://www.intel.com/
products/processor/
xeon3000/
documentation.htm#therma
l_models
http://download.intel.com/
design/intarch/specupdt/
319007.pdf
http://www.intel.com/
design/processor/applnots/
313214.htm
http://intel.com/design/
Pentium4/guides/
302666.htm
http://www.intel.com/
products/processor/
manuals/
Datasheet
§
11
Introduction
12Datasheet
Electrical Specifications
2Electrical Specifications
2.1Power and Ground Lands
The processor has VCC (power), VTT, and VSS (ground) inputs for on-chip power
distribution. All power lands must be connected to V
connected to a system ground plane. The processor VCC lands must be supplied the
voltage determined by the Voltage IDentification (VID) lands.
The signals denoted as VTT provide termination for the front side bus and power to the
I/O buffers. A separate supply must be implemented for these lands, that meets the
V
specifications outlined in Table 2-3.
TT
2.2Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings. This may cause voltages on power planes
to sag below their minimum specified values if bulk decoupling is not adequate. Larger
bulk storage (C
current during longer lasting changes in current demand by the component, such as
coming out of an idle condition. Similarly, they act as a storage well for current when
entering an idle condition from a running condition. The motherboard must be designed
to ensure that the voltage provided to the processor remains within the specifications
listed in Table 2-3. Failure to do so can result in timing violations or reduced lifetime of
the component. For further information and guidelines, refer to the appropriate
platform design guidelines.
2.2.1VCC Decoupling
VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the
processor voltage specifications. This includes bulk capacitance with low effective series
resistance (ESR) to keep the voltage rail within specifications during large swings in
load current. In addition, ceramic decoupling capacitors are required to filter high
frequency content generated by the front side bus and processor activity. Consult the
Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For
Desktop LGA775 Socket and appropriate platform design guidelines for further
information.
), such as electrolytic or aluminum-polymer capacitors, supply
BULK
, while all VSS lands must be
CC
2.2.2VTT Decoupling
Decoupling must be provided on the motherboard. Decoupling solutions must be sized
to meet the expected load. To ensure compliance with the specifications, various
factors associated with the power delivery solution must be considered including
regulator type, power plane and trace sizing, and component placement. A
conservative decoupling solution would consist of a combination of low ESR bulk
capacitors and high frequency ceramic capacitors. For further information regarding
power delivery, decoupling and layout guidelines, refer to the appropriate platform
design guidelines.
2.2.3FSB Decoupling
The processor integrates signal termination on the die. In addition, some of the high
frequency capacitance required for the FSB is included on the processor package.
However, additional high frequency capacitance must be added to the motherboard to
Datasheet
13
properly decouple the return currents from the front side bus. Bulk decoupling must
also be provided by the motherboard for proper [A]GTL+ bus operation. Decoupling
guidelines are described in the appropriate platform design guidelines.
2.3Voltage Identification
The Voltage Identification (VID) specification for the processor is defined by the Voltage
Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage
to be delivered to the processor VCC lands (see Chapter 2.7.3 for V
specifications). Refer to Table 2-11 for the DC specifications for these signals. Voltages
for each processor frequency is provided inTable 2-3.
NOTE: To support the Deeper Sleep State the platform must use a VRD 11.1 compliant
solution. The Deeper Sleep State also requires additional platform support. Refer to the
platform design guide and the Voltage Regulator-Down (VRD) 11.1 Processor Power Delivery Design Guidelines for further details.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core speed may have different default VID settings. This is
reflected by the VID Range values provided in Table 2-3. Refer to the Processor
Specification Update for further details on specific valid core frequency and VID values
of the processor. Note that this differs from the VID employed by the processor during
a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep
technology, or Extended HALT State).
Electrical Specifications
overshoot
CC
®
The processor uses eight voltage identification signals, VID[7:0], to support automatic
selection of power supply voltages. Table 2-1 specifies the voltage level corresponding
to the state of VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers
to a low voltage level. If the processor socket is empty (VID[7:0] = 11111110), or the
voltage regulation circuit cannot supply the voltage that is requested, it must disable
itself.
The processor provides the ability to operate while transitioning to an adjacent VID and
its associated processor core voltage (V
line. It should be noted that a low-to-high or high-to-low voltage state change may
). This will represent a DC shift in the load
CC
result in as many VID transitions as necessary to reach the target core voltage.
T ransitions abo ve the specified VID are not permitted. Table 2-3 includes VID step sizes
and DC shift ranges. Minimum and maximum v oltages must be maintained as shown in
Table 2-4 and Figure 2-1as measured across the VCC_SENSE and VSS_SENSE lands.
The VRM or VRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for dynamic VID transitions are included in Table 2-3
and Table 2-4. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for further details.
All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS,
or to any other signal (including each other) can result in component malfunction
V
TT ,
or incompatibility with future processors. See Chapter 4 for a land listing of the
processor and the location of all RESERVED lands.
In a system level design, on-die termination has been included by the processor to
allow signals to be terminated within the processor silicon. Most unused GTL+ inputs
should be left as no connects as GTL+ termination is provided on the processor silicon.
However, see Table 2-6 for details on GTL+ signals that do not include on-die
termination.
Electrical Specifications
Unused active high inputs, should be connected through a resistor to ground (V
Unused outputs can be left unconnected, however this may interfere with some TAP
SS
).
functions, complicate debug probing, and prevent boundary scan testing. A resistor
must be used when tying bidirectional signals to power or ground. When tying any
signal to power or ground, a resistor will also allow for system testability. Resistor
values should be within ± 20% of the impedance of the motherboard trace for front
side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the
same value as the on-die termination resistors (R
). For details see Table 2-13.
TT
TAP and CMOS signals do not include on-die termination. Inputs and utilized outputs
must be terminated on the motherboard. Unused outputs may be terminated on the
motherboard or left unconnected. Note that leaving unused outputs unterminated may
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing. Signal termination for these signal types is discussed in the appropriate
platform design guidelines.
All TESTHI[13,11:10:7:0] lands should be individually connected to V
resistor which matches the nominal trace impedance.
via a pull-up
TT
The TESTHI signals may use individual pull-up resistors or be grouped together as
detailed below. A matched resistor must be used for each group:
•TESTHI[1:0]
•TESTHI[7:2]
• TESTHI10 – cannot be grouped with other TESTHI signals
• TESTHI11 – cannot be grouped with other TESTHI signals
• TESTHI13 – cannot be grouped with other TESTHI signals
Terminating multiple TESTHI pins together with a single pull-up resistor is not
recommended for designs supporting boundary scan for proper Boundary Scan testing
of the TESTHI signals. For optimum noise margin, all pull-up resistor values used for
TESTHI[13, 11:10,7:0] lands should have a resistance value within ± 20% of the
impedance of the board transmission line traces. For example, if the nominal trace
impedance is 50
2.5Flexible Motherboard Guidelines (FMB)
The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the
processor will have over certain time periods. The values are only estimates and actual
specifications for future processors may differ. Processors may or may not have
specifications equal to the FMB value in the foreseeable future. System designers
should meet the FMB values to ensure their systems will be compatible with future
processors. The FMB values are shown in Table 2-3 and Table 5-1.
16Datasheet
Ω, then a value between 40 Ω and 60 Ω should be used.
Electrical Specifications
2.6Power Segment Identifier (PSID)
Power Segment Identifier (PSID) is a mechanism to prevent booting under mismatched
power requirement situations. The PSID mechanism enables BIOS to detect if the
processor in use requires more power than the platform voltage regulator (VR) is
capable of supplying. For example, a 130W TDP processor installed in a board with a
65W or 95W TDP capable VR may draw too much power and cause a potential VR issue.
2.7Voltage and Current Specification
2.7.1Absolute Maximum and Minimum Ratings
Table 2-2 spe cifies absolute maximum and minimum ratings only and lie outside the
functional limits of the processor. Within functional operation limits, functionality and
long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function, or its reliability will be
severely degraded.
Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
electric fields.
Table 2-2.Absolute Maximum and Minimum Ratings
SymbolParameterMinMax UnitNotes
V
CC
V
TT
T
CASE
T
STORAGE
NOTES:
1.For functional operation, all processor electrical, signal quality, mechanical and thermal
2.Overshoot and undershoot voltage guidelines for input, output and I/O signals are outlined
3.Storage temperature is applicable to storage conditions only. In this scenario, the
Core voltage with respect to
V
SS
FSB termination voltage with
respect to V
Processor case temperatureSee Section 5
Processor storage
temperature
specifications must be satisfied.
in Chapter 3. Excessive overshoot or undershoot on any signal will likely result in
permanent damage to the processor.
processor must not receive a clock, and no lands can be connected to a voltage bias.
SS
–0.31.45V-
–0.31.45V-
See
Section 5
–40 85°C3, 4, 5
°C-
1, 2
Datasheet
17
Storage within these limits will not affect the long-term reliability of the device . For
functional operation, refer to the processor case temperature specifications.
4.This rating applies to the processor and does not include any tray or packaging.
5.Failure to adhere to this specif ication can affect the long term reliability of the processor.
2.7.2DC Voltage and Current Specification
Table 2-3.Voltage and Current Specifications
Electrical Specifications
SymbolParameterMinTypMaxUnit
VID RangeVID0.8500-1.3625V1
Processor
Number
for 775_VR_CONFIG_05A
V
CC
(95W)
775_VR_CONFIG_06A
(65W)
3.16 GHz (12MB Cache)
3.00 GHz (12MB Cache)
2.83 GHz (12MB Cache)
2.66 GHz (6MB Cache)
2.83 GHz (12MB Cache)
2.66 GHz (12MB Cache)
2.50 GHz (6MB Cache)
for 775_VR_CONFIG_05A
I
CC
(95W)
Refer to Table 2-4 and
Figure 2-1
- 5%1.50+ 5%
V
Core
V
CC
V
CC_BOOT
V
CCPLL
X3380
X3370
L3360
X3330
X3360
X3350
X3320
Default VCC voltage for initial power up-1.10-V
PLL V
CC
Processor
Number
775_VR_CONFIG_06A
(65W)
X3380
I
CC
X3370
L3360
X3330
X3360
X3350
X3320
V
TT
FSB termination voltage
(DC + AC specifications)
3.16 GHz (12MB Cache)
3.00 GHz (12MB Cache)
2.83 GHz (12MB Cache)
2.66 GHz (6MB Cache)
2.83 GHz (12MB Cache)
2.66 GHz (12MB Cache)
2.50 GHz (6MB Cache)
--100A6, 7
1.0451.101.155V8, 9
VTT_OUT_LEFT
and
VTT_OUT_RIGHT
I
CC
I
TT
I
CC_VCCPLL
I
CC_GTLREF
DC Current that may be drawn from
VTT_OUT_LEFT and VTT_OUT_RIGHT per land
ICC for VTT supply before VCC stable
for VTT supply after VCC stable
I
CC
--580mA
--
8.0
7.0
A10
ICC for PLL land130mA
ICC for GTLREF--200µA
Notes
2, 11
3, 4, 5
NOTES:
1.Each processor is programmed with a maximum valid voltage identification value (VID),
which is set at manufacturing and can not be altered. Individual maximum VID values are
calibrated during manufacturing such that two processors at the same frequency may have
18Datasheet
Electrical Specifications
2.Unless other w ise noted, all specifications in this table are based on estima tes and
3.These voltages are targets only. A variable voltage source should exist on systems in the
4.The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE
5.Refer to Table 2-4 and Figure 2-1 for the minimum, typical, and maximum V
6.FMB is the Flexi b le Motherboard guideline. These guidelines are for estimation purpose s
7.I
8.V
9.Baseboard bandwidth is limited to 20 M H z.
10.This is the maximum total current drawn from the V
11.Adherence to the voltage specifications for the processor are required to ensure reliable
different settings within the VID range. Note that this differ s from the VID employed by the
processor during a power management event (Thermal Monitor 2, Enhanced Intel
SpeedStep
®
Technology, or Extended HALT State).
simulations or empirical data. These specifications will be updated with characterized data
from silicon measurements at a later date.
event that a different voltage is required. See Section 2.3 and Table 2-1 for more
information.
lands at the socket with a 100MHz bandwidth oscilloscope, 1.5 pF maxi mum probe
capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the
probe should be less than 5 mm. Ensure external noise from the system is not coupled into
the oscilloscope probe.
allowed for
a given current. The processor should not be subjected to any V
wherein V
exceeds V
CC
for a given current.
CC_MAX
and ICC combination
CC
CC
only. See Section 2.5 for further details on FMB guidelines.
specification is based on V
CC_MAX
must be provided via a separate voltage source and not be connected to VCC. This
TT
specification is measured at the land.
specification does not include the current coming from on-board termination (R
through the signal line. Refer to the appropriate platform design guide and the Voltage
loadline. Refer to Figure 2-1 for details.
CC_MAX
plane by only the processor. This
TT
),
TT
Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket to determine the total I
1.The loadline specification includes both static and transient limits except for overshoot
allowed as shown in Section 2.7.3.
2.This table is intended to aid in reading discrete points on Figure 2-1.
3.The loadlines specify voltage limits at the die measured at the VCC_SENSE and
VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be tak en
from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline
guidelines and VR implementation details.
4.Adherence to this loadline specification is required to ensure reliable processor operation.
Maximum Voltage
1.30 mΩ
Typical Voltage
1.38 mΩ
Electrical Specifications
1, 2, 3, 4
Minimum Voltage
1.45 mΩ
Figure 2-1. VCC Static and Transient Tolerance
VID - 0.000
VID - 0.013
VID - 0.025
VID - 0.038
VID - 0.050
VID - 0.063
VID - 0.075
VID - 0.088
VID - 0.100
Vcc [V]
VID - 0.113
VID - 0.125
VID - 0.138
VID - 0.150
VID - 0.163
VID - 0.175
VID - 0.188
0 102030405060708090100
Vcc Typical
Vcc Minimum
Icc [A]
Vcc Maximum
NOTES:
1.The loadline specification includes both static and transient limits except for overshoot
allowed as shown in Section 2.7.3.
2.This loadline specification shows the deviation from the VID set point.
20Datasheet
Electrical Specifications
3.The loadlines specify voltage limits at the die measured at the VCC_SENSE and
VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken
from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadli ne
guidelines and VR implementation details.
2.7.3VCC Overshoot
The processor can tolerate short transient overshoot events where VCC exceeds the VID
voltage when transitioning from a high to low current load condition. This overshoot
cannot exceed VID + V
The time duration of the overshoot event must not exceed T
OS_MAX
maximum allowable time duration above VID). These specifications apply to the
processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.
Table 2-5.VCC Overshoot Specifications
SymbolParameterMinMaxUnitFigureNotes
V
OS_MAX
T
OS_MAX
NOTES:
1.Adherence to these s pecifications is required to ensure reliable processor operation.
Magnitude of VCC overshoot above
VID
Time duration of VCC overshoot above
VID
(V
OS_MAX
is the maximum allowable overshoot voltage).
OS_MAX
(T
OS_MAX
-50mV2-2
-25µs2-2
is the
1
1
Figure 2-2. VCC Overshoot Example Waveform
Example Overshoot Waveform
VID + 0.050
Voltage [V]
VID - 0.000
0510152025
TOS: Overshoot time above VID
V
: Overshoot above VID
OS
NOTES:
1.V
2.T
is measured overshoot voltage.
OS
is measured time duration above VID.
OS
T
OS
Time [us]
V
OS
Datasheet
21
2.7.4Die Voltage Validation
Overshoot events on processor must meet the specifications in Table 2-5 when
measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are <
10 ns in duration may be ignored. These measurements of processor die level
overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or
equal to 100 MHz bandwidth limit.
2.8Signaling Specifications
Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling
technology. This technology provides improved noise margins and reduced ringing
through low voltage swings and controlled edge rates.Platforms implement a
termination voltage level for GTL+ signals defined as V
separate power planes for each processor (and chipset), separate V
are necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address busses have caused
signal integrity considerations and platform design methods to become even more
critical than with previous processor families. Design guidelines for the processor front
side bus are detailed in the appropriate platform design guides (refer to Section 1.2).
The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see Table 2-13 for GTLREF specifications). Refer to the applicable
platform design guidelines for details. Termination resistors (R
provided on the processor silicon and are terminated to V
provide on-die termination, thus eliminating the need to terminate the bus on the
motherboard for most GTL+ signals.
Electrical Specifications
. Because platforms implement
TT
TT
. Intel chipsets will also
TT
and V
CC
supplies
TT
) for GTL+ signals are
2.8.1FSB Signal Groups
The front side bus signals have been combined into groups by buffer type. GTL+ input
signals have differential input buffers, which use GTLREF[3:0] as a reference level. In
this document, the term “GTL+ Input” refers to the GTL+ input group as well as the
GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output
group as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle. Table 2-6 identifies which signals are common clock, source synchronous,
and asynchronous.
2.In processor systems where no debug port is implemented on the system board, the se
signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
3.The value of these signals during the active-to-inactive edge of RESET# defines the
processor configuration options. See Section 6.1 for details.
4.PROCHOT# signal type is open drain output and CMOS input.
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS
input buffers. All of the CMOS and Open Drain signals are required to be asserted/
deasserted for at least eight BCLKs in order for the processor to recognize the proper
signal state. See Section 2.8.3 for the DC specifications. See Section 6.2 for additional
timing requirements for entering and leaving the low power states.
2.8.3Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads)
unless otherwise stated. All specifications apply to all frequencies and cache sizes
unless otherwise stated.
Table 2-9.GTL+ Signal Group DC Specifications
SymbolParameterMinMaxUnitNotes
V
V
V
I
24Datasheet
Input Low Voltage-0.10GTLREF - 0.10V2, 6
IL
Input High VoltageGTLREF + 0.10V
IH
Output High VoltageV
OH
Output Low CurrentN/A
OL
- 0.10V
TT
[(R
TT_MIN
+ 0.10V3, 4, 6
TT
TT
V
) + (2 * R
TT_MAX
/
ON_MIN
)]
V4, 6
A-
1
Electrical Specifications
Table 2-9.GTL+ Signal Group DC Specifications
SymbolParameterMinMaxUnitNotes
I
I
R
Input Leakage
LI
Current
Output Leakage
LO
Current
Buffer On Resistance7.499.16Ω5
ON
N/A± 100µA7
N/A± 100µA8
NOTES:
1.Unless other wise noted, all specifications in this table apply to all processor frequencies.
2.V
3.V
is defined as the voltage range at a receiving agent that will be interpreted as a logical
IL
low value.
is defined as the voltage r ange at a rec eiving age nt that will be interpreted as a logical
IH
high value.
4.V
and VOH may experience excursions above VTT. However, input signal drivers must
IH
comply with the signal quality specifi cations in Chapter 3.
5.Refer to processor I/O Buffer Models for I/V characteristics.
6.The V
7.Leakage to V
8.Leakage to V
referred to in these specifications is the instantaneous VTT.
TT
with land held at VTT.
SS
with land held at 300mV.
TT
Table 2-10. Open Drain and TAP Output Signal Group DC Specifications
SymbolParameterMinMaxUnitNotes
1
1
V
I
I
Output Low Voltage00.20V-
OL
Output Low Current1650mA2
OL
Output Leakage CurrentN/A± 200µA3
LO
NOTES:
1.Unless other wise noted, all specifications in this table apply to all processor frequencies.
2.Measured at V
3.For Vin between 0 and V
* 0.2V.
TT
OH
.
Table 2-11. CMOS Signal Group DC Specifications
SymbolParameterMinMaxUnitNotes
V
V
V
V
I
I
I
NOTES:
1.Unless other wise noted, all specifications in this table apply to all processor frequencies.
2.All outputs are open drain.
Input Low Voltage -0.10VTT * 0.30V3, 6
IL
Input High VoltageVTT * 0.70V
IH
Output Low Voltage-0.10VTT * 0.10V6
OL
Output High Voltage0.90 * V
OH
Output Low Current
OL
Output Low Current
OH
I
Input Leakage CurrentN/A± 100µA8
LI
Output Leakage CurrentN/A± 100µA9
LO
TT
TT
V
* 0.10 / 67VTT * 0.10 /
TT
V
* 0.10 / 67VTT * 0.10 /
TT
V
TT
+ 0.10V4, 5, 6
+ 0.10V2, 5, 6
27
27
A6, 7
A6, 7
1
Datasheet
25
Electrical Specifications
3.VIL is defined as the voltage range at a receiving agent that will be interpret ed as a l ogical
low value.
4.V
5.V
6.The V
7.I
8.Leakage to VSS with land held at VTT.
9.Leakage to V
is defined as the voltage range at a receiving agent that will be int erpreted as a logic al
IH
high value.
and VOH may experience excursions above VTT. However, input signal drivers must
IH
comply with the signal quality specifications in Chapter 3.
referred to in these specifications refers to instantaneous VTT.
TT
is measured at 0.10 * V
OL
with land held at 300 mV.
TT
is measured at 0.90 * V
TT. IOH
TT .
2.8.3.1Platform Environment Control Interface (PECI) DC Specifications
PECI is an Intel proprietary one-wire interface that provides a communication channel
between Intel processors, chipsets, and external thermal monitoring devices. The
Yorkfield processor contains Digital Thermal Sensors (DTS) distributed throughout die.
These sensors are implemented as analog-to-digital converters calibrated at the factory
for reasonable accuracy to provide a digital representation of relative processor
temperature. PECI provides an interface to relay the highest DTS temper ature within a
die to external management devices for thermal/fan speed control. More detailed
information may be found in the Platform Environment Control Interface (PECI)
Specification.
Table 2-12. PECI DC Electrical Limits
SymbolDefinition and ConditionsMinMaxUnitsNotes
V
V
hysteresis
V
V
I
source
I
sink
I
leak+
I
leak-
C
V
noise
NOTES:
1. V
TT
refer to Table 2-3 for VTT specifications.
2. The leakage specification applies t o powered devices on the PECI bus.
3. The input buffers use a Schmitt-triggered input design for improved noise immunity.
4. One node is counted for each client and one node for the sy stem ho st. Ex tended trace lengths
might appear as additional nodes.
.
Input Voltage Range-0.15V
in
Hysteresis0.1 * V
Negative-edge threshold voltage0.275 * VTT0.500 * V
n
Positive-edge threshold voltage0.550 * VTT0.725 * V
p
High level output source
= 0.75 * VTT)
(V
OH
Low level output sink
= 0.25 * VTT)
(V
OL
High impedance state leakage to V
TT
-6.0N/AmA
0.51.0mA
N/A50µA
TT
TT
-V
V
V
TT
V
TT
High impedance leakage to GND N/A10µA2
Bus capacitance per node-10pF4
bus
Signal noise immunity above 300 MHz0.1 * V
TT
-V
p-p
supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. Please
1
2
3
2.8.3.2GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the
processor silicon. See Table 2-7 for details on which GTL+ signals do not include on-die
termination. Refer to the appropriate platform design guidelines for specific
implementation details.
26Datasheet
Electrical Specifications
Valid high and low levels are determined by the input buffers by comparing with a
reference voltage called GTLREF. Table 2-13 lists the GTLREF specifications. The GTL+
reference voltage (GTLREF) should be generated on the system board using high
precision voltage divider circuits. For more details on platform design, see the
applicable platform design guide.
Table 2-13. GTL+ Bus Voltage Definitions
SymbolParameterMinTypMaxUnits Notes
GTLREF_PU GTLREF pull up resistor57.6 * 0.9957.657.6 * 1.01Ω2
GTLREF_PD GTLREF pull down resistor 100 * 0.99100100 * 1.01Ω2
R
1.Unless other wise noted, all specifications in this table apply to all processor frequencies.
2.GTLREF is to be generated from VTT by a voltage divider of 1% resistors. If an Variable
3.R
4.COMP resistance must be provided on the system board with 1% resistors. See the
Termination Resistance455055Ω3
GTLREF circuit is used on the board the GTLREF lands connected to the Variable GTLREF
circuit may require different resistor values. Each GTLREF land must be connected, refer to
the platform design guide for implementation details.
is the on-die termination resistance measured at VTT/3 of the GTL+ output driver.
TT
Refer to the appropriate platform design guide for the board impedance. Refer to processor
I/O buffer models for I/V characteristics.
applicable platform design guide for implementation details. COMP[3:0] and COMP8
resistors are to V
SS
.
1
Datasheet
27
Electrical Specifications
2.9Clock Specifications
2.9.1Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor’s core frequency is a
multiple of the BCLK[1:0] frequency . The processor bus r atio multiplier will be set at its
default ratio during manufacturing. The processor supports Half Ratios between 7.5
and 13.5, refer to Table 2-14 for the processor supported ratios.
The processor uses a differential clo cking implem entation. For more information on the
processor clocking, contact your Intel field representative.
Table 2-14. Core Frequency to FSB Multiplier Configuration
Multiplication of
System Core
Frequency to FSB
Frequency
1/6
1/7
1/7.5
1/8
1/8.5
1/9
1/9.5
1/10
1/10.5
1/11
1/11.5
1/12
1/12.5
1/13
1/13.5
1/14
1/15
Core Frequency
(333 MHz BCLK/1333
MHz FSB)
2 GHz
2.33 GHz
2.50 GHz
2.66 GHz
2.83 GHz
3 GHz
3.16 GHz
3.33 GHz
3.50 GHz
3.66 GHz
3.83 GHz
4 GHz
4.16 GHz
4.33 GHz
4.50 GHz
4.66 GHz
5 GHz
Notes
1, 2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
NOTES:
1.Individual processors operate only at or below the rated frequency.
2.Listed frequencies are not necessarily committed production frequencies.
2.9.2FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). Table 2-15 defines the possible combinations of the signals and the
frequency associated with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All agents must operate at the same
frequency.
28Datasheet
Electrical Specifications
The Yorkfield processor will operate at a 1333 MHz FSB frequency (selected by a 333
MHz BCLK[1:0] frequency). Individual processors will only operate at their specified
FSB frequency.
For more information about these signals, refer to Section 4.2 and the appropriate
platform design guidelines.
Table 2-15. BSEL[2:0] Frequency Tab le for BCLK[1:0]
An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is
used for the PLL. Refer to Table 2-3 for DC specifications. Refer to the appropriate
platform design guidelines for decoupling and routing guidelines.
Datasheet
29
2.9.4BCLK[1:0] Specifications
Table 2-16. Front Side Bus Differential BCLK Specifications
SymbolParameterMinTypMaxUnitFigureNotes
V
V
V
CROSS(abs)
∆V
CROSS
V
OS
V
US
V
SWING
NOTES:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.Crossing voltage is defined as the instantaneous voltage value when the rising edge of
3.“Steady state” voltage, not including overshoot or undershoot.
4.Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined
BCLK[1:0] Frequency331.633-333.367MHz-7
T1: BCLK[1:0] Period2.99970-3.01538ns2-32
T2: BCLK[1:0] Period Stability--150ps2-33, 4
T5: BCLK[1:0] Rise and Fall Slew
Rate
Slew Rate MatchingN/AN/A20%-6
NOTES:
1.Unless otherwise noted, all specifications in this table apply to all processor core
frequencies based on a 333 MHz BCLK[1:0].
2.The period specified here is the average period. A given period may vary from this
specification as governed by the period stability specification (T2). Min period specification
is based on -300 PPM deviation from a 3 ns period. Max period specification is based on
the summation of +300 PPM deviation from a 3 ns period and a +0.5% maxi mum variance
due to spread spectrum clocking.
3.For the clock jitter specification, refer to the CK505 Clock Synthesizer Specification.
4.In this context, period stability is defined as the worst case timing difference between
successive crossover voltages. In other words, the largest absolute difference between
adjacent clock periods must be less than the period stability.
5.Slew rate is measured through the VSWING voltage range centered about differential zero.
Measurement taken from differential waveform.
6.Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is
measured using a ±75mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
2.5-8V/ns2-45
1
30Datasheet
Electrical Specifications
.
7.Duty Cycle (High time/Period) must be between 40 and 60%
Figure 2-3. Differential Clock Waveform
BCLK1
Threshold
Region
BCLK0
Tp = T 1 : B CLK[1 :0 ] period
T2: BCLK[1:0] pe r io d stability ( n ot shown)
Tph = T3: BCLK[1:0] pulse high time
Tpl = T4: BCLK[1:0] pulse low time
T5: BCLK[1:0] rise time through the threshold region
T6: BCLK[1 :0 ] fa ll time thr o u gh the th reshold r e g i o n
Tph
V
CROSS (ABS
)V
Tp
CROSS (ABS
Tpl
Overshoot
VH
Rising Edge
Ringback
)
Margin
Ringback
Falling Edge
VL
Undershoot
Ringback
Figure 2-4. Measurement Points for Differential Clock Waveforms
Slew_rise
+150 mV
0.0 V0.0V
V_swing
-150 mV
Diff
T5 = BCLK[1:0] rise and fall time through the swing region
§
Slew _fall
+150mV
-150mV
Datasheet
31
Electrical Specifications
32Datasheet
Package Mechanical Specifications
3Package Mechanical
Specifications
3.1Package Mechanical Specifications
The processor is packaged in a Flip-Chip Land Grid Array (FC-L GA8) package that
interfaces with the motherboard via an LGA775 socket. The package consists of a
processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS)
is attached to the package substrate and core and serves as the mating surface for
processor component thermal solutions, such as a heatsink. Figure 3-1 shows a sketch
of the processor package components and how they are assembled together. Refer to
the LGA775 Socket Mechanical Design Guide for complete details on the LGA775
socket.
The package components shown in Figure 3-1 include the following:
1. Integrated Heat Spreader (IHS)
2. Thermal Interface Material (TIM)
3. Processor core (die)
4. Package substrate
5. Capacitors
Figure 3-1. Processor Package Assembly Sketch
Substrate
Substrate
System Board
System Board
IHS
IHS
NOTE:
1.Socket and motherboard are included for reference and are not part of processor package.
Core (die)
Core (die)
TIM
TIM
Capacitors
Capacitors
LGA775 Socket
LGA775 Socket
Datasheet
33
3.1.1Package Mechanical Drawing
The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The
drawings include dimensions necessary to design a thermal solution for the processor.
These dimensions include:
1. Package reference with tolerances (total height, length, width, etc.)
2. IHS parallelism and tilt
3. Land dimensions
4. Top-side and back-side component keep-out dimensions
5. Reference datums
6. All drawing dimensions are in mm [in].
7. Guidelines on potential IHS flatness variation with socket load plate actuation and
installation of the cooling solution is available in the processor Thermal/Mechanical
Design Guidelines.
Package Mechanical Specifications
34Datasheet
Package Mechanical Specifications
Figure 3-2. Processor Package Drawing Sheet 1 of 3
Datasheet
35
Figure 3-3. Processor Package Drawing Sheet 2 of 3
Package Mechanical Specifications
36Datasheet
Package Mechanical Specifications
Figure 3-4. Processor Package Drawing Sheet 3 of 3
Datasheet
37
3.1.2Processor Component Keep-Out Zones
The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into
the required keep-out zones. Decoupling capacitors are typically mounted to either the
topside or land-side of the package substrate. See Figure 3-2 and Figure 3-3 for keepout zones. The location and quantity of package capacitors may change due to
manufacturing efficiencies but will remain within the component keep-in.
3.1.3Package Loading Specifications
Table 3-1 provides dynamic and static load specifications for the processor package.
These mechanical maximum load limits should not be exceeded during heatsink
assembly, shipping conditions, or standard use condition. Also, any mechanical system
or component testing should not exceed the maximum limits. The processor package
substrate should not be used as a mechanical reference or load-bearing surface for
thermal and mechanical solution. The minimum loading specification must be
.
Table 3-1.Processor Loading Specifications
maintained by any thermal and mechanical solutions.
ParameterMinimumMaximumNotes
Static80 N [17 lbf]311 N [70 lbf]1, 2, 3
Dynamic-756 N [170 lbf]1, 3, 4
Package Mechanical Specifications
NOTES:
1.These specifications apply to uniform compressive l oading in a direction normal to the
processor IHS.
2.This is the maximum force that can be applied by a heatsink retention clip. The clip must
3.These specifications are based on limited testing for design characterization. Loading limits
4.Dynamic loading is defined as an 11 ms duration average load superimposed on the static
also provide the minimum specified load on the processor package.
are for the package only and do not include the limits of the processor socket.
load requirement.
3.1.4Package Handling Guidelines
Table 3-2 includes a list of guidelines on package handling in terms of recommended
maximum loading on the processor IHS relative to a fixed substrate. These package
handling loads may be experienced during heatsink removal.
Table 3-2.Package Handling Guidelines
ParameterMaximum RecommendedNotes
Shear311 N [70 lbf]1, 4
Tensile111 N [25 lbf]2, 4
Torque3.95 N-m [35 lbf-in]3, 4
NOTES:
1.A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top
surface.
2.A tensile load is defined as a pulling load applied to the IHS in a direction normal to the
3.A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal
IHS surface.
to the IHS top surface.
38Datasheet
Package Mechanical Specifications
4.These guidelines are bas ed on limited testing for design characterization.
3.1.5Package Insertion Specifications
The processor can be inserted into and removed from a LGA775 socket 15 times. The
socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide.
3.1.6Processor Mass Specification
The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all
the components that are included in the package.
3.1.7Processor Materials
Table 3-3 lists some of the package components and associated materials.
This chapter provides the processor land assignment and signal descriptions.
4.1Processor Land Assignments
This section contains the land listings for the processor. The land-out footprint is shown
in Figure 4-1 and Figure 4-2. These figures represent the land-out arranged by land
number and they show the physical location of each signal on the package land array
(top view). Table 4-1 is a listing of all processor lands ordered alphabetically by land
(signal) name. Table 4-2 is also a listing of all processor lands; the ordering is by land
number.
Datasheet
41
Land Listing and Signal Descriptions
Figure 4-1.land-out Diagram (Top View – Left Side)
D25#D13Source SynchInput/Outpu t
D26#E13Source SynchInput/Outpu t
D27#G13Source SynchInput/Output
D28#F14Source SynchInput/Output
D29#G14Source SynchInput/Output
D3#C6Source SynchInput/Output
D30#F15Source SynchInput/Output
D31#G15Source SynchInput/Output
D32#G16Source SynchInput/Output
D33#E15Source SynchInput/Outpu t
D34#E16Source SynchInput/Outpu t
D35#G18Source SynchInput/Output
D36#G17Source SynchInput/Output
D37#F17Source SynchInput/Output
D38#F18Source SynchInput/Output
D39#E18Source SynchInput/Outpu t
D4#A5Source SynchInput/Output
D40#E19Source SynchInput/Outpu t
D41#F20Source SynchInput/Output
D42#E21Source SynchInput/Outpu t
D43#F21Source SynchInput/Output
D44#G21Source SynchInput/Output
D45#E22Source SynchInput/Outpu t
D46#D22Source SynchInput/Outpu t
D47#G22Source SynchInput/Output
D48#D20Source SynchInput/Outpu t
D49#D17Source SynchInput/Outpu t
A[35:3]# (Address) define a 2
space. In sub-phase 1 of the address phase, these signals transmit
the address of a transaction. In sub-phase 2, these signals transmit
transaction type information. These signals must connect the
A[35:3]#
A20M#Input
ADS#
ADSTB[1:0]#
Input/
Output
Input/
Output
Input/
Output
appropriate pins/lands of all agents on the processor FSB. A[35:3]#
are source synchronous signals and are latched into the receiving
buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the proce ssor
samples a subset of the A[35:3]# signals to determine power-on
configuration. See Section 6.1 for more details.
If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any internal
cache and before driving a read/write transaction on the bus.
Asserting A20M# emulates the 8086 processor's address wraparound at the 1-MB boundary. Assertion of A20M# is only supported
in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of
this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[35:3]# and REQ[4:0]# signals. All bus
agents observe the ADS# activation to begin protocol checking,
address decode, internal snoop, or deferred reply ID match
operations associated with the new transaction.
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their
rising and falling edges. Strobes are associated with signals as shown
below.
Signals
Land Listing and Signal Descriptions
36
-byte physical memory address
Associated
Strobe
BCLK[1:0]Input
BNR#
64Datasheet
Input/
Output
REQ[4:0]#, A[16:3]# ADSTB0#
A[35:17]#ADSTB1#
The differential pair BCLK (Bus Clock) determines the FSB frequency.
All processor FSB agents must receive these signals to drive their
outputs and latch their inputs.
All external timing parameters are speci fied with r espect to the ri sing
edge of BCLK0 crossing V
BNR# (Block Next Request) is used to assert a bus stall by any bus
agent unable to accept new bus transactions. During a bus stall, the
current bus owner cannot issue any new transactions.
CROSS
.
Land Listing and Signal Descriptions
Table 4-3.Signal Description (Sheet 2 of 10)
NameTypeDescription
BPM[5:0]# and BPMb[3:0]# (Breakpoint Monitor) are breakpoint and
performance monitor signals. They are outputs from the processor
which indicate the status of breakpoints and programmable counters
used for monitoring processor performance. BPM[5:0]# and
BPMb[3:0]# should connect the appropriate pins/lands of all
processor FSB agents. BPM[3:0]# are associated with core 0.
BPMb[3:0]# are associated with core 1.
BPM[5:0]#
BPMb[3:0]#
Input/
Output
BPRI#Input
BR0#
Input/
Output
BSEL[2:0]Output
COMP[3:0],
COMP8
Analog
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port.
PRDY# is a processor output used by debug tools to determine
processor debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP
port. PREQ# is used by debug tools to request debug operation of the
processor.
Refer to the appropriate platform design guide for more detailed
information.
These signals do not have on-die termination. Refer to Section 2.7.2,
and appropriate platform design guide for termination requirements.
BPRI# (Bus Priority Request) is used to arbitrate for ownershi p of the
processor FSB. It must connect the appropriate pins/lands of all
processor FSB agents. Observing BPRI# active (as asserted by the
priority agent) causes all other agents to stop issuing new requests,
unless such requests are part of an ongoing locked operation. The
priority agent keeps BPRI# asserted until all of its requests are
completed, then releases the bus by de-asserting BPRI#.
BR0# drives the BREQ0# signal in the system and is used by the
processor to request the bus. During power-on configuration this
signal is sampled to determine the agent ID = 0.
This signal does not have on-die termination and must be terminated.
The BCLK[1:0] frequency select signals BSEL[2:0] are used to select
the processor input clock frequency. Table 2-15 defines the possible
combinations of the signals and the frequency associated with each
combination. The required frequency is determined by the processor,
chipset and clock synthesizer. All agents must operate at the same
frequency. For more information about these signals, including
termination recommendations refer to Section 2.9.2 and the
appropriate platform design guidelines.
COMP[3:0] and COMP8 must be terminated to V
board using precision resistors. Refer to the appropriate platform
design guide for details on implementation.
on the system
SS
Datasheet
65
Table 4-3.Signal Description (Sheet 3 of 10)
NameTypeDescription
D[63:0]# (Data) are the data signals. These signals provide a 64-bit
data path between the processor FSB agents, and must connect the
appropriate pins/lands on all such agents. The data driver asserts
DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will, thus, be driven four
times in a common clock period. D[63:0]# are latched off the falling
edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data
signals correspond to a pair of one DSTBP# and one DSTBN#. The
following table shows the grouping of data signals to data strobes and
DBI#.
Quad-Pumped Signal Groups
D[63:0]#
Input/
Output
Data Group
D[15:0]#00
D[31:16]#11
D[47:32]#22
D[63:48]#33
DSTBN#/
DSTBP#
Land Listing and Signal Descriptions
DBI#
DBI[3:0]#
Input/
Output
DBR#Output
DBSY#
Input/
Output
Furthermore, the DBI# signals determine the polarity of the data
signals. Each group of 16 data signals corresponds to one DBI#
signal. When the DBI# signal is active, the corresponding data group
is inverted and therefore sampled active high.
DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate
the polarity of the D[63:0]# signals.The DBI[3:0]# signals are
activated when the data on the data bus is inverted. If more than half
the data bits, within a 16-bit group, would have been asserted
electrically low, the bus agent may invert the data bus signals for that
particular sub-phase for that 16-bit group.
DBI[3:0] Assignment To Data Bus
Bus Signal
Data Bus
Signals
DBI3#D[63:48]#
DBI2#D[47:32]#
DBI1#D[31:16]#
DBR# (Debug Reset) is used only in processor systems where no
debug port is implemented on the system board. DBR# is used by a
debug port interposer so that an in-target probe can drive system
reset. If a debug port is implemented in the system, DBR# is a no
connect in the system. DBR# is not a processor signal.
DBSY# (Data Bus Busy) is asserted by the agent responsible for
driving data on the processor FSB to indicate that the data bus is in
use. The data bus is released after DBSY# is de-asserted. This signal
must connect the appropriate pins/lands on all processor FSB agents.
66Datasheet
Land Listing and Signal Descriptions
Table 4-3.Signal Description (Sheet 4 of 10)
NameTypeDescription
DEFER# is asserted by an agent to indicate that a transaction cannot
be ensured in-order completion. Assertion of DEFER# is normally the
DEFER#Input
DPRSTP#Input
DPSLP#Input
responsibility of the addressed memory or input/output agent. This
signal must connect the appropriate pins/lands of all processor FSB
agents.
DPRSTP#, when asserted on the platform, causes the processor to
transition from the Deep Sleep State to the Deeper Sleep state. To
return to the Deep Sleep State, DPRSTP# must be deasserted. Use of
the DPRSTP# pin, and corresponding low power state, requires
chipset support and may not be available on all platforms. Refer to
the appropriate platform design guide for implementation details.
NOTE: Some processors may not have the Deeper Sleep State
enabled, refer to the Specification Update for specific sku and
stepping guidance.
DPSLP#, when asserted on the platform, causes the processor to
transition from the Sleep State to the Deep Sleep state. To return to
the Sleep State, DPSLP# must be deasserted. Us e of the DPSLP# pin,
and corresponding low power state, requires chipset support and may
not be available on all platforms. Refer to the appropriate platform
design guide for implementation details.
DRDY#
DSTBN[3:0]#
DSTBP[3:0]#
FC0/
BOOTSELECT
Input/
Output
Input/
Output
Input/
Output
Other
NOTE: Some processors may not have the Deep Sleep State enabled,
refer to the Specification Update for specific sku and stepping
guidance.
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be de-asserted to insert idle clocks.
This signal must connect the appropriate pins/lands of all processor
FSB agents.
DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
FC0/BOOTSELECT is not used by the Yorkfield processor. When this
land is tied to Vss previous processors based on the Intel NetBurst®
microarchitecture should be disabled and prevented from booting.
Refer to appropriate platform design guide for termination guidance.
Datasheet
67
Table 4-3.Signal Description (Sheet 5 of 10)
NameTypeDescription
FCxOther
FERR#/PBE#Output
GTLREF[3:0]Input
Input/
HIT#
HITM#
Output
Input/
Output
IERR#Output
IGNNE#Input
FC signals are signals that are available for compatibility with other
processors. Refer to the appropriate platform design guide for more
information on how these are connected on the motherboard.
FERR#/PBE# (floating point error/pending break event) is a
multiplexed signal and its meaning is qualified by STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating-point
error and will be asserted when the processor detects an unmasked
floating-point error. When STPCLK# is not asserted, FERR#/PBE# is
similar to the ERROR# signal on the Intel 387 coprocessor, and is
included for compatibility with systems using MS-DOS*-type floatingpoint error reporting. When STPCLK# is asserted, an assertion of
FERR#/PBE# indicates that the processor has a pending break event
waiting for service. The assertion of FERR#/PBE# indicates that the
processor should be returned to the Normal state. For additional
information on the pending break event functionality, including the
identification of support of the feature and enable/disable
information, refer to volume 3 of the Intel Architecture Software
Developer's Manual and the Intel Processor Identification and the
CPUID Instruction application note.
GTLREF[3:0] determine the signal reference level for GTL+ input
signals. GTLREF is used by the GTL+ receivers to determine if a
signal is a logical 0 or logical 1. Refer to the applicable platform
design guide for more information.
HIT# (Snoop Hit) and HITM# (Hit Modified) convey tr ansaction snoop
operation results. Any FSB agent may assert both HIT# and HITM#
together to indicate that it requires a snoop stall, which can be
continued by reasserting HIT# and HITM# together.
IERR# (Internal Error) is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor FSB. This transaction may
optionally be converted to an external error signal (e.g., NMI) by
system core logic. The processor will keep IERR# asserted until the
assertion of RESET#.
This signal does not have on-die termination. Refer to Section 2.7.2
for termination requirements.
IGNNE# (Ignore Numeric Error) is asserted to the processor to ignore
a numeric error and continue to execute noncontrol floating-point
instructions. If IGNNE# is de-asserted, the processor generates an
exception on a noncontrol floating-point instruction if a previous
floating-point instruction caused an error. IGNNE# has no effect when
the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of
this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
Land Listing and Signal Descriptions
68Datasheet
Land Listing and Signal Descriptions
Table 4-3.Signal Description (Sheet 6 of 10)
NameTypeDescription
INIT# (Initialization), when asserted, resets integer registers inside
the processor without affecting its internal caches or floating-point
registers. The processor then begins e xecutio n at the power -on Res et
vector configured during power-on configuration. The processor
INIT#Input
ITP_CLK[1:0]Input
LINT[1:0]Input
LOCK#
Input/
Output
MSID[1:0]Output
PECI
PROCHOT#
Input/
Output
Input/
Output
continues to handle snoop requests during INIT# assertion. INIT# is
an asynchronous signal and must connect the appropriate pins/lands
of all processor FSB agents.
If INIT# is sampled active on the active to inactive transition of
RESET#, then the processor executes its Built-in Self-Test (BIST).
ITP_CLK[1:0] are copies of BCLK that are used only in processor
systems where no debug port is implemented on the system board.
ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port
implemented on an interposer. If a debug port is implemented in the
system, ITP_CLK[1:0] are no connects in the system. These are not
processor signals.
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins/
lands of all APIC Bus agents. When the APIC is disabled, the LINT0
signal becomes INTR, a maskable interrupt request signal, and LINT1
becomes NMI, a nonmaskable interrupt. INTR and NMI are backward
compatible with the signals of those names on the Pentium processor .
Both signals are asynchronous.
Both of these signals must be software configured via BIOS
programming of the APIC register space to be used either as NMI/
INTR or LINT[1:0]. Because the APIC is enabled by default after
Reset, operation of these signals as LINT[1:0] is the default
configuration.
LOCK# indicates to the system that a transaction must occur
atomically. This signal must connect the appropriate pins/lands of all
processor FSB agents. For a locked sequence of transactions, LOCK#
is asserted from the beginning of the first transaction to the end of
the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of
the processor FSB, it will wait until it observes LOCK# de-asserted.
This enables symmetric agents to retain ownership of the processor
FSB throughout the bus locked operation and ensure the atomicity of
lock.
On a Yorkfield processor these signals are not connected on the
package (they are floating). As an alternative to MSID, Intel has
implemented the Power Segment Identifier (PSID) to report the
maximum Thermal Design Power of the processor. Refer to the
Platform Design Guide for additional information regarding PSID.
PECI is a proprietary one-wire bus interface. See Chapter 5.3 for
details.
As an output, PROCHOT# (Processor Hot) will go active when the
processor temperature monitoring sensor detects that the processor
has reached its maximum safe operating temperature. This indicates
that the processor Thermal Control Circuit (TCC) has been activated,
if enabled. As an input, assertion of PROCHOT# by the system will
activate the TCC, if enabled. The TCC will remain active until the
system de-asserts PROCHOT#. See Section 5.2.4 for more details.
Datasheet
69
Table 4-3.Signal Description (Sheet 7 of 10)
NameTypeDescription
PWRGOOD (Power Good) is a processor input. The processor requires
this signal to be a clean indication that the clocks and power supplies
are stable and within their specifications. ‘Clean’ implies that the
signal will remain low (capable of sinking leakage current), without
glitches, from the time that the power supplies are turned on until
PWRGOODInput
REQ[4:0]#
Input/
Output
RESET#Input
RESERVED
RS[2:0]#Input
SKTOCC#Output
SMI#Input
they come within specification. The signal must then transition
monotonically to a high state. PWRGOOD can be driven inactive at
any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to
protect internal circuits against voltage sequencing issues. It should
be driven high throughout boundary scan operation.
REQ[4:0]# (Request Command) must connect the appropriate pins/
lands of all processor FSB agents. They are asserted by the current
bus owner to define the currently active transaction type. These
signals are source synchronous to ADSTB0#.
Asserting the RESET# signal resets the processor to a known state
and invalidates its internal caches without writing back any of their
contents. For a power-on Reset, RESET# must stay active for at least
one millisecond after V
specifications. On observing active RESET#, all FSB agents will deassert their outputs within two clocks. RESET# must not be kept
asserted for more than 10 ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive
transition of RESET# for power-on configuration. These configuration
options are described in the Section 6.1.
This signal does not have on-die termination and must be terminated
on the system board.
All RESERVED lands must remain unconnected. Connection of these
lands to V
CC
can result in component malf unction or incompatibility with f u ture
processors.
RS[2:0]# (Response Status) are driven by the response agent (the
agent responsible for completion of the current transaction), and
must connect the appropriate pins/lands of all processor FSB agents.
SKTOCC# (Socket Occupied) will be pulled to ground by the
processor. System board designers may use this signal to determine
if the processor is present.
SMI# (System Management Int errupt) is asserted a synchronously by
system logic. On accepting a System Management Interrupt, the
processor saves the current state and enter System Management
Mode (SMM). An SMI Acknowledge transaction is issued, and the
processor begins program execution from the SMM handler.
If SMI# is asserted during the de-assertion of RESET#, the processor
will tri-state its outputs.
Land Listing and Signal Descriptions
and BCLK have reached their proper
CC
, VSS, VTT, or to any other signal (including each other)
70Datasheet
Land Listing and Signal Descriptions
Table 4-3.Signal Description (Sheet 8 of 10)
NameTypeDescription
STPCLK# (Stop Clock), when asserted, causes the processor t o enter
a low power Stop-Grant state. The processor issues a Stop-Grant
Acknowledge transaction, and stops providing internal clock signals
to all processor core units except the FSB and APIC units. The
STPCLK#Input
TCKInput
TDI, TDI_MInput
TDO, TDO_MOutput
TESTHI[13,
11:10,7:0]
Input
THERMTRIP#Output
TMSInput
TRDY#Input
TRST#Input
processor continues to snoop bus transactions and service interrupts
while in Stop-Grant state. When STPCLK# is de-asserted, the
processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
TCK (Test Clock) provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TDI and TDI_M (Test Data In) transfers serial test data into the
processor. TDI and TDI_M provide the serial input needed for JTAG
specification support. TDI connects to core 0. TDI_M con nects to core
1. Refer to the appropriate platform design guide for more
information.
TDO and TDO_M (Test Data Out) transfers serial test data out of the
processor . TDO and TDO_M provide the serial output needed for JTAG
specification support. TDO connects to core 1. TDO_M connects to
core 0. Refer to the appropriate platform design guide for more
information.
TESTHI[13,11:10,7:0] must be connected to the processor’s
appropriate power source (refer to VTT_OUT_LEFT and
VTT_OUT_RIGHT signal description) through a resistor for proper
processor operation. See Section 2.4 for more details.
In the event of a catastrophic cooling failure, the processor will
automatically shut down when the silicon has reached a temperature
approximately 20 °C above the maximum T
THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level beyond where permanent silicon
damage may occur. Upon assertion of THERMTRIP#, the processor
will shut off its internal clocks (thus, halting program execution) in an
attempt to reduce the processor junction temperature. To protect the
processor, its core voltage (V
assertion of THERMTRIP#. Driving of the THERMTRIP# signal is
enabled within 10 µs of the assertion of PWRGOOD (provided V
V
are asserted) and is disabled on de-assertion of PWRGOOD (if VTT
CC
or V
are not valid, THERMTRIP# may also be disabled). Once
CC
activated, THERMTRIP# remains latched until PWRGOOD, V
is de-asserted. While the de-assertion of the PWRGOOD, V
signal will de-assert THERMTRIP#, if the processor’s junction
temperature remains at or above the trip level, THERMTRIP# will
again be asserted within 10 µs of the assertion of PWRGOOD
(provided V
TMS (Test Mode Select) is a JTAG specification support signal used by
debug tools.
TRDY# (Target Ready) is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins/lands of all FSB agents.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset. Refer to the Debug Port Design Guide for UP / DP Systems for complete implementation
details.
TT
and V
are valid).
CC
. Assertion of
C
) must be removed following the
CC
TT
TT
TT
or V
or V
and
CC
CC
Datasheet
71
Table 4-3.Signal Description (Sheet 9 of 10)
NameTypeDescription
VCCInput
VCCAInput
VCCIOPLLInput
VCCPLLInputVCCPLL provides isolated power for internal processor FSB PLLs.
VCC_SENSEOutput
VCC_MB_
REGULATION
Output
VID[7:0]Output
VID_SELECTOutput
VRDSELInput
VSSInput
VSSAInput
VSS_SENSEOutput
VSS_MB_
REGULATION
Output
VTTMiscellaneous voltage supply.
VCC are the power pins for the processor. The voltage supplied to
these pins is determined by the VID[7:0] pins.
VCCA provides isolated power for internal PLLs on previous
generation processors. It may be left as a No-Connect on boards
supporting the Wolfdale processor.
VCCIOPLL provides isolated power for internal processor FSB PLLs on
previous generation processors. It may be left as a No-Connect on
boards supporting the Wolfdale processor.
VCC_SENSE is an isolated low impedance connection to processor
core power (V
the silicon with little noise.
This land is provided as a voltage regulator feedback sense point for
V
. It is connected internally in the processor package to the sense
CC
point land U27 as described in the Voltage Regulator-Down (VRD)
11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket.
The VID (Voltage ID) signals are used to support automatic selection
of power supply voltages (V
design guide or the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for
more information. The voltage supply for these signals must be valid
before the VR can supply V
output must be disabled until the voltage supply for the VID signals
becomes valid. The VID signals are needed to support the processor
voltage specification variations. See Table 2-1 for definitions of these
signals. The VR must supply the voltage that is requested by the
signals, or disable itself.
This land is tied high on the processor package and is used by the VR
to choose the proper VID table. Refer to the appropriate platform
design guide or the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for
more information.
This input should be left as a no connect in order for the processor to
boot. The processor will not boot on legacy platforms where this land
is connected to V
VSS are the ground pins for the processor and should be connected
to the system ground plane.
VSSA provides isolated ground for internal PLLs on previous
generation processors. It may be left as a No-Connect on boards
supporting the Wolfdale processor.
VSS_SENSE is an isolated low impedance connection to processor
core V
with little noise.
. It can be used to sense or measure gro un d n ear th e si licon
SS
This land is provided as a voltage regulator feedback sense point for
V
. It is connected internally in the processor package to the sense
SS
point land V27 as described in the Voltage Regulator-Down (VRD)
11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket.
Land Listing and Signal Descriptions
). It can be used to sense or measure voltage near
CC
). Refer to the appropriate platform
CC
to the processor. Conversely, the VR
CC
.
SS
72Datasheet
Land Listing and Signal Descriptions
Table 4-3.Signal Description (Sheet 10 of 10)
NameTypeDescription
VTT_OUT_LEFT
Output
VTT_OUT_RIGHT
VTT_SELOutput
The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to
provide a voltage supply for some signals that require termination to
V
on the motherboard. Refer to the appropriate platform design
TT
guide for details on implementation.
The VTT_SEL signal is used to select the correct V
the processor. This land is connected internally in the package to V
§
voltage level for
TT
SS
.
Datasheet
73
Land Listing and Signal Descriptions
74Datasheet
Thermal Specifications and Design Considerations
5Thermal Specifications and
Design Considerations
5.1Processor Thermal Specifications
The processor requires a thermal solution to maintain temperatures within the
operating limits as set forth in Section 5.1.1. Any attempt to operate the processor
outside these operating limits may result in permanent damage to the processor and
potentially other components within the system. As processor technology changes,
thermal management becomes increasingly crucial when building computer systems.
Maintaining the proper thermal environment is key to reliable, long-term system
operation.
A complete thermal solution includes both component and system level thermal
management features. Component level thermal solutions can include active or passive
heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system
level thermal solutions may consist of system fans combined with ducting and venting.
For more information on designing a component level thermal solution, refer to the
Yorkfield Processor Thermal and Mechanical Design Guidelines Addendum.
Note:The boxed processor will ship with a component thermal solution. Refer to Chapter 7
for details on the boxed processor.
5.1.1Thermal Specifications
To allow for the optimal operation and long-term reliability of Intel processor-based
systems, the system/processor thermal solution should be designed such that the
processor remains within the minimum and maximum case temperature (T
specifications when operating at or below the Thermal Design Power (TDP) value listed
per frequency in Table 5-1. Thermal solutions not designed to provide this level of
thermal capability may affect the long-term reliability of the processor and system. For
more details on thermal solution design, refer to the Yorkfield Processor Thermal and Mechanical Design Guidelines Addendum.
The processor uses a methodology for managing processor temperatures which is
intended to support acoustic noise reduction through fan speed control. Selection of the
appropriate fan speed is based on the relative temperature data reported by the
processor’s Platform Environment Control Interface (PECI) bus as described in
Section 5.3. If the value reported via PECI is less than T
temperature is permitted to exceed the Thermal Profile. If the value reported via PECI
is greater than or equal to T
at or below the temperature as specified by the thermal profile. The temperature
reported over PECI is always a negative value and represents a delta below the onset of
thermal control circuit (TCC) activation, as indicated by PROCHOT# (see Section 5.2).
Systems that implement fan speed control must be designed to take these conditions in
to account. Systems that do not alter the fan speed only need to ensure the case
temperature meets the thermal profile specifications.
In order to determine a processor's case temperature specification based on the
thermal profile, it is necessary to accurately measure processor power dissipation. Intel
has developed a methodology for accurate power measurement that correlates to Intel
test temperature and voltage conditions. Refer to the Yorkfie ld Proce ssor Thermal and
Mechanical Design Guidelines Addendum and the Live Die System Thermal Testing
Basics for the details of this methodology.
CONTROL
, then the processor case temperature must remain
CONTROL
, then the case
)
C
Datasheet
75
The case temperature is defined at the geometric top center of the processor. Analysis
indicates that real applications are unlikely to cause the processor to consume
maximum power dissipation for sustained time periods. Intel recommends that
complete thermal solution designs target the Thermal Design Power (TDP) indicated in
Table 5-1 instead of the maximum processor power consumption. The Thermal Monitor
feature is designed to protect the processor in the unlikely event that an application
exceeds the TDP recommendation for a sustained periods of time. For more details on
the usage of this feature, refer to Section 5.2. To ensure maximum flexibility for future
requirements, systems should be designed to the Flexible Motherboard (FMB)
guidelines, even if a processor with a lower thermal dissipation is currently planned. In
all cases the Thermal Monitor or Thermal Monitor 2 feat ure must be enabled
for the processor to remain within specification.
Table 5-1.Processor Thermal Specifications
Thermal Specifications and Design Considerations
Processor
Number
X3380
X3370
X3330
X3360
X3350
X3320
L3360
Core
Frequency
(GHz)
3.16
3.00
2.66
2.83
2.66
2.50
2.83
Thermal
Design
Power (W)
2, 3
95
95
95
95
95
95
65
Extended
HALT
Power
1
(W)
12
16
16
12
12
12
12
FMB Guidance
4
775_VR_CONFIG_05A
(95W)
775_VR_CONFIG_05A
(95W)
775_VR_CONFIG_06A
(65 W) [L3360]
Minimum
T
(°C)
C
5
5
Maximum T
(°C)
See Table 5-2
and
Figure 5-1
See Table 5-2
and
Figure 5-1
C
Notes
NOTES:
1.Specification is at 37°C Tc and minimum voltage loadline. Specification is guaranteed by
design characterization and not 100% tested.
2.Thermal Design Power (TDP) should be used for processor thermal solution design targets.
The TDP is not the maximum power that the processo r can dissipate.
3.This table shows the maximum TDP for a given frequency range. Individual processors
may have a lower TDP. Therefore, the maximum T
individual processor. Refer to thermal profile figure and associated table for the allowed
combinations of power and T
.
C
will vary depending on the TDP of the
C
4.FMB, or Flexible Motherboard, guidelines provide a design target for meeting future
thermal requirements.
The maximum and minimum case temperatures (TC) for the processor is specified in
Table 5-1. This temperature specification is meant to help ensure proper operation of
the processor. Figure 5-3 illustrates where Intel recommends TC thermal
measurements should be made. For detailed guidelines on temperature measurement
methodology, refer to the Yorkfield Processor Thermal and Mechanical Design Guidelines Addendum.
Thermal Specifications and Design Considerations
Figure 5-3. Case Temperature (T
37.5 mm
37.5 mm
) Measurement Location
C
(geometric center of the package)
(geometric center of the package)
37.5 mm
37.5 mm
Measure TCat this point
Measure TCat this point
5.2Processor Thermal Features
5.2.1Thermal Monitor
The Thermal Monitor feature helps control the processor temper ature by activ ating the
thermal control circuit (TCC) when the processor silicon reaches its maximum operating
temperature. The TCC reduces processor power consumption by modulating (starting
and stopping) the internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to be operating within specifications. The
temperature at which Thermal Monitor activates the thermal control circuit is not user
configurable and is not software visible. Bus traffic is snooped in the normal manner,
and interrupt requests are latched (and serviced during the time that the clocks are on)
while the TCC is active.
When the Thermal Monitor feature is enabled, and a high temperature situation exists
(i.e., TC C is active), the clocks will be modulated by alternately turning the clocks off
and on at a duty cycle specific to the processor (typically 30-50%). Clocks often will not
be off for more than 3.0 microseconds when the TCC is active. Cycle times are
processor speed dependent and will decrease as processor core frequencies increase. A
small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the TCC goes inactive and clock
modulation ceases.
With a properly designed and characterized thermal solution, it is anticipated that the
TCC would only be activated for very short periods of time when running the most
power intensive applications. The processor performance impact due to these brief
80Datasheet
Thermal Specifications and Design Considerations
periods of TCC activation is expected to be so minor that it would be immeasurable. An
under-designed thermal solution that is not able to prevent excessive activation of the
TCC in the anticipated ambient environment ma y cause a noticeable performance loss,
and in some cases may result in a T
and may affect the long-term reliability of the processor. In addition, a thermal solution
that is significantly under-designed may not be capable of cooling the processor even
when the TCC is active continuously. Refer to the Yorkfield Processor Thermal and Mechanical Design Guidelines Addendum for information on designing a thermal
solution.
The duty cycle for the TCC, when activated by the Thermal Monitor, is factory
configured and cannot be modified. The Thermal Monitor does not require any
additional hardware, software drivers, or interrupt handling routines.
5.2.2Thermal Monitor 2
The processor also supports an additional power reduction capability known as Thermal
Monitor 2. This mechanism provides an efficient means for limiting the processor
temperature by reducing the power consumption within the processor.
When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the
Thermal Control Circuit (TCC) will be activated. The TCC causes the processor to adjust
its operating frequency (via the bus multiplier) and input voltage (via the VID signals).
This combination of reduced frequency and VID results in a reduction to the processor
power consumption.
that exceeds the specified maximum temperature
C
A processor enabled for Thermal Monitor 2 includes two operating points, each
consisting of a specific operating frequency and voltage. The first operating point
represents the normal operating condition for the processor. Under this condition, the
core-frequency-to-FSB multiple utilized by the processor is that contained in the
CLK_GEYSIII_STAT MSR and the VID is that specified in Table 2-3. These parameters
represent normal system operation.
The second operating point consists of both a lower operating frequency and voltage.
When the TCC is activated, the processor automatically transitions to the new
frequency. This transition occurs very rapidly (on the order of 5 µs). During the
frequency transition, the processor is unable to service any bus requests, and
consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and
kept pending until the processor resumes operation at the new frequency.
Once the new operating frequency is engaged, the processor will transition to the new
core operating voltage by issuing a new VID code to the voltage regulator. The voltage
regulator must support dynamic VID steps in order to support Thermal Monitor 2.
During the voltage change, it will be necessary to transition through multiple VID codes
to reach the target operating voltage. Each step will likely be one VID table entry (see
Table 2-3). The processor continues to execute instructions during the voltage
transition. Operation at the lower voltage reduces the power consumption of the
processor.
A small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the operating frequency and
voltage transition back to the normal system operating point. Transition of the VID code
will occur first, in order to ensure proper operation once the processor reaches its
normal operating frequency. Refer to Figure 5-4 for an illustration of this ordering.
Datasheet
81
Thermal Specifications and Design Considerations
Figure 5-4. Thermal Monitor 2 Frequency and Voltage Ordering
T
f
f
TM2
MAX
TM2
Temperature
Frequency
VID
VID
TM2
VID
PROCHOT#
The PROCHOT# signal is asserted when a high temperature situation is detected,
regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled.
It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on
demand mode. The Thermal Monitor TCC, however, can be activated through the use of
the on demand mode.
5.2.3On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force
the processor to reduce its power consumption. This mechanism is referred to as “OnDemand” mode and is distinct from the Thermal Monitor feature. On-Demand mode is
intended as a means to reduce system level power consumption. Systems using the
processor must not rely on software usage of this mechanism to limit the processor
temperature.
If bit 4 of the ACPI P_CNT Control Register (located in the processor
IA32_THERM_CONTROL MSR) is written to a '1', the processor will immediately reduce
its power consumption via modulation (starting and stopping) of the internal core clock,
independent of the processor temperature. When using On-Demand mode, the duty
cycle of the clock modulation is programmable via bits 3:1 of the same ACPI P_ CN T
Control Register. In On-Demand mode, the duty cycle can be programmed from 12.5%
on/87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be
used in conjunction with the Thermal Monitor. If the system tries to enable On-Demand
mode at the same time the TCC is engaged, the factory configured duty cycle of the
TCC will override the duty cycle selected by the On-Demand mode.
82Datasheet
Thermal Specifications and Design Considerations
5.2.4PROCHOT# Signal
An external signal, PROCHOT# (processor hot), is asserted when the processor core
temperature has reached its maximum operating temperature. If the Thermal Monitor
is enabled (note that the Thermal Monitor must be enabled for the processor to be
operating within specification), the TCC will be active when PROCHOT# is asserted. The
processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.
PROCHOT# is a bi-directional signal. As an output, PROCHOT# (Processor Hot) will go
active when the processor temperature monitoring sensor detects that one or both
cores has reached its maximum safe operating temperature. This indicates that the
processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input,
assertion of PROCHOT# by the system will activate the T CC, if enabled, for both cores.
The TCC will remain active until the system de-asserts PROCHOT#.
PROCHOT# allows for some protection of various components from over-temperature
situations. The PROCHOT# signal is bi-directional in that it can either signal when the
processor (either core) has reached its maximum operating temperature or be driven
from an external source to activate the TCC. The ability to activate the TCC via
PROCHOT# can provide a means for thermal protection of system components.
Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained
current instead of maximum current. Systems should still provide proper cooling for the
VR, and rely on bi-directional PROCHOT# only as a backup in case of system cooling
failure. The system thermal design should allow the power delivery circuitry to operate
within its temperature specification even while the processor is operating at its Thermal
Design Power. With a properly designed and characterized thermal solution, it is
anticipated that bi-directional PROCHOT# would only be asserted for very short periods
of time when running the most power intensive applications. An under-designed
thermal solution that is not able to prevent excessive assertion of PROCHOT# in the
anticipated ambient environment may cause a noticeable performance loss. Refer to
the appropriate platform design guide and the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for details on
implementing the bi-directional PROCHOT# feature.
5.2.5THERMTRIP# Signal
Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the
event of a catastrophic cooling failure, the processor will automatically shut down when
the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in
Table 4-3). At this point, the FSB signal THERMTRIP# will go active and stay active as
described in Table 4-3. THERMTRIP# activation is independent of processor activity and
does not generate any bus cycles.
5.3Platform Environment Control Interface (PECI)
5.3.1Introduction
PECI offers an interface for thermal monitoring of Intel processor and chipset
components. It uses a single wire, thus alleviating routing congestion issues. PECI uses
CRC checking on the host side to ensure reliable transfers between the host and client
devices. Also, data transfer speeds across the PECI interface are negotiable within a
wide range (2Kbps to 2Mbps). The PECI interface on the Wolfdale processor is disabled
by default and must be enabled through BIOS. More information can be found in the
Platform Environment Control Interface (PECI) Specification.
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83
Thermal Specifications and Design Considerations
5.3.1.1T
CONTROL
Fan speed control solutions based on PECI utilize a T
processor IA32_TEMPERATURE_TARGET MSR. The T
temperature format as PECI though it contains no sign bit. Thermal management
devices should infer the T
should utilize the relative temperature value delivered over PECI in conjunction with the
T
CONTROL
fan control diagram using PECI temperatures.
and TCC activation on PECI-Based Systems
CONTROL
CONTROL
CONTROL
value as negative. Thermal management algorithms
MSR value to control or optimize fan speeds. Figure 5-5 shows a conceptual
value stored in the
MSR uses the same offset
The relative temperature value reported over PECI represents the delta below the onset
of thermal control circuit (TCC) activation as indicated by PROCHOT# assertions. As the
temperature approaches TCC activation, the PECI value approaches zero. T CC activates
at a PECI count of zero.
Figure 5-5. Conceptual Fan Control Diagram on PECI-Based Platforms
5.3.2PECI Specifications
5.3.2.1PECI Device Address
The PECI register resides at address 0x30.
5.3.2.2PECI Command Support
PECI command support is covered in detail in the Platform Environment Control
Interface Specification. Please refer to this document for details on supported PECI
command function and codes.
5.3.2.3PECI Fault Handling Requirements
PECI is largely a fault tolerant interface, including noise immunity and error checking
improvements over other comparable industry standard interfaces. The PECI client is
as reliable as the device that it is embedded in, and thus given operating conditions
84Datasheet
Thermal Specifications and Design Considerations
that fall under the specification, the PECI will always respond to requests and the
protocol itself can be relied upon to detect any transmission failures. There are,
however, certain scenarios where the PECI is know to be unresponsive.
Prior to a power on RESET# and during RESET# assertion, PECI is not guaranteed to
provide reliable thermal data. System designs should implement a default power-on
condition that ensures proper processor operation during the time frame when reliable
data is not available via PECI.
To protect platforms from potential operational or safety issues due to an abnormal
condition on PECI, the Host controller should take action to protect the system from
possible damage. It is recommended that the PECI host controller take appropriate
action to protect the client processor device if valid temperature readings have not
been obtained in response to three consecutive GetTe mp()s or for a one second time
interval. The host controller may also implement an alert to software in the event of a
critical or continuous fault condition.
5.3.2.4PECI GetTemp0() Error Code Support
The error codes supported for the processor GetTemp() command are listed in Table 5-
4:
Table 5-4.GetTemp0() Error Codes
Error CodeDescription
0x8000General sensor error
0x8002
Sensor is operational, but has detected a temperature below its operational
range (underflow)
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85
Thermal Specifications and Design Considerations
86Datasheet
Features
6Features
6.1Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples
the hardware configuration at reset, on the active-to-inactive transition of RESET#. F or
specifications on these options, refer to Table 6-1.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor; for configuration purposes, the processor does not distinguish between
a "warm" reset and a "power-on" reset.
1.Asserting this signal during RESET# will select the corresponding option.
2.Address signals not identified in this table as configuration options should not be asserted
3.Disabling of any of the cores within a Yorkfield processor must be handled by configuring
during RESET#.
the EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a
single core per die within the Yorkfield package.
6.2Clock Control and Low Power States
The processor allows the use of AutoHALT and Stop-Grant states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on
each particular state. See Figure 6-1 for a visual representation of the processor low
power states.
Datasheet
87
Figure 6-1. Processor Low Power State Machine
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
Normal State
- Normal Ex ec u tio n
INIT#, IN TR , NMI, SM I#, RESET#,
FSB interrupts
Features
Extended HALT or HALT
State
- BCLK running
- Snoops and interrup ts
allowe d
STPCLK#
Asserted
Stop Grant State
- BCLK ru n n ing
- Snoops and interrup ts
allow e d
STPCLK#
De-asserted
STPCLK#
Asserted
Snoop Event Occurs
Snoop Event Serviced
STPCLK#
De-asserted
Extended HALT Snoop or
HALT Snoop State
- BCLK running
- Service S n oo p s t o ca ch e s
Stop Grant Snoop State
- BCLK running
- Service S n oo p s t o ca ch e s
6.2.1Normal State
This is the normal operating state for the processor.
6.2.2HALT and Extended HALT Powerdown States
The processor supports the HALT or Extended HALT powerdown state. The Extended
HALT Powerdown state must be configured and enabled via the BIOS for the processor
to remain within specification.
The Extended HALT state is a lower power state as compared to the Stop Grant State.
Snoop
Event
Occurs
Snoop
Event
Serviced
If Extended HALT is not enabled, the default Powerdown state entered will be HALT.
Refer to the sections below for details about the HALT and Extended HALT states.
6.2.2.1HALT Powerdown State
HAL T is a low power state entered when all the processor cores have executed the HALT
or MWAIT instructions. When one of the processor cores executes the HALT instruction,
that processor core is halted, however, the other processor continues normal operation.
The halted core will transition to the Normal state upon the occurrence of SMI#, INIT#,
or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize
itself.
The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume 3B: System Programming Guide, Part 2 for more
information.
88Datasheet
Features
The system can generate a STPCLK# while the processor is in the HALT Power Down
state. When the system deasserts the STPCLK# interrupt, the processor will return
execution to the HALT state.
While in HALT Power Down state, the processor will process bus snoops.
6.2.2.2Extended HALT Powerdown State
Extended HALT is a low power state entered when all processor cores have executed
the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
When one of the processor cores executes the HALT instruction, that logical processor
is halted; however, the other processor continues normal operation. The Extended
HALT Powerdown must be enabled via the BIOS for the processor to remain within its
specification.
The processor will automatically transition to a lower frequency and voltage operating
point before entering the Extended HALT state. Note that the processor FSB frequency
is not altered; only the internal core frequency is changed. When entering the low
power state, the processor will first switch to the lower bus ratio and then transition to
the lower VID.
While in Extended HALT state, the processor will process bus snoops.
The processor exits the Extended HALT state when a break event occurs. When the
processor exits the Extended HALT state, it will first transition the VID to the original
value and then change the bus ratio back to the original value.
6.2.3Stop Grant State
When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered
20 bus clocks after the response phase of the processor-issued Stop Grant
Acknowledge special bus cycle.
Since the GTL+ signals receive power from the FSB, these signals should not be driven
(allowing the level to return to V
resistors in this state. In addition, all other input signals on the FSB should be driven to
) for minimum power drawn by the termination
TT
the inactive state.
RESET# will cause the processor to immediately initialize itself, but the processor will
stay in Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal.
A transition to the Grant Snoop state will occur when the processor detects a snoop on
the FSB (see Section 6.2.4).
While in the Stop-Grant State, SMI#, INIT# and LINT[1:0] will be latched by the
processor, and only serviced when the processor returns to the Normal State. Only one
occurrence of each event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process a FSB snoop.
6.2.4Extended HALT Snoop or HALT Snoop State,
Stop Grant Snoop State
The Extended HAL T Snoop State is used in conjunction with the Extended HAL T state. If
Extended HALT state is not enabled in the BIOS, the default Snoop State entered will
be the HALT Snoop State. Refer to the sections below for details on HALT Snoop State,
Grant Snoop State and Extended HALT Snoop State.
Datasheet
89
6.2.4.1HALT Snoop State, Stop Grant Snoop State
The processor will respond to snoop transactions on the FSB while in Stop-Grant state
or in HALT Power Down state. During a snoop transaction, the processor enters the
HAL T Snoop State:Stop Grant Snoop state. The processor will stay in this state until the
snoop on the FSB has been serviced (whether by the processor or another agent on the
FSB). After the snoop is serviced, the processor will return to the Stop Grant state or
HALT Power Down state, as appropriate.
6.2.4.2Extended HALT Snoop State
The Extended HALT Snoop State is the default Snoop State when the Extended HALT
state is enabled via the BIOS. The processor will remain in the lower bus ratio and VID
operating point of the Extended HALT state.
While in the Extended HALT Snoop State, snoops are handled the same way as in the
HAL T Snoop State. After the snoop is serviced the processor will return to the Extended
HALT state.
6.2.5Enhanced Intel SpeedStep® Technology
The processor supports Enhanced Intel SpeedStep T echnology. This technology enables
the processor to switch between frequency and voltage points, which may result in
platform power savings. In order to support this technology, the system must support
dynamic VID transitions. Switching between voltage/frequency states is software
controlled.
Features
Enhanced Intel SpeedStep Technology is a technology that creates processor
performance states (P states). P states are power consumption and capability states
within the Normal state as shown in Figure 6-1. Enhanced Intel SpeedStep Technology
enables real-time dynamic switching between frequency and voltage points. It alters
the performance of the processor by changing the bus to core frequency ratio and
voltage. This allows the processor to run at different core frequencies and voltages to
best serve the performance and power requirements of the processor and system. Note
that the front side bus is not altered; only the internal core frequency is changed. In
order to run at reduced power consumption, the voltage is altered in step with the bus
ratio.
The following are key features of Enhanced Intel SpeedStep Technology:
• Voltage/Frequency selection is software controlled by writing to processor MSR's
(Model Specific Registers), thus eliminating chipset dependency.
- If the target frequency is higher than the current frequency, Vcc is incremented in
steps (+12.5 mV) by placing a new value on the VID signals after which the
processor shifts to the new frequency. Note that the top frequency for the
processor can not be exceeded.
- If the target frequency is lower than the current frequency, the processor shifts to
the new frequency and Vcc is then decremented in steps (-12.5 mV) by changing
the target VID through the VID signals.
6.2.6Processor Power Status Indicator (PSI) Signal
The processor incorporates the PSI# signal that is asserted when the processor is in a
reduced power consumption state. PSI# can be used to improve efficiency of the
voltage regulator, resulting in platform power savings. For details, refer to the
compatible chipset Platform Design Guide and Voltage Regulator-Down (VRD) 11.1 Processor Power Delivery Design Guidelines.
PSI# may be asserted only when the processor is in the Deeper Sleep state.
90Datasheet
Boxed Processor Specifications
7Boxed Processor Specifications
7.1Introduction
The processor will also be offered as an Intel boxed processor. Intel boxed processors
are intended for system integrators who build systems from baseboards and standard
components. The boxed processor will be supplied with a cooling solution. This chapter
documents baseboard and system requirements for the cooling solution that will be
supplied with the boxed processor. This chapter is particularly important for OEMs that
manufacture baseboards for system integrators.
Note:Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and
inches [in brackets]. Figure 7-1 shows a mechanical representation of a boxed
processor.
Note:Drawings in this section reflect only the specifications on the Intel boxed processor
product. These dimensions should not be used as a generic keep-out zone for all
cooling solutions. It is the system designers’ responsibility to consider their proprietary
cooling solution when designing to the required keep-out zone on their system
platforms and chassis. Refer to the Yorkfield Processor Thermal and Mechanical Design Guidelines Addendum for further guidance. Contact your local Intel Sales
Figure 7-1. Mechanical Representation of the Boxed Processor
Representative for this document.
NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.
Datasheet
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Boxed Processor Specifications
7.2Mechanical Specifications
7.2.1Boxed Processor Cooling Solution Dimensions
This section documents the mechanical specifications of the boxed processor. The
boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a
mechanical representation of the boxed processor.
Clearance is required around the fan heatsink to ensure unimpeded airflow for proper
cooling. The physical space requirements and dimensions for the boxed processor with
assembled fan heatsink are shown in Figure 7-2 (Side View), and Figure 7-3 (Top
View). The airspace requirements for the boxed processor fan heatsink must also be
incorporated into new baseboard and system designs. Airspace requirements are
shown in Figure 7-7 and Figure 7-8. Note that some figures have centerlines shown
(marked with alphabetic designations) to clarify relative dimensioning.
Figure 7-2. Side View Space Requirements for the Boxed Processor
95.0
[3.74]
81.3
[3.2]
10.0
[0.39]
25.0
[0.98]
Boxed_Proc_SideView
92Datasheet
Boxed Processor Specifications
Figure 7-3. Top View Space Requirements for the Boxed Processor
95.0
[3.74]
95.0
[3.74]
Boxed_Proc_TopView
NOTES:
1.Diagram does not show the attached hardware for the clip design and is provided only as a
mechanical representation.
Figure 7-4. Overall View Space Requirements for the Boxed Processor
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93
Boxed Processor Specifications
7.2.2Boxed Processor Fan Heatsink Weight
The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5
and the Yorkfield Processor Thermal and Mechanical Design Guidelines Addendum for
details on the processor weight and heatsink requirements.
7.2.3Boxed Processor Retention Mechanism and Heatsink
Attach Clip Assembly
The boxed processor thermal solution requires a heatsink attach clip assembly, to
secure the processor and fan heatsink in the baseboard socket. The boxed processor
will ship with the heatsink attach clip assembly.
7.3Electrical Requirements
7.3.1Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12V power supply. A fan power cable
will be shipped with the boxed processor to draw power from a power header on the
baseboard. The power cable connector and pinout are shown in Figure 7-5. Baseboards
must provide a matched power header to support the boxed processor. Table 7-1
contains specifications for the input and output signals at the fan heatsink connector.
The fan heatsink outputs a SENSE signal, which is an open- collector output that pulses
at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides VOH to
match the system board-mounted fan speed monitor requirements, if applicable. Use of
the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector
should be tied to GND.
The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the
connector labeled as CONTROL.
The boxed processor's fanheat sink requires a constant +12 V supplied to pin 2 and
does not support variable voltage control or 3-pin PWM control.
The power header on the baseboard must be positioned to allow the fan heatsink power
cable to reach it. The power header identification and location should be documented in
the platform documentation, or on the system board itself. Figure 7-6 shows the
location of the fan power connector relative to the processor socket. The baseboard
power header should be positioned within 110 mm [4.33 inches] from the center of the
processor socket.
94Datasheet
Boxed Processor Specifications
Figure 7-5. Boxed Processor Fan Heatsink Power Cable Connector Description
Signal
Pin
1
2
3
4
GND
+12 V
SENSE
CONTROL
Straight square pi n, 4-pin terminal housing with
polarizi ng r ibs and fric tion locking ramp.
0.100" pitch, 0.025" square pin width.
Match with straight pin, friction lock header on
mainboard.
34
12
Table 7-1.Fan Heatsink Power and Signal Specifications
DescriptionMinTypMaxUnitNotes
+12V: 12 volt fan power supply11.41212.6V-
IC:
- Maximum fan steady-state current draw
- Average fan steady-state current draw
- Maximum fan start-up current draw
- Fan start-up current draw maximum
duration
SENSE: SENSE frequency—2—
CONTROL212528kHz
NOTES:
1. Baseboard should pull this pin up to 5V with a resistor.
2. Open drain type, pulse width modulated.
3. Fan will have pull-up resistor for this signal to maximum of 5.25 V.
—
—
—
—
1.2
0.5
2.2
1.0
—
—
—
—
Second
pulses per
fan
revolution
A
A
A
-
1
2, 3
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95
Boxed Processor Specifications
Figure 7-6. Baseboard Power Header Placement Relative to Processor Socket
R110
B
[4.33]
C
Boxed_Proc_PwrHeaderPlacement
7.4Thermal Specifications
This section describes the cooling requirements of the fan heatsink solution utilized by
the boxed processor.
7.4.1Boxed Processor Cooling Requirements
The boxed processor may be directly cooled with a fan heatsink. However, meeting the
processor's temperature specification is also a function of the thermal design of the
entire system, and ultimately the responsibility of the system integrator. The processor
temperature specification is found in Chapter 5 of this document. The boxed processor
fan heatsink is able to keep the processor temperature within the specifications (see
Table 5-1) in chassis that provide good thermal management. For the boxed processor
fan heatsink to operate properly, it is critical that the airflow provided to the fan
heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the
sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow
through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink
reduces the cooling efficiency and decreases fan life. Figure 7-7 and Figure 7-8
illustrate an acceptable airspace clearance for the fan heatsink. The air temperature
entering the fan should be kept below 38 ºC. Again, meeting the processor's
temperature specification is the responsibility of the system integrator.
If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin
motherboard header it will operate as follows:
The boxed processor fan will operate at different speeds over a short range of internal
chassis temperatures. This allows the processor fan to operate at a lower speed and
noise level, while internal chassis temperatures are low. If internal chassis temperature
increases beyond a lower set point, the fan speed will rise linearly with the internal
temperature until the higher set point is reached. At that point, the fan speed is at its
maximum. As fan speed increases, so does fan noise levels. Systems should be
designed to provide adequate air around the boxed processor fan heatsink that remains
cooler then lower set point. These set points, represented in Figure 7-9 and Table 7-2,
can vary by a few degrees from fan heatsink to fan heatsink. The internal chassis
temperature should be kept below 38 ºC. Meeting the processor's temperature
specification (see Chapter 5) is the responsibility of the system integrator.
The motherboard must supply a constant +12V to the processor's power header to
ensure proper operation of the variable speed fan for the boxed processor. Refer to
Table 7-1 for the specific requirements.
98Datasheet
Boxed Processor Specifications
Figure 7-9. Boxed Processor Fan Heatsink Set Points
Table 7-2.Fan Heatsink Power and Signal Specifications
Boxed Processor
Fan Heatsink Set
Point (
NOTES:
1. Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink.
X ≤ 30
Y = 35
Z ≥ 39
ºC)
When the internal chassis temperature is below or equal to this
set point, the fan operates at its lowest speed. Recommended
maximum internal chassis temperature for nominal operating
environment.
When the internal chassis temperature is at this point, the fan
operates between its lowes t and highest speeds. Recommended
maximum internal chassis temperature for worst-case operating
environment.
When the internal chassis temperature is above or equal to this
set point, the fan operates at its highest speed.
Boxed Processor Fan SpeedNotes
If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin
motherboard header and the motherboard is designed with a fan speed controller with
PWM output (CONTROL see Table 7-1) and remote thermal diode measurement
capability the boxed processor will operate as follows:
As processor power has increased the required thermal solutions have generated
increasingly more noise. Intel has added an option to the boxed processor that allows
system integrators to have a quieter system in the most common usage.
The 4th wire PWM solution provides better control over chassis acoustics. This is
achieved by more accurate measurement of processor die temperature through the
processor's Digital Thermal Sensors (DTS) and PECI. Fan RPM is modulated through the
use of an ASIC located on the motherboard that sends out a PWM control signal to the
4th pin of the connector labeled as CONTROL. The fan speed is based on actual
processor temperature instead of internal ambient chassis temperatures.
1
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Datasheet
99
Boxed Processor Specifications
If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard
CPU fan header it will default back to a thermistor controlled mode, allowing
compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode,
the fan RPM is automatically varied based on the Tinlet temperature measured by a
thermistor located at the fan inlet.
For more details on specific motherboard requirements for 4-wire based fan speed
control see the Yorkfield Processor Thermal and Mechanical Design Guidelines Addendum.
§
100Datasheet
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