Intel Quad-Core Xeon 3300 Series, Xeon X3380, Xeon X3360, Xeon X3350, Xeon X3330 Datasheet

Quad-Core Intel® Xeon® Processor
3300 Series

Datasheet

February 2009

Version -002

Document Number: 319005-002

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∆

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor
family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time
processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not
intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number
progression is not necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details.

Intel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled
for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary
depending on your hardware and software configurations. See http://www.intel.com/info/em64t for more information including
details on which processors support Intel 64, or consult with your system vendor for more information.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting
operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

±

Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor
(VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary
depending on hardware and software configur ations and may re quire a BIOS update. S oftware applicatio ns may not be compatible
with all operating systems. Please check with your application vendor.

Not all specified units of this processor support Thermal Monitor 2, Enhanced HALT State and Enhanced Intel SpeedStep®
Technology. See the Processor Spec Finder at http://processorfinder.intel.com or contact your Intel representative for more
information.

Intel, Pentium, Xeon, Intel Core, Intel SpeedStep, and the Intel logo are trademarks of Intel Corporation in the U.S. and other
countries.

*Other names and brands may be claimed as the property of others.
Copyright © 2009, Intel Corporation. All Rights Reserved.

2 Datasheet

Contents

1Introduction..............................................................................................................9

1.1 Terminology .......................................................................................................9

1.1.1 Processor Terminology Definitions ............................................................10

1.2 References.......................................................................................................11

2 Electrical Specifications...........................................................................................13

2.1 Power and Ground Lands....................................................................................13

2.2 Decoupling Guidelines ........................................................................................13

2.2.1 Vcc Decoupling ......................................................................................13

2.2.2 Vtt Decoupling.......................................................................................13

2.2.3 FSB Decoupling......................................................................................13

2.3 Voltage Identification.........................................................................................14

2.4 Reserved, Unused, and TESTHI Signals ................................................................16

2.5 Flexible Motherboard Guidelines (FMB)............................. ... .. .. ........................... ..16

2.6 Power Segment Identifier (PSID).........................................................................17

2.7 Voltage and Current Specification........................................................................17

2.7.1 Absolute Maximum and Minimum Ratings ..................................................17

2.7.2 DC Voltage and Current Specification.................................................... .. ..18

2.7.3 VCC Overshoot ......................................................................................21

2.7.4 Die Voltage Validation............................................................... ..............22

2.8 Signaling Specifications............................................ .. ........................................22

2.8.1 FSB Signal Groups..................................................................................22

2.8.2 CMOS and Open Drain Signals .................................................................24

2.8.3 Processor DC Specifications .....................................................................24

2.8.3.1 Platform Environment Control Interface (PECI) DC Specifications..... 26

2.8.3.2 GTL+ Front Side Bus Specifications.............................................26

2.9 Clock Specifications...........................................................................................28

2.9.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking............................28

2.9.2 FSB Frequency Select Signals (BSEL[2:0]).................................................29

2.9.3 Phase Lock Loop (PLL) and Filter..............................................................29

2.9.4 BCLK[1:0] Specifications.........................................................................30

3 Package Mechanical Specifications ..........................................................................33

3.1 Package Mechanical Specifications.......................................................................33

3.1.1 Package Mechanical Drawing........................................... .. .......................34

3.1.2 Processor Component Keep-Out Zones..................................... ... ..............38

3.1.3 Package Loading Specifications ................................................................38

3.1.4 Package Handling Guidelines.............................. .. ............................ .. .. .. ..38

3.1.5 Package Insertion Specifications.......................................... .. .. .................39

3.1.6 Processor Mass Specification....................................................................39

3.1.7 Processor Materials.................................................................................39

3.1.8 Processor Markings.................................................................................39

3.1.9 Processor Land Coordinates.....................................................................40

4 Land Listing and Signal Descriptions .......................................................................41

4.1 Processor Land Assignments...............................................................................41

4.2 Alphabetical Signals Reference............................................................................64

5 Thermal Specifications and Design Considerations ..................................................75

5.1 Processor Thermal Specifications.........................................................................75

5.1.1 Thermal Specifications............................................................................75

5.1.2 Thermal Metrology .................................................................................80

Datasheet 3

5.2 Processor Thermal Features ................................................................................80

5.2.1 Thermal Monitor.......................... .. .. .......................... .. ......................... ..80

5.2.2 Thermal Monitor 2 ...................................... ......................... .. .. ...............81

5.2.3 On-Demand Mode...................................................................................82

5.2.4 PROCHOT# Signal ................... ......................... .. .. .......................... .. .. ....83

5.2.5 THERMTRIP# Signal................................................................................83

5.3 Platform Environment Control Interface (PECI)......................................................83

5.3.1 Introduction...........................................................................................83

5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems..................84

5.3.2 PECI Specifications .................................................................................84

5.3.2.1 PECI Device Address............................ .. .......................... .. ........84

5.3.2.2 PECI Command Support......................... .. .......................... .. ......84

5.3.2.3 PECI Fault Handling Requirements...............................................84

5.3.2.4 PECI GetTemp0() Error Code Support ......................... .. ...............85

6Features..................................................................................................................87

6.1 Power-On Configuration Options..........................................................................87

6.2 Clock Control and Low Power States........................... .. .. ............................ ..........87

6.2.1 Normal State .........................................................................................88

6.2.2 HALT and Extended HALT Powerdown States..............................................88

6.2.2.1 HALT Powerdown State.................................................. .. .. ........88

6.2.2.2 Extended HALT Powerdown State ................................................89

6.2.3 Stop Grant State ....................................................................................89

6.2.4 Extended HALT Snoop or HALT Snoop State,

Stop Grant Snoop State...........................................................................89

6.2.4.1 HALT Snoop State, Stop Grant Snoop State ..................................90

6.2.4.2 Extended HALT Snoop State .......................................................90

6.2.5 Enhanced Intel SpeedStep

®

Technology .......................................... ..........90

6.2.6 Processor Power Status Indicator (PSI) Signal ............................................90

7 Boxed Processor Specifications................................................................................91

7.1 Introduction......................................................................................................91

7.2 Mechanical Specifications....................................................................................92

7.2.1 Boxed Processor Cooling Solution Dimensions.............................................92

7.2.2 Boxed Processor Fan Heatsink Weight .......................................................94

7.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly .....94

7.3 Electrical Requirements ....................... .. .. ................................................... .. .. .. ..94

7.3.1 Fan Heatsink Power Supply.................................. .. ... .. ........................... ..94

7.4 Thermal Specifications........................... ........................... ..................................96

7.4.1 Boxed Processor Cooling Requirements......................................................96

7.4.2 Variable Speed Fan............................ .......................... .. .........................98

8 Debug Tools Specifications ....................................................................................101

8.1 Logic Analyzer Interface (LAI) ...........................................................................101

8.1.1 Mechanical Considerations .....................................................................101

8.1.2 Electrical Considerations........................................................................ 101

Figures

2-1 VCC Static and Transient Tolerance.........................................................................20

2-2 V

2-3 Differential Clock Waveform.................. .. .. ........................... ... .. ........................... ..31

2-4 Measurement Points for Differential Clock Waveforms ...............................................31

3-1 Processor Package Assembly Sketch.......................................................................33

3-2 Processor Package Drawing Sheet 1 of 3 ........................... ............................ .. ........35

3-3 Processor Package Drawing Sheet 2 of 3 ........................... ............................ .. ........36

3-4 Processor Package Drawing Sheet 3 of 3 ........................... ............................ .. ........37

3-5 Processor Top-Side Markings Example.....................................................................39

4 Datasheet

Overshoot Example Waveform .........................................................................21

CC

3-6 Processor Land Coordinates and Quadrants, Top View...............................................40

4-1 land-out Diagram (Top View – Left Side).................................................................42

4-2 land-out Diagram (Top View – Right Side)...............................................................43

5-1 Quad-Core Intel

® Xeon® Processor 3300 Series

Thermal Profile(95W)................................78

5-2 Quad-Core Intel® Xeon® Processor 3300 Series Thermal Profile (65W) ................ ....... 79

5-3 Case Temperature (TC) Measurement Location ........................................................80

5-4 Thermal Monitor 2 Frequency and Voltage Ordering..................................................82

5-5 Conceptual Fan Control Diagram on PECI-Based Platforms ........................................84

6-1 Processor Low Power State Machine.......................................................................88

7-1 Mechanical Representation of the Boxed Processor ...................................................91

7-2 Side View Space Requirements for the Boxed Processor............................................92

7-3 Top View Space Requirements for the Boxed Processor.............................................93

7-4 Overall View Space Requirements for the Boxed Processor ........................................93

7-5 Boxed Processor Fan Heatsink Power Cable Connector Description..............................95

7-6 Baseboard Power Header Placement Relative to Processor Socket...............................96

7-7 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)...............97

7-8 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)...............98

7-9 Boxed Processor Fan Heatsink Set Points................................................................99

Tables

1-1 References..........................................................................................................11

2-1 Voltage Identification Definition .............................................................................14

2-2 Absolute Maximum and Minimum Ratings................................................................17

2-3 Voltage and Current Specifications.........................................................................18

2-4 V

2-5 VCC Overshoot Specifications.................................................................................21

2-6 FSB Signal Groups...............................................................................................23

2-7 Signal Characteristics...........................................................................................24

2-8 Signal Reference Voltages.....................................................................................24

2-9 GTL+ Signal Group DC Specifications .....................................................................24

2-10 Open Drain and TAP Output Signal Group DC Specifications.......................................25

2-11 CMOS Signal Group DC Specifications.....................................................................25

2-12 PECI DC Electrical Limits.......................................................................................26

2-13 GTL+ Bus Voltage Definitions................................................................................27

2-14 Core Frequency to FSB Multiplier Configuration........................................................28

2-15 BSEL[2:0] Frequency Table for BCLK[1:0]...............................................................29

2-16 Front Side Bus Differential BCLK Specifications ........................................................30

2-17 FSB Differential Clock Specifications (1333 MHz FSB) ................................ ............... 30

3-1 Processor Loading Specifications............................................................................38

3-2 Package Handling Guidelines.................................................................................38

3-3 Processor Materials..............................................................................................39

4-1 Alphabetical Land Assignments..............................................................................44

4-2 Numerical Land Assignment .............................................. ... .. .. .............................54

4-3 Signal Description................................................................................................64

5-1 Processor Thermal Specifications ...........................................................................76

5-2 Quad-Core Intel
5-3 Quad-Core Intel

5-4 GetTemp0() Error Codes.......................................................................................85

6-1 Power-On Configuration Option Signals...................................................................87

7-1 Fan Heatsink Power and Signal Specifications ..........................................................95

7-2 Fan Heatsink Power and Signal Specifications ..........................................................99

Static and Transient Tolerance.........................................................................19

CC

® Xeon® Processor 3300 Series
® Xeon® Processor 3300 Series

Thermal Profile (95W)...............................77

Thermal Profile (65W)...............................79

Datasheet 5

Revision History

Document

Number

319005 1.0 -001 • Initial release

Version

Number

Revision Description

• Added Quad-Core Intel® Xeon® Processor

-002

X3380 & L3360

• Updated VID information

• Added PSI# Signal

Revision

Date

January

2008

February

2009

6 Datasheet

Quad-Core Intel® Xeon® Processor 3300 Series Features

• Available at 3.16 GHz, 3.00 GHz, 2.83 GHz,

2.66 GHz, and 2.50 GHz (Quad-Core Intel
Xeon® Processor 3300 Series)

®

• Enhanced Intel Speedstep

®

•Supports Intel

•Supports Intel

64 architecture

®

Virtualization Technology

Technology

• Supports Execute Disable Bit capability

• FSB frequency at 1333 MHz

• Binary compatible with applications running
on previous members of the Intel
microprocessor line

• Advance Dynamic Execution

• Enhanced branch prediction

• Very deep out-of-order execution

®

• Optimized for 32-bit applications running on
advanced 32-bit operating systems

®

•Intel

Advanced Smart Cache

• Two 6 MB Level 2 caches (Quad-Core Intel
Xeon® Processor X3350, X3360)

• Two 3 MB Level 2 caches (Quad-Core Intel
Xeon® Processor X3320)

®

•Intel

Advanced Digital Media Boost

• Enhanced floating point and multimedia unit
for enhanced video, audio, encryption, and
3D performance

• Power Management capabilities

• System Management mode

®

®

• Multiple low-power states

• 8-way cache associativity provides improved
cache hit rate on load/store operations

• 775-land Package

The Quad-Core Intel® Xeon® Processor 3300 Series deliver Intel's advanced, powerful processors for
desktop PCs. The processor is designed to deliver performance across applications and usages where
end-users can truly appreciate and experience the performance. These applications include Internet
audio and streaming video, image processing, video content creation, speech, 3D, CAD, games,
multimedia, and multitasking user environments.

Intel® 64 architecture enables the processor to execute operating systems and applications written to
take advantage of the Intel 64 architecture. The processor, supporting Enhanced Intel Speedstep

®

technology, allows tradeoffs to be made between performance and power consumption.

®

The Quad-Core Intel

Xeon® Processor 3300 Series also includes the Execute Disable Bit capability.
This feature, combined with a supported operating system, allows memory to be marked as
executable or non-executable.

®

The Quad-Core Intel

Xeon® Processor 3300 Series support Intel® Virtualization Technology.
Virtualization Technology provides silicon-based functionality that works together with compatible
Virtual Machine Monitor (VMM) software to improve on software-only solutions.

Datasheet 7

§

8 Datasheet

Introduction

1 Introduction

The Quad-Core Intel® Xeon® Processor 3300 Series, like the Quad-Core Intel® Xeon®
Processor 3200 Series, is a based on the Intel® CoreTM microarchitecture. The Intel
Core microarchitecture combines the performance of previous generation Desktop
products with the power efficiencies of a low-power microarchitecture to enable
smaller, quieter systems.The Quad-Core Intel® Xeon® Processor 3300 Series are 64­bit processors that maintain compatibility with IA-32 software.

The processor utilizes Flip-Chip Land Grid Array (FC-LGA6) package technology, and
plug into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the
LGA775 socket.

Note: In this document the Quad-Core Intel® Xeon® Processor 3300 Series may be referred

to simply as "the processor."

Note: The Quad-Core Intel® Xeon® Processor 3300 Series refers to X3380, X3360, X3350,

X3330, X3320, L3360.
The processor is a quad-core processor, based on 45 nm process technology. The

processor features the Intel
cache that significantly reduces latency to frequently used data. The processors feature
a 1333 MHz front side bus (FSB) and either two independent but shared 6 MB of L2
cache (2x6M) or two independent but shared 3 MB of L2 cache (2x3M).The processor
supports all the existing Streaming SIMD Extensions 2 (SSE2), Streaming SIMD
Extensions 3 (SSE3), Supplemental Streaming SIMD Extension 3 (SSSE3), and the
Streaming SIMD Extensions 4.1 (SSE4.1). The processor supports several Advanced
Technologies: Execute Disable (XD) Bit, Intel
Intel SpeedStep

The processor's front side bus (FSB) utilizes a split-transaction, deferred reply protocol.
The FSB uses Source-Synchronous Transfer of address and data to improve
performance by transferring data four times per bus clock (4X data transfer rate).
Along with the 4X data bus, the address bus can deliver addresses two times per bus
clock and is referred to as a "double-clocked" or 2X address bus. Working together, the
4X data bus and 2X address bus provide a data bus bandwidth of up to 10.7 GB/s.

The processor use some of the infrastructure already enabled by 2005 FMB platforms
including heatsink, heatsink retention mechanism, and socket. Manufacturability is a
high priority; hence, mechanical assembly may be completed from the top of the
baseboard and should not require any special tooling.

®

Technology, and Intel® Virtualization Technology (Intel® VT).

1.1 Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

®

Advanced Smart Cache, a shared multi-core optimized

®

64 architecture (Intel® 64), Enhanced

“Front Side Bus” refers to the interface between the processor and system core logic
(a.k.a. the chipset components). The FSB is a multiprocessing interface to processors,
memory, and I/O.

Datasheet

9

1.1.1 Processor Terminology Definitions

Commonly used terms are explained here for clarification:

• Quad-Core Intel® Xeon® Processor 3300 Series — Quad core processor in the
FC-LGA6 package with two 6 MB L2 cache or two 3 B L2 cache.

• Processor — For this document, the term processor is the generic form of the
Quad-Core Intel® Xeon® Processor 3300 Series.

• Intel

• Keep-out zone — The area on or near the processor that system design can not

• Processor core — Processor die with integrated L2 cache.

• LGA775 socket — The processor mates with the system board through a surface

• Integrated heat spreader (IHS) —A component of the processor package used

• Retention mechanism (RM) — Since the LGA775 socket does not include any

• FSB (Front Side Bus) — The electrical interface that connects the processor to

• Storage conditions — Refers to a non-operational state. The processor may be

• Functional operation — Refers to normal operating conditions in which all

• Execute Disable (XD) Bit — XD allows memory to be marked as executable or

• Intel

• Enhanced Intel SpeedStep

• Intel® Virtualization Technology (Intel® VT) — A set of hardware

®

CoreTM microarchitecture — A new foundation for Intel® architecture-

based desktop, mobile and mainstream server multi-core processors. For additional
information refer to: http://www.intel.com/technology/architecture/coremicro/

utilize.

mount, 775-land, LGA socket.

to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.

mechanical features for heatsink attach, a retention mechanism is required.
Component thermal solutions should attach to the processor via a retention
mechanism that is independent of the socket.

the chipset. Also referred to as the processor system bus or the system bus. All
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.

installed in a platform, in a tray , or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased, or receive any clocks.
Upon exposure to “free air”(i.e., unsealed packaging or a device removed from
packaging material) the processor must be handled in accordance with moisture
sensitivity labeling (MSL) as indicated on the packaging material.

processor specifications, including DC, AC, system bus, signal quality, mechanical
and thermal are satisfied.

non-executable, when combined with a supporting operating system. If code
attempts to run in non-executable memory the processor raises an error to the
operating system. This feature can prevent some classes of viruses or worms that
exploit buffer over run vulnerabilities and can thus help improve the overall security
of the system. See the Intel® Architecture Software Developer's Manual for more
detailed information.

®

64 Architecture — An enhancement to Intel's IA-32 architec ture, allowing

the processor to execute operating systems and applications written to take
advantage of Intel 64 architecture. Further details on Intel 64 architecture and
programming model can be found in the Software Developer Guide at http://
developer.intel.com/technology/64bitextensions/.

®

Technology — Enhanced Intel SpeedStep

Te chnology allows trade-offs to be made between performance and power
consumptions, based on processor utilization. This may lower average power
consumption (in conjunction with OS support).

enhancements to Intel server and client platforms that can improve virtualization
solutions. Intel VT will provide a foundation for widely-deployed virtualization

Introduction

10 Datasheet

Introduction

solutions and enables more robust hardware assisted virtualization solutions. More
information can be found at: http://www.intel.com/technology/virtualization/

• Platform Environment Control Interface (PECI) — A proprietary one-wire bus
interface that provides a communication channel between the processor and
chipset components to external monitoring devices.

1.2 References

Material and concepts available in the following documents may be beneficial when
reading this document:

Table 1-1. References

Quad-Core Intel® Xeon® Processor 3300 Series
Thermal and Mechanical Design Guidelines Addendum

Quad-Core Intel® Xeon® Processor 3300 Series
Specification Update

Voltage Regulator-Down (VRD) 11.0 Processor Power
Delivery Design Guidelines For Desktop LGA775 Socket

LGA775 Socket Mechanical Design Guide

IA-32 Intel Architecture Software Developer's Manual

Volume 1: Basic Architecture
Volume 2A: Instruction Set Reference, A-M
Volume 2B: Instruction Set Reference, N-Z
Volume 3A: System Programming Guide, Part 1
Volume 3B: System Programming Guide, Part 2

Document Location

http://www.intel.com/

products/processor/

xeon3000/

documentation.htm#therma

l_models

http://download.intel.com/

design/intarch/specupdt/

319007.pdf

http://www.intel.com/

design/processor/applnots/

313214.htm

http://intel.com/design/
Pentium4/guides/

302666.htm

http://www.intel.com/

products/processor/

manuals/

Datasheet

§

11

Introduction

12 Datasheet

Electrical Specifications

2 Electrical Specifications

2.1 Power and Ground Lands

The processor has VCC (power), VTT, and VSS (ground) inputs for on-chip power
distribution. All power lands must be connected to V
connected to a system ground plane. The processor VCC lands must be supplied the
voltage determined by the Voltage IDentification (VID) lands.

The signals denoted as VTT provide termination for the front side bus and power to the
I/O buffers. A separate supply must be implemented for these lands, that meets the
V

specifications outlined in Table 2-3.

TT

2.2 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings. This may cause voltages on power planes
to sag below their minimum specified values if bulk decoupling is not adequate. Larger
bulk storage (C
current during longer lasting changes in current demand by the component, such as
coming out of an idle condition. Similarly, they act as a storage well for current when
entering an idle condition from a running condition. The motherboard must be designed
to ensure that the voltage provided to the processor remains within the specifications
listed in Table 2-3. Failure to do so can result in timing violations or reduced lifetime of
the component. For further information and guidelines, refer to the appropriate
platform design guidelines.

2.2.1 VCC Decoupling

VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the
processor voltage specifications. This includes bulk capacitance with low effective series
resistance (ESR) to keep the voltage rail within specifications during large swings in
load current. In addition, ceramic decoupling capacitors are required to filter high
frequency content generated by the front side bus and processor activity. Consult the

Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For
Desktop LGA775 Socket and appropriate platform design guidelines for further

information.

), such as electrolytic or aluminum-polymer capacitors, supply

BULK

, while all VSS lands must be

CC

2.2.2 VTT Decoupling

Decoupling must be provided on the motherboard. Decoupling solutions must be sized
to meet the expected load. To ensure compliance with the specifications, various
factors associated with the power delivery solution must be considered including
regulator type, power plane and trace sizing, and component placement. A
conservative decoupling solution would consist of a combination of low ESR bulk
capacitors and high frequency ceramic capacitors. For further information regarding
power delivery, decoupling and layout guidelines, refer to the appropriate platform
design guidelines.

2.2.3 FSB Decoupling

The processor integrates signal termination on the die. In addition, some of the high
frequency capacitance required for the FSB is included on the processor package.
However, additional high frequency capacitance must be added to the motherboard to

Datasheet

13

properly decouple the return currents from the front side bus. Bulk decoupling must
also be provided by the motherboard for proper [A]GTL+ bus operation. Decoupling
guidelines are described in the appropriate platform design guidelines.

2.3 Voltage Identification

The Voltage Identification (VID) specification for the processor is defined by the Voltage
Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage

to be delivered to the processor VCC lands (see Chapter 2.7.3 for V
specifications). Refer to Table 2-11 for the DC specifications for these signals. Voltages
for each processor frequency is provided in Table 2-3.

NOTE: To support the Deeper Sleep State the platform must use a VRD 11.1 compliant
solution. The Deeper Sleep State also requires additional platform support. Refer to the
platform design guide and the Voltage Regulator-Down (VRD) 11.1 Processor Power
Delivery Design Guidelines for further details.

Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core speed may have different default VID settings. This is
reflected by the VID Range values provided in Table 2-3. Refer to the Processor
Specification Update for further details on specific valid core frequency and VID values
of the processor. Note that this differs from the VID employed by the processor during
a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep
technology, or Extended HALT State).

Electrical Specifications

overshoot

CC

®

The processor uses eight voltage identification signals, VID[7:0], to support automatic
selection of power supply voltages. Table 2-1 specifies the voltage level corresponding
to the state of VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers
to a low voltage level. If the processor socket is empty (VID[7:0] = 11111110), or the
voltage regulation circuit cannot supply the voltage that is requested, it must disable
itself.

The processor provides the ability to operate while transitioning to an adjacent VID and
its associated processor core voltage (V
line. It should be noted that a low-to-high or high-to-low voltage state change may

). This will represent a DC shift in the load

CC

result in as many VID transitions as necessary to reach the target core voltage.
T ransitions abo ve the specified VID are not permitted. Table 2-3 includes VID step sizes
and DC shift ranges. Minimum and maximum v oltages must be maintained as shown in

Table 2-4 and Figure 2-1as measured across the VCC_SENSE and VSS_SENSE lands.

The VRM or VRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for dynamic VID transitions are included in Table 2-3
and Table 2-4. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power
Delivery Design Guidelines For Desktop LGA775 Socket for further details.

Table 2-1. Voltage Identification Def inition

VID7VID6VID5VID4VID3VID2VID1VID

00000000 OFF 010111001.0375
00000010 1.6 01011110 1.025

000001001.5875 011000001.0125
00000110 1.575 01100010 1

000010001.5625 011001000.9875
00001010 1.55 01100110 0.975

000011001.5375 011010000.9625

0

Voltage

VID7VID6VID5VID4VID3VID2VID1VID

0

Voltage

14 Datasheet

Electrical Specifications

VID7VID6VID5VID4VID3VID2VID1VID

0

Voltage

VID7VID6VID5VID4VID3VID2VID1VID

0

Voltage

00001110 1.525 01101010 0.95

000100001.5125 011011000.9375
00010010 1.5 01101110 0.925

000101001.4875 011100000.9125
00010110 1.475 01110010 0.9

000110001.4625 011101000.8875
00011010 1.45 01110110 0.875

000111001.4375 011110000.8625
00011110 1.425 01111010 0.85

001000001.4125 011111000.8375
00100010 1.4 01111110 0.825

001001001.3875 100000000.8125
00100110 1.375 10000010 0.8

001010001.3625 100001000.7875
00101010 1.35 10000110 0.775

001011001.3375 100010000.7625
00101110 1.325 10001010 0.75

001100001.3125 100011000.7375
00110010 1.3 10001110 0.725

001101001.2875 100100000.7125
00110110 1.275 10010010 0.7

001110001.2625 100101000.6875
00111010 1.25 10010110 0.675

001111001.2375 100110000.6625
00111110 1.225 10011010 0.65

010000001.2125 100111000.6375
01000010 1.2 10011110 0.625

010001001.1875 101000000.6125
01000110 1.175 10100010 0.6

010010001.1625 101001000.5875
01001010 1.15 10100110 0.575

010011001.1375 101010000.5625
01001110 1.125 10101010 0.55

010100001.1125 101011000.5375
01010010 1.1 10101110 0.525

010101001.0875 101100000.5125
01010110 1.075 10110010 0.5

010110001.0625 11111110 OFF
01011010 1.05

Datasheet

15

2.4 Reserved, Unused, and TESTHI Signals

All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS,

or to any other signal (including each other) can result in component malfunction

V

TT ,

or incompatibility with future processors. See Chapter 4 for a land listing of the
processor and the location of all RESERVED lands.

In a system level design, on-die termination has been included by the processor to
allow signals to be terminated within the processor silicon. Most unused GTL+ inputs
should be left as no connects as GTL+ termination is provided on the processor silicon.
However, see Table 2-6 for details on GTL+ signals that do not include on-die
termination.

Electrical Specifications

Unused active high inputs, should be connected through a resistor to ground (V
Unused outputs can be left unconnected, however this may interfere with some TAP

SS

).

functions, complicate debug probing, and prevent boundary scan testing. A resistor
must be used when tying bidirectional signals to power or ground. When tying any
signal to power or ground, a resistor will also allow for system testability. Resistor
values should be within ± 20% of the impedance of the motherboard trace for front
side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the
same value as the on-die termination resistors (R

). For details see Table 2-13.

TT

TAP and CMOS signals do not include on-die termination. Inputs and utilized outputs
must be terminated on the motherboard. Unused outputs may be terminated on the
motherboard or left unconnected. Note that leaving unused outputs unterminated may
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing. Signal termination for these signal types is discussed in the appropriate
platform design guidelines.

All TESTHI[13,11:10:7:0] lands should be individually connected to V
resistor which matches the nominal trace impedance.

via a pull-up

TT

The TESTHI signals may use individual pull-up resistors or be grouped together as
detailed below. A matched resistor must be used for each group:

•TESTHI[1:0]

•TESTHI[7:2]

• TESTHI10 – cannot be grouped with other TESTHI signals

• TESTHI11 – cannot be grouped with other TESTHI signals

• TESTHI13 – cannot be grouped with other TESTHI signals

Terminating multiple TESTHI pins together with a single pull-up resistor is not
recommended for designs supporting boundary scan for proper Boundary Scan testing
of the TESTHI signals. For optimum noise margin, all pull-up resistor values used for
TESTHI[13, 11:10,7:0] lands should have a resistance value within ± 20% of the
impedance of the board transmission line traces. For example, if the nominal trace
impedance is 50

2.5 Flexible Motherboard Guidelines (FMB)

The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the
processor will have over certain time periods. The values are only estimates and actual
specifications for future processors may differ. Processors may or may not have
specifications equal to the FMB value in the foreseeable future. System designers
should meet the FMB values to ensure their systems will be compatible with future
processors. The FMB values are shown in Table 2-3 and Table 5-1.

16 Datasheet

Ω, then a value between 40 Ω and 60 Ω should be used.

Electrical Specifications

2.6 Power Segment Identifier (PSID)

Power Segment Identifier (PSID) is a mechanism to prevent booting under mismatched
power requirement situations. The PSID mechanism enables BIOS to detect if the
processor in use requires more power than the platform voltage regulator (VR) is
capable of supplying. For example, a 130W TDP processor installed in a board with a
65W or 95W TDP capable VR may draw too much power and cause a potential VR issue.

2.7 Voltage and Current Specification

2.7.1 Absolute Maximum and Minimum Ratings

Table 2-2 spe cifies absolute maximum and minimum ratings only and lie outside the

functional limits of the processor. Within functional operation limits, functionality and
long-term reliability can be expected.

At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function, or its reliability will be
severely degraded.

Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
electric fields.

Table 2-2. Absolute Maximum and Minimum Ratings

Symbol Parameter Min Max Unit Notes

V

CC

V

TT

T

CASE

T

STORAGE

NOTES:

1. For functional operation, all processor electrical, signal quality, mechanical and thermal

2. Overshoot and undershoot voltage guidelines for input, output and I/O signals are outlined

3. Storage temperature is applicable to storage conditions only. In this scenario, the

Core voltage with respect to
V

SS

FSB termination voltage with
respect to V

Processor case temperature See Section 5

Processor storage
temperature

specifications must be satisfied.

in Chapter 3. Excessive overshoot or undershoot on any signal will likely result in
permanent damage to the processor.

processor must not receive a clock, and no lands can be connected to a voltage bias.

SS

–0.3 1.45 V -

–0.3 1.45 V -

See

Section 5

–40 85 °C 3, 4, 5

°C -

1, 2

Datasheet

17

Storage within these limits will not affect the long-term reliability of the device . For
functional operation, refer to the processor case temperature specifications.

4. This rating applies to the processor and does not include any tray or packaging.

5. Failure to adhere to this specif ication can affect the long term reliability of the processor.

2.7.2 DC Voltage and Current Specification

Table 2-3. Voltage and Current Specifications

Electrical Specifications

Symbol Parameter Min Typ Max Unit

VID Range VID 0.8500 - 1.3625 V 1

Processor
Number

for 775_VR_CONFIG_05A

V

CC

(95W)
775_VR_CONFIG_06A
(65W)

3.16 GHz (12MB Cache)

3.00 GHz (12MB Cache)

2.83 GHz (12MB Cache)

2.66 GHz (6MB Cache)

2.83 GHz (12MB Cache)

2.66 GHz (12MB Cache)

2.50 GHz (6MB Cache)

for 775_VR_CONFIG_05A

I

CC

(95W)

Refer to Table 2-4 and

Figure 2-1

- 5% 1.50 + 5%

V

Core

V

CC

V

CC_BOOT

V

CCPLL

X3380

X3370

L3360

X3330
X3360
X3350
X3320

Default VCC voltage for initial power up - 1.10 - V
PLL V

CC

Processor
Number

775_VR_CONFIG_06A
(65W)

X3380

I

CC

X3370

L3360

X3330
X3360
X3350
X3320

V

TT

FSB termination voltage
(DC + AC specifications)

3.16 GHz (12MB Cache)

3.00 GHz (12MB Cache)

2.83 GHz (12MB Cache)

2.66 GHz (6MB Cache)

2.83 GHz (12MB Cache)

2.66 GHz (12MB Cache)

2.50 GHz (6MB Cache)

- - 100 A 6, 7

1.045 1.10 1.155 V 8, 9

VTT_OUT_LEFT
and
VTT_OUT_RIGHT
I

CC

I

TT

I

CC_VCCPLL

I

CC_GTLREF

DC Current that may be drawn from
VTT_OUT_LEFT and VTT_OUT_RIGHT per land

ICC for VTT supply before VCC stable

for VTT supply after VCC stable

I

CC

- - 580 mA

--

8.0

7.0

A10

ICC for PLL land 130 mA
ICC for GTLREF - - 200 µA

Notes

2, 11

3, 4, 5

NOTES:

1. Each processor is programmed with a maximum valid voltage identification value (VID),
which is set at manufacturing and can not be altered. Individual maximum VID values are
calibrated during manufacturing such that two processors at the same frequency may have

18 Datasheet

Electrical Specifications

2. Unless other w ise noted, all specifications in this table are based on estima tes and

3. These voltages are targets only. A variable voltage source should exist on systems in the

4. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE

5. Refer to Table 2-4 and Figure 2-1 for the minimum, typical, and maximum V

6. FMB is the Flexi b le Motherboard guideline. These guidelines are for estimation purpose s

7. I

8. V

9. Baseboard bandwidth is limited to 20 M H z.

10. This is the maximum total current drawn from the V

11. Adherence to the voltage specifications for the processor are required to ensure reliable

different settings within the VID range. Note that this differ s from the VID employed by the
processor during a power management event (Thermal Monitor 2, Enhanced Intel
SpeedStep

®

Technology, or Extended HALT State).

simulations or empirical data. These specifications will be updated with characterized data
from silicon measurements at a later date.

event that a different voltage is required. See Section 2.3 and Table 2-1 for more
information.

lands at the socket with a 100MHz bandwidth oscilloscope, 1.5 pF maxi mum probe
capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the
probe should be less than 5 mm. Ensure external noise from the system is not coupled into
the oscilloscope probe.

allowed for
a given current. The processor should not be subjected to any V
wherein V

exceeds V

CC

for a given current.

CC_MAX

and ICC combination

CC

CC

only. See Section 2.5 for further details on FMB guidelines.

specification is based on V

CC_MAX

must be provided via a separate voltage source and not be connected to VCC. This

TT

specification is measured at the land.

specification does not include the current coming from on-board termination (R
through the signal line. Refer to the appropriate platform design guide and the Voltage

loadline. Refer to Figure 2-1 for details.

CC_MAX

plane by only the processor. This

TT

),

TT

Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket to determine the total I

design characterization and is not tested.

drawn by the system. This parameter is based on

TT

processor operation.

Table 2-4. VCC Static and Transient Tolerance

Voltage Deviation from VID Setting (V)

ICC (A)

0 0.000 -0.019 -0.038

5 -0.007 -0.026 -0.045
10 -0.013 -0.033 -0.053
15 -0.020 -0.040 -0.060
20 -0.026 -0.047 -0.067
25 -0.033 -0.053 -0.074
30 -0.039 -0.060 -0.082
35 -0.046 -0.067 -0.089
40 -0.052 -0.074 -0.096
45 -0.059 -0.081 -0.103
50 -0.065 -0.088 -0.111
55 -0.072 -0.095 -0.118
60 -0.078 -0.102 -0.125
65 -0.085 -0.108 -0.132
70 -0.091 -0.115 -0.140
75 -0.098 -0.122 -0.147
80 -0.101 -0.126 -0.151

Maximum Voltage

1.30 mΩ

Typical Voltage

1.38 mΩ

1, 2, 3, 4

Minimum Voltage

1.45 mΩ

Datasheet

19

Table 2-4. VCC Static and Transient Tolerance (Continued)

Voltage Deviation from VID Setting (V)

ICC (A)

85 -0.111 -0.136 -0.161
90 -0.117 -0.143 -0.169
95 -0.124 -0.150 -0.176

100 -0.130 -0.157 -0.183

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot
allowed as shown in Section 2.7.3.

2. This table is intended to aid in reading discrete points on Figure 2-1.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and
VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be tak en
from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0
Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline
guidelines and VR implementation details.

4. Adherence to this loadline specification is required to ensure reliable processor operation.

Maximum Voltage

1.30 mΩ

Typical Voltage

1.38 mΩ

Electrical Specifications

1, 2, 3, 4

Minimum Voltage

1.45 mΩ

Figure 2-1. VCC Static and Transient Tolerance

VID - 0.000

VID - 0.013

VID - 0.025

VID - 0.038

VID - 0.050

VID - 0.063

VID - 0.075

VID - 0.088

VID - 0.100

Vcc [V]

VID - 0.113

VID - 0.125

VID - 0.138

VID - 0.150

VID - 0.163

VID - 0.175

VID - 0.188

0 102030405060708090100

Vcc Typical

Vcc Minimum

Icc [A]

Vcc Maximum

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot
allowed as shown in Section 2.7.3.

2. This loadline specification shows the deviation from the VID set point.

20 Datasheet

Electrical Specifications

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and
VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken
from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0
Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadli ne
guidelines and VR implementation details.

2.7.3 VCC Overshoot

The processor can tolerate short transient overshoot events where VCC exceeds the VID
voltage when transitioning from a high to low current load condition. This overshoot
cannot exceed VID + V
The time duration of the overshoot event must not exceed T

OS_MAX

maximum allowable time duration above VID). These specifications apply to the
processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.

Table 2-5. VCC Overshoot Specifications

Symbol Parameter Min Max Unit Figure Notes

V

OS_MAX

T

OS_MAX

NOTES:

1. Adherence to these s pecifications is required to ensure reliable processor operation.

Magnitude of VCC overshoot above
VID

Time duration of VCC overshoot above
VID

(V

OS_MAX

is the maximum allowable overshoot voltage).

OS_MAX

(T

OS_MAX

-50mV2-2

-25µs2-2

is the

1

1

Figure 2-2. VCC Overshoot Example Waveform

Example Overshoot Waveform

VID + 0.050

Voltage [V]

VID - 0.000

0 5 10 15 20 25

TOS: Overshoot time above VID
V

: Overshoot above VID

OS

NOTES:

1. V

2. T

is measured overshoot voltage.

OS

is measured time duration above VID.

OS

T

OS

Time [us]

V

OS

Datasheet

21

2.7.4 Die Voltage Validation

Overshoot events on processor must meet the specifications in Table 2-5 when
measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are <
10 ns in duration may be ignored. These measurements of processor die level
overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or
equal to 100 MHz bandwidth limit.

2.8 Signaling Specifications

Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling
technology. This technology provides improved noise margins and reduced ringing
through low voltage swings and controlled edge rates. Platforms implement a
termination voltage level for GTL+ signals defined as V
separate power planes for each processor (and chipset), separate V
are necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address busses have caused
signal integrity considerations and platform design methods to become even more
critical than with previous processor families. Design guidelines for the processor front
side bus are detailed in the appropriate platform design guides (refer to Section 1.2).

The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see Table 2-13 for GTLREF specifications). Refer to the applicable
platform design guidelines for details. Termination resistors (R
provided on the processor silicon and are terminated to V
provide on-die termination, thus eliminating the need to terminate the bus on the
motherboard for most GTL+ signals.

Electrical Specifications

. Because platforms implement

TT

TT

. Intel chipsets will also

TT

and V

CC

supplies

TT

) for GTL+ signals are

2.8.1 FSB Signal Groups

The front side bus signals have been combined into groups by buffer type. GTL+ input
signals have differential input buffers, which use GTLREF[3:0] as a reference level. In
this document, the term “GTL+ Input” refers to the GTL+ input group as well as the
GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output
group as well as the GTL+ I/O group when driving.

With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle. Table 2-6 identifies which signals are common clock, source synchronous,
and asynchronous.

22 Datasheet

Electrical Specifications

Table 2-6. FSB Signal Groups

Signal Group Type Signals

GTL+ Common
Clock Input

GTL+ Common
Clock I/O

GTL+ Source
Synchronous I/O

Synchronous to
BCLK[1:0]

Synchronous to
BCLK[1:0]

Synchronous to
assoc. strobe

1

BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#

ADS#, BNR#, BPM[5:0]#, BPMb[3:0]#, BR0#
DRDY#, HIT#, HITM#, LOCK#

Signals Associated Strobe

REQ[4:0]#, A[16:3]#
A[35:17]#

3

3

ADSTB0#

ADSTB1#
D[15:0]#, DBI0# DSTBP0#, DSTBN0#
D[31:16]#, DBI1# DSTBP1#, DSTBN1#
D[47:32]#, DBI2# DSTBP2#, DSTBN2#
D[63:48]#, DBI3# DSTBP3#, DSTBN3#

3

, DBSY#,

GTL+ Strobes

CMOS

Synchronous to
BCLK[1:0]

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

A20M#, DPSLP#, DPRSTP#, IGNNE#, INIT#, LINT0/
INTR, LINT1/NMI, SMI#

3

, STPCLK#, PWRGOOD, SLP#,
TCK, TDI, TDI_M, TMS, TRST#, BSEL[2:0], VID[7:0],

PSI#

Open Drain
Output

Open Drain
Input/Output

FSB Clock Clock BCLK[1:0], ITP_CLK[1:0]

FERR#/PBE#, IERR#, THERMTRIP#, TDO, TDO_M

PROCHOT#

4

2

VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA,
GTLREF[3:0], COMP[8,3:0], RESERVED,

Power/Other

TESTHI[13,11:10,7:0], VCC_SENSE,
VCC_MB_REGULATION, VSS_SENSE,
VSS_MB_REGULATION, DBR#

2

, VTT_OUT_LEFT,

VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0]

NOTES:

1. Refer to Section 4.2 for signal descriptions.

2. In processor systems where no debug port is implemented on the system board, the se
signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.

3. The value of these signals during the active-to-inactive edge of RESET# defines the
processor configuration options. See Section 6.1 for details.

4. PROCHOT# signal type is open drain output and CMOS input.

Datasheet

23

.

Table 2-7. Signal Characteristics

Electrical Specifications

Signals with R

A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,
HITM#, LOCK#, PROCHOT#, REQ[4:0]#,
RS[2:0]#, TRDY#

Open Drain Signals

THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,
BPMb[3:0]#, BR0#, TDO, TDO_M, FCx

NOTES:

1. Signals that do not have R

Table 2-8. Signal Reference Voltages

GTLREF VTT/2

BPM[5:0]#, BPMb[3:0]#, RESET#, BNR#, HIT#,
HITM#, BR0#, A[35:0]#, ADS#, ADSTB[1:0]#,
BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, LOCK#,
REQ[4:0]#, RS[2:0]#, TRDY#

NOTE:

1. See Table 2-10 for more information.

TT

Signals with No R

A20M#, BCLK[1:0], BSEL[2:0],
COMP[8,3:0], FERR#/PBE#, IERR#, IGNNE#,
INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/
NMI, MSID[1:0], PWRGOOD, RESET#, SMI#,
STPCLK#, TDO, TDO_M,
TESTHI[13,11:10,7:0], THERMTRIP#,
VID[6:0], GTLREF[3:0], TCK, TDI, TDI_M,
TMS, TRST#, VTT_SEL

1

, nor are actively driven to their high-voltage level.

TT

A20M#, LINT0/INTR, LINT1/NMI,
IGNNE#, INIT#, PROCHOT#,
PWRGOOD
TDI

1

1

, SMI#, STPCLK#, TCK1,

, TDI_M1, TMS1, TRST#

TT

1

2.8.2 CMOS and Open Drain Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS
input buffers. All of the CMOS and Open Drain signals are required to be asserted/
deasserted for at least eight BCLKs in order for the processor to recognize the proper
signal state. See Section 2.8.3 for the DC specifications. See Section 6.2 for additional
timing requirements for entering and leaving the low power states.

2.8.3 Processor DC Specifications

The processor DC specifications in this section are defined at the processor core (pads)
unless otherwise stated. All specifications apply to all frequencies and cache sizes
unless otherwise stated.

Table 2-9. GTL+ Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

V

V

V

I

24 Datasheet

Input Low Voltage -0.10 GTLREF - 0.10 V 2, 6

IL

Input High Voltage GTLREF + 0.10 V

IH

Output High Voltage V

OH

Output Low Current N/A

OL

- 0.10 V

TT

[(R

TT_MIN

+ 0.10 V 3, 4, 6

TT

TT

V
) + (2 * R

TT_MAX

/

ON_MIN

)]

V4, 6

A-

1

Electrical Specifications

Table 2-9. GTL+ Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

I

I

R

Input Leakage

LI

Current
Output Leakage

LO

Current
Buffer On Resistance 7.49 9.16 Ω 5

ON

N/A ± 100 µA 7

N/A ± 100 µA 8

NOTES:

1. Unless other wise noted, all specifications in this table apply to all processor frequencies.

2. V

3. V

is defined as the voltage range at a receiving agent that will be interpreted as a logical

IL

low value.

is defined as the voltage r ange at a rec eiving age nt that will be interpreted as a logical

IH

high value.

4. V

and VOH may experience excursions above VTT. However, input signal drivers must

IH

comply with the signal quality specifi cations in Chapter 3.

5. Refer to processor I/O Buffer Models for I/V characteristics.

6. The V

7. Leakage to V

8. Leakage to V

referred to in these specifications is the instantaneous VTT.

TT

with land held at VTT.

SS

with land held at 300mV.

TT

Table 2-10. Open Drain and TAP Output Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

1

1

V

I
I

Output Low Voltage 0 0.20 V -

OL

Output Low Current 16 50 mA 2

OL

Output Leakage Current N/A ± 200 µA 3

LO

NOTES:

1. Unless other wise noted, all specifications in this table apply to all processor frequencies.

2. Measured at V

3. For Vin between 0 and V

* 0.2V.

TT

OH

.

Table 2-11. CMOS Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

V

V
V
V

I

I

I

NOTES:

1. Unless other wise noted, all specifications in this table apply to all processor frequencies.

2. All outputs are open drain.

Input Low Voltage -0.10 VTT * 0.30 V 3, 6

IL

Input High Voltage VTT * 0.70 V

IH

Output Low Voltage -0.10 VTT * 0.10 V 6

OL

Output High Voltage 0.90 * V

OH

Output Low Current

OL

Output Low Current

OH

I

Input Leakage Current N/A ± 100 µA 8

LI

Output Leakage Current N/A ± 100 µA 9

LO

TT

TT

V

* 0.10 / 67VTT * 0.10 /

TT

V

* 0.10 / 67VTT * 0.10 /

TT

V

TT

+ 0.10 V 4, 5, 6

+ 0.10 V 2, 5, 6

27

27

A6, 7

A6, 7

1

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25

Electrical Specifications

3. VIL is defined as the voltage range at a receiving agent that will be interpret ed as a l ogical
low value.

4. V

5. V

6. The V

7. I

8. Leakage to VSS with land held at VTT.

9. Leakage to V

is defined as the voltage range at a receiving agent that will be int erpreted as a logic al

IH

high value.

and VOH may experience excursions above VTT. However, input signal drivers must

IH

comply with the signal quality specifications in Chapter 3.

referred to in these specifications refers to instantaneous VTT.

TT

is measured at 0.10 * V

OL

with land held at 300 mV.

TT

is measured at 0.90 * V

TT. IOH

TT .

2.8.3.1 Platform Environment Control Interface (PECI) DC Specifications

PECI is an Intel proprietary one-wire interface that provides a communication channel
between Intel processors, chipsets, and external thermal monitoring devices. The
Yorkfield processor contains Digital Thermal Sensors (DTS) distributed throughout die.
These sensors are implemented as analog-to-digital converters calibrated at the factory
for reasonable accuracy to provide a digital representation of relative processor
temperature. PECI provides an interface to relay the highest DTS temper ature within a
die to external management devices for thermal/fan speed control. More detailed
information may be found in the Platform Environment Control Interface (PECI)

Specification.

Table 2-12. PECI DC Electrical Limits

Symbol Definition and Conditions Min Max Units Notes

V

V

hysteresis

V
V

I

source

I

sink

I

leak+

I

leak-

C

V

noise

NOTES:

1. V

TT

refer to Table 2-3 for VTT specifications.

2. The leakage specification applies t o powered devices on the PECI bus.

3. The input buffers use a Schmitt-triggered input design for improved noise immunity.

4. One node is counted for each client and one node for the sy stem ho st. Ex tended trace lengths

might appear as additional nodes.

.

Input Voltage Range -0.15 V

in

Hysteresis 0.1 * V
Negative-edge threshold voltage 0.275 * VTT0.500 * V

n

Positive-edge threshold voltage 0.550 * VTT0.725 * V

p

High level output source

= 0.75 * VTT)

(V

OH

Low level output sink

= 0.25 * VTT)

(V

OL

High impedance state leakage to V

TT

-6.0 N/A mA

0.5 1.0 mA

N/A 50 µA

TT

TT

-V

V

V

TT

V

TT

High impedance leakage to GND N/A 10 µA 2
Bus capacitance per node -10pF4

bus

Signal noise immunity above 300 MHz 0.1 * V

TT

-V

p-p

supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. Please

1

2

3

2.8.3.2 GTL+ Front Side Bus Specifications

In most cases, termination resistors are not required as these are integrated into the
processor silicon. See Table 2-7 for details on which GTL+ signals do not include on-die
termination. Refer to the appropriate platform design guidelines for specific
implementation details.

26 Datasheet

Electrical Specifications

Valid high and low levels are determined by the input buffers by comparing with a
reference voltage called GTLREF. Table 2-13 lists the GTLREF specifications. The GTL+
reference voltage (GTLREF) should be generated on the system board using high
precision voltage divider circuits. For more details on platform design, see the
applicable platform design guide.

Table 2-13. GTL+ Bus Voltage Definitions

Symbol Parameter Min Typ Max Units Notes

GTLREF_PU GTLREF pull up resistor 57.6 * 0.99 57.6 57.6 * 1.01 Ω 2
GTLREF_PD GTLREF pull down resistor 100 * 0.99 100 100 * 1.01 Ω 2
R

TT

COMP[3:0] COMP Resistance 49.40 49.90 50.40 Ω 4
COMP8 COMP Resistance 24.65 24.90 25.15 Ω 4

NOTES:

1. Unless other wise noted, all specifications in this table apply to all processor frequencies.

2. GTLREF is to be generated from VTT by a voltage divider of 1% resistors. If an Variable

3. R

4. COMP resistance must be provided on the system board with 1% resistors. See the

Termination Resistance 45 50 55 Ω 3

GTLREF circuit is used on the board the GTLREF lands connected to the Variable GTLREF
circuit may require different resistor values. Each GTLREF land must be connected, refer to
the platform design guide for implementation details.

is the on-die termination resistance measured at VTT/3 of the GTL+ output driver.

TT

Refer to the appropriate platform design guide for the board impedance. Refer to processor
I/O buffer models for I/V characteristics.

applicable platform design guide for implementation details. COMP[3:0] and COMP8
resistors are to V

SS

.

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27

Electrical Specifications

2.9 Clock Specifications

2.9.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor’s core frequency is a
multiple of the BCLK[1:0] frequency . The processor bus r atio multiplier will be set at its
default ratio during manufacturing. The processor supports Half Ratios between 7.5
and 13.5, refer to Table 2-14 for the processor supported ratios.

The processor uses a differential clo cking implem entation. For more information on the
processor clocking, contact your Intel field representative.

Table 2-14. Core Frequency to FSB Multiplier Configuration

Multiplication of

System Core

Frequency to FSB

Frequency

1/6
1/7

1/7.5

1/8

1/8.5

1/9

1/9.5

1/10

1/10.5

1/11

1/11.5

1/12

1/12.5

1/13

1/13.5

1/14
1/15

Core Frequency

(333 MHz BCLK/1333

MHz FSB)

2 GHz

2.33 GHz

2.50 GHz

2.66 GHz

2.83 GHz
3 GHz

3.16 GHz

3.33 GHz

3.50 GHz

3.66 GHz

3.83 GHz
4 GHz

4.16 GHz

4.33 GHz

4.50 GHz

4.66 GHz
5 GHz

Notes

1, 2

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

NOTES:

1. Individual processors operate only at or below the rated frequency.

2. Listed frequencies are not necessarily committed production frequencies.

2.9.2 FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). Table 2-15 defines the possible combinations of the signals and the
frequency associated with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All agents must operate at the same
frequency.

28 Datasheet

Electrical Specifications

The Yorkfield processor will operate at a 1333 MHz FSB frequency (selected by a 333
MHz BCLK[1:0] frequency). Individual processors will only operate at their specified
FSB frequency.

For more information about these signals, refer to Section 4.2 and the appropriate
platform design guidelines.

Table 2-15. BSEL[2:0] Frequency Tab le for BCLK[1:0]

BSEL2 BSEL1 BSEL0 FSB Frequency

L L L RESERVED
L L H RESERVED
L H H RESERVED

L H L RESERVED
H H L RESERVED
H H H RESERVED
H L H RESERVED
HL L333 MHz

2.9.3 Phase Lock Loop (PLL) and Filter

An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is
used for the PLL. Refer to Table 2-3 for DC specifications. Refer to the appropriate
platform design guidelines for decoupling and routing guidelines.

Datasheet

29

2.9.4 BCLK[1:0] Specifications

Table 2-16. Front Side Bus Differential BCLK Specifications

Symbol Parameter Min Typ Max Unit Figure Notes

V
V

V

CROSS(abs)

∆V

CROSS

V

OS

V

US

V

SWING

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of

3. “Steady state” voltage, not including overshoot or undershoot.

4. Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined

5. Measurement taken from differential waveform.

Input Low Voltage -0.30 N/A N/A V 2-3 3

L

Input High Voltage N/A N/A 1.15 V 2-3 3

H

Absolute Crossing
Point

Range of Crossing
Points

0.300 N/A 0.550 V 2-3 2

N/A N/A 0.140 V 2-3 -

Overshoot N/A N/A 1.4 V 2-3 4
Undershoot -0.300 N/A N/A V 2-3 4
Differential Output

Swing

0.300 N/A N/A V 2-4 5

BCLK0 equals the falling edge of BCLK1.

as the absolute value of the minimum voltage.

Electrical Specifications

1

Table 2-17. FSB Differential Clock Specifications (1333 MHz FSB)

T# Parameter Min Nom Max Unit Figure Notes

BCLK[1:0] Frequency 331.633 - 333.367 MHz - 7
T1: BCLK[1:0] Period 2.99970 - 3.01538 ns 2-3 2
T2: BCLK[1:0] Period Stability - - 150 ps 2-3 3, 4
T5: BCLK[1:0] Rise and Fall Slew

Rate
Slew Rate Matching N/A N/A 20 % - 6

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor core
frequencies based on a 333 MHz BCLK[1:0].

2. The period specified here is the average period. A given period may vary from this
specification as governed by the period stability specification (T2). Min period specification
is based on -300 PPM deviation from a 3 ns period. Max period specification is based on
the summation of +300 PPM deviation from a 3 ns period and a +0.5% maxi mum variance
due to spread spectrum clocking.

3. For the clock jitter specification, refer to the CK505 Clock Synthesizer Specification.

4. In this context, period stability is defined as the worst case timing difference between
successive crossover voltages. In other words, the largest absolute difference between
adjacent clock periods must be less than the period stability.

5. Slew rate is measured through the VSWING voltage range centered about differential zero.
Measurement taken from differential waveform.

6. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is
measured using a ±75mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.

2.5 - 8 V/ns 2-4 5

1

30 Datasheet