Intel PXA27x Series Specification Update

Intel® PXA27x Processor Family

Specification Update

October 2004

.Notice: The Intel® PXA27x Processor Family may contain design defects or errors known as errata that may ca use the pr oduct to deviate from pu blish ed spe cificati ons. Cur rent c haracter ized errata are documented in this s pecification update.

Order Number: 280071-003

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Revision History

Revision Date Version Description

October, 2004 003 Added Errata 51, 52, 53, 54

August, 2004 002

April, 2004 001 First publication

Added Errata 48, 49, 50 Added Documentation Changes 5 - 15

Revision History

Intel® PXA27x Processo r Family Specification Update 3

Preface

This document contains updates to the specifications for the Intel® PX A27 x Processor Family, listed in Table 1. clarifications, and spec ification changes. software developers of applications, operating systems, a nd tools.

Intel Corporation has endeavored to incl ude a ll documented errata in the cons olidation pr oc ess. However, Intel makes no representa tions or warranties concerning the com ple teness of the Intel®

PXA27x Processor Family Specification Upda te .

Information types defined in Nomenclature are consolidated into the Intel® PXA27x Processor

Family Specification Update a nd are no longer published in other documents.

This document might also contain information that was not previously published.

This document is a co mpilation of device and docu mentation errata, specif ication

It is intended for hardware system m anufacturers and

4 Intel® PXA27x Processor Family Specification Update

Affected and Rel ated Documents

Affected and Related Documents

Table 1 lists the documents affected by and related to this errata update.

Contact an Intel® representative to obtain the latest revisio ns of these documents.

Table 1. Affect ed Do cument s / Related Documents

Title

Intel® PXA27x Processor Family Developer’s Manual Intel® PXA27x Processor Family Design Guide Intel® PXA27x Processor Family Electrical, Mechanical, and Thermal Specification

Intel® PXA27x Processo r Family Specification Update 5

Nomenclature

Errata are design defects or errors. These errata mi ght cause the Inte l® PXA27x Pro c e ssor Family’s behavior to deviate from publishe d specifications. used with any given processor stepping must assume that all errata documented for that stepping are present on all devices unless oth erw is e noted.

Document at io n cha ng es include typos, errors, and omissions from the c urrent published specifications. These changes will be incorporated in the next release of the document.

Specification clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. any new release of the document.

Specification changes are modifications to the current published specifications. These changes will be incorporated in the next release of the document.

Note: Errata remain in the specification update thr oughout the produ ct’s life cycle, or until a partic ular

stepping is no longer commercially available. Under these circumstances, errata removed from the specification update are arch ived and made available upon request. Specif ication changes, specification clarif ications, and documentation changes are removed f rom the specification update when the appropriate changes are made to the appropriate product specification or user documentat ion (data sheets, manuals, a nd so forth).

Hardware and software designed to be

These clarifications will be in corporated in

6 Intel® PXA27x Processor Family Specification Update

Intel® PXA27x Processor Family Package Markings

The following figure depicts the location, on specific Intel® PXA27x Processor Family packages, where the actual markings are located. Actual markings are described in Table 2.

Figure 1.Intel® PXA27x Processor Family Package Ma rkings Locations

“LINE 1”

PIN 1 INDICATOR for PXA271 and PXA272 Processor Family

“LINE 2” “LINE 3” “LINE 4” “LINE 5” “LINE 6”

PIN 1 INDICATOR for PXA270 Processor

Table 2 describes the actual markings that are on th e package at the locat ion indicated by “LINE x”

for each package offered.

Intel® PXA27x Processo r Family Specification Update 7

Intel® PXA27x Processor Family Package Markings

Note: This table is for example only. It must not be used to determine fina l production offerings.

Table 2. Example Processor Package Markings (For Example Only)

Discrete/

MCP

Max.

Freq.

Lead/

Lead Free

Stepping C0 C0 C0 C0 C0

Line 1 RCPXA270C0C624 RTPXA270C0C416 LVPXA271FC0312 RVPXA272FC0520 RVPXA272FC0416 Line 2 {FPO#} {FPO#} {MCP FPO#} {MCP FPO#} {MCP FPO#} Line 3 {QDF#} {QDF#} {QDF#} {QDF#} {QDF#} Line 4 {M} {C} ’04 {M} {C} ’04 {M} {C} ’04 {M} {C} ’04 {M} {C} ’04 Line 5 ATPO# ATPO# ATPO # Line 6 COO COO COO

13x13 T-PBGA 13x13 T-PBGA

624 MHz 416 MHz 312 MHz 520 MHz 416 MHz

Lead (Pb) Lead (Pb) Free Lead (Pb) Lead (Pb) Free Lead (Pb) Free

14x14 FFCSP/

256LTyax/256SD

14x14 FFCSP/

256LTyax/256SD

14x14 FFSCP/

2x256L Tyax

8 Intel® PXA27x Processor Family Specification Update

Summary of Changes

The following tables summarize the er rata, specification changes, specification clarifi cations, and documentation chang es that apply to the In tel® PXA2 7x Process or Family . the errata in a future steppi ng of the component and account for the other ou ts tanding issues through documentatio n or specification changes a s noted.

Notation Meaning

Summary of Ch an ges

Intel migh t fi x s ome of

These tables use the following notations:

(No mark) or (Blank Box)

Plan Fix This erratum might be fixed in a future stepping of the product. Fixed This erratum has been previously fixed. No Fix There are no plans to fix this erratum. Doc Intel plans to update the appropriate documentation in a future revision. No Bug This erratum has been determined to be a false erratum. Shaded This item is either new or modified from the previous version of the document.

This erratum exists in the stepping indicated. specification change or clarification that applies to this stepping.

This erratum is fixed in the listed stepping, or the specification change doe s n ot app ly to th e listed stepping.

Table 3. Summ ary of Errata (Sheet 1 of 3)

References C0 Status

Number Title Page

CORE: IFU misses an external abort when a lock command is outstanding

CORE: Aborted store that hits D-cache might mark write-back data as dirty

CORE: Performance Monitor Unit Counts, using performance monitoring event number 0x1, can be incremented erroneously by unrelated core events

CORE: In SDS mode, back-to-back memory operations where the first instruction aborts might hang

CORE: Lock aborts resulting from I-cache or I-TLB lock operations are not presented properly on the trace interface

CORE: CP15 ID register accesses with opcode2 > 0b001 r eturn unpredictable values

CORE: Disabling and re-enabling the MMU can hang the core or cause it to execute the wrong code

CORE: JTAG parallel register updates require an extra TCK rising edge

MMC: SPI mode – if card is deselected, PROG_DONE will not be set

MEMC: No MRS command is given when exiting from Alternate Bus Master Mode when SA1111 Address Muxi ng Mode is enabled

13 X No Fix

14 X No Fix

15 X No Fix

16 X No Fix

Intel® PXA27x Processo r Family Specification Update 9

Summary of Changes

Table 3. Summary of Errata (Sheet 2 of 3)

Number Title Page

11 KBD: Extra Keypad matrix interrupt in IMKP Mode 16 X No Fix 12 13 AC97: Command Done bit remains set after an AC97 cold reset 17 X No Fix 14

20 21 LCD: LCD not enabling in dual panel mode. 21 X No Fix

22 UDC: UDC does not correctly support alternate interfaces. 22 X No Fix 23

24 25 LCD: Enabling Overlay 2 for YUV420 hangs LCD controller. 23 X Plan Fix 26

32 33 SSP: TXD line does not tristate when SSP is Slave to Frame 29 X No Fix 34

USBH: USBH Register UHCRHPSx[CCS] Bit Set Incorrectly After Power On

POWER MANAGER: Fast Ramp rates on voltage pins can cause high current consumption.

LCD: Reconfiguring the LCD controller retains the previous PPL value for the first line.

MSHC: Memory Stick does not come out of SLEEP mode after wake up process.

LCD: Overlay1 is not enabled intermittently after re-enabling LCD.

POWER MANAGER: Processor ignores BA TT/V CC faults while exiting sleep mode.

KBD: Keyboard Edge-Detect Status Register Incorrect After Standby Mode Wakeup.

UART: Character Timeout interrupt remains set under certain software conditions

ICP: Receiver Aborts randomly occur prematurely and without End of frame/Error in FIFO interrupt

SSP: OSTimer counter increments incorrectly for SSP Frames in Network mode

USBOTG: Unable to measure duration of Single-Ended Zero (SE0) for Session Request Protocol (SRP)

MEMC: Write/Read to/from SDRAM can collide with alternate bus master mode when MDREFR:ALTREFB is set.

Power Manger: Core hangs during voltage change when there are outstanding transactions on the bus

MMC: MMC unit in SPI mode always waits a minimum of 1 Ncx cycles, even though the MMC spec dictates that SPI mode CMD9 can have a minimum of 0 Ncx cycles.

SD: SD Controller in SPI mode not receiving data response for CMD9 and CMD10 from some SD Cards

MEMC: SDRAM Refresh Commands are issued too often during a VLIO access while BREQ is asserted.

Interrupt Controller: Unexpected exception vector when ICCR[DIM]=0 and ICMR=0.

PowerManager: Simultaneous BATT and VDD faults results in going to DeepSleep mode twice.

CORE: Non-branch instruction in vector table may execute twice after a thumb mode exception

UART: UART does not correctly indicate a Framing Error Interrupt in DMA mode.

References C0 Status

17 X No Fix

18 X No Fix

19 X No Fix

19 X Plan Fix

20 X No Fix

21 X No Fix

23 X No Fix

24 X Plan Fix

25 X No Fix

27 X Plan Fix

28 X No Fix

29 X No Fix

30 X No Fix

10 Intel® PXA27x Processor Family Specification Update

Table 3. Summ ary of Errata (Sheet 3 of 3)

References C0 Status

Number Title Page

37 38 CLOCKS: System Hangs when enabling HalfTurbo Switching 31 X No Fix 39 40 SDIO: SDIO Devices Not Working at 19.5 Mbps 32 X Plan Fix 41

44 KBD: Keypress wakeup from Standby mode is not reliable 34 X No Fix 45

51 52 LCDC: Disable Done Interrupt does not always occur 38 X No Fix 53 54 AC97: AC97 CAR[CAIP] bit field can be incorrectly set 38 X No Fix

CLOCKS: System Hangs when enabling RUN/TURBO switching at 520MHz

MEMC: Memory Controller hangs when entering Self Refresh Mode.

AC97: Command Done bit is never set when data is written in slot12

SD/MMC: SD/MMC controller CRC errors with some SD/MMC cards

USBH: There is no Individual Power Sense Polarity bit for each Host Port. The Power Sense Polarity bit controls the polarity for all three Host Ports.

USBH: USB Host Port 3 in Transceiverless Mode may not work correctly with an external device.

SD/MMC: SPI mode commands fail even on cards that are compatible with SPI spec 1.0

CLOCKS AND POWER: PWM Clock Enables do not work as specified

ICP: Occasionally EIF, EOF and CRC interrupt are missed when a CRC error is recei ved

POWER MANAGER: Batt Fault does not always re-enable GPIO 0 and GPIO 1 as wake-up sources.

POWER MANAGER: The processor does not exit from Sleep/ Deep-Sleep Mode.

SDIO: CMD53 multiple block data transfer with block count set to 0 not supported

UDC: RCV can not be tied high during UDC transmission when using an external transceiver

Summary of Ch an ges

30 X No Fix

32 X No Fix

33 X No Fix

33 X Plan Fix

34 X Plan Fix

35 X Plan Fix

35 X No Fix

36 X No Fix

37 X Plan Fix

37 X No Fix

38 X No Fix

Table 4. Summary of Specifi cation Changes

Number Title Page

NOTE: There are no specification changes at this time.

Table 5. Summ ary of Speci fi cation Clarifications

Number Document Revision Page Status Specification Clarifications

NOTE: There are no specification clarifications at this time.

Intel® PXA27x Processo r Family Specification Update 11

References Status

Summary of Changes

Table 6. Summary of Documentation Changes

Number Document Revision Page Status Documentation Changes

NOTE: There are no documentation changes at this time.

12 Intel® PXA27x Processor Family Specification Update

Errata

E1. CORE: IFU misses an external abort when a lock command is

outstanding.

Problem: A bus abort occurs on a code fetch while an I-TLB lo ck mcr is outstanding. The IFU fails to abort,

instead executing t he ins tructi on return ed on th e abort ing trans action. P arity e rrors are not aff ected. The bus a bort might be due to either an ABORT pin asserti on or a mult i-bit ECC error on the c ore. On the core, the bus abort can occur as th e result of a master abort, a targe t abort, or a single data phase disconnect on the system bus.

Implication: TBD Workaround: Branch flush after every ITLB or I-ca che lock. Status: No Fix

E2. CORE: Aborted store that hits D- cache might mark write-back data as

dirty.

Problem: If an aborted store hits clean data in the data cache (data in an aligned four-word range that has not

been modified from the core since it was last loaded in from memory or cleaned), the data in the array will not be modified (the store will be blocked), but the dirty bit will be set.

When that line is then aged out of the data cache or explicitly cleaned, the data in that four-wor d range will be evicted to external memory, even though it has never been changed. In normal operation, this will be nothing more than an extra store on the bus that writes the same data to memory as is already there.

This problem might be visible at the following boundary condition:

1. A cache line is loaded into the cache at address A

2. Another master externally modifies address A

3. An Intel XScale® core sto re in stru ction atte mpts to mod ify A, hits the cache, aborts becau se o f MMU permissions, and is back ed out the of cache. That lin e should no t be marked “d irty”, but because of this defect it will be.

4. The cache line at A then ages out or is explicitly cleaned. The origin al data from location A will be evicted to external memory, overwriting the data written by the external master.

This situation happen sonly if software is allowing an exter nal m aster to modify memory that is write-back or w rite- allocate in the XScale pag e tables , an d depen ding o n the f act th at t he data is n ot dirty in the XScale cache to preclu de the cached version from overwriting the ext ern al memory version. If there are any semaphor es or any other handshaking to prevent collis ions on shared memory, this should not be a problem.

Implication: TBD Workaround: For a shared memory region , mark it as write-through mem ory in the XScale page table to prevent

the data from ever being written out as dirty, so the defect does not appear. Alternatively, ensure that any cached copy of t he data in exte rnal memory is inv alidated if an ext ernal ag ent mod ifies th e external copy.

Status: No Fix

Intel® PXA27x Processo r Family Specification Update 13

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