Intel PXA27X User Manual
Intel® PXA27x Processor Family
Power Requirements
Application Note
Order Number: 280005-002
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ii Application Note
Intel® PXA27x Processor Family Power Requirements
Contents
Contents
1.0 Introduction.................................................................................................................................... 5
1.1 Naming Conventions ............................................................................................................5
2.0 Intel® PXA27x Processor Power Supply Domains..................................................................... 5
2.1 Power Domains and System Voltage/Current Requirements...............................................8
2.1.1 Intel® PXA27x Processor Power Supplies ..............................................................8
2.1.2 Power Supply Configuration in a Minimal System ................................................. 10
2.1.3 Intel® PXA27x Processor Supply Current for Each Power Domain ...................... 11
2.1.4 Intel® PXA27x Processor VCC_CORE Supply Current ........................................12
2.1.5 Default Reset Values ............................................................................................. 13
2.2 Batteries..............................................................................................................................14
2.2.1 Main Battery........................................................................................................... 14
2.2.2 Backup Battery ...................................................................................................... 14
2.2.3 Battery Chargers and Main Power.........................................................................15
3.0 Intel® PXA27x Processor Low Power Operating Modes .........................................................17
4.0 Power Controller Interface Signals............................................................................................ 18
4.1 Power Enable (PWR_EN)...................................................................................................19
4.2 System Power Enable (SYS_EN) / GPIO<2>.....................................................................19
4.3 Power Manager I2C Clock (PWR_SCL) / GPIO<3>...........................................................19
4.4 Power Manager I2C Data (PWR_SDA) / GPIO<4>)...........................................................20
4.5 System-Level Considerations for I2C .................................................................................20
4.6 On, Off, and RESET ...........................................................................................................20
4.6.1 On and Off Control.................................................................................................20
4.6.2 User-Initiated Hard Reset Input ............................................................................. 20
4.6.3 nRESET Output from PMIC to the Intel® PXA27x Processor ............................... 21
4.7 Universal Subscriber Identity Module (USIM)..................................................................... 21
4.8 Power Manager Capacitor Signals .....................................................................................21
5.0 Power Mode Sequencing ............................................................................................................ 22
5.1 Power-On............................................................................................................................22
5.1.1 Cold-Start Power-On and Hardware Reset............................................................22
5.1.2 Initial Power Up and Deep Sleep Exit Sequence...................................................23
5.1.3 Hardware Reset Behavior......................................................................................24
5.2 Sleep and Deep Sleep........................................................................................................27
5.2.1 Sleep Entry and Exit ..............................................................................................27
5.2.2 Deep Sleep Entry and Exit.....................................................................................28
6.0 Dynamic Voltage Management (DVM) .......................................................................................29
6.1 VCC_CORE Regulator and Dynamic Voltage Management.............................................. 29
6.2 Intel® PXA27x Processor Voltage Manager.......................................................................30
6.3 Power Manager I2C Interface.............................................................................................31
6.4 DVM Sequencing................................................................................................................31
7.0 Fault Management .......................................................................................................................31
7.1 nVDD_FAULT..................................................................................................................... 31
Application Note iii
Intel® PXA27x Processor Family Power Requirements
Contents
7.2 nBATT_FAULT ...................................................................................................................32
8.0 Power Management Integrated Circuit Requirements ............................................................. 32
8.1 General PMIC Characteristics ............................................................................................ 32
8.2 Features of a PMIC............................................................................................................. 33
8.3 Programmable Voltage Control ..........................................................................................34
8.3.1 DVM Control Register 1......................................................................................... 34
8.3.2 DVM Control Register 2......................................................................................... 34
8.3.3 DVM Control and Status Register 3....................................................................... 35
8.3.4 Other Aspects of an Integrated Power Controller .................................................. 35
9.0 Summary ......................................................................................................................................35
Figures
1 Intel® PXA27x Processor Internal and External Power Domains ................................................7
2 Typical Battery and External Regulator Configuration................................................................ 16
3 Overview of Power Management Operating Modes................................................................... 18
4 Intel® PXA27x Processor Power Manager Sleep Reset State Diagram.................................... 26
Tables
1 External Power Supply Descriptions ............................................................................................ 6
2 Intel® PXA27x Processor Voltage Domains................................................................................. 9
3 Regulators Required to Power the Intel® PXA27x Processor....................................................11
4 Intel® PXA27x Processor Supply Current For Each Power Domain..........................................11
5 Intel® PXA27x Processor VCC_CORE Supply Current............................................................. 13
6 Possible Backup Battery Configurations ....................................................................................14
7 Intel® PXA27x Processor Operating Modes .............................................................................. 17
8 Power Controller Interface Signals .............................................................................................19
9 General PMIC Characteristics ....................................................................................................33
iv Application Note
1.0 Introduction
The Intel® PXA27x Processor Family (PXA27x processor) is a highly integrated system-on-chip
optimized for handheld battery-powered devices such as PDAs and 2.5G or 3G cell phones. The
PXA27x processor is ideal for products requiring substantial computing and multimedia capability
with very low power consumption.
The PXA27x processor combines a high-performance CPU with a variety of integrated peripheral
functions. The processor has separate power supply domains for the processor core, memory, and
peripherals to enable low-power system design. The PXA27x processor provides several dedicated
control signals as well as an I
circuit.
Other system components, such as SDRAM and flash memory, audio codecs, touchscreen
controllers, and specialized companion chips, have with their own unique power requirements. In
many designs, a highly integrated power controller supplies power for these other components,
particularly those that interface directly to the PXA27x processor. An advanced power controller
can contain circuitry for charging batteries, powering the display panel, and include other analog
functions required by the system.
In any system design, factors such as operating conditions, application workload, environmental
considerations and the sophistication of the device’s power management software all play a role in
determining the amount of power consumed. When designing a system, manufacturers need to take
into account where the device is intended to be used (such as high temperature environments) and
what it is expected to do for an end user (such as play a game, a video or do simple email
transactions).
Intel® PXA27x Processor Family Power Requirements
2
C interface to connect to an external power management integrated
The Intel® PXA27x Processor Family EMTS provides manufacturers with a typical system power
consumption specification for all frequencies of the processor family. The purpose of this
application note is to provide guidance on how power consumption, in a typical environment can
change, based on different software workloads. In addition, this application note provides further
details on the requirements for providing power to the processor and for interfacing to its power
control signals, including behavioral requirements and typical system design examples under these
workloads.
The power numbers generated utilized Intel development platforms in lab conditions and the
information provided should be used as a guideline only.
1.1 Naming Conventions
In this document, active low items are prefixed with a lowercase “n”.
nRESET
Bits within a signal name are enclosed in angle brackets:
EXTERNAL_ADDRESS<31:0>
nCS<1>
Bits within a register bit field are enclosed in square brackets:
REGISTER_BITFIELD[3:0]
REGISTER_BIT[0]
Application Note 5
Intel® PXA27x Processor Family Power Requirements
The terms run mode and normal mode are used interchangeably, although normal mode comprises
both the run-mode and turbo-mode settings.
2.0 Intel® PXA27x Processor Power Supply Domains
Viewed externally, the main or backup battery powers ten power-supply domains. Additional
supply domains are present internally, but power for these is derived from the external supply
inputs.
All functional units within a power domain connect to the same power supply and are powered up
and down together. The PXA27x processor architecture, with its multiple power-supply domains,
provides flexibility in system configuration (including selection of I/O voltages for different
memory and peripherals) and efficient power management (for instance, flexibility in selecting
which peripherals are powered at the same time). Together, these let system designers make power/
complexity trade-offs and optimize a product for intended markets.
Product designers can also choose to strap certain supplies together (to power several domains
from a common regulator) to reduce complexity, cost, and the number of regulators in the system.
Guidelines showing which supplies can be combined are provided in this document.
A summary of the voltage and tolerance requirements for each external supply input is shown in
Tab l e 1. Figure 1 shows the PXA27x processor internal and external power domains and their
connections.
Table 1. External Power Supply Descriptions
Power Domain Enable
VCC_BATT None
VCC_IO SYS_EN Peripheral input/output 3.0, 3.3
VCC_LCD SYS_EN LCD input/output 1.8, 2.5, 3.0, 3.3
VCC_MEM SYS_EN Memory controller input/output 1.8, 2.5, 3.0, 3.3
VCC_BB SYS_EN Baseband interface 1.8, 2.5, 3.0, 3.3
VCC_USIM SYS_EN USIM interface 1.8, 3.0
VCC_USB SYS_EN Differential USB input/output 3.0, 3.3 ±10
VCC_PLL PWR_EN Phase-locked loops 1.3 ±10
VCC_SRAM PWR_EN Internal SRAM units 1.1 ±10
VCC_CORE PWR_EN CPU and other internal units variable 0.85 – 1.55
NOTE: SYS_EN and PWR_EN are PXA27x processor output control signals.
1. PXA27x processors have different maximum frequencies and VCC_CORE voltages. Refer to both of the
Processor Family EMTSs for details.
1
Sleep-control subsystem, oscillators and
real-time clock
Units
Specified Levels
(Volts)
3.0 ± 25
1
Tol eranc e
(%)
±10 (@ 3.0 V
=10%, -10.3%)
+20,-5 (@ 1.8 V)
otherwise ±10
+20,-5 (@ 1.8 V)
otherwise ±10
+20,-5 (@ 1.8 V)
otherwise ±10
+20,-5 (@ 1.8 V)
otherwise ±10
-5 +10
Intel® PXA27x
6 Application Note
Intel® PXA27x Processor Family Power Requirements
Figure 1. Intel® PXA27x Processor Internal and External Power Domains
VCC_PLL VCC_CORE VCC_SRAM
VCC_OSC
VCC_REG
C-PLL
prg. frq.
P-PLL
312 M
PXTAL
13 M
TXTAL
32.768 k
V-R eg
CPM
32.768 k
RTC
32.768 k
PWR_I2C
13 M
Timer
13 M
DC-DC
Lin-Reg L1
VCC_PI
VCC_PLL
VCC_OSC
VCC_RTC
VCC_CPU
VCC_PER
SRAM
Control
VCC_R3
SRAM
3
VCC_R2
SRAM
2
VCC_R1
SRAM
1
VCC_R0
SRAM
0
CPU
DMA/
Bridge
Intr
Control
MEM
Control
LCD
Control
USB-H
48.000 M
USB-C
48.000 M
ICP
48.000 M
I2S
prg. frq.
MMC
19.500 M
BB
48.000 M
USIM
48.000 M
VCC_MEMVCC_LCDVCC_IO
VCC_USB
VCC_BBVCC_IO
VCC_USIM
JTAG
TCK
KYBD
32.768 k
SSPs
13 M
PWMs
13 M
I2C
32.842 M
UARTs
14.857 M
AC
(ext clk)
MSHC
19.500 M
VCC_BATT
Application Note 7
Intel® PXA27x Processor Family Power Requirements
2.1 Power Domains and System Voltage/Current Requirements
The following sections document the power requirements for the PXA27x processor, but do not
include external support, memory, or other peripheral components.
The power consumption values shown in Tab le 5 are all worst-case numbers. These numbers give
the worst-case system power-supply requirements and do not reflect typical system power
consumption.
2.1.1 Intel® PXA27x Processor Power Supplies
Viewed externally, the processor can require up to nine independent voltages provided by regulated
supplies. In some cases, multiple voltage domains might be strapped together, reducing the number
of separate regulators to as few as four. Internally, there are more domains, but these are powered
from the externally supplied domains by on-chip regulators. The internal domains are documented
for informational purposes only; the external power controller does not have to consider them in its
design.
Tab l e 2 shows the PXA27x processor voltage domains.
8 Application Note
Intel® PXA27x Processor Family Power Requirements
Table 2. Intel® PXA27x Processor Voltage Domains (Sheet 1 of 2)
Voltage Description
VCC_BATT BATTERY VOLTAGE:
Voltage-limited power from the main battery, or directly from a backup battery, at
nominal 3.0 V (±25%). VCC_BATT must be supplied to start the power manager. When
the main battery is installed, VCC_BATT powers the real-time clock and power
management circuitry during initial power-on, sleep, deep sleep and sleep wake-up, so
it remains powered from the backup battery when the main power source has been
discharged or removed. See Section 2.2, “Batteries” on page 14 for information about
directly connecting VCC_BATT to the backup battery or main battery.
NOTE: The power management integrated circuit (PMIC) output drivers for logic
NOTE: VCC_BATT must be driven by a regulator whose output is matched to the
VCC_CORE CORE VOLTAGE:
Dynamically variable core voltage of 0.85 V to 1.55 V. VCC_CORE also powers internal
peripheral logic blocks such as the memory controller, LCD controller, digital audio, and
serial ports. It does not power the internal SRAM. In a full featured system, this supply
is software controllable as described in Section 6.1, “VCC_CORE Regulator and
Dynamic Voltage Management” on page 29. In a simple system, this supply might be a
fixed voltage chosen to meet the minimum voltage requirement for the highest
frequency at which the PXA27x processor operates. In systems that use standby mode,
there must also be a provision to set VCC_CORE to 1.10 V (±10%) prior to entry into
standby mode. VCC_CORE must be enabled when PWR_EN is asserted and disabled
when PWR_EN is de-asserted.
VCC_PLL PHASE-LOCK LOOP VOLTAGE:
1.3 V (±10%) for internal PLL circuits, fixed. VCC_PLL must not be connected to
VCC_CORE, even though they both may be at the same voltage: 1.3 V. A separate
low-noise voltage source is recommended to keep the PLL supply clean. This supply
must be enabled when PWR_EN is asserted and disabled when PWR_EN is
de-asserted.
VCC_SRAM Power for the internal SRAM during operation in run or turbo modes. This supply is
fixed at 1.1 V (±10%). If the core supply (VCC_CORE) is also fixed at 1.1V (no dynamic
voltage changes are used and the maximum core clock frequency is not supported),
these two supplies are connected together and powered by a common regulator. In
sleep and deep-sleep modes, VCC_SRAM is powered down and the internal SRAM
banks, under program control, are powered from an internal regulator connected to
VCC_BATT. Doing so retains their contents although no accesses are allowed.
VCC_SRAM must be enabled when PWR_EN is asserted and disabled when
PWR_EN is de-asserted.
signals nRESET, nVDD_FAULT, nBATT_FAULT, PWR_SDA, GPIO0 and
GPIO1 must be powered from the VCC_BATT supply. This also applies to all
other digital outputs such as the JTAG signals driving PXA27x processor
inputs on the VCC_REG domain. Any devices that have a digital input driven
by a PXA27x processor digital output powered from the VCC_REG domain
must tolerate output high drive levels between 2.25 V and 3.75 V.
VCC_IO regulator so that VCC_IO and VCC_BATT remain within 200 mV of
each other when the VCC_IO regulator is enabled.
Application Note 9
Intel® PXA27x Processor Family Power Requirements
Table 2. Intel® PXA27x Processor Voltage Domains (Sheet 2 of 2)
Voltage Description
VCC_IO Fixed 3.0 V or 3.3 V (±10%) for standard CMOS I/Os interfacing to external
VCC_LCD Power for output drivers to LCD panel, 1.8 V (+20%, -5%), 2.5 V, 3.0V or 3.3 V (± 10%).
VCC_MEM Power for memory/system bus I/O at 1.8 V (+20%, -5%), 2.5 V, 3.0V or 3.3 V (±10%);
VCC_BB Power for I/Os to an external baseband module or device, at 1.8 V (+20%, -5%), 2.5 V,
VCC_USIM Power for I/Os to an external Universal Subscriber Identity Module (USIM) card. The
VCC_USB Power for USB at 3.0 V or 3.3V (±10%) for standard differential USB I/Os interfacing to
components, which are also supplied from fixed 3.0 V or 3.3 V. The I/Os for external
components connected to the corresponding signals on the PXA27x processor must be
supplied from the same regulator. Driving VCC_BATT in this manner prevents forwardbiasing of protection diodes and inadvertent charging of the backup battery through
inputs on the PXA27x processor VCC_REG domain. The VCC_IO supply must be the
highest potential in the system (excluding VCC_BATT and VCC_USB) and must be
sequenced on at the same time or before the other supplies enabled by SYS_EN.
VCC_IO are connected to any of the VCC_LCD, VCC_MEM, VCC_BB or VCC_USIM
supplies as long as none of these supplies are driven at a voltage higher than VCC_IO.
VCC_IO must be enabled when SYS_EN is asserted and disabled when SYS_EN is
de-asserted.
NOTE: When the main battery is installed, VCC_BATT must be driven by a regulator
Optionally, these are strapped to one of the existing I/O supplies at 3.3 V, 2.5 V, or
1.8 V if appropriate for the panel used. This supply must be enabled when SYS_EN is
asserted and disabled when SYS_EN is de-asserted.
fixed, strappable by input signals on the power controller to one of these voltages. The
power controller automatically powers up VCC_MEM to the voltage specified by its
input control signals when this regulator is enabled. Corresponding I/Os of the memory
components or companion chips must be powered from the same regulator. This
supply must be enabled when SYS_EN is asserted and disabled when SYS_EN is
de-asserted.
3.0V,or 3.3 V (±10%). Corresponding I/Os of the baseband device must be powered
from the same regulator. In systems that use PCMCIA or Compact flash and the
baseband interface, VCC_BB must be tied to VCC_MEM because some of the card
interface signals are multiplexed with baseband interface signals. This supply must be
enabled when SYS_EN is asserted and disabled when SYS_EN is de-asserted if any of
these GPIOs are used (as either a GPIO or as an alternate function): GPIO<48>,
GPIO<57:50>, GPIO<85:81>.
VCC_USIM voltage generated by the PMIC is software configurable at settings of 1.8 V
(+20%, -5%) or 3.0 V (± 10%) or disabled (0 V). The software voltage control is
implemented using I
nUVS1, and nUVS2 outputs. Refer to Section 4.7, “Universal Subscriber Identity
Module (USIM)” on page 21 for more information.
external components, which are also supplied from fixed 3.0 V or 3.3 V.
whose output is matched to the VCC_IO regulator so that VCC_IO and
VCC_BATT remain within 200 mV of each other when the VCC_IO regulator is
enabled.
2
C commands or the PMIC decodes the PXA27x processor UVS0,
NOTE: VCC_USB powers the I/O for the USB interfaces, the USB differential signals
NOTE: The +5 V VBUS source from USB host controller, which must be available for
D+. D- is out of compliance with the USB specification if VCC_USB is below
2.8 V.
bus-powered peripherals, must be supplied from an external source, but it is
not part of the PXA27x processor silicon.
2.1.2 Power Supply Configuration in a Minimal System
For minimal systems, only five (four if VCC_USIM is disabled) regulators are required to power
the PXA27x processor and its input/output interfaces, as shown in Tab le 3 .
10 Application Note
Intel® PXA27x Processor Family Power Requirements
Table 3. Regulators Required to Power the Intel® PXA27x Processor
Regulator Description
1
2
3 VCC_USIM at 1.8V and 3.0 V (±10%)
4
5 VCC_PLL at 1.3 V.
Regulated main battery voltage, nominally 3.0 V (limited to a maximum of 3.75 V) to power
VCC_BATT and charge the optional backup battery also connected to VCC_BATT.
VCC_IO, VCC_LCD, VCC_MEM, VCC_BB, VCC_USB connected together (can be powered at
3.0V or 3.3 V (±10%)).
VCC_CORE and VCC_SRAM may be connected together, fixed at 1.1 V. Dynamic voltage
management cannot be used and the maximum core clock frequency is not supported using
this arrangement.
More complex systems might require further separation of supply domains and additional
regulators. Independent PXA27x power domains provide flexibility when supporting peripherals
with different I/O voltages, which makes it possible to reduce overall system power by supporting
1.8 V low-power memory with 3.0 V peripherals.
2.1.3 Modeling Intel PXA27x processor power consumption
This section provides guidelines for the power consumption required for the processor by varying
the software workload. In this analysis, the information is divided into two groups:
- Core (modeled as VCC_CORE) - Section 2.1.3.1
- All other power domains (such as memory controller, LCD, etc.) - Section 2.1.3.2
The core model section contains power consumption data with differing workloads. The model for
the remaining domains shows power consumption data for each domain.
Use the guidelines detailed in Section 2.1.3.1 and Section 2.1.3.2 in conjunction with the Power
Consumption Specifications listed in the Intel® PXA27x Processor Family EMTS.
2.1.3.1 Intel® PXA27x Processor VCC_CORE Supply Current
This section specifies the power consumption expected for VCC_CORE power supply domain
across differing workloads.
Tab le 4 shows the typical current consumption for the VCC_CORE power domain at room
temperature, at nominal voltage levels but with differing workloads. All data is taken using the
Intel PXA270 Processor Development Kit processor card running low level boot code, no
operating system (unless specified).
— Dhrystones 2.1 - Dhrystones workload. Configured to run 20,000,000 cycles with LCD
disabled.
— MPEG4 Decode - Frame rate unlimited, Intel® IPP Performance Suite v4.0 for the Intel
PXA270 processor for Linux, QVGA LCD with frame buffer in SRAM.
— Power Stress Test Code - Low level code executing a repetitive test case of back to back
64bit MAC instructions in an infinite loop. This stress code is written specifically to
exercise the core power domain to yield data at the higher end of usage. It does not
represent a real application.
Application Note 11
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