Intel PXA26X User Manual

Intel® PXA26x Processor Family

Developer’s Manual

March, 2003

Order Number: 278638-002

Contents

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEP T AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WH A TSOEVER, AND INTEL DISC LAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR W ARRANTIES
RELA TING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibilit y whatsoeve r for conf licts or incompatibil ities arisi ng from futu re chang es to them.
The Intel® PXA26x Processor Family may contain desi gn defe cts or errors known as errata which may cause the product to deviat e from published

specifications. Current characteri zed errata are available on requ est.
MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled

platforms may require licenses from various entities, includ ing Intel Corporat ion.
This document and the software described in it are furnished under licen se and may only be use d or copied in accorda nce w ith the terms of the

license. The information in this document is furnished for informational use only, is subject to change without notice, and should not be construed as a
commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this
document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may
be reproduced, stored in a retrieval system, or transm itted in any form or by any means wit hout the express w ritten con sent of Intel Corporation.

Contact your local Intel sales office or your distributor to obtain the latest specifications and befo re placi ng your product order.
Copies of documents which have an ordering number and are referenc ed in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel's website at http://ww w.intel.com.
Copyright © Intel Corporation, 2003
AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, C ableP ort, Celeron , Chips, Co mmer ce Ca rt, CT Con nect, CT Media, Dialogic,

DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, iCat, iCOMP, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740,
IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel
NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel Team Station,
Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer
logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Y our Command, ProShare,
RemoteExpress, Screamline, S hiva, Sm artD ie, Solu tions9 60, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In,
TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trade marks of Intel Corp orati on or its subsidiaries in the United States and
other countries.

*Other names and brands may be claimed as the property of others.

ii Intel® PX A26x P r oces sor Fa mil y Dev elope r’s M anual

Contents

Contents

1 Introduction...................................................................................................................................1-1

1.1 Intel® XScale™ Core Features ..................... .... .......................... ........................... ...........1-1

1.2 System Integrati on Feat ur es................................. ........................... ..................................1-2

1.2.1 Memory Control ler...................... ... ........................... .......................... ..................1-2

1.2.2 Clocks and Power Controllers...............................................................................1 -2

1.2.3 Universal Serial Bus (USB) Client.........................................................................1-3

1.2.4 Direct Memory Access Controller (DMAC)...........................................................1-3

1.2.5 Liquid Crystal Display (LCD) Controller................................................................1-3

1.2.6 AC97 Controller....................................................................................................1-3

1.2.7 Inter-Integrated Circuit Sound (I2S) Controller.....................................................1-3

1.2.8 Multimedia Card (MMC) Controller.......................................................................1 -4

1.2.9 Fast Infrared (FIR) Communication Port...............................................................1-4

1.2.10 Synchronous Serial Protocol Controller (SSPC)...................................................1 -4

1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit....................................................1-4

1.2.12 General Purpose Input/Output (GPIO) .................................................................1-4

1.2.13 Universal Asynchronous Receiver/Transmitters (UARTs)....................................1-4

1.2.14 Real-Time Clock (RTC).........................................................................................1-5

1.2.15 Operating System (OS) Timers.............................................................................1-5

1.2.16 Pulse-Width Modulator (PWM).............................................................................1-5

1.2.17 Interrupt Controller................................................................................................1-5

1.2.18 Integrated Synch ro n ous Flash................. ........................... .......................... ........1-5

1.2.19 Single-ended Universal Seria l Bus Client interface ..............................................1-5

1.2.20 Network Synchronous Serial Protocol Port...........................................................1-6

1.2.21 Audio Synchronou s Seri al Proto co l Port......... ... ........................... ........................1-6

1.2.22 Hardware UART (HWUART)................................................................................1-6

2 System Architecture........................................... .......................... ........................... .....................2-1

2.1 Overview............................................................................................................................2-1

2.2 Package Types..................................................................................................................2-2

2.3 Intel® XScale™ Microa rc hit ec tur e Implemen tat i on Opti o ns............... ... ............................2-3

2.3.1 CPU Core Fault Registe r — PSFS Bit............................................. .....................2-3

2.3.2 Coprocessor 14 Registers 0-3 – Performance Monitoring....................................2-3

2.3.3 Coprocessor 14 Register 6 and 7– Clo ck and Power Management.....................2-4

2.3.4 Coprocessor 15 Register 0 – ID Register Definition.............................................2-4

2.3.5 Coprocessor 15 Register 1 – P-Bit.......................................................................2-5

2.4 Input/Output Ordering........................................................................................................2-5

2.5 Semaphores......................................................................................................................2-6

2.6 Interrupts............................................................................................................................2-6

2.7 Reset .................................................................................................................................2-7

2.8 Internal Registe rs....... .......................... ........................... ...................................................2-7

2.9 Selecting Peripherals vs. General Purpose Input/Output..................................................2-8

2.10 Power on Reset and Boot Operati o n............. .............. ... ........................... ........................2-8

2.11 Power Management...........................................................................................................2-8

2.12 Pin List...............................................................................................................................2-9

2.13 Register Address Summary.............. ........................... .......................... ..........................2-21

2.14 Memory Map....................................................................................................................2-33

Intel® PXA26x Processo r Family Develop er’s Manual iii

Contents

3 Clocks and Power Manager.............. .......................... ........................... ......................................3-1

3.1 Clock Manager Introduction...............................................................................................3-1

3.2 Power Manager Introduction..............................................................................................3-2

3.3 Clock Manager...................................................................................................................3-2

3.3.1 32.768-KHz Oscillator...........................................................................................3-4

3.3.2 3.6864-MHz Oscillator................... .......................................................................3-4

3.3.3 Core Phase Locked Loop.....................................................................................3-4

3.3.4 95.85-MHz Peripheral Phase Locked Loop..........................................................3-5

3.3.5 147.46-MHz Pe ripheral Phase Locked Loop........................................................3-6

3.3.6 Clock Gating.........................................................................................................3-6

3.4 Resets and Power Modes..................................................................................................3-6

3.4.1 Hardware Reset....................................................................................................3-7

3.4.2 Watchdog Reset...................................................................................................3-7

3.4.3 GPIO Reset............................ ... ........................... ................................................3-8

3.4.4 Run Mode........... ... ........................... ........................... .........................................3-9

3.4.5 Turbo Mode..........................................................................................................3-9

3.4.6 Idle Mode............ ........................................ ........................... .......................... ...3-10

3.4.7 33-MHz Idle Mode............................ ... ........................... ........................... .........3-12

3.4.8 Frequency Change Sequence............................................................................3-13

3.4.9 Sleep Mode.........................................................................................................3 -15

3.4.10 Power Mode Summary.......................................................................................3-20

3.5 Power Manager Registers...............................................................................................3-22

3.5.1 Power Manager Control Register (PMCR).........................................................3-23

3.5.2 Power Manager General Configuration Register (PCFR)...................................3-24

3.5.3 Power Manager Wake-Up Enable Register (PWER)..........................................3-25

3.5.4 Power Manager Rising-Edge Detect Enable Register (PRER) ..........................3-26

3.5.5 Power Manager Falling-Edge Detect Enable Register (PFER)..........................3-27

3.5.6 Power Manager GPIO Edge Detect Status Register (PEDR).............................3 -28

3.5.7 Power Manager Sleep Status Register (PSSR) .................................................3 -29

3.5.8 Power Manager Scratch Pad Register (PSPR)..................................................3-30

3.5.9 Power Manager Fast Sleep Wake Up Configurat i on Register (PM F WR).... .......3-31

3.5.10 P ower Manage r GP IO Sleep State Registers (PGSR0, PGSR1, PGSR2).. .. . .. ..3-31

3.5.11 Reset Controller Status Register (RCSR)...........................................................3-33

3.5.12 Power Manager Register Locations....................................................................3-34

3.6 Clocks Manager Registers......... ............. .... .......................... ........................... ................3-35

3.6.1 Core Clock Configuration Register (CCCR) .......................................................3-35

3.6.2 Clock Enable Register (CKEN).................................................................. ... ......3-37

3.6.3 Oscillator Configura tio n Registe r (OSCC)................... .......................... .............3-39

3.6.4 Clocks Manager Register Locations...................................................................3-39

3.7 Coprocessor 14: Clock and Power Management............................................................3-40

3.7.1 Core Clock Configuration Register (CCLKCFG).................................................3 -40

3.7.2 Power Mode Register (PWRMODE)...................................................................3-41

3.8 External Hardwa r e Considerations......... ........................... ..............................................3-41

3.8.1 Power-On-Reset Considerations........................................................................3-41

3.8.2 Driving the Cr ystal Pins from an External Clock Sour ce.... .... .............................3-41

3.8.3 Noise Coupling Between Driven Crystal Pin s and a Crystal Oscillator...............3 -42

4 System Integration Unit................................................................................................................4-1

4.1 General-Purpose Input/Output...........................................................................................4-1

4.1.1 GPIO Operation............................................. .......................................................4-1

iv Intel® PXA26x Processor Family Developer’s Manual

4.1.2 GPIO Alternate Functions.....................................................................................4-3

4.1.3 GPIO Register Definitions.....................................................................................4-7

4.1.4 GPIO Register Locations....................................................................................4-21

4.2 Interrupt Contro l ler............... ... ........................... ..............................................................4-22

4.2.1 Interrupt Controller Operation.............................................................................4-23

4.2.2 Interrupt Con tr olle r Re gis te r De fi n iti o ns.......... ... .................................................4-24

4.2.3 Interrupt Con tr olle r Re gis te r Lo ca tio ns........... .................................... .... ............4-31

4.3 Real-Time Clock (RTC) ...................................................................................................4-32

4.3.1 Real-Time Clock Operation.................................................................................4-32

4.3.2 Real-Time Clock Register Definitions.................................................................4-32

4.3.3 Trim Procedure...................................................................................................4-35

4.3.4 Real-Time Clock Register Locations...................................................................4-38

4.4 Operating System Timer.......................................... ........................... ........................... ..4-38

4.4.1 Watchdog Timer Operation............... .... .......................... ........................... .........4-38

4.4.2 Operating System Timer Register Definitions.....................................................4-39

4.4.3 Operating System Timer Register Locations......................................................4-42

4.5 Pulse Width Modulator.....................................................................................................4-43

4.5.1 Pulse Width Modulator Operation.......................................................................4-43

4.5.2 Register Descriptions..........................................................................................4-44

4.5.3 Pulse Width Modulator Output Wave Example...................................................4-47

4.5.4 Register Summary..............................................................................................4-48

Contents

5 Direct Memory Access Controller.................................................................................................5-1

5.1 Direct Memory Access Description....................................................................................5-1

5.1.1 Direct Memory Access Controller Channels.........................................................5-2

5.1.2 Signal Descriptions................................................................ ... ........................... .5-3

5.1.3 Direct Memory Access Channel Priority Scheme.................................................5-4

5.1.4 Direct Memory Access Descriptors.......................................................................5-6

5.1.5 Channel States.....................................................................................................5-9

5.1.6 Read and Write Order...........................................................................................5-9

5.1.7 Byte Transfer Order............................................................................................5-10

5.1.8 Trailing Bytes......................................................................................................5-11

5.2 Transferring Data.............................................................................................................5-11

5.2.1 Servicing Internal Peripherals.............................................................................5-12

5.2.2 Quick Reference for Direct Memory Access Programming ................................5-13

5.2.3 Servicing Companion Chips a nd External Peripherals.......................................5-14

5.2.4 Memory-to-Mem ory Mov es................... ............. ... ........................... ...................5-16

5.3 Direct Memory Access Controller Registers....................................................................5-17

5.3.1 DMA Interrupt Register.......................................................................................5-17

5.3.2 DMA Channel Control/Status Register...............................................................5-17

5.3.3 DMA Request to Channel Map Registers ...........................................................5-19

5.3.4 DMA Descriptor Address Registers....................................................................5-20

5.3.5 DMA Source Address Registers.........................................................................5-21

5.3.6 DMA Target Address Registers..........................................................................5-22

5.3.7 DMA Command Registers..................................................................................5-23

5.4 Examples.........................................................................................................................5-25

5.5 Direct Memory Access Controller Registers Locations....................................................5-28

6 Memory Controller........................................................................................................................6-1

6.1 Overview............................................................................................................................6-1

Intel® PXA26x Processo r Family Develop er’s Manual v

Contents

6.2 Functional Description.......................................................................................................6-2

6.2.1 SDRAM Interface Overview..................................................................................6-2

6.2.2 Static Memory Inter fac e / Variab le Late nc y I/O Interf ac e................... ..................6-3

6.2.3 16-Bit PC Card / Compact Flash Interface...........................................................6-4

6.3 Memory System Example s............................... .... .......................... ........................... ........6-4

6.4 Memory Accesses...................................... .......................................................................6-6

6.4.1 Reads and Writes................... ........................... ...................................................6-7

6.4.2 Aborts and Nonexistent Memory .............................................. ........................... .6-7

6.5 Memory Configu rati o n Regis te rs................ .................................... .... .......................... .....6-8

6.6 Synchronous DRAM Memory Interface.............................................................................6-9

6.6.1 SDRAM MDCNFG Register..................................................................................6-9

6.6.2 SDRAM Mode Register Set Configuration Register...........................................6-12

6.6.3 SDRAM MDREFR Register................................................................................6-14

6.6.4 SDRAM Memory Options ...................................................................................6-17

6.6.5 SDRAM Command Overview.............................................................................6-25

6.6.6 SDRAM Waveforms............................................................................................6-27

6.7 Synchronous Static Memory Interface.............................................................................6-30

6.7.1 Synchronous Static Memory Configuration Register..........................................6-30

6.7.2 Sy nchronous Static Memory Mode Register Set Configuratio n Register ...........6 -36

6.7.3 Synchronous Static Memory Timing Diagrams...................................................6-37

6.7.4 Non-SDRAM Timing SXMEM Operation............................................................6-38

6.8 Asynchronous Static Memory..........................................................................................6-41

6.8.1 Static Memory Inter fac e............. ........................................ ........................... ......6-41

6.8.2 Asynchronous Static Memory Control Registers (MSC0 – 2).............................6 -44

6.8.3 ROM Interface ....................................................................................................6-48

6.8.4 SRAM Interface Overv i ew................ ........................... .......................... .............6-51

6.8.5 Variable Latency I/O (VLIO) Interface Overview.................................................6 -53

6.8.6 FLASH Memory Interface...................................................................................6-56

6.9 16-Bit PC Card/Compact Flash Interface........................................................................6-57

6.9.1 Expansion Memory Timing Configuration Register ............................................6-58

6.9.2 Expansion Memory Configuration Register (MECR)..........................................6 -61

6.9.3 16-Bit PC Card Overview....................................................................................6-61

6.9.4 External Logic for 16-Bit PC Card Implementation .............................................6-64

6.9.5 Expansion Card Interface Timing Diagrams and Parameters............................6-67

6.10 Companion Chip Inter fa ce................... ... ........................... ........................... ...................6-68

6.10.1 Alternate Bus Master Mode................................................................................6-70

6.11 Options and Settings for Boot Memory............................................................................6-72

6.11.1 Alternate Booting................................................................................................6-72

6.11.2 Boot Time Defaults................. ... ........................... ........................... ...................6-72

6.11.3 Memory Interface Reset and Initialization...........................................................6-75

6.12 Hardware, Watchdog, or Sleep Reset Operation............................................................6 -76

6.13 General Purpose Input/Output Reset Procedure.............................................................6-78

7 Liquid Crystal Display Controller..................................................................................................7-1

7.1 Overview............................................................................................................................7-1

7.1.1 Features................................................................................................................7-2

7.1.2 Pin Descriptions....................................................................................................7-4

7.2 Liquid Crystal Display Controller Operation.......................................................................7-4

7.2.1 Enabling the Controller.........................................................................................7-4

7.2.2 Disabling the Controller........................................................................................7-5

vi Intel® PXA26x Processor Family Developer’s Manual

7.2.3 Resetting the Controller........................................................................................7-5

7.3 Detailed Module Descriptions............................................................................................7-5

7.3.1 Input FIFOs...........................................................................................................7-6

7.3.2 Lookup Palette......................................................................................................7-6

7.3.3 Temporal Modulate d Ener gy Distr i buti o n (TMED ) Dith e rin g.. ... ........................... .7-6

7.3.4 Output FIFOs................ .............. ... ........................... .......................... ..................7-9

7.3.5 Liquid Crystal Display Controller Pin Usage.........................................................7-9

7.3.6 Direct Memory Access........................................................................................7-10

7.4 Liquid Crystal Display External Palet te and Frame Bu ffe rs............. ................................7-11

7.4.1 External-Palette Buffer........................................................................................7-11

7.4.2 External-Frame Buffer ........................................................................................7-12

7.5 Functional Timing................... ........................... .......................... ....................................7-15

7.6 Liquid Crystal Di sp la y Regi ster Descriptions........... .... ....................................................7-19

7.6.1 LCD Controller Control Register 0 (LCCR0) .......................................................7-20

7.6.2 LCD Controller Control Register 1 (LCCR1) .......................................................7-28

7.6.3 LCD Controller Control Register 2 (LCCR2) .......................................................7-30

7.6.4 LCD Controller Control Register 3 (LCCR3) .......................................................7-33

7.6.5 LCD Controller DMA...........................................................................................7-37

7.6.6 LCD DMA Frame Branch Registers (FBRx).......................................................7-41

7.6.7 LCD Controller Status Register (LCSR)..............................................................7-42

7.6.8 LCD Controlle r In te rrup t ID Re gis ter (L IID R)................................................ .... ..7-46

7.6.9 TMED RGB Seed Register.................................................................................7-46

7.6.10 TMED Control Register (TCR)............................................................................7-47

7.6.11 LCD Controller Re gis te r Summary..................................... .......................... ......7-49

Contents

8 Synchronous Seri al Port Co nt ro ll er.................... ... .......................................................................8-1

8.1 Overview............................................................................................................................8-1

8.2 Signal Description..............................................................................................................8-1

8.2.1 External Interface to Synchronous Serial Peripherals..........................................8-1

8.3 Functional Descr ip ti o n...................... ..................................... ... ........................... ..............8-2

8.3.1 Data Transfer........................................................................................................8-2

8.4 Data Formats.....................................................................................................................8 -2

8.4.1 Serial Data Formats for Transfer to/from Peripherals...........................................8-2

8.4.2 Parallel Data Formats for FIFO Storage...............................................................8-6

8.5 FIFO Operation and Data Transfers..................................................................................8-6

8.5.1 Using Programmed I/O Data Tran sfers.............................................. ..................8-7

8.5.2 Using DMA Data Transfers................... .......................... ........................... ...........8-7

8.6 Baud Rate Generation.......................................................................................................8-7

8.7 SSP Serial Port Registers..................................................................................................8-7

8.7.1 SSP Control Register 0 (SSCR0).........................................................................8-8

8.7.2 SSP Control Register 1 (SSCR1).......................................................................8-11

8.7.3 SSP Data Register (SSDR)................................................................................8-15

8.7.4 SSP Status Register (SSSR)..............................................................................8-16

8.7.5 SSP Register Address Map................................................................................8-19

9 Inter-Integrated Circuit Bus Interface Unit....................................................................................9-1

9.1 Overview............................................................................................................................9-1

9.2 Signal Description..............................................................................................................9-1

9.3 Functional Descr ip ti o n...................... ..................................... ... ........................... ..............9-1

9.3.1 Operational Blocks................................................................................................9-3

Intel® PXA26x Processo r Family Develop er’s Manual vii

Contents

9.3.2 Inter-Integrated Circuit Bus Interface Modes.......................................................9-3

9.3.3 Start and Stop Bus States....................................................................................9-4

9.4 Inter-Integ ra te d Cir cu it Bus Ope rati o n........ .......................... .............................................9-6

9.4.1 Serial Clock Line (SCL) Generation......................................................................9-7

9.4.2 Data and Addressing Management......................................................................9-7

9.4.3 Inter-Integrated Circuit Acknowledge....................................................................9-8

9.4.4 Arbitration .............................................................................................................9-9

9.4.5 Master Operations..............................................................................................9-11

9.4.6 Slave Operatio ns................. .......................... ........................... ..........................9-15

9.4.7 General Call Address..........................................................................................9-16

9.5 Slave Mode Programming Examples..............................................................................9 -18

9.5.1 Initialize Unit.......................................................................................................9-18

9.5.2 Write n Bytes as a Slave.....................................................................................9-18

9.5.3 Read n Bytes as a Slave....................................................................................9-19

9.6 Master Programming Examples......................................................................................9-19

9.6.1 Initialize Unit.......................................................................................................9-19

9.6.2 Write 1 Byte as a Master....................................................................................9-19

9.6.3 Read 1 Byte as a Master....................................................................................9-20

9.6.4 Write 2 Bytes and Repeated Start Read 1 Byte as a Master..............................9 -20

9.6.5 Read 2 Bytes as a Master - Send STOP Using the Abort..................................9-21

9.7 Glitch Suppressio n Logi c........ .......................... ........................... ....................................9-22

9.8 Reset Conditions.............................................................................................................9-22

9.9 Register Definitions..........................................................................................................9-22

9.9.1 I2C Bus Monitor Registe r- IBMR................ ........................................ ................9-22

9.9.2 I2C Data Buffer Register- IDBR..........................................................................9-23

9.9.3 I2C Control Register- ICR...................................................................................9-24

9.9.4 I2C Status Register.............................................................................................9-26

9.9.5 I2C Slave Address Register- ISAR.....................................................................9-28

10 Universal Asynchronous Receiver/Transmitter ..........................................................................10-1

10.1 Feature List............ ... ........................... ........................... .......................... .......................10-1

10.2 Overview..........................................................................................................................10-2

10.2.1 Full Function UART................ ............. .... .......................... ........................... ......10-2

10.2.2 Bluetooth UART..................................................................................................1 0-2

10.2.3 Standard UART ..................................................................................................10-2

10.2.4 Compatibility with 16550.....................................................................................10-2

10.3 Signal Descrip ti o ns.................... ... ........................... ........................................................10-3

10.4 UART Operational Description ........................................................................................10-4

10.4.1 Reset..................................................................................................................10-5

10.4.2 Internal Register Descript ion s.... ........................... ..............................................10-5

10.4.3 FIFO Interrupt Mod e Opera ti o n............................ ... ........................... ..............10-21

10.4.4 FIFO Polled Mode Operation............................................................................10-22

10.4.5 DMA Requests. ... ..............................................................................................10-22

10.4.6 Slow Infrared Asy nc hron o us Inte rfa ce........... .... .......................... .....................10-23

10.5 Register Summary.........................................................................................................10-26

10.5.1 UART Register Differences ..............................................................................10-27

11 Fast Infrared Communication Port..............................................................................................11-1

11.1 Signal Descrip ti o n............ ... .............................................................................................11-1

11.2 Fast Infrared Communic at i ons Por t Operat i on............... ... ........................... ...................11-1

viii Intel® PXA26x Processor Family Developer’s Manual

11.2.1 Four-Positio n Puls e Modula tio n.................. ........................................ ................11-2

11.2.2 Frame Format.....................................................................................................11-3

11.2.3 Address Field......................................................................................................11-4

11.2.4 Control Field................. .... .......................... ........................... .............................11-4

11.2.5 Data Field ...........................................................................................................11-4

11.2.6 CRC Field...........................................................................................................11-4

11.2.7 Baud Rate Generation............ ........................... .................................................11-5

11.2.8 Receive Operatio n........................................................................................ ......11-5

11.2.9 Transmit Operation.............................................................................................11-6

11.2.10 Transmit and Receive FIFOs..............................................................................11-7

11.2.11 Trailing or Error Bytes in the Receive FIFO........................................................11-7

11.3 Fast Infrared Communications Port Register Descriptions..............................................11-8

11.3.1 FICP Control Regis te r 0..................................... ........................... ......................11-8

11.3.2 FICP Control Regis te r 1..................................... ........................... ....................11-10

11.3.3 FICP Control Regis te r 2..................................... ........................... ....................11-11

11.3.4 FICP Data Register...........................................................................................11-12

11.3.5 FICP Status Register 0.....................................................................................11-13

11.3.6 FICP Status Register 1.....................................................................................11-14

11.4 Fast Infrared Communications Port Register Locations................................................11-16

Contents

12 Universal Serial Bus Device Controller.......................................................................................12-1

12.1 Universal Serial Bus Overview ........................................................................................12-1

12.2 Device Configuration .......................................................................................................12-2

12.3 Universal Serial Bus Protocol..........................................................................................12-3

12.3.1 Signalling Levels.................................................................................................12-3

12.3.2 Bit Encoding........................................................................................................12-4

12.3.3 Field Formats.................... ... ............................................................... ................12-4

12.3.4 Packet Formats...................................................................................................12-5

12.3.5 Transaction Formats...........................................................................................12-7

12.3.6 UDC Device Requests ........................................................................................12-8

12.3.7 Configuration ....................................................................................................12-10

12.4 UDC Hardware Connection...........................................................................................1 2-10

12.4.1 Self-Powered De vice ............................... ........................... ..............................12-10

12.4.2 Bus-Powered De vic es................... .................................................. ... ..............12-12

12.5 UDC Operation.............................................................................................................. 12-12

12.5.1 Case 1: EP0 Control Read ............................................. ..................................12-12

12.5.2 Case 2: EP0 Control Read with a Premature Status Stage..............................12-13

12.5.3 Case 3: EP0 Control Write With or Without a Premature Status Stage............12-14

12.5.4 Case 4: EP0 No Data Command......................................................................12-15

12.5.5 Case 5: EP1 Data Transmit (BULK-IN)....... ........................... ...........................12-15

12.5.6 Case 6: EP2 Data Receive (BULK-OUT)..........................................................12-16

12.5.7 Case 7: EP3 Data Transmit (ISOCHR ON OUS-IN)............................. .... ..........12-17

12.5.8 Case 8: EP4 Data Receive (ISOCHRONOUS-OUT)........................................12-18

12.5.9 Case 9: EP5 Data Transmit (INTERRUPT-IN)............... .............. ... .................12-20

12.5.10 Case 10: RESET Interrupt................................................................................12-20

12.5.11 Case 11: SUSPEND Interrupt...........................................................................12-21

12.5.12 Case 12: RESUME Interrupt.............................................................................12-21

12.6 UDC Register Descriptions............................................................................................12-21

12.6.1 UDC Control Register.......................................................................................1 2-22

12.6.2 UDC Endpoint 0 Contro l/Sta tu s Re gis te r (UD CCS 0).......................... ..............12-24

Intel® PXA26x Processo r Family Develop er’s Manual ix

Contents

12.6.3 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 1, 6, or 11....12-26

12.6.4 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 2, 7, or 12....12-28

12.6.5 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 3, 8, or 13....12-31

12.6.6 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 4, 9, or 14....12-33

12.6.7 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 5, 10, or 15..12-35

12.6.8 UDC Interrupt Control Register 0 (UICR0).......................................................12-37

12.6.9 UDC Interrupt Control Register 1 (UICR1).......................................................12-38

12.6.10 U DC Status/Interrupt Register 0 (USIR0).........................................................12-40

12.6.11 U DC Status/Interrupt Register 1 (USIR1).........................................................12-41

12.6.12 U DC Frame Number High Register (UFNHR)..................................................12-43

12.6.13 U DC Frame Number Low Register (UFNLR)...................................................12-45

12.6.14 UDC Byte Count Register x (UBCRx), Where x is 2, 4, 7, 9, 12, or 14............12-45

12.6.15 UDC Endpoint 0 Data Register (UDDR0).........................................................12-46

12.6.16 UDC Data Register x (UDDRx), Where x is 1, 6, or 11 ....................................12-47

12.6.17 UDC Data Register x (UDDRx), Where x is 2, 7, or 12 ....................................12-48

12.6.18 UDC Data Register x (UDDRx), Where x is 3, 8, or 13 ....................................12-48

12.6.19 UDC Data Register x (UDDRx), Where x is 4, 9, or 14 ....................................12-49

12.6.20 UDC Data Register x (UDDRx), Where x is 5, 10, or 15 ..................................12-49

12.6.21 U DC Register Locations...................................................................................12-50

13 AC97 Controller Unit...................................................................................................................1 3-1

13.1 Overview..........................................................................................................................13-1

13.2 Feature List............ ... ........................... ........................... .......................... .......................13-1

13.3 Signal Descrip ti o n............ ... .............................................................................................13-2

13.3.1 Signal Configuration Steps.................................................................................13-2

13.3.2 Example AC-lin k ................................................................................................. 1 3-2

13.4 AC-link Digital Serial Interface Protocol...........................................................................13-3

13.4.1 AC-link Audio Output Frame (SDATA_OUT)......................................................13-4

13.4.2 AC-link Audio Input Frame (SDATA_IN).............................................................13-8

13.5 AC-link Low Power Mode........................................ ......................................................13-12

13.5.1 Powering Down the AC-l in k............................... ... ........................... .................13-12

13.5.2 Waking up th e AC-link......................................................................................13-13

13.6 ACUNIT Operation.........................................................................................................13-14

13.6.1 Initialization.......................................................................................................13-15

13.6.2 Trailing bytes....................................................................................................13-16

13.6.3 Operational Flow for Accessing Codec Registers............................................ 13-16

13.7 Clocks and Sampling Fre que nc ies.......................... ... ........................... ........................13-16

13.8 Functional Description...................................................................................................13-17

13.8.1 FIFOs................................................................................................................13-17

13.8.2 Interrupts...........................................................................................................13-18

13.8.3 Registers...........................................................................................................13-18

14 Inter-Integrated Circuit Sound Controller....................................................................................14-1

14.1 Overview..........................................................................................................................14-1

14.2 Signal Descrip ti o ns.................... ... ........................... ........................................................14-2

14.3 Controller Operation........................................................................................................14-3

14.3.1 Initialization.........................................................................................................14-3

14.3.2 Disabling and Enabling Audio Replay.................................................................14-4

14.3.3 Disabling and Enabling Audio Record................................................................14-4

14.3.4 Transmit FIFO Errors..........................................................................................14-5

x Intel® PXA26x Processor Family Developer’s Manual

Contents

14.3.5 Receive FIFO Errors................... ... ............................................................... ......14-5

14.3.6 Trailing Bytes......................................................................................................14-5

14.4 Serial Audio Clocks and Sampling Frequencies..............................................................14-5

14.5 Data Formats...................................................................................................................14-6

14.5.1 FIFO and Memory Format..................................................................................14-6

14.5.2 I2S and MSB-Justified Serial Audi o Format s................................... ...................14-6

2

14.6 I

S Controller Register Descriptions................................................................................14-7

14.6.1 Serial Audio Controller Global Control Register (SACR0)..................................14-8

14.6.2 Serial Audio Contro ll e r I2S/MSB-Justified Contr ol Re gis te r (SAC R1 )..............14-10

14.6.3 Serial Audio Controller I2S/MSB-Justified Status Register (SASR0)................14-11

14.6.4 Serial Audio Clock Divider Register (SADIV)....................................................14-13

14.6.5 Serial Audio Interrupt Clear Register (SAICR)..................................................1 4-13

14.6.6 Serial Audio Interrupt Mask Register (SAIMR) .................................................14-14

14.6.7 Serial Audio Data Register (SADR)..................................................................14-14

14.6.8 Controller: Register Memory Map.....................................................................14-15

14.7 Interrupts........................................................................................................................14-16

15 MultiMediaCard Controller..........................................................................................................15-1

15.1 Overview..........................................................................................................................15-1

15.2 MultiMediaCa rd Con tr olle r Fun ct i onal De scription ................... ... ........................... .........15-4

15.2.1 Signal Descrip ti o n................... .... ........................................................................15-4

15.2.2 MultiMediaCard Controller Reset.......... ... ...........................................................15-5

15.2.3 Card Initializa tion Sequence.................... ........................... .......................... ......15-5

15.2.4 MMC and SPI Modes ..........................................................................................15-5

15.2.5 Error Detection....................................................................................................15-7

15.2.6 Interrupts.............................................................................................................15-7

15.2.7 Clock Control ......................................................................................................15-7

15.2.8 Data FIFOs.........................................................................................................15-8

15.3 Card Communication Protocol.......................................................................................15-11

15.3.1 Basic, No Data, Command and Response Sequence......................................15-11

15.3.2 Data Transfer....................................................................................................15-12

15.3.3 Busy Sequence.................................................................................................15-15

15.3.4 SPI Functionality...............................................................................................15-15

15.4 MultiMediaCard Controller Operation............................................................................15-15

15.4.1 Start and Stop Clock................... ... ........................... .......................... ..............15-16

15.4.2 Initialize.............................................................................................................15-16

15.4.3 Enabling SPI Mode...........................................................................................15-16

15.4.4 No Data Command and Response Sequence..................................................15-16

15.4.5 Erase ................................................................................................................15-17

15.4.6 Single Data Block Wri te.............. ............. ... ........................... ...........................15-17

15.4.7 Single Block Read ................................ .......................... ........................... .......15-18

15.4.8 Multiple Block Write..........................................................................................15-18

15.4.9 Multiple Block Read..........................................................................................15-19

15.4.10 Stream Write................. ........................................ ........................... .................15-19

15.4.11 Stream Read....... .... .......................... ........................... ........................... ..........15-20

15.5 MultiMediaCa rd Con tr oller Register Descri p tions..........................................................15-21

15.5.1 MMC_STRPCL Register...................................................................................15-21

15.5.2 MMC_STAT Register................................................ ........................................15-22

15.5.3 MMC_CLKRT Register.....................................................................................15-23

15.5.4 MMC_SPI Register...........................................................................................15-24

Intel® PXA26x Processo r Family Develop er’s Manual xi

Contents

15.5.5 MMC_CMDAT Register........................................... .........................................15-25

15.5.6 MMC_RESTO Register ....................................................................................15-26

15.5.7 MMC_RDTO Register.......................................................................................15-27

15.5.8 MMC_BLKLEN Register...................................................................................15-28

15.5.9 MMC_NOB Register.........................................................................................15-28

15.5.10 MMC_PRTBUF Register ..................................................................................15-28

15.5.11 MMC_I_MASK Register....................................................................................15-29

15.5.12 MMC_I_REG Register......................................................................................15-30

15.5.13 MMC_CMD Register.......................................... .......................... .....................15-31

15.5.14 MMC_ARGH Register ......... ... ........................... .................................... .... .......15-34

15.5.15 MMC_ARGL Register.................................................................. .... .................15-34

15.5.16 MMC_RES FIFO (read only) ............... ........................... ........................... .......15-35

15.5.17 MMC_RXFIFO FIFO (read only)....................................................................... 15-35

15.5.18 MMC_TXFIFO FIFO ................................ .......................... ........................... ....15-35

16 Network/Audio Synchronous Serial Protocol Serial Ports..........................................................16-1

16.1 Overview..........................................................................................................................16-1

16.2 Features...........................................................................................................................16-1

16.3 Signal Descrip ti o n............ ... .............................................................................................16-2

16.4 Operation .........................................................................................................................16-2

16.4.1 Processor and DMA FIFO Access......................................................................16-3

16.4.2 Trailing Bytes in the Receive FIFO .....................................................................16-3

16.4.3 Data Formats......................................................................................................16-4

16.4.4 Hi-Z on SSPTXD...............................................................................................16-13

16.4.5 FIFO Operation............. ........................... .......................... ...............................16-17

16.4.6 Baud-Rate Generation......................................................................................16-17

16.5 SSP Port Register Descriptions.....................................................................................16-18

16.5.1 SSP Control Register 0 (SSCR0)..................................................................... 16-18

16.5.2 SSP Control Register 1 (SSCR1)..................................................................... 16-21

16.5.3 SSP Programmable Serial Protocol Register (SSPSP) ....................................16-27

16.5.4 SSP Time Out Register (SSTO).......................................................................16-28

16.5.5 SSP Interrupt Test Register (SSITR)................................................................16-29

16.5.6 SSP Status Register (SSSR)............................................................................16-30

16.5.7 SSP Data Register (SSDR)..............................................................................16-34

16.6 Register Summary.........................................................................................................16-34

17 Hardware UART.........................................................................................................................17-1

17.1 Overview..........................................................................................................................17-1

17.2 Features...........................................................................................................................17-2

17.3 Signal Descrip ti o ns.................... ... ........................... ........................................................17-3

17.4 Operation .........................................................................................................................17-3

17.4.1 Reset..................................................................................................................17-5

17.4.2 FIFO Operation............. ........................... .......................... .................................17-5

17.4.3 Autoflow Control .................................................................................................1 7-7

17.4.4 Auto-Baud-R at e Dete cti o n............. .....................................................................17-8

17.4.5 Slow Infrared Asy nc hron o us Inte rfa ce........... .... .......................... .......................17-8

17.5 Hardware UART Register Descriptions.........................................................................17-10

17.5.1 Receive Buffer Register (RBR).........................................................................17-10

17.5.2 Transmit Holding Register (THR).....................................................................17-11

17.5.3 Divisor Latch Registers (DLL and DLH)............................................................17-11

xii Intel® PXA26x Processor Family Devel oper’s Manual

Contents

17.5.4 Interrupt Enable Register (IER) ........................................................................17-13

17.5.5 Interrupt Ide nti fi ca tio n Re gis te r (II R).................. ... ........................... .................17-14

17.5.6 FIFO Control Regis te r (FCR)................... ........................... ..............................17-17

17.5.7 Receive FIFO Occupa ncy Reg ister (FOR).................. ... ..................................17-18

17.5.8 Auto-Baud Control Register (ABR)...................................................................17-19

17.5.9 Auto-Baud Count Re gis ter (AC R)................... ... ..................................... ... .......17-20

17.5.10 Line Control Register (LCR)..............................................................................17-21

17.5.11 Line Status Register (LSR)...............................................................................17-23

17.5.12 Modem Control Register (MCR).............. ... ........................... ...........................17-26

17.5.13 Modem Status Register (MSR).........................................................................17-28

17.5.14 Scratchpad Register (SPR) ..............................................................................17-29

17.5.15 Infrared Selection Register (ISR)......................................................................17-30

17.6 Hardware UART Regis ter Summary............................ ... ...............................................17-31

18 Internal Flash................. ... ........................... ........................... .......................... ..........................18-1

18.1 Initialization......................................................................................................................18-1

18.1.1 Intel StrataFlash® Memory Reset Configuration................................................18-1

18.1.2 BOOT_SEL[2:0] Configuration ...........................................................................18-2

18.1.3 Determining the Size and Confi g ura ti o n of Flash Usin g Softw ar e.................... ..18-2

18.1.4 SXCNFG Configuration ......................................................................................18-2

18.1.5 Configuring the Int el Str ataF la sh ® Memory.................................. ............. ... ......18-3

18.2 Additional Intel StrataFlash® Memory Information..........................................................18-6

Figures

2-1 Block Diagram ...........................................................................................................................2-2

2-2 Memory Map (Part One) — From 0x8000 0000 to 0xFFFF FFFF ...........................................2-34

2-3 Memory Map (Part Two) — From 0x0000 0000 to 0x7FFF FFFF...........................................2-35

3-1 Clocks Manager Block Di agr am............... ........................................ .........................................3-3

4-1 General-Purpose I/O Block Diagram.........................................................................................4-2

4-2 Interrupt Con tr olle r Blo ck Di a gram.............. ........................... ..................................... ... .........4-24

4-3 PWMn Block Diagram.... .............. ... ........................... .......................... ....................................4-43

4-4 Basic Pulse Width Waveform..................................................................................................4-47

5-1 DMAC Block Diagram................................................................................................................5-2

5-2 DREQ timing requirements........................................................................................................5-3

5-3 No-Descrip to r Fetc h Mode Chann el Sta te............. ........................... ..................................... ... .5-7

5-4 Descriptor Fetch Mode Channel State.......................................................................................5-8

5-5 Little Endian Transfers.............................................................................................................5-10

6-1 General Memory Interface Configuration...................................................................................6-2

6-2 SDRAM Memory System Example............................................................................................6-5

6-3 Asynchronous Static Memory System Example........................................................................6-6

6-4 External to Internal Address Mapping Options........................................................................6-19

6-5 SDRAM Read....................... ........................... .......................... ........................... ...................6-27

6-6 SDRAM Read With a Second Read to Same Bank, Same Row.............................................6-27

6-7 SDRAM Read With a Second Read to Same Bank, Different Row.........................................6-28

6-8 SDRAM Read With a Second Read to a Differen t Bank............... .......................... ................6-28

6-9 SDRAM Write.................... ... ............................................................... ....................................6-29

6-10 SDRAM Write With a Second Write to Same Bank, Same Row .............................................6-29

6-11 SMROM Read Timing Diagram Half-Memory Cloc k Freque n cy,............... ........................... ..6-38

6-12 Burst-of-Eight Synchronous Flash Timing Diagram (non-divide-by-2 mode) ..........................6-40

6-13 MSC0/1/2 Registe r Bitmap......................................................................................................6-44

Intel® PXA26x Processo r Family Develop er’s Manual xiii

Contents

6-14 32-Bi t Burst-of-Eig ht ROM or Flash R ead Timing Diagram (MSC0:R DF = 4,

MSC0:RDN = 1, MSC0:RRR = 1)............................................................................................6-49

6-15 Eight-Beat Burst Read from 16-B i t B urst-of-Four ROM or Flash (M S C0:RDF = 4,

MSC0:RDN = 1, MSC0:RRR = 0)............................................................................................6-50

6-16 32-Bi t Non-burst ROM, SRAM, or Flash Read Tim i ng Diagram - F our Data Beats

(MSC0:RDF = 4, MSC0:RRR = 1)...........................................................................................6 -51

6-17 32-Bit SRAM Write Timing Diagram (4-beat Burst) (MSC0:RDN = 2, MSC0:RRR = 1)..........6-52

6-18 32-Bit Variable Latency I/O Read Tim i ng (Burst-of -F our, One Wait C yc l e P e r Beat)

(MSC0:RDF = 2, MSC0:RDN = 2, MSC0:RRR = 1) ...............................................................6-54

6-19 32-Bit Variable Latency I/O Write T i m i ng (Burst-of-Four, Variabl e Wait Cycles Per Beat)......6-55

6-20 Asynchronous 32-Bit Flash Write Timing Diagram (2 Writes).................................................6-57

6-21 MCMEM1 Register Bitmap......................................................................................................6-58

6-22 MCATT1 Register Bitmap........................................................................................................6-58

6-23 MCIO1 Register Bitmap...........................................................................................................6 -59

6-24 16-Bit PC Card Memory Map ..................................................................................................6-62

6-25 Expansion Card External Logic for a One-Socket Configuration.............................................6-65

6-26 Expansion Card External Logic for a Two-Socket Configuration.............................................6-66

6-27 16-Bit PC Card Memory or I/O 16-Bit (Half-word) Access.......................................................6-67

6-28 16-Bit PC Card I/O 16-Bit Access to 8-Bit Device...................................................................6-68

6-29 Alternate Bus Master Mode..................................................................................................... 6-69

6-30 Variable Latency IO.................................................................................................................6-69

6-31 Asynchronous Boot Time Configurations and Register Defaults.............................................6-73

6-32 SMROM Boot Time Configurations and Register Defaults......................................................6-74

6-33 SMROM Boot Time Configurations and Register Defaults (Continued)..................................6-75

7-1 LCD Controller Block Diagram ..................................................................................................7-3

7-2 Temporal Dithering Concept - Single Color...............................................................................7-7

7-3 Compare Range for TMED........................................................................................................7-7

7-4 TMED Block Diagram............. ........................... .......................... .............................................7-8

7-5 Palette-Bu ffe r For mat................. ................................................................ .............................7-12

7-6 1-Bit Per Pixe l Data Memory Organization..............................................................................7 -12

7-8 4-Bits Per Pixel Data Memory Organization............................................................................7 -13

7-9 8-Bits Per Pixel Data Memory Organization............................................................................7 -13

7-10 16-Bits Per Pixel Data Memory Organization – Passive Mode ...............................................7-13

7-7 2-Bits Per Pixel Data Memory Organization............................................................................7 -13

7-11 16-Bits Per Pixel Data Memory Organization – Active Mode..................................................7-14

7-12 Passive Mode Start-of-Frame Timing ......................................................................................7-16

7-13 Passive Mode End-of-Frame Timing.......................................................................................7 -17

7-14 Passive Mode Pixel Clock and Data Pin Timing......................................................................7-17

7-15 Active Mode Timing.................................................................................................................7-18

7-16 Active Mode Pixel Clock and Data Pin Timing ........................................................................7-19

7-17 Frame Buffer/Palette Output to LCD Data Pins in Active Mode..............................................7-25

7-18 LCD Data-Pin Pixel Ordering...................................................................................................7-27

8-1 Texas Instru ments’ Synchronous Serial Fram e* For mat.................. .......................... ...............8-4

8-2 Motorola SPI* Frame Format.....................................................................................................8-5

8-3 National Micro wir e* Fra me For mat.............. ........................................ ......................................8-6

8-4 Motorola SPI* Frame Formats for SPO and SPH Programming.............................................8-14

9-1 I

2

C Bus Configuratio n Exam ple............... ... ........................... ...................................................9-2

9-2 Start and Stop Conditions..........................................................................................................9-5

9-3 START and STOP Conditio n s........... ... .......................................................................... ... ........9-6

9-4 Data Format of First Byte in Master Transaction.......................................................................9-8

xiv Intel® PXA26x Processor Family Developer’s Manual

Contents

9-5 Acknowledge on the I2C Bus.....................................................................................................9-8

9-6 Clock Synchronization During the Arbitration Procedure.........................................................9-10

9-7 Arbitration Procedure of Two Masters.....................................................................................9-10

9-8 Master-Receiver Read from Slave-Transmitter.......................................................................9-14

9-9 Mas t er-Receiver Read from Slave-Transmit ter / Repeated Start / Master -T ransmitter

Write to Slave-Rec eiv er........ ... ................................................................ .......................... ......9-14

9-10 A Complete Data Transfer.......................................................................................................9-14

9-11 Master-Transmitter Write to Slave-Receiver............................................................................9-16

9-12 Master-Receiver Read to Slave-Transmitter...........................................................................9-16

9-13 Master-Receiver Read to Slave-Transmitter, Repeated START, Master-Transmitter

Write to Slave-Rec eiv er........ ... ................................................................ .......................... ......9-16

9-14 General Call Address...............................................................................................................9-17

10-1 Example UART Data Frame....................................................................................................10-4

10-2 Example NRZ Bit Encoding (0b0100 1011).............................................................................10-5

10-3 IR Transmit and Receive Example........................................................................................10-25

10-4 XMODE Example...................................................................................................................10-25

11-1 4PPM Modulation Encodings...................................................................................................11-2

11-2 4PPM Modulation Example.....................................................................................................11-3

11-3 Frame Format fo r IrDA Transmission (4.0 Mbps)....................................................................11-3

12-1 NRZI Bit Encoding Example....................................................................................................12-4

12-2 Self-Powere d Devi c e............................. ... ........................... .......................... ........................12-11

13-1 Data Transfer Through the AC-link..........................................................................................13-3

13-2 AC97 Standard Bidire cti o n al Audio Frame...................... ........................... ........................... ..13-4

13-3 AC-link Audio Output Frame....................................................................................................13-5

13-4 Start of Audio Output Frame....................................................................................................13-5

13-5 AC97 Input Frame ...................................................................................................................13-9

13-6 Start of an Audio Input Frame..................................................................................................13-9

13-7 AC-link Powerd ow n Timi ng........................................... .........................................................13-12

13-8 SDATA_IN Wake Up Signaling..............................................................................................13-13

13-9 PCM Transmit and Receive Operation..................................................................................13-27

13-10 Mic-in Receive-Only Operation..............................................................................................13-29

13-11 Modem Transmit and Receive Operation..............................................................................13-32

14-1 I2S Data Formats (16 bits).......................................................................................................14-7

14-2 MSB-Justified Data Formats (16 bits)......................................................................................14-7

14-3 Transmit and Receive FIFO Accesses Through the SADR...................................................14-15

15-1 MMC System Interaction.........................................................................................................15-1

15-2 MMC Mode Operation Without Data Token.............................................................................15-3

15-3 MMC Mode Operation With Data Token..................................................................................15-3

15-4 SPI Mode Operation Without Data Token...............................................................................15-3

15-5 SPI Mode Read Operation.......................................................................................................15-4

15-6 SPI Mode Write Operation.......................................................................................................15-4

16-1 Texas Instruments Synchronous Serial Frame* Protocol (multiple transfers).........................16-6

16-2 Texas Instruments Synchronous Serial Frame* Protocol (single transfers)............................16-6

16-3 Motorola SPI* Frame Protocol (multiple transfers)..................................................................16-7

16-4 Motorola SPI* Frame Protocol (single transfers).....................................................................16-7

16-5 Motorola SPI* Frame Protocols for SPO and SPH Programming (multiple transfers).............16-8

16-6 Motorola SPI* Frame Protocols for SPO and SPH Programming (single transfers)................16-9

16-7 National Semiconductor Microwire* Frame Protocol (multiple transfers)..............................16-10

16-8 National Semiconductor Microwire* Frame Protocol (single transfers).................................16-10

16-9 Programmable Serial Protocol (multiple transfers)................................................................16-11

Intel® PXA26x Processo r Family Develop er’s Manual xv

Contents

16-10 Programmable Serial Protocol (single transfers)...................................................................16-12

16-11 TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=0.................................................................16-13

16-12 TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=1.................................................................16-14

16-13 Motorola SPI with SSCR[TTE]=1...........................................................................................16-14

16-14 National Semiconductor Microwire with SSCR1[TTE]=1.......................................................16-15

16-15 PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (slave to frame).............................16-15

16-16 PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (master to frame) ..........................16-16

16-17 PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=1 (must be slave to frame)...............16-16

17-1 Example UART Data Frame....................................................................................................17-4

17-2 Example NRZ Bit Encoding (0b0100 1011).............................................................................17-4

17-3 IR Transmit and Receive Example..........................................................................................17-9

17-4 XMODE Example. .................................................................................................................17-10

18-1 Flash Memory Reset Using State Machine.............................................................................18-1

18-2 Flash Memory Reset Logic if Watchdog Reset is Not Necessary ...........................................18-2

Tables

2-1 CPU Core Fault Register Bitmap...............................................................................................2-3

2-2 ID Register Bitma p and Bit Def initions (Read-o nly )......... ........................... ...............................2-4

2-3 PXA26x processor family ID Values.......................................................................................... 2-5

2-4 Effect of Each Type of Reset on Internal Register State ..........................................................2-7

2-5 Processor Pin Types........................... .... .......................... ........................... ............................2-9

2-6 Pin & Signal Descrip ti o ns for the PXA26 x Proce ss or Family................. .... .......................... .....2-9

2-7 Pin Description Notes..............................................................................................................2-21

2-8 Register Address Summary............................................. ........................... .......................... .. .2-21

3-1 Core PLL Output Frequencies for 3.6864-MHz Crystal.............................................................3-5

3-2 95.85-MHz Perip h eral PLL Outp ut Fre que nc i es for 3.6864 - MHz Crystal............. ... ..................3-5

3-3 147.46-MHz Pe ripheral PLL Output Frequencies for 3.6864-MHz Crystal................................3-6

3-4 Power Mode Entry Sequence Table.......................................................................................3-20

3-5 Power Mode Exit Sequence Table.........................................................................................3-21

3-6 Power and Clock Supply Sources and Sta tes During Power Modes.....................................3-22

3-7 PMCR Bit Definitions...............................................................................................................3 -23

3-8 PCFR Bit Definitions................................................................................................................3-24

3-9 PWER Bit Definitions...............................................................................................................3-25

3-10 PRER Bit Definitions................................................................................................................3-26

3-11 PFER Bit Definit ion s...................................................................................... ..........................3-27

3-12 PEDR Bit Definitions................................................................................................................3-28

3-13 PSSR Bit Definitions................................................................................................................3-29

3-14 PSPR Bit Definitions................................................................................................................3-30

3-15 PMFWR Registe r Bitma p and Bit Defi n iti o ns ............................................. .......................... ...3-31

3-16 PGSR0 Bit Definitions.............................................................................................................3-32

3-17 PGSR1 Bit Definitions.............................................................................................................3-32

3-18 PSPR Bit Definitions................................................................................................................3-32

3-19 RCSR Bit Definitions...............................................................................................................3-34

3-20 Power Manager Register Locations ........................................................................................3-34

3-21 CCCR Regis te r Bitma p and Bit Def initions............... ..................................... ... .......................3-36

3-22 CKEN Register Bitmap and Bit Definitions..............................................................................3-37

3-23 OSCC Bit Definit i ons.................. .... .......................... ........................... ....................................3-39

3-24 Clocks Manager Register Locations........................................................................................3-39

3-25 Coprocessor 14 Clock and Power Management Summary.....................................................3-40

xvi Intel® PXA26x Processor Family Developer’s Manual

Contents

3-26 CCLKCFG Bit Definitions.........................................................................................................3-40

3-27 PWRMODE Bit Defini tio ns. ............. ... ........................... ........................... .......................... ......3-41

4-1 GPIO Alternate Functions..........................................................................................................4-3

4-2 GPIO Register Definitions..........................................................................................................4-7

4-3 GPLR0 Bit Definitions................................................................................................................4-8

4-4 GPLR1 Bit Definitions................................................................................................................4-9

4-5 GPLR2 Register Bitmap............................................................................................................4-9

4-6 GPDR0 Bit Definiti o ns.............................................................................................................4-10

4-7 GPDR1 Bit Definiti o ns.............................................................................................................4-10

4-8 GPDR2 Register Bitma p.............. ............. ... ........................... ........................... ......................4-10

4-9 GPSR0 Bit Definitions............................ .......................... ........................... .............................4-11

4-10 GPSR1 Bit Definiti ons.... ........................... ........................... .......................... ..........................4-11

4-11 GPSR2 Register Bi tmap............................................................ .............................................. 4-12

4-12 GPCR0 Bit Defini tio ns............. .... .......................... ..................................................................4-12

4-13 GPCR1 Bit Defini tio ns............. .... .......................... ..................................................................4-12

4-14 GPCR2 Registe r Bitma p.............. ............................................................................................4-13

4-15 GRER0 Bit Definiti o ns.......................................................................................... ...................4-14

4-16 GRER1 Bit Definiti o ns.......................................................................................... ...................4-14

4-17 GRER2 Register Bitma p.............. .......................... ........................... ........................... ............4-14

4-18 GFER0 Bit Definitions..............................................................................................................4-15

4-19 GFER1 Bit Definitions..............................................................................................................4-15

4-20 GFER2 Registe r Bitmap..........................................................................................................4-15

4-21 GEDR0 Bit Defini tio ns............. .... .......................... ..................................................................4-16

4-22 GEDR1 Bit Defini tio ns............. .... .......................... ..................................................................4-17

4-23 GEDR2 Registe r Bitma p.............. ............................................................................................4-17

4-24 GAFR0_L Bit Definitions..........................................................................................................4-18

4-25 GAFR0_U Bit Definitions.........................................................................................................4-18

4-26 GAFR1_L Bit Definitions..........................................................................................................4-19

4-27 GAFR1_U Bit Definitions.........................................................................................................4-19

4-28 GAFR2_L Bit Definitions..........................................................................................................4-20

4-29 GAFR2_U Register Bitmap......................................................................................................4-20

4-30 GPIO Register Addresses.......................................................................................................4-21

4-31 ICMR Register Bitma p....................... ................................................................ ......................4-25

4-32 ICLR Register Bitmap..............................................................................................................4-25

4-33 ICCR Bit Definitions.................................................................................................................4-26

4-34 ICIP Register Bitma p............................. ... ........................... .......................... ..........................4-27

4-35 ICFP Register Bitmap..............................................................................................................4-27

4-36 ICPR Register Bitmap..............................................................................................................4-28

4-37 List of First–Level Interrupts ....................................................................................................4-30

4-38 Interrupt Contr oll e r Register Addresses........................................... .......................................4-31

4-39 RTTR Bit Definitions................................................................................................................4-33

4-40 RTAR Bit Definitions................................................................................................................4-34

4-41 RCNR Bit Definitions...............................................................................................................4-34

4-42 RTSR Bit Definitions................................................................................................................4-35

4-43 RTC Register Addresses .........................................................................................................4-38

4-44 OSMR[x] Bit Defini ti ons......................................... ........................... ........................... ............4-39

4-45 OIER Bit Definitions .................................................................................................................4-40

4-46 OWER Bit Definitions...............................................................................................................4-40

4-47 OSCR Bit Definitions...............................................................................................................4-41

4-48 OSSR Bit Definitions................................................................................................................4-42

Intel® PXA26x Processo r Family Develop er’s Manual xvii

Contents

4-49 OS Timer Register Locations ..................................................................................................4-42

4-50 PWM_CTRLn Bit Definitions ...................................................................................................4-45

4-51 PWM_DUTYn Bit Defi nit i ons.................................... ........................... ........................... .........4-46

4-52 PWM_PERVALn Bit Definitions...............................................................................................4-47

4-53 PWM Register Loca tio ns...................................................................................... ...................4-48

5-1 DMAC Signal List ......................................................................................................................5-3

5-2 Channel Priority (if all channels are running concurrently)........................................................5-5

5-3 Channel Priority.........................................................................................................................5-5

5-4 Priority Sch emes Exa mple s.................. .... .......................... ........................... ........................ ....5-5

5-5 DMA Quick Reference for Inter n al Peri p hera ls.................. .....................................................5-13

5-6 DINT Register Bitmap and Bit Definitions................................................................................5 -17

5-7 DMA Channel Control/Status Register Bitmap and Bit Definitions..........................................5-18

5-8 DRCMRx Registers Bitmap Bit Definitions..............................................................................5-20

5-9 DMA Descriptor Address Register Bit Definitions....................................................................5-21

5-10 DSADRx Reg iste r Bitma p Bit Def initions............... ........................... .......................................5-22

5-11 DTADRx Register Bitmap Bit Definitions.................................................................................5-23

5-12 DCMDx Register Bitmap and Bit Definitions ...........................................................................5 -24

5-13 DMA Controll er Registers........... ........................... ............................................................. .....5-28

6-1 Device Transactions..................................................................................................................6-7

6-2 Memory Interface Control Registers..........................................................................................6-8

6-3 MDCNFG Regis te r Bitma p and Bit Defi nit i ons........................................................ ... ...............6-9

6-4 MDMRS Register Bitmap ........................................................................................................6-12

6-5 MDMRSLP Register Bit Definitions.........................................................................................6 -14

6-6 MDREFR Register Bitmap.......................................................................................................6-15

6-7 Sample SDRAM Memory Size Options...................................................................................6-18

6-8 External to Internal Address Mapping for Normal Bank Addressing .......................................6-19

6-9 External to Internal Address Mapping for SA-1111 Addressing..............................................6 -21

6-10 Pin Mapping to SDRAM Devices with Normal Bank Addressing.............................................6-22

6-11 Pin Mapping to SDRAM Devices with SA-1111 Addressing ...................................................6-24

6-12 SDRAM Command Encoding..................................................................................................6-26

6-13 SDRAM Mode Register Opcode Table....................................................................................6-26

6-14 SXCNFG Regis te r Bitma p.............. .........................................................................................6-30

6-15 SXCNFG Regis te r Bitma p.............. .........................................................................................6-35

6-16 Synchronous Static Memory Exte rnal to Internal Address Mapping Options..........................6-35

6-17 SXMRS Registe r Bitma p.................................... .......................... ........................... ................6-36

6-18 Read Configuration Registe r Programming Values.................................................................6 -39

6-19 Frequenc y Code Co nf igu rati o n Values Bas ed on Clo ck Sp eed..............................................6-39

6-20 32-Bit Bus Write Access..........................................................................................................6-41

6-21 16-Bit Bus Write Access..........................................................................................................6-42

6-22 32-Bit Byte Address Bits MA[1:0] for Reads Based on DQM[3:0]...........................................6-43

6-23 16-Bit Byte Address Bit MA[0] for Reads Based on DQM[1:0]................................................6-43

6-24 SA-1111 Register Bit Definitions.............................................................................................6-43

6-25 MSC0/1/2 Register Bit Definitions...................... .................................... .... .......................... ...6-45

6-26 Asynchronous Static Memory and Variable Latency I/O Capabilities......................................6-47

6-27 MCMEMx Registe r Bitma p.................................... ........................... .......................... .............6-58

6-28 MCATTx Regis te r Bitma p.................. ... ........................... ........................... .............................6-58

6-29 MCIOx Regis te r Bitma p.................. ... ........................... ...........................................................6-59

6-30 Card Inter fa ce Comman d Asser ti o n Code Table........................................... ... .......................6-59

6-31 MECR Configuration Register Bitmap.....................................................................................6-61

6-32 Common Memory Space Write Commands............................................................................6 -63

xviii Intel® PXA26x Processor Family Developer’s Manual

Contents

6-33 Common Memory Space Read Commands.......... .... .......................... ........................... .........6-63

6-34 Attribute Memory Space Write Commands .............................................................................6-63

6-35 Attribute Memory Space Read Commands.............................................................................6-63

6-36 16-Bit I/O Sp ace Write Commands (nIOIS16 = 0)...................................................................6-63

6-37 16-Bit I/O Sp ace Read Commands (nIOIS16 = 0)...................................................................6-63

6-38 8-Bit I/O Space Write Commands (nIOIS16 = 1).....................................................................6-64

6-39 8-Bit I/O Space Read Commands (nIOIS16 = 1).....................................................................6-64

6-40 BOOT_DEF Register Bitmap...................................................................................................6-72

6-41 Memory Controller Pin Reset Values.......................................................................................6-76

7-1 Pin Descriptions.........................................................................................................................7-4

7-2 LCD Controller Control Register 0...........................................................................................7-20

7-3 LCD Controller Data Pin Utilization..........................................................................................7-26

7-4 LCD Controller Control Register 1...........................................................................................7-28

7-5 LCD Controller Control Register 2...........................................................................................7-31

7-6 LCD Controller Control Register 3...........................................................................................7-33

7-7 LCD DMA Frame Descriptor Address Registers .....................................................................7-38

7-8 LCD DMA Frame Source Address Registers..........................................................................7-39

7-9 LCD Frame ID Registers.........................................................................................................7-39

7-10 LCD DMA Command Registers...............................................................................................7-40

7-11 LCD DMA Frame Branch Registers (FBRx)............................................................................7-42

7-12 LCD Controller Status Register ...............................................................................................7-43

7-13 LCD Controller Interrupt ID Register........................................................................................7-46

7-14 TMED RGB Seed Register......................................................................................................7-47

7-15 TMED Control Register............................................................................................................7-47

7-16 LCD Controlle r Register Locations.................. ... .....................................................................7-49

8-1 External Interface to Codec.......................................................................................................8-1

8-2 SSP Control Register 0 (SSCR0) Bitmap and Bit Definitions....................................................8-9

8-3 SSP Control Register 1 (SSCR1) Bitmap and Definitions.......................................................8-11

8-4 TFT and RFT Values for DMA Servicing.................................................................................8-15

8-5 SSP Data Register (SSDR) Bitmap and Definitions................................................................8-16

8-6 SSP Status Register (SSSR) Bitma p and Bit Defini tions............................ .............................8-17

8-7 SSP Register Address Map.....................................................................................................8-19

9-1 MMC Signal Description............................................................................................................9-1

9-2 I2C Bus Definitions.............. ............. .... .......................... ........................... ...............................9-2

9-3 Modes of Operation.............. ........................................ .............................................................9-3

9-4 START and STOP Bit Definitions..............................................................................................9-5

9-5 Master Transactions................................................................................................................9-12

9-6 Slave Transactions..................................................................................................................9-15

9-7 General Call Address Second Byte Definitio ns .......................................................................9-17

2

9-8 I

C Register Definitions...........................................................................................................9-22

9-9 I2C Bus Monitor Register - IBMR................... .......................... ........................... ...................9-23

9-10 I2C Data Buffer Register - IDBR.............................................................................................9-23

9-11 I2C Control Register - ICR......................................................................................................9-24

9-12 I2C Status Register - ISR........................ ... ........................... ........................... ......................9-27

9-13 I2C Slave Address Regis te r - ISAR.................................... ....................................................9-28

10-1 UART Signal Descriptions.......................................................................................................10-3

10-2 UART Register Addresses as Offsets of a Base.....................................................................10-6

10-3 Receive Buffer Register – RBR...............................................................................................10-6

10-4 Transmit Holding Register – THR............................................................................................10-7

10-5 Divisor Latch Low Re gister – DLL ......... ............. ... ........................... .......................................10-8

Intel® PXA26x Processo r Family Develop er’s Manual xix

Contents

10-6 Divisor Latch High Register – DLH..........................................................................................10-8

10-7 Interrupt Enable Register – IER...............................................................................................10-9

10-8 Interrupt Conditions...............................................................................................................10-11

10-9 Interrupt Identification Register – IIR.....................................................................................10-11

10-10 Interrupt Identification Register Decode................................................................................10-12

10-11 FIFO Control Register – FCR................................................................................................10-13

10-12 Line Control Register – LCR..................................................................................................10-14

10-13 Line Status Register – LSR................................................................................................... 10-16

10-14 Modem Control Register – MCR ...........................................................................................10-18

10-15 Modem Status Register – MSR.............................................................................................10-20

10-16 Scratch Pad Register – SPR.................................................................................................10-21

10-17 Infrared Selection Register – ISR..........................................................................................10-24

10-18 FFUART Regis te r Addre ss es............ ........................... .......................... ...............................10-26

10-19 BTUART Register Locations .................................................................................................10-26

10-20 STUART Register Locations .................................................................................................10-27

10-21 Flow Control Registers in BTUART and STUART.................................. ...............................10-27

11-1 FICP Signal Desc rip tio n................. ... ........................... .......................... .................................11-1

11-2 Fast Infrare d Co mmunication Port Control Reg iste r 0.......................................................... ...11-9

11-3 Fast Infrare d Co mmunication Port Control Reg iste r 1.......................................................... .11-11

11-4 Fast Infrare d Co mmunication Port Control Reg iste r 2.......................................................... .11-11

11-5 Fast Infrare d Co mmunication Port Data Registe r......... .......................... ...............................11-13

11-6 Fast Infrare d Commun ica ti o n Port Sta tus Registe r 0.......................... ... ........................... ....11-14

11-7 Fast Infrare d Commun ica ti o n Port Sta tus Registe r 1.......................... ... ........................... ....11-15

11-8 FICP Contro l, Da ta, and Status Register Loca tio ns............................... .... ...........................11-16

12-1 Endpoint Co nfig u rati o n............ ........................... .....................................................................12-2

12-2 USB States............. ........................... ........................... .......................... .................................12-3

12-3 IN, OUT, and SETUP Token Packet F orm at............ .............. ... ........................... ...................12-6

12-4 SOF Token Packet Form at................ ... ........................... ........................... .............................12-6

12-5 Data Packet Format.................................................................................................................12-6

12-6 Handshak e Packe t Forma t.................................... ........................... .......................................12-6

12-7 Bulk Transaction Formats........................................................................................................1 2-7

12-8 Isochron ous Tra ns ac ti o n Formats................................... ........................... .............................12-7

12-9 Control Transaction Formats...................................................................................................12-8

12-10 Interrupt Transaction Formats.................................................................................................12-8

12-11 Host Device Request Summary ..............................................................................................12-9

12-12 UDC Control Register............................................................................................................12-23

12-13 UDC Endpoint 0 Control Sta tus Register ..............................................................................12-26

12-14 UDC Endpoint x Control Status Register, Where x is 1, 6 or 11 ...........................................12-28

12-15 UDC Endpoint x Control Status Register, Where x is 2, 7, or 12 ..........................................12-30

12-16 UDC Endpoint x Control Status Register, Where x is 3, 8, or 13 ..........................................12-33

12-17 UDC Endpoint x Control Status Register, Where x is 4, 9, or 14 ..........................................12-35

12-18 UDC Endpoint x Control Status Register, Where x is 5, 10, or 15 ........................................12-37

12-19 UDC Interrupt Control Register 0..........................................................................................12-38

12-20 UDC Interrupt Control Register 1..........................................................................................12-39

12-21 UDC Status / Interrupt Register 0..........................................................................................12-41

12-22 UDC Status / Interrupt Register 1..........................................................................................12-43

12-23 UDC Frame Number High Register.......................................................................................12-44

12-24 UDC Frame Number Low Registe r........................................................................................12-45

12-25 UDC Byte Count Regis te r x, Wher e x is 2, 4, 7, 9, 12, or 14............ .....................................12-46

12-26 UDC Endpoint 0 Data Register..............................................................................................12-47

xx Intel® PXA26x Processor Family Developer’s Manual

Contents

12-27 UDC Endpoint x Data Registe r, Where x is 1, 6, or 11..........................................................12-47

12-28 UDC Endpoint x Data Registe r, Where x is 2, 7, or 12..........................................................12-48

12-29 UDC Endpoint x Data Register, where x is 3, 8, or 13...........................................................12-48

12-30 UDC Endpoint x Data Registe r, Where x is 4, 9, or 14..........................................................12-49

12-31 UDC Endpoint x Data Registe r, Where x is 5, 10, or 15........................................................12-49

12-32 UDC Control, Data, and Status Register Locations ...............................................................12-50

13-1 External Interface to Codecs ...................................................................................................13-2

13-2 Supported Data Stream Formats.............................................................................................13-3

13-3 Slot 1 Bit Definition s. .......................... ........................... ........................... ................................13-7

13-4 Slot 2 Bit Definition s. .......................... ........................... ........................... ................................13-7

13-5 Input Slot 1 Bit Definitions......................................................................................................13-10

13-6 Input Slot 2 Bit Definitions......................................................................................................13-11

13-7 Register Mapping Summary..................................................................................................13-19

13-8 Global Control Register .........................................................................................................13-20

13-9 Global Status Register...........................................................................................................13-22

13-10 PCM-Out Control Register .....................................................................................................13-24

13-11 PCM-In Control Register (PICR)............................................................................................13-24

13-12 PCM-Out Status Register......................................................................................................13-25

13-13 PCM_In Status Registe r........................................ ........................... ........................... ..........13-25

13-14 Codec Access Register......................................................................................................... 1 3-26

13-15 PCM Data Register................................................................................................................13-26

13-16 Mic-In Control Register..........................................................................................................13-27

13-17 Mic-In Status Register...........................................................................................................13-28

13-18 Mic-In Data Register..............................................................................................................13-28

13-19 Modem-Out Control Register.................................................................................................13-29

13-20 Modem-In Cont rol Register.......... ... ........................... .......................... ..................................13-30

13-21 Modem-Out Status Register..................................................................................................13-30

13-22 Modem-In Status Regi st er................. ............................................................................. .......13-31

13-23 Modem Data Register............................................................................................................13-31

13-24 Address Mapping for Codec Registers..................................................................................13-33

14-1 External Interface to CODEC...................................................................................................14-2

14-2 Supported Sampling Frequencies ...........................................................................................14-6

14-3 SACR0 Bit Descriptions...........................................................................................................14-8

14-4 FIFO Write/Read table...........................................................................................................14-10

14-5 TFTH and RFTH Values for DMA Servicing..........................................................................14-10

14-6 SACR1 Bit Descriptions.........................................................................................................14-11

14-7 SASR0 Bit Descriptions.........................................................................................................14-12

14-8 SADIV Bit Descript ion s.............................................. ............................................................14-13

14-9 SAICR Bit Descriptions..........................................................................................................14-14

14-10 SAIMR Bit Descriptions.........................................................................................................14-14

14-11 SADR Bit Descript ion s............. ..............................................................................................14-15

14-12 Register Memory Map ...........................................................................................................14-16

15-1 Command Token Format.........................................................................................................15-2

15-2 MMC Data Token Format........................................................................................................15-2

15-3 SPI Data Token Format...........................................................................................................15-2

15-4 MMC Signal Description..........................................................................................................15-5

15-5 MMC Controller Registers.....................................................................................................15-21

15-6 MMC_STRPCL Register........................................................................................................15-22

15-7 MMC_STAT Register.. ... ........................... ........................... .......................... ........................15-22

15-8 MMC_CLK Registe r........... ... ........................... .......................... ........................... .................15-24

Intel® PXA26x Processo r Family Develop er’s Manual xxi

Contents

15-9 MMC_SPI Register................................................................................................................15-24

15-10 MMC_CMDAT Regis te r.................. .......................... .............................................................15-25

15-11 MMC_RESTO Register.........................................................................................................15-27

15-12 MMC_RDTO Register ...........................................................................................................15-27

15-13 MMC_BLKLEN Register........................................................................................................15-28

15-14 MMC_NOB Register..............................................................................................................15-28

15-15 MMC_PRTBUF Register.......................................................................................................15-29

15-16 MMC_I_MASK Register ........................................................................................................ 15-29

15-17 MMC_I_REG Register...........................................................................................................15-31

15-18 MMC_CMD Registe r.................. .............. ... ........................... .......................... ..................... 15-32

15-19 Command Index Values.................... ........................... .......................... ........................... ....15-32

15-20 MMC_ARGH Register.......................... .... .......................... ..................................... ... ...........15-34

15-21 MMC_ARGL Regis te r.............. ........................... ...................................................................15-34

15-22 MMC_RES, FIFO Entry.........................................................................................................15-35

15-23 MMC_RXFIFO, FIF O Entry...................... .......................... ........................... ........................15-35

15-24 MMC_TXFIFO, FIFO Entry....................................................................................................15-36

16-1 SSP Serial Port I/O Signals............ ........................................ .......................... .......................16-2

16-2 Programmable Serial Protocol ( PSP) Parameters ................................................................16-12

16-3 SSCR0 Bit Defini ti ons........................... .................................................................................16-19

16-4 SSCR1 Bit Defini ti ons........................... .................................................................................16-21

16-5 SSPSP Bit Definition s.... ........................... .......................... ........................... ........................16-27

16-6 SSTO Bit Definitions..............................................................................................................16-29

16-7 SSITR Bit Definitions.............................................................................................................16-29

16-8 SSSR Bit Definitions..............................................................................................................16-31

16-9 SSDR Bit Definitions..............................................................................................................16-34

16-10 NSSP Register Address Map ................................................................................................16-35

16-11 ASSP Register Address Map ................................................................................................16-35

17-1 UART Signal Descriptions.......................................................................................................17-3

17-2 RBR Bit Definitions................................................................................................................17-11

17-3 THR Bit Defin iti o ns................................... .................................... .... .......................... ...........17-11

17-4 Divisor Latch Register Low (DLL) Bit Definitions...................................................................17-12

17-5 Divisor Latch Register High (DLH) Bit Definitions .................................................................17-12

17-6 IER Bit Definitions..................................................................................................................17-13

17-7 Interrupt Conditions...............................................................................................................17-15

17-8 IIR Bit Definitions...................................................................................................................17-15

17-9 Interrupt Identification Register Decode................................................................................17-16

17-10 FCR Bit Defin iti o ns................................... .................................... .... .......................... ...........17-17

17-11 FOR Bit Definitions................................................................................................................17-19

17-12 ABR Bit Definiti ons............................................. ...................................................................17-20

17-13 ACR Bit Definitions................................................................................................................17-21

17-14 LCR Bit Definitions ................................................................................................................17-22

17-15 LSR Bit Definitions.................................................................................................................17-24

17-16 MCR Bit Definitions...............................................................................................................17-27

17-17 MSR Bit Definit ion s........ ............................................................................. ...........................17-29

17-18 SPR Bit Definiti ons............................................. ...................................................................17-29

17-19 ISR Bit Definitions..................................................................................................................17-30

17-20 HWUART Registe r Loca ti o ns............ ............. .... .......................... ........................... ..............17-31

18-1 SXCNFG Confi gura tio n for Inter n al F las h....................... ........................... .............................18-3

18-2 RCR Values for Each PXA26x processor family Applications Processor Version ..................1 8-3

xxii Intel® PXA26x Processor Family Devel oper’s Manual

Revision History

Date Revision Description

October 2002 Public Release -001 Released to the public

March 2003 Release -002 Added fast wake-up and 33-MHz idle mode.

Contents

Intel® PXA26x Processo r Family Develop er’s Manual xxiii

Contents

xxiv Intel® PXA26x Processor Family Devel oper’s Manual

Introduction 1

The Intel® PXA26x Processor Family is a 32-bit, multi-chip device which combines a processor
based on Inte l® XS cale™ microarchitecture and Intel S trataFlash® memory. (Intel StrataFlash®
memory is avail a ble on some versions.) The PXA26x processor fami ly provides industry-leading
MIPS/mW performance for handheld comp uting and cell phon e a pplications.

The PXA26x proces sor fam ily is availab le in a 13 x13mm 2 94-pi n TF-BG A pa ckage . It i s avail able
in multiple versions with different flash configurations:

• PXA260 processor – No Intel StrataFlash® memory

• PXA261 processor – 128 megabit x 16 Intel StrataFlash® memory

• PXA262 processor – 256 megabit x 16 Intel StrataFlash® memory

• PXA263 processor – 256 megabit x 32 Intel StrataFlash® memory

1.1 Intel® XScale™ Core Features

The Intel® XScale™ core has these features:

• ARM* version 5TE ISA compliant .

— ARM* thumb instruction support
— ARM* DSP enhanced instr uctions

• Low power consumption and hi gh performance

• Intel media processing techno logy

— Enhanced 16-bit multiply
— 40-bit accumula tor

• 32-KByte instru ction cache

• 32-KByte data cache

• 2-KByte mini data cache

• 2-KByte mini inst ruction cache

• Instructio n and data memory management units

• Branch target buffer

• Debug capability via JTAG port

Refer to the Intel® XScale™ Micr oarchitecture for the Intel® PXA255 Processor User’s Manual
for more details.

Intel® PXA26x Processor Family Deve lo p er’s Manua l 1-1

Introduction

1.2 System Integration Features

The PXA26x processo r family features are:

• Integrated synchronous Inte l StrataFlash® mem ory on some versions

• Single-ended universal serial bus client interface

• Network synchronous serial protocol port

• Audio synchronous serial prot ocol port

• Low voltage suppor t (2.775 volts) for VCCQ

• Low voltage support (2.5 volts) for VCCN

• Memory controller

• Clock and power controllers

• Universal serial bus client

• DMA controller

• LCD controller

• AC97

2

• I

S

• MultiMediaCard

• FIR communication

• Synchronous serial protocol port

2

• I

C

• General purpose I/O pins

• Four UARTs, one with hardware flow control

• Real-time clock

• OS timers

• Pulse width modulation

• Interru p t c on t ro l

1.2.1 Memory Controller

The memory controller provides glueless control signals with programmable timing for a wide
assortment of mem ory-chip types and organizations. It supports up to four SDRAM partitions; six
static chip selects for SRAM, SSRAM, flash, ROM, SROM, and companion chips; as well as
support fo r two PCMCIA or Com pact Flash slots

1.2.2 Clocks and Power Contr oller s

The PXA26x processor family fu nctional blocks are driven by clocks th at are derived from a

3.6864-MHz crystal and an optional 32.768-KHz crystal.

1-2 Intel® PXA26x P rocess or Family Deve loper’s Man ual

The 3.6864-MHz crystal drives a core phase locked loop (PLL) and a peripheral PLL. The PLLs
produce selected clock frequencies to run particula r functional bloc ks.

The 32.768-KHz crystal provides an optional clock source that must be selected after a hard reset.
This clock drives the real time clock, power managemen t controller, and interrupt controller. The

32.768-KHz crystal is on a separate power island to provid e an active clock while the proc essor is
in sleep mode.

Power management controls the transition between the turbo/run, idl e, and sleep operating modes.

1.2.3 Universal Ser ial Bu s (USB) Clien t

The USB client module is based on the U niversal Seria l Bus Specificat ion, Revision 1. 1. It suppor ts
up to sixteen endpoints and provi des an internally generated 48-MHz clock. The USB device
controller provides FIFOs with direct memory access (DMA) to or from memory.

1.2.4 Direct Memory Access Controller (DMAC)

The DMAC provide s sixteen prioritize d channels to service transf er requests from inte rnal
peripherals and up to two data transfer requests from extern al companion chips. The DMAC is
descriptor-based to allow command chaining and looping constructs.

Introduction

The DMAC operates in flow-through mode when per forming periph eral-to-memory, memory-to­peripheral, and memory-to-memory transfers. The DMAC is compatible with peripherals that us e
word, half-word, or byte data sizes.

1.2.5 Liquid Crystal Display (LCD) Controller

The LCD controller supports both passive (DSTN) and active (TFT) flat-panel displays with a
maximum recom mended resolution of 640x480x16-bit per pixel for 32 bit SDRAM bu ses, or
320x240x16-bit per pi xel for 16 bit SDRAM buses . An internal 256 entry palette expa nds 1, 2, 4,
or 8-bit encod e d pixels. Non-encoded 16-bit pixels bypass the palette.

Two dedicated DMA channels allow th e LCD Controller to support single- and dual-panel
displays. Pa ssive monochrome mo de supports up to 256 gr ay-scale levels and passive color mode
supports up to 64K colors. Active color mode supports up to 64K colors.

1.2.6 AC97 Controller

The AC97 controller su pports AC97 Revision 2.0 CODECs . These CODECs operate at s amp le
rates up to 48 KHz. The controller provides independent 16-bit channels for stereo pulse code
modulation (PCM) in, stereo PCM out, modem in, modem out, and mono microphone in. Each
channel includes a FIFO that support s DMA access to memory.

1.2.7 Inter-Integrated Circuit Sound (I2S) Controller

The I2S controller provides a seri al link to standard I2S CODECs for digital stereo sound. It
supports both the normal I
connection to an I
The controller includes FIFOs that support DMA access to memory.

Intel® PXA26x Processor Family Deve lo p er’s Manua l 1-3

2

2

S and MSB-justified I2S formats, and provides four signals for

S CODEC. I2S controller signals are multiplexed with AC97 contro ller pins.

Introduction

1.2.8 Multimedia Card (MMC) Controller

The MMC controlle r provides a serial interface to standard memory cards. The controller supports
up to two cards in either MMC or SPI modes with s e rial data transfer s up to 20 Mbps. The MMC
controller has FIFOs that support DMA access to and from memor y.

1.2.9 Fast Infrared (FIR) Communication Port

The FIR communication port is based on the 4-Mbps Infrare d Data Association (IrDA)
Specification. It operates at half-duplex and has FIFOs with DMA access to me mory . The F IR
communication por t uses the STUART’s transmit and receive pins to directly connect to external
IrDA LED transceivers.

1.2.10 Synchronous Serial Protocol Controller (SSPC)

The SSP port provides a full-duplex synchronous serial inte rf ace that operates at bit rates from

7.2 KHz to 1.84 MHz. It supports National Semicondu ctor’s Microwire*, Texas Instruments’
Synchronous Serial Protocol*, a nd Motorola’s Serial Peripheral Interface*. The SS PC has FIFOs
with DMA access to memory.

1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit

The I2C bus interface unit provides a general purpose 2-pin serial com mu nication port. The
interface uses one pin for data and address and a second pin for clocking.

1.2.12 General Purpose Input/Output (GPIO)

Each GPIO pin can be individually programmed as an output or an input. Inputs can cause
interrupts on rising or falling edges. Primary GPIO pins are not shared with peripherals while
secondary GPIO pins have alternate functions which can be mapped to the peripherals.

1.2.13 Universal Asynchronous Receiver/Transmitters (UARTs)

The processor provides three UARTs. Each UART can be used as a slow infrared (SIR) transmitter/
receiver based on the Inf rared Data Association Serial Infrared (SIR) Physical Layer Link
Specification. The three UARTs are (refer to Section 1.2.22, “Hardware UART (HWUART)” on

page 1-6 for a brief overview of the HWUART):

• Full Function UART (FFUAR T) – The FFUA RT baud rate is p rogr ammab le u p t o 921. 6 Kbps.

The FFUART provides a complete set of modem control pins: nCTS, nRTS, nDSR, nDTR,
nRI, and nDCD. It h as F IF Os with DMA access to or fr om memory.

• Bluetooth UART (BTUART) – The BTUART baud rate is programmable up to 921.6 Kbps.

The BTUART provides a partial set of modem control pins: nCTS and nRTS. Other modem
control pins can be implemented via GPIOs. The BTUART has FIFOs with DMA access to or
from memory.

• Standard UART (STUART) – The STUART baud rate is pr ogram mable up to 9 21.6 Kbps. The

STUART does not provide any modem control pins. The modem control pins can be
implemented via GPIOs. The ST UART has FIFOs with DMA access to or from memory.

1-4 Intel® PXA26x P rocess or Family Deve loper’s Man ual

The STUART’s transmit and receive pins are multiplexed with the fast infrared communication
port.

1.2.14 Real-Time Clock (RTC)

The R T C can be clocked from eit her the 3.6864-MHz crys tal or from an optional 32-KHz crysta l.
A system with a 32.768-KHz crystal consumes less power during sleep versus a system using only
the 3.6864-MHz crystal. The RTC provides a constant frequency output with a programmable
alarm register. This alarm register can be used to wake up the processor from sleep mode.

1.2.15 Operating System ( OS) Timers

The OS timers can be us ed to provide a 3. 68-MHz reference counter with four match registers.
When equal to t he ref erence cou nte r , the four mat ch r egist ers can be conf igured to ca use int errup ts.
One match regist er can be used to cause a watchdog reset.

1.2.16 Pulse-Wi dth Modulator (PWM)

The PWM has two independent outputs that can be programmed to drive two GPIOs. The
frequency and duty cycle are independen tly programmable. For exam ple, one GPIO can control
LCD contrast and the other LCD bri ghtness.

Introduction

1.2.17 Interrupt Controller

The interrupt controller directs the processor interrupts into the core’s interrupt request (IRQ) and
fast interrup t request (FIQ) inputs. The Mask Register enables or disables individual interrupt
sources.

1.2.18 Integrated Synchronous Flash

The synchron ous flash integr ated into some versions of the PXA26 x processor famil y is based on
the synchronous Intel St rataFlash® memory (K3). 128 Mbit or 256 Mbit of flash in a x16
configurat ion, and 256 Mbit of flash in a x32 configuration are available. This flash supports bus
frequencies as fas t as 66 MHz. This flash uses on e chip-select, nCS0.

1.2.19 Single-ended Universal Serial Bus Client interface

On the Intel® PXA26x Processor Family, a sing le-ended interface to an exter nal transceiver was
added which can be used ins tead of the differential interface.

The extra pins required are multiplexed on the AC97 s econd codec interface, MMC second card
chip select, and the FFUART. Multiplexing these pins with the FFUART lets you easily switch
between a USB interface or UART interface for a cradle.

Intel® PXA26x Processor Family Deve lo p er’s Manua l 1-5

Introduction

1.2.20 Network Synchronous Serial Protocol Port

The PXA26x processor family has an SSP port optim i zed for connection to other network AS ICs.
This NSSP adds a Hi-Z functi on to TXD, the abi lity to cont rol when Hi-Z occur s, and swappi ng the
TXD/RXD pins.

This port is not multiplexed with other interfaces.

1.2.21 Audio Synchronous Serial Protocol Port

The PXA26x processor family has an SSP port optimized for connection to audio ASICs. This
ASSP adds a Hi-Z fu nction to TXD and the ability to control when Hi-Z occurs.

This port is multiplexed on the same pins as the I

2

S port and the AC97 port.

1.2.22 Hardware UART (HWUART)

The PXA26x processor f amily has a UART with hardware flow control . The HWU ART provides a
partial set of modem control pi ns: nCTS and nRTS. These modem control pins provide full
hardware flow control. Other modem control pins can be implemented via GPIOs. The HWUART
baud rate is programmable as fast as 921.6 Kbps.

The HWUART’s pins are multiplexed wit h the PCMCIA control pins. Because of this, these
HWUART pins operate at the same voltage as the memory bus. Also, since the PCMCIA pin
nPWE is used for variable-lat ency input/output (VLIO), while using these pins for the HWUART,
VLIO is unavailable. The HW UART pins are also available over the BTUA RT pins. When
operating over the BTUA RT pins, the HWUART pins operate at the I/O voltage.

1-6 Intel® PXA26x P rocess or Family Deve loper’s Man ual

System Architecture 2

2.1 Overview

The Intel® PXA26x Processor Family is an integrated system-on-a-chip microprocessor for high
performance, low-power -portable handheld and handset devices. It incorporates the Intel®
XScale™ microarchitecture with on-the-fly frequency scaling and sophisticated power
management to provide industry lead ing MIPs/mW performance. The processor is ARM* Version
5TE instruction set compliant (excluding floating point instructions) and follows the A R M*
programmer’s model.

The processor memory interface supports a variety of memory types to allow design flexibility.
The PXA26x pro cessor family come s either without flash, or with 128- or 256-Mbit flash. As
many as two companion chips may be connected to members of the PXA26x processor family
which permits a glueless interface to external devices. An integrated LCD display controller
provides support for displays up to 320x240 pixels for platforms with 16-bit SDRAM bus,
640x480 pixels for version s with 32-bit SDRAM bus, and permits 1- , 2- , 4-, and 8-bit grays cale
and 8- or 16-bit color pixels. A 256 entry/512 byte palette RAM provides flexibility in color
mapping.

A set of serial devices and general system resources provide computational and connectivit y
capability for a variety of applications. Refer to Figure 2-1, “Block Diagram” on page 2-2 for an
overview of the microprocessor system architecture.

Intel® PXA26x Processor Family Deve lo p er’s Manua l 2-1

System Ar ch itecture

Figure 2-1. Block Diagram

RTC

OS Timer

PWM(2)

Int.

Controller

Clocks &

Power Man.

I2S

I2C

AC97
UART1
UART2

General Purpose I/O

Slow IrDA

Fast IrDA

SSP
USB

Client

MMC

NSSP
ASSP

HWUART

and Bridge

Peripheral Bus

DMA Controller

Color or

Grayscale

LCD

Controller

System Bus

(R)

Intel
Microarchitecure

3.6864
MHz

Osc

XScale

32.768
KHz
Osc

TM 

Memory

Controller

Variable

Latency I/O

Control

PCMCIA

& CF

Control

Dynamic
Memory

Control

Static

Memory

Control

Synchronous

Intel

StrataFlash

Memory

ASIC

XCVR

(R)

Socket 0
Socket 1

SDRAM/
SMROM

4 banks

ROM/
Flash/
SRAM

4 banks

2.2 Package Types

The PXA26x proces sor fa mily i s avail able in a 1 3x 13mm 294 -pin TF -BGA packa ge. It is availab le
in multiple versions with different flas h configuratio ns:

• PXA260 proces sor – No Intel StrataFlash® memory

• PXA261 proces sor – 128 megabit x 16 Intel StrataFlash® memory

• PXA262 proces sor – 256 megabit x 16 Intel StrataFlash® memory

• PXA263 proces sor – 256 megabit x 32 Intel StrataFlash® memory

Please contact your local Intel represent ative for details.
Software can detect the pr ocesso r version by check ing the flash si ze and configu ration. Info rmation

about the flash internal to the PXA26x processor family can be found in Section 18, “Internal

Flash”.

2-2 Intel® PXA26x P rocess or Family Deve loper’s Man ual

System Arch itecture

2.3 Intel® XScale™ Microarchitecture Implementation Options

The processor incorporates the Intel® XScale™ microarchitecture . This core contains
implementation options which an Application Specif ic Standard Product (ASSP) may elect to
implement or omit. This section descr ibes these options.

Most of these options are specified within the coprocessor registe r space. The processor does not
implement any coprocessor regis ters beyond those defined in the Intel® XScale™
Microarchitecture for the Intel® PXA255 Processor User’s Manual. The coprocessor registers
which are ASSP specific, as stated in the Intel® XScale™ Microarchitecture for the Intel®
PXA255 Processor User’s Manual, are defined in the following sections.

2.3.1 CPU Core Fault Register — PSFS Bit

Bit 5 of the Coprocessor 7 Register 4 – PSFS Bit, shown in Table 2-1, is defined as the Power
Source Fault Status (PSFS) bit. T his bit is set when either nVDD_FAULT or nBATT_FAULT pins
are asserted and the Imprecise Data Abort Enable (IDAE) bit in the Power Manager Control
Register (PMCR) is set.

This is a read-only register. Ignore reads fr om reserved bits.

Table 2-1. CPU Core Fault Register Bitmap

Coprocessor 7

Register 4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31:6] — Reserved

5 PSFS

[4:0] — Reserved

CPU Core Fault System Architecture

Reserved

POWER SOURC E FAULT STATUS:
0 – nVDD_FAULT or nBATT_FAULT pin has not been asserted since it was

last cleared by a reset or the CPU.

1 – nVDD_FAULT or nBATT_FAULT pin was asserted and PMCR[IDAE]

equals one.

Cleared by hardware, watchdog, and GPIO Resets.

PSFS

Reserved

2.3.2 Coprocessor 14 Registers 0-3 – Performance Monitoring

The processor does not define any pe rformance monitor ing features beyond those called out in the
Intel® XScale™ Micr o architecture for the Intel® PXA255 Processor User’s Manual. The interrupt
generated by per formance monitoring events is defined in Chapter 4, “System Integration Unit”.
The ASSP defined performan ce monitoring events (events 0x10 – 0x17), defined through the
PMNC register, are reserved for the processor.

Intel® PXA26x Processor Family Deve lo p er’s Manua l 2-3

System Ar ch itecture

2.3.3 Coprocessor 14 Register 6 and 7– Clock and Power
Management

These registers allo w software to use the clocking and power management mod es. The valid
operation s are desc rib ed i n Table 3-25, “Co pro cess or 14 Clo c k and Power Management Sum mary”

on page 3-40.

2.3.4 Coprocessor 15 Register 0 – ID Register Definition

The Coprocessor 15 regis ter may be read by software to determine the device type and revision.
The contents of this register for the PXA26x processor family is defined in the table below . This
register must read as 0x6 905 2X0R wh ere R = 0b0 01 1 for the f irst step pin g and then incre ments for
subsequent steppings, and X is the revision of the Intel® XScale™ microarchitecture present.
Please see the Intel® Developer Homepage at http://developer.intel.com for updates.

Table 2-2. ID Register Bitmap and Bit Definitions (Read-onl y) (S h eet 1 of 2)

CP15 Register 0 ID CP15

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

Trademark

Implementation

Reset 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 0 1 0 1

[31:16]

[23:16]

[15:13] Core Generation

[12:10] Core Revision

Implementation

Trademark

Architecture

Version

Version

Architecture

Implementation trademark.
0x69 – Intel® Corporation.

ARM* Architecture version of the core.
0x05 – ARM* architecture version 5TE

This field is updated when new sets of features are added to the core. This
allows software that is dependant on core features to target a specific core.

Core generation:
0b001 – Intel® XScale™ Core

This field is updated each time a core is revised. Differences may include
errata, software workarounds, etc.

Core revision:
0b000 – First version of the core
0b010 – Third version of the core
0b011 – Fourth ve rsion of the core

Core

generation

Core

Revision

Product

Number

Product

Revision

2-4 Intel® PXA26x P rocess or Family Deve loper’s Man ual

System Arch itecture

Table 2-2. ID Register Bi tmap and Bit Definitions (Read-only) (Sh eet 2 of 2)

CP15 Register 0 ID CP15

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Trademark

Implementation

Reset 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 0 1 0 1

[9:4] Product Number

[3:0] Product Revision

Version

Architecture

This field is specific to each ASSP.
Product Number
0b010000 = PXA26x processor family

This field tracks the different steppings for each ASSP.
Product Revision
0b0000 – Reserved
0b0001 – Reserved
0b0010 – Reserved
0b0011 – A0 Stepping
0b0101 – B0 Stepping
0b0110 – B1 Stepping

Core

Core

generation

Revision

Product

Number

Product

Revision

Table 2-3. PXA26x process o r fam ily ID Values

Stepping ARM* ID JTAG ID

A0 0x69052903 0x39264013
B0 0x69052D05 0x59264013
B1 0x69052D06 0x69264013

2.3.5 Coprocessor 15 Registe r 1 – P-Bi t

Bit 1 of this regis ter is defined as the Page T able Memory Attribute bit or P-bit. It is not
implemented in the processor and must be written as zero. Similarly, the P-bit in the page table
descriptor in the

Memory Management Unit (MMU) is not implemented and must be wr itten to

zero.

2.4 Input/Output Ordering

The processor uses queues that accept memory requests from th e three internal masters: core,
DMA controller, and LCD controller. Operations issued by a master are com pleted in the order
they were receiv ed. Operations from one master may be interrupted by operations from another
master. The processor does not provide a method to regulate the order of operations from different
masters.

Intel® PXA26x Processor Family Deve lo p er’s Manua l 2-5

System Ar ch itecture

Loads and stores to internal addresses are gen e rally completed more quickly than those issued to
external addresses . The difference in com pletion time allows one operation to be received before
another operati on, but completed af ter the second operation.

In the following sequ ence, the st ore to the addres s in r4 is complet ed befor e the sto re to the ad dress
in r2 because the first store waits for memory in the queue while the second is not de layed.

If the two stores are cont rol opera tions th at must be complet ed in order , the recommended s equence
is to insert a load to an unbuffered, uncached memory page followed by an operation that depends
on data from the lo ad:

str r1, [r2] ; store to external memory address [r2].
str r3, [r4] ; store to internal (on-chip ) me mo ry address [r4].

str r1, [r2] ; first store issued
ldr r5, [r6] ; load from external unbuffere d, uncached address ([r2] if possibl e)
mov r5, r5 ; nop stalls until r5 is lo aded
str r3, [r4] ; second store compl etes in program order

2.5 Semaphores

The Swap (SWP) and Swap Byte (SWPB) instructions, as described in the ARM* architectu re
reference, may be us ed for semaphore manipulation. No on-c hip master or process can access a
memory location be tween the load and store port ion of a SWP or SWPB to the same locat ion.

Note: Semaphore coherency may be interrupted because an exter nal companion chip that us es th e

MBREQ/MBGNT handshake can take ownership of the bus during a locked sequence. To allow
semaphore manipulation by external companion chips, the software must manage coherency.

2.6 Interrupts

The interrupt con troller is described in detail in Section 4.2, “Interrupt Controller”. A ll on-chip
interrupts are enabled, masked, and routed to the core fast interrupt request (FIQ) or interrupt
request (IRQ). Each interrupt is enabled or disabled at the source through an interrupt mask bit.
Generally, all interrupt bits in a unit are ORed to gether and present a sing le value to the interrupt
controller.

Each interrupt goes through the Interrupt Controller Mask Register and then the Interrupt
Controller Level Register directs the interrupt into either the IRQ or FIQ. If an interrupt is taken,
the software may read the Interrupt Controller Pending Register to identify the source. After it
identifies the interrupt source, the software is responsible for ser vicing the interrupt and clearing it
in the source unit before exiting the serv ice routine.

2-6 Intel® PXA26x P rocess or Family Deve loper’s Man ual

System Arch itecture

Note: Clearing interrupts may take a delay. To allow the status bit to clear before returning from an

interrupt service routine (ISR), clear the interrupt early in the routine.

2.7 Reset

Table 2-4 shows each pin’s state after each type of reset.

Table 2-4. Effect of Each Type of Reset on Internal Register State

Unit Sleep Mode GPIO Reset Watchdog Reset Hard Reset

Core reset reset reset reset

Memory Controller reset

LCD Controller reset reset reset reset
DMA Controller reset reset reset reset
Full Function UART reset reset reset reset
Bluetooth UART reset reset reset reset
Standard UART reset reset reset reset
Hardware UART reset reset res et reset

2

I

C reset reset reset reset

2

I

S reset reset reset reset
AC97 reset reset reset reset
USB reset reset reset reset
ICP reset reset reset reset
RTC preserved preserved reset (except RTTR) reset
OS Timer reset reset reset reset
PWM reset reset reset reset
Interrupt Controller reset reset reset reset
GPIO reset reset reset reset
Power Manager preserved reset reset reset
SSP reset reset reset reset
Network SSP reset reset reset reset
Audio SSP reset reset reset reset
MMC reset reset reset reset
Clocks preserved (except CP14) preserved (except CP14) reset (except OSCC) reset

All registers except
configuration registers
(refresh maintained)

reset reset

2.8 Internal Registers

All internal regis ters are mapped in phys ical memory space on 32-bit address boundaries. Use
word access loads and stores to access internal registers. Internal regist er space must be m a pped as
non-cacheable.

Intel® PXA26x Processor Family Deve lo p er’s Manua l 2-7

System Ar ch itecture

Byte and halfword accesses to internal registers are not permitted and yield unpredictable results.
Register space, where a register is not specifically mapped, is defined as reserved space. Reading

or writing reserved space causes unpredictable results.
The processor does no t use all register bit locations. The unused bit locations are marked reserved

and are allocated f or f uture use. Write reserved bit locatio ns as z ero s. Ign ore th e va lues of th ese bi ts
during reads because their states are unpredictable.

2.9 Selecting Peripherals vs. General Purpose Input/ Output

Most peripherals connect to the extern al pins through GPIOs. T o use a peripheral connected
through a GPIO, the software must first confi gure the GPIO so that the desired peripheral is
connected to its pi ns. The default state for most of the pins is GPI O inputs. Some of the GPI Os
default to their alternate functio n and do not need to be configured for use.

T o allocate a peripheral to a pin, disable the GPIO function for that pin, then map the peripher al
function onto the pin by selecting the proper alternate function for the pin. Some GPIOs have
multiple alternate f unctions. After a function is selected for a pin, all other functions are excluded.
For this reason some periph era ls are mapped to mu ltiple GP IOs, as show n in Section 4.1.2, “GPIO

Alternate Functions” on page 4-3. Multiple mapping does not mean multiple instances of a

peripheral – only that the peripheral is connected to the pins in several ways.

2.10 P ower on Reset and Boot Operation

Before the device using the processor is powered on, the system must assert nRESET and nTRST.
To allow the internal clocks to stabilize, all power supplies must be stab le for a specified period
before nRESET or nTRST are deasser ted. When nRESET is asserted, nRESET_OUT is driven
active and can be used to reset other devices in the system. For additional information, see the

Intel® PXA26x Processor Family Design Guide.

When the system deasserts nRESET and nTRST, the processor deasserts nRESET_OUT a
specified time later and the device attempts to boot from phys ical address location 0x0000 0000,
located in flash.

The BOOT_SEL[2:0] pins are sampled when reset is deasserted. The PXA26x processor family
version defi nes the BOOT_SEL[2:0] pins configuration.

2.11 Power Management

The processor offers a number of modes to manage system powe r. These range widely in level of
power savings and level of function a lity. These modes are supported:

• Turbo mode – lo w latency (nanoseconds) switch between two preprogrammed frequencies

• Run mode – normal full function mode

• Idle mode – core clocks are stopped – resume through an interrupt

2-8 Intel® PXA26x P rocess or Family Deve loper’s Man ual

• Sleep mode – low pow er mode that does not save state but keeps I/Os powered. While the

RTC , power manager, and clock mo dule states are saved, coprocessor 14 is not.

Note: In low power modes, ensure th at input pins are not floating and output pins are not driven by an

external device in conflict with how the processor is driving th at pin. In either case, the syst em
draws excess current . Current draw that varies in sl eep mode or varies greatly between parts is
typically a sign of floating pins.

Section 3.4, “Resets and Pow er Modes” describes the modes in detail.

2.12 Pin List

Some of the processor pin s can be connected to mu ltiple s ignals . The signal conn ected to the pin is
determined by the G PI O Alternate Function Select Registers (GAFRn_m). Some signals can be
connected to mu ltiple pins. The signal must be routed to only one pin by using the GAF Rn_m
registers. Because this is true, some pins are listed twice, once in each unit that can use the pin.

Table 2-5. Processor Pin Types

Type Function

System Arch itecture

IC C M OS input
OC CMOS output
OCZ CMOS output, Hi-Z
ICOCZ CMOS bidirectional, Hi-Z
IA Analog input
OA Analog output
IAOA Analog bidirectional
SUP Supply pin (either VCC or VSS)

Table 2-6 describ e s the PXA26x proces sor family pins .

Table 2-6. Pin & Signal Descriptions fo r the PXA26x Pr o cessor Family (Sheet 1 of 12)

Pin Name Type Signal Descriptions Reset State Sleep State

Memory Controller Pins

MA[25:0] OCZ

MD[15:0] ICOCZ

MD[31:16] ICOCZ

nOE OCZ

nWE OCZ

MEMORY ADDR ESS BUS (output):
Signals the address requested for memory accesses.

MEMORY DATA BUS (input/output):
Lower 16 bits of the data bus.

MEMORY DATA BUS (input/output):
Used for 32-bit memories.

MEMORY OUTPUT ENABLE (output):
Connect to the output enables of memory devices to

control data bus drivers.
MEMORY WRITE EN ABLE (output):

Connect to the write enables of memory devices.

Driven Low Driven Low

Hi-Z Driven Low

Hi-Z Driven Low

Driven High Note [4]

Driven High Note [4]

Intel® PXA26x Processor Family Deve lo p er’s Manua l 2-9

System Ar ch itecture

Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 2 of 12)

Pin Name Type Signal Descriptions Reset State Sleep State

nSDCS[0] OCZ
nSDCS[1] OC Driven High Driven High
nSDCS[2]/

GPIO[86]
nSDCS[3]/

GPIO[87]

DQM[3:0] OCZ

nSDRAS OCZ

nSDCAS OCZ

SDCKE[0] OC

SDCKE[1] OC

SDCLK[0] OC

SDCLK[1]

SDCLK[2] OC Driven Low Driven Low

ICOC

ICOC

OCZ

SDRAM CS FOR BANKS 0 THROUGH 3 (output):
Connect to the chip select (CS) pins for SDRAM. For the

PXA26x processor family nSDCS0 can be Hi-Z, nSDCS1­3 cannot.

SDRAM DQM FOR DATA BYTES 3 T H ROUGH 0 (output ) :
Connect to the data output mask enables (DQM) for

SDRAM.
SDRAM RAS (outp ut):

Connect to the row address strobe (RAS) pins for all
banks of SDRAM.

SDRAM CAS (outp ut):
Connect to the column address strobe (CAS) pins for all

banks of SDRAM.
Synchronous Static Memory clock enable (output):

Connect to the CKE pins of SMROM. The memory
controller provides control register bits for deassertion.

SDRAM OR SYNCHRONOUS ST A TIC MEMORY CLOCK
ENABLE (output):

Connect to the clock enable pins of SDRAM. It is
deasserted during sleep. SDCKE[1] is always deasserted
upon reset. The memory controller provides control
register bits for deassertion.

SYNCHRONO US STATIC MEMORY CLOCK (output):
Connect to the clock (CLK) pins of SMROM. It is driven by

either the internal memory controller clock, or the internal
memory controller clock divided by 2. At reset, all clock
pins are free running at the divide by 2 clock speed and
may be turned off via free running control register bits in
the memory controller. The memory controller also
provides control register bits for clock division and
deassertion of each SDCLK pin. SDCLK[0] control regis ter
assertion bit defaults to on if the boot-time static memory
bank 0 is configured for SMROM.

SDRAM CLOCKS (o utput):
Connect SDCLK[1] and SDCLK[2] to the clock pins of

SDRAM in bank pairs 0/1 and 2/3, respectively. They are
driven by either the int ernal memory controll er cloc k, or the
internal memory controller clock divided by 2. At reset, all
clock pins are free running at the divide by 2 clock speed
and may be turned off via free running control register bits
in the memory controller. The memory controller also
provides control register bits for clock division and
deassertion of each SDCLK pin. SDCLK[2:1] control
register assertion bits are always deasserted upon reset.

Driven High Driven High

Driven High (but see
Note[8])

Driven High (but see
Note[8])

Driven Low Driven Low

Driven High Driven High

Driven High Driven High

Driven Low Driven Low

Driven Low Driven Low

Driven Low

Driven High (but
see Note [8])

Driven High (but
see Note [8])

Driven Low

2-10 Inte l® PXA26x P rocesso r Family Deve loper’s Man ual

System Arch itecture

Table 2-6. Pin & Signal Descriptions fo r the PXA26x Pr o cessor Family (Sheet 3 of 12)

Pin Name Type Signal Descriptions Reset State Sleep State

nCS[5]/
GPIO[33]

nCS[4]/
GPIO[80]

nCS[3]/
GPIO[79]

nCS[2]/
GPIO[78]

nCS[1]/
GPIO[15]

nCS[0] ICOCZ

RD/nWR/
GPIO[88]

RDY/
GPIO[18]

L_DD[8]/
GPIO[66]

L_DD[15]/
GPIO[73]

MBGNT/GP[13] ICOCZ

MBREQ/GP[14] ICOCZ

PCMCIA/CF Control Pins
nPOE/

GPIO[48]

nPWE/
GPIO[49]

nPIOW/
GPIO[51]

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

OCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

STATIC CHIP SELECTS (output):
Chip selects to static memory devices such as ROM and

flash. Individually programmable in the memory
configuration registers. nCS[5:0] can be use d with variable
latency I/O devices.

STATIC CHIP SELECT 0 (output):
Chip select for the boot memory. nCS[0] is a dedicated pin

used for internal flash.
READ/WRITE FOR STATIC INTERFACE (output):

Signals that the current transaction is a read or write.
VARIABLE LATENCY I/O READY PIN (input):

Notifies the memory controller when an external bus
device is ready to transfer data.

LCD DISPLAY DATA (output):
Transfers pixel information from the LCD Controller to the

external LCD panel.
Memory Controller alternate bus master request. (input)

Allows an external device to request the system bus from
the Memory Controller.

LCD DISPLAY DATA (output):
Transfers pixel information from the LCD Controller to the

external LCD panel.
Memory Controller grant. (output) Notifies an external

device that it has been granted the system bus.
MEMORY CONTROLLER GRANT (output):

Notifies an external device that it has been granted the
system bus.

MEMORY CONTROLLER ALTERNATE BUS MASTER
REQUEST (input):

Allows an external device to request the system bus from
the Memory Controller.

PCMCIA OUTPUT ENABLE (output):
Reads from PCMCIA memory and to PCMCIA attribute

space.
PCMCIA WRITE ENABLE (output):

Performs writes to PCMCIA memory and to PCMCIA
attribute space. Also used as the write enable signal for
Variable Latency I/O.

PCMCIA I/O WRITE (output):
Performs write transactions to PCMCIA I/O space.

Pulled High
Note [1]

Driven High Note [4]

Driven Low
(but see Note[8])

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Note [4]

Driven High (but
see Note[8])

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [5]

Note [5]

Note [5]

Intel® PXA26x Processor Family Deve lo p er’s Manua l 2-11

System Ar ch itecture

Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 4 of 12)

Pin Name Type Signal Descriptions Reset State Sleep State

nPIOR/
GPIO[50]

nPCE[2]/
GPIO[53]

nPCE[1]/
GPIO[52]

nIOIS16/
GPIO[57]

nPWAIT/
GPIO[56]

PSKTSEL/
GPIO[54]

nPREG/
GPIO[55]

LCD Controller Pins
L_DD(7:0)/

GPIO[65:58]

L_DD[8]/
GPIO[66]

L_DD[9]/
GPIO[67]

L_DD[10]/
GPIO[68]

L_DD[11]/
GPIO[69]

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

PCMCIA I/O READ (output):
Performs read transactions from PCMCIA I/O space.

PCMCIA CARD ENABLE 2 (output):
Selects a PCMCIA card. nPCE[2] enables the high byte

lane and nPCE[1] enables the low byte lane.
MMC clock. (output) Clock signal for the MMC Controller.

PCMCIA CARD ENABLE 1 (outputs):
Selects a PCMCIA card. nPCE[2] enables the high byte

lane and nPCE[1] enables the low byte lane.
IO SELECT 16 (input):

Acknowledge from the PCMCIA card that the current
address is a valid 16 bit wide I/O address.

PCMCIA WAIT (input):
Driven low by the P CMCIA c ard to extend the length of the

transfers to/from the PXA26x processor family.
PCMCIA SOCKET SELECT (output):

Used by external steering logic to route control, address,
and data signals to one of the two PCMCIA sockets. When
PSKTSEL is low, socket zero is selected. When PSKTSEL
is high, socket one is selected. Has the same timing as the
address bus.

PCMCIA REGISTER SEL ECT (output):
Indicates that the target address on a memory transaction

is attribute space. Has the same timing as the address
bus.

LCD DISPLAY DATA (outputs):
Transfers pixel information from the LCD Controller to the

external LCD panel.
LCD DISPLAY DATA (output):

Transfers pixel information from the LCD Controller to the
external LCD panel.

Memory Controller alternate bus master request. (input)
Allows an external device to request the system bus from
the Memory Controller.

LCD DISPLAY DATA (output):
Transfers pixel information from the LCD Controller to the

external LCD panel.
MMC chip select 0. (output) Chip select 0 for the MMC

Controller.
LCD DISPLAY DATA (output):

Transfers pixel information from the LCD Controller to the
external LCD panel.

MMC chip select 1. (output) Chip select 1 for the MMC
Controller.

LCD DISPLAY DATA (output):
Transfers pixel information from the LCD Controller to the

external LCD panel.
MMC clock. (output) Clock for the MMC Controller.

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Note [5]

Note [5]

Note [5]

Note [5]

Note [5]

Note [5]

Note [5]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

2-12 Inte l® PXA26x P rocesso r Family Deve loper’s Man ual

System Arch itecture

Table 2-6. Pin & Signal Descriptions fo r the PXA26x Pr o cessor Family (Sheet 5 of 12)

Pin Name Type Signal Descriptions Reset State Sleep State

LCD DISPLAY DATA (output):

L_DD[12]/
GPIO[70]

L_DD[13]/
GPIO[71]

L_DD[14]/
GPIO[72]

L_DD[15]/
GPIO[73]

L_FCLK/
GPIO[74]

L_LCLK/
GPIO[75]

L_PCLK/
GPIO[76]

L_BIAS/
GPIO[77]

Full Function UART Pins
FFRXD/

GPIO[34]

FFTXD/
GPIO[39]

FFCTS/
GPIO[35]

FFDCD/
GPIO[36]

FFDSR/
GPIO[37]

FFRI/
GPIO[38]

FFDTR/
GPIO[40]

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ FULL FUNCT ION UART CLEAR-TO-SEND (input)

ICOCZ

ICOCZ FULL FUNCTION UART DATA-SET-READY (input)

ICOCZ FULL FUNCTION UART RING INDICATOR (input)

ICOCZ

Transfers pixel information from the LCD Controller to the
external LCD panel.

RTC clock. (output) Real time clock 1 Hz tick.
LCD DISPLAY DATA (output):

Transfers pixel information from the LCD Controller to the
external LCD panel.

3.6864-MHz clock. (output) Output from 3.6864-MHz
oscillator.

LCD DISPLAY DATA (output):
Transfers pixel information from the LCD Controller to the

external LCD panel.
32-KHz clock. (output) Output from the 32-KHz oscillator.

LCD DISPLAY DATA (output):
Transfers pixel information from the LCD Controller to the

external LCD panel.
Memory Controller grant. (output) Notifies an external

device it has been granted the system bus.
LCD FRAME CLOCK (output):

Indicates the start of a new frame. Also referred to as
Vsync.

LCD LINE CLOCK (output):
Indicates the start of a new line. Also referred to as Hsync.

LCD PIXEL CLOCK (output):
Clocks valid pixel data into the LCD’s line shift buffer.

AC BIAS DRIVE (outp ut):
Notifies the panel to change the polarity for some passive

LCD panel. For TFT pane ls, this signal indicates valid pixel
data.

FULL FUNCTION UART RECEIVE (input):
MMC chip select 0. (output) Chip select 0 for the MMC

Controller.
FULL FUNCTION UART TRANSMIT (output):

MMC chip select 1. (output) Chip select 1 for the MMC
Controller.

FULL FUNCTION UART DATA-CARRIER-DETECT
(input)

FULL FUN CT ION UART DATA-TERMINAL-READY
(output)

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Intel® PXA26x Processor Family Deve lo p er’s Manua l 2-13

System Ar ch itecture

Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 6 of 12)

Pin Name Type Signal Descriptions Reset State Sleep State

FFRTS/
GPIO[41]

Bluetooth UART Pins
BTRXD/

GPIO[42]
BTTXD/

GPIO[43]
BTCTS/

GPIO[44]
BTRTS/

GPIO[45]
Standard UART and ICP Pins

IRRXD/
GPIO[46]

IRTXD/
GPIO[47]

MMC Controller Pins
MMCMD ICOCZ MULTIMEDIA CARD COMMAND (bidirectional) Hi-Z Hi-Z
MMDAT ICOCZ MULTIMEDIA CARD DATA (bidirectional) Hi-Z Hi-Z

nPCE[2]/
GPIO[53]

L_DD[9]/
GPIO[67]

L_DD[10]/
GPIO[68]

L_DD[11]/
GPIO[69]

FFRXD/
GPIO[34]

ICOCZ FULL FUNCTION UART REQUEST-TO-SEND (output):

ICOCZ BLUETOOTH UART RECEIVE (input):

ICOCZ BLUETOOTH UART TRANSMIT (output):

ICOCZ BLUETOOTH UART CLEAR-TO-SEND (input):

ICOCZ BLUETOOTH UART DATA-TERMINAL-READY (output):

IRDA RECEIV E SI GNAL (input):

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

Receive pin for the FIR function.
STANDARD UART RECEIVE (input)

IRDA TRANSMIT SIGNAL (output):
Transmit pin for the Standard UART, SIR and FIR

functions.
STANDARD UART TRANSMIT (output)

PCMCIA CARD ENABLE 2 (outputs):
Selects a PCMCIA card. Bit one enables the high byte

lane and bit zero enables the low byte lane.
MMC clock. (output) Clock signal for the MMC Controller.

LCD DISPLAY DATA (output):
Transfers pixel information from the LCD Controller to the

external LCD panel.
MMC CHIP SELECT 0 (output):
Chip select 0 for the MMC Controller.

LCD DISPLAY DATA (output):
Transfers pixel information from the LCD Controller to the

external LCD panel.
MMC CHIP SELECT 1 (output):
Chip select 1 for the MMC Controller.

LCD DISPLAY DATA (output):
Transfers pixel information from the LCD Controller to the

external LCD panel.
MMC CLOCK (output):
Clock for the MMC Controller.

FULL FUNCTION UART RECEIVE (input)
MMC CHIP SELECT 0 (output):
Chip select 0 for the MMC Controller.

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [5]

Note [3]

Note [3]

Note [3]

Note [3]

2-14 Inte l® PXA26x P rocesso r Family Deve loper’s Man ual

System Arch itecture

Table 2-6. Pin & Signal Descriptions fo r the PXA26x Pr o cessor Family (Sheet 7 of 12)

Pin Name Type Signal Descriptions Reset State Sleep State

FFTXD/
GPIO[39]

MMCCLK/GP[6] ICOCZ

MMCCS0/GP[8] ICOCZ

MMCCS1/GP[9] ICOCZ

SSP Pins
SSPSCLK/

GPIO[23]
SSPSFRM/

GPIO[24]
SSPTXD/

GPIO[25]
SSPRXD/

GPIO[26]
SSPEXTCLK/

GPIO[27]
USB Client Pins
USB_P IAOAZ USB CLIENT POSITIVE (bidirectional) Hi-Z Hi-Z
USB_N IAOAZ USB CLIENT NEGATIVE PIN (bidirectional) Hi-Z Hi-Z
Single Ended USB Pins

USB_RCV/
GPIO[9]

USB_VP/
GPIO[32]

USB_VM/
GPIO[34]

USB_VPO/
GPIO[39]

USB_VMO/
GPIO[56]

USB_nOE/
GPIO[57]

ICOCZ

ICOCZ SYNCHRONOUS SERIAL PORT CLOCK (output)

ICOCZ SYNCHRONOUS SERIAL PORT FRAME (output)

ICOCZ SYNCHRONOUS SERIAL PORT TRANSMIT (output)

ICOCZ SYNCHRONOUS SERIAL PORT RECEIVE (input)

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

FULL FUNCTION UART TRANSMIT (output)
MMC CHIP SELECT 1 (output):
Chip select 1 for the MMC Controller.

MMC CLOCK (output):
Clock signal for the MMC Controller.

MMC CHIP SELECT 0 (output):
Chip select 0 for the MMC Controller.

MMC CHIP SELECT 1 (output):
Chip select 1 for the MMC Controller.

SYNCHRONOUS SERIAL PORT EXTERNAL CLOCK
(input)

USB CLIENT SINGLE-ENDED INTERFACE RCV (input):
Differential receive data from the USB transceiver.

USB CLIENT SINGLE-ENDED INTERFACE VP (input):
Gated version of D+ from the USB transceiver.

USB CLIENT SINGLE-ENDED INTERFACE VM (input):
Gated version of D- from the USB transceiver.

USB CLIENT SINGLE-ENDED INTERFACE VPO
(output):

Output to USB transceiver differential driver D+.
USB CLIENT SINGLE-ENDED INTERFACE VMO

(output):
Output to USB transceiver differential driver D-.

USB CLIENT SINGLE-END ED INTERFAC E n OE (output):
Output enable for the USB transceiver to transmit data on

the bus. When deasserted, the transceiver is in receive
mode.

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Intel® PXA26x Processor Family Deve lo p er’s Manua l 2-15

System Ar ch itecture

Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 8 of 12)

Pin Name Type Signal Descriptions Reset State Sleep State

AC97 Controller and I2S Controller Pins

AC97 AUDIO PORT BIT CLOCK (input):
AC97 clock is generated by Codec 0 and fed into the

PXA26x processor family and Codec 1.

AC97 AUDIO PORT BIT CLOCK (output):
BITCLK/
GPIO[28]

SDATA_IN0/
GPIO[29]

SDATA_IN1/
GPIO[32]

SDATA_OUT/
GPIO[30]

SYNC/
GPIO[31]

nACRESET/
GPIO[89]

I2C Controller Pins
SCL ICOCZ I2C CLOCK (bidirectional) Hi-Z Hi-Z
SDA ICOCZ I2C DATA (bidirectional). Hi-Z Hi-Z
PWM Pins
PWM[1:0]/

GPIO[17:16]
DMA Pins

DREQ[1:0]/
GPIO[19:20]

GPIO Pins

GPIO[1:0] ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOCZ

ICOC AC97 AUDIO PORT RESET SIGNAL (output)

ICOCZ

ICOCZ

AC97 clock is generated by the PXA26x processor family.

I2S BIT CLOCK (input):

I2S clock is generated externally and fed into PXA26x

processor family.

I2S BIT CLOCK (output):

I2S clock is generated by the PXA26x processor family.

AC97 AUDIO PORT DATA IN (input):

Input line for Codec 0.

I2S DATA IN (input):

Input line for the I2S Controller.

AC97 AUDIO PORT DATA IN (input):

Input line for Codec 1.

I2S SYSTEM CLOCK (o utput):

System clock from I2S Controller.

AC97 AUDIO PORT DATA OUT (output):

Output from the PXA26x processor family to C odecs 0 and

1.

I2S DATA OUT (output):

Output line for the I2S Controller.

AC97 AUDIO PORT SYNC SIGNAL (output):

Frame sync signal for the AC97 Controller.

I2S SYNC (output):

Frame sync signal for the I2S Controller.

PULSE WIDTH MODULATION CHANNELS 0 AND 1

(outputs)

DMA REQUEST (input):

Notifies the DMA Controller that an external device

requires a DMA transaction. DREQ[1] is GPIO[19].

DREQ[0] is GPIO[20].

GENERAL PURPOSE I/O:

Walk-up sources on both rising and falling edges on

nRESET.

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Driven Low
(but see Note[8])

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Driven Low (but see
Note[8])

Note [3]

Note [3]

Note [3]

2-16 Inte l® PXA26x P rocesso r Family Deve loper’s Man ual

System Arch itecture

Table 2-6. Pin & Signal Descriptions fo r the PXA26x Pr o cessor Family (Sheet 9 of 12)

Pin Name Type Signal Descriptions Reset State Sleep State

GPIO[14:2] ICO CZ

GPIO[22:21] ICOCZ

GPIO[85] ICOCZ

Crystal and Clock Pins

PXTAL OA

PEXTAL IA

TXTAL OA

TEXTAL IA

L_DD[12]/
GPIO[70]

L_DD[13]/
GPIO[71]

L_DD[14]/
GPIO[72]

48MHz/GP[7] ICOCZ

RTCCLK/GP[10] ICOCZ

3.6MHz/GP[11] ICOCZ

32KHz/GP[12] ICOCZ

ICOCZ

ICOCZ

ICOCZ

GENERAL PURPOSE I/O:
More wake-up sources for sleep mode.

GENERAL PURPOSE I/O:
Additional General Purpose I/O pins.

GENERAL PURPOSE I/O:
Additional General Purpose I/O pins.

3.6864-MHz CRYSTAL OUTPUT:
No external caps are required.

3.6864-Mhz CRYSTAL INPUT:
No external caps are required.

32.768-Khz CRYSTAL OUTPUT:
No external caps are required.

32.768-Khz CRYSTAL INPUT:
No external caps are required.

LCD DISPLAY DATA (output):
Transfers pixel information from the LCD Controller to the

external LCD panel.
RTC CLOCK (output):
Real time clock 1Hz tick.

LCD DISPLAY DATA (output):
Transfers the pixel information from the LCD Controller to

the external LCD panel.

3.6864-MHz CLOCK (output):
Output from 3.6864-MHz oscillator.

LCD DISPLAY DATA (output):
Transfers pixel information from the LCD Controller to the

external LCD panel.
32-KHz CLOCK (output):
Output from the 32-KHz oscillator.

48-MHz CLOCK (output):
Peripheral clock output derived from the PLL.

NOTE: This clock is only generated when the USB unit

clock enable is set.

REAL TIME CLOCK (output):
1-Hz output derived from the 32-KHz or 3.6864-MHz

output.

3.6864-MHz CLOCK (output):
Output from 3.6864-MHz oscillator.

32-KHz CLOCK (output):
Output from the 32-KHz oscillator.

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Note [2] Note [2]

Note [2] Note [2]

Note [2] Note [2]

Note [2] Note [2]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Intel® PXA26x Processor Family Deve lo p er’s Manua l 2-17

System Ar ch itecture

Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 10 of 12)

Pin Name Type Signal Descriptions Reset State Sleep State

Miscellaneous Pins

BOOT_SEL
[2:0]

PWR_EN OC

nBATT_FAULT IC

nVDD_FAULT IC

nRESET IC

nRESET_OUT OC

JTAG and Test Pins

nTRST IC

TDI IC

TDO OCZ

IC

BOOT SELECT PINS (input):

Indicates type of boot device. See Section 18.1,

“Initialization” for information on configuring BOOT_SEL

for proper flash initialization.

POWER ENABLE FOR THE POWER SUPPLY (output):

When negated, it signals the power supply to remove

power to the core because the system is entering sleep

mode.

MAIN BATTERY FAULT (input):

Signals that main battery is low or removed. Assertion

causes PXA26x processor family to enter sleep mode or

force an imprecise data exception, which cannot be

masked. PXA26x processor family will not recognize a

wake-up event while this signal is asserted. Minimum

assertion time for nBATT_FAULT is 1 ms.

VDD FAULT (input):

Signals that the main power source is going out of

regulation. nVDD_FAULT causes the PXA26x processor

family to enter sleep mode or force an Imprecise Data

Exception, which cannot be masked. nVDD_FAULT is

ignored after a wake-up event until the power supply tim er

completes (ap proximate ly 10 ms ). Mini mum asser tion time

for nVDD_FAULT is 1 ms.

HARD RESET (input):

Level sensitive input used to start the processor from a

known address. Asserti on causes the c urrent instruc tion to

terminate abnormally and causes a reset. When nRESET

is driven high, the processor start s execution from address

0. nRESET must remain low until the power supply is

stable.

RESET OUT (output):

Asserted when nRESET is asserted and deasserts after

nRESET is deasserted but before the first instruction

fetch. nRESET_OUT is also asserted for “soft” reset

events: sleep, watchdog reset, or GPIO reset.

JTAG TEST INTERFACE RESET:

Resets the JTAG/D ebug port. If JTAG/Debug is used,

drive nTRST from low to high either before or at the same

time as nRESET. If JTAG is not used, nTRST must be

either tied to nRESET or tied low.

JTAG TEST DATA INPUT (input):

Data from the JTAG controller is sent to the PXA26x

processor family using this pin. This pin has an internal

pull-up resistor.

JTAG TEST DATA OUTPUT (output):

Data from the PXA26x processor family is returned to the

JTAG controller using this pin.

Input Input

Driven low while

Driven High

Input Input

Input Input

Input

Driven low during
any reset sequence –
driven high prior to
first fetch.

Input Input

Input Input

Hi-Z Hi-Z

entering sleep
mode. Driven high
when sleep exit
sequence begins.

Input. Driving low
during sleep will
cause normal reset
sequence and exit
from sleep mode.

Driven Low

2-18 Inte l® PXA26x P rocesso r Family Deve loper’s Man ual

System Arch itecture

Table 2-6. Pin & Signal Descriptions fo r the PXA26x Pr o cessor Family (Sheet 11 of 12)

Pin Name Type Signal Descriptions Reset State Sleep State

JTAG TEST MODE SELECT (input):

TMS IC

TCK IC

TEST IC

TESTCLK IC

Power and Ground Pins

VCC SUP

VSS SUP

PLL_VCC SUP

PLL_VSS SUP

VCCQ SUP

VSSQ SUP

VCCN SUP

VSSN SUP

Network SSP pins
NSSPSCLK/

GPIO[81]
NSSPSFRM/

GPIO[82]
NSSPTXD/

GPIO[83]
NSSPRXD/

GPIO[84]
Audio SSP Pins
ASSPSCLK/

GPIO[28]

ICOCZ NETWORK SYNCHRONOUS SERIAL PORT CLOCK

ICOCZ

ICOCZ NETWORK SYNCHRONOUS SERIAL PORT TRANSMIT

ICOCZ NETWORK SYNCHRONOUS SERIAL PORT RECEIVE

ICOCZ AUDIO SYNCHRONOU S SERIAL PORT CLO CK

Selects the test mode required from the JTAG controller.
This pin has an internal pull-up resistor.

JTAG TEST CLOCK (input):
Clock for all transfers on the JTAG test interface.

TEST MODE (input):
Reserved. Must be grounded.

TEST CLOCK (inp ut) :
Reserved. Must be grounded.

INTERNAL LOGIC POSITIVE SUPPLY:
Must be connected to the low voltage (.85 – 1.3v) supply

on the PCB.
INTERNAL LOGIC GROUND SUPPLY:

Must be connected to the common ground plane on the
PCB.

PLLS AND OSCILLATORS POSITIVE SUPPLY:
Must be connected to the common low voltage supply.

PLL GROUND SUPPLY:
Must be connected to common ground plane on the PCB.

CMOS I/O POSITIVE SUPPLY:
EXCEPT memory bus and PCMCIA pins. Must be

connected to the common 2.775 – 3.3v supply on the
PCB.

CMOS I/O GROUND SUPPLY:
Except memory bus and PCMCIA pins. Must be

connected to the common ground plane on the PCB.
MEMORY BUS AN D PCMCIA PINS POSITIVE SUPPLY:

Must be connected to the common 2.5 – 3.3v supply on
the PCB.

MEMORY BUS AND PCMCIA PINS GROUND SUPPLY:
Must be connected to the common ground plane on the

PCB.

NETWORK SYNCHRONOUS SER IAL PORT FRAME
SIGNAL

Input Input

Input Input

Input Input

Input Input

Powered Note [6]

Grounded Grounded

Powered Note [6]

Grounded Grounded

Powered Note [7]

Grounded Grounded

Powered Note [7]

Grounded Grounded

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Intel® PXA26x Processor Family Deve lo p er’s Manua l 2-19

System Ar ch itecture

Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 12 of 12)

Pin Name Type Signal Descriptions Reset State Sleep State

ASSPSFRM/
GPIO[31]

ASSPTXD/
GPIO[30]

ASSPRXD/
GPIO[29]

HWUART Pins
HWTXD/

GPIO[48]
HWRXD/

GPIO[49]
HWCTS/

GPIO[50]
HWRTS/

GPIO[51]
Internal flash pins (See Section 18, “Internal Flash” for more information)

nRST_F IC

nWP_F IC

VPEN_F IC

WAIT_F1

WAIT_F2

VCC_F SUP

VSS_F SUP

VCCQ_F SUP

VSSQ_F SUP

ICOCZ

ICOCZ AUDIO SYNCH RONOUS SERIAL PORT TRANSMIT

ICOCZ AUDIO SYNCHRONOUS SERIAL PORT REC E IVE

ICOCZ HARDWARE UART TRANSMIT DATA

ICOCZ HARDWARE UART RECEIVE DATA

ICOCZ HARDWARE UART CLEAR-TO-SEND

ICOCZ HARDWARE UART REQUEST-TO-SEND

OCZ

AUDIO SYNCHRONOUS SERI AL PORT FRAME

SIGNAL

RESET FOR FLASH ONLY (input):

Resets internal circuitry and inhibits all operations. Exit

from reset places the flash in asynchronous read-array

mode.

FLASH WRITE PROTE CT (in put):

Enables the lock-down mechanism. Blocks locked down

cannot be unlocked with the unlock command. nWP_F

high overrides the lock-down function enabling blocks to

be erased or programmed through software.

FLASH ERASE/PROGRAM/BLOCK LOCK ENABLE

(input):

Controls device protection. When VPEN_F is less than the

lock voltage, flash contents are protected against Program

and Erase.

FLASH WAIT (output):

Indicates invalid data in synchronous-read (burst) modes.

Not used by the processor, can be used for flash memory

programmers.

FLASH CORE LOGIC SUPPLY:

Writes to the flash array are inhibited when VCC_F is less

than lockout voltage. Operations at invalid VCC voltages

must not be attempted.

FLASH CORE GROUND:

Ground reference for flash core.

FLASH I/O POWER SUPPLY:

Must be the same voltage as the PXA26x processor family

VCCN.

FLASH I/O GROUND:

Ground reference for flash I/O.

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Pulled High
Note [1]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

Note [3]

——

——

——

——

——

——

——

——

2-20 Inte l® PXA26x P rocesso r Family Deve loper’s Man ual

System Arch itecture

Table 2-7. Pi n Description No tes

Note Description

GPIO Reset Operation: Configured as GPIO inputs by default after any reset. The input buffers for these pins

are disabled to prevent current drain and the pins are pulled high with 10K to 60K internal resistors. The input
paths must be enabled and the pull-ups turned off by clearing the Read Disable Hold (RDH) bit described in

[1]

Section 3.5.7, “Power Manager Sleep Status Register” on page 3-27. Even though sleep mode sets the RDH bit,

the pull-up resistors are not r e-enabled by sleep mode. The exact val ue of the internal pull-up resistor cannot be
guaranteed; always use an external pull-up for signals that require pull-ups.

Crystal oscillator pins: These pins are used to connect the external crystals to the on-chip oscillators. Refer to

[2]

Section 3.3, “Clock Manager” on page 3-2 for details on sleep mode operation.

GPIO Sleep operation: During the transition into sleep mode, the state of these pins is determined by the
corresponding PGSRn. See Section 3.5.9, “Power Manager GPIO Sleep State Registers” and Section 4.1.3.2,

“GPIO Pin Direction Registers (GPDR)” on page 4-6. If selected as an input, this pi n does not d ri ve duri ng sl eep.

[3]

If selected as an output, the val ue contai ned in th e Sl eep State Register i s drive n out onto the pin and h eld ther e
while the PXA26x processor family is in sleep mode.

GPIOs configured as inputs after exiting sleep mode cannot be used until PSSR[RDH] is cleared.
Static Memory Control Pins: During sleep mode, these pins can be programmed to either drive the value in

the Sleep State Register or to be placed in Hi-Z. To select the Hi-Z state, software must set the FS bit in the
Power Manager General Configuration Register. If PCFR[FS] is not set, then during the transition to s leep these

[4]

pins function as described in [3], above. For nWE, nOE, and nCS[0], if PCFR[FS] is not set, they ar e driven high
by the Memory Controller before entering sleep. If PCFR[FS] is set, these pins are placed in Hi-Z.

PCMCIA Control Pins: During sleep mode: Can be programmed either to drive the value in the Sleep State

[5]

Register or to be placed in Hi -Z. To select the Hi-Z state, software must set PCFR[FP]. If it is not set, then during
the transition to sleep these pins function as described in [3], above.

[6] During sleep, this supply must be driven low to conserve power.
[7] Remains powered in sleep mode.

There are four GPIO pins on the PXA26x processor family that do not default to GPIOs out of reset. Instead,
these four pins, nSDCS[3:2], RDnWR, nACRESET, default to their alternate function. During sleep, if the pins
are configured or left in their alternate function, their sleep state is as shown in the table above. If the pins are

[8]

configured as GPIOs, their sleep state is determined similar to other GPIOs (See Note[3]); however, on sleep
exit they default to their alternate function and the state after sleep exit is determined by their alternate function.
See Section 4.1, “General-Purpose I/O” for more information.

2.13 Register Address Summary

Table 2-8 lists the registers present in the PXA26x processor family.

Table 2-8. Register Address Summary (Sheet 1 of 13)

Unit Address Register Symbol Register Description

DMA
Controller

0x4000 0000
0x4000 0000 DCSR 0 DMA Control / Status Register for Channel 0

0x4000 0004 DCSR 1 DMA Control / Status Register for Channel 1
0x4000 0008 DCSR 2 DMA Control / Status Register for Channel 2
0x4000 000C DCSR3 DMA Control / Status Register for Channel 3
0x4000 0010 DCSR 4 DMA Control / Status Register for Channel 4
0x4000 0014 DCSR 5 DMA Control / Status Register for Channel 5
0x4000 0018 DCSR 6 DMA Control / Status Register for Channel 6

Intel® PXA26x Processor Family Deve lo p er’s Manua l 2-21

System Ar ch itecture

Table 2-8. Register Address Summa r y (S h eet 2 of 13)

Unit Address Register Symbol Register Description

0x4000 001C DCSR7 DMA Control / Status Register for Channel 7
0x4000 0020 DCSR8 DMA Control / Status Register for Channel 8
0x4000 0024 DCSR9 DMA Control / Status Register for Channel 9
0x4000 0028 DCSR10 DMA Control / Status Register for Channel 10
0x4000 002C DCSR11 DMA Control / Status Register for Channel 11
0x4000 0030 DCSR12 DMA Control / Status Register for Channel 12
0x4000 0034 DCSR13 DMA Control / Status Register for Channel 13
0x4000 0038 DCSR14 DMA Control / Status Register for Channel 14
0x4000 003C DCSR15 DMA Control / Status Register for Channel 15

0x4000 00f0 DINT DMA Interrupt Register
0x4000 0100 DRCMR0 Request to Channel Map Register for DREQ 0
0x4000 0104 DRCMR1 Request to Channel Map Register for DREQ 1
0x4000 0108 DRCMR2 Request to Channel Map Register for I2S receive Request
0x4000 010C DRCMR3 Request to Channel Map Register for I2S transmit Request

0x4000 0110 DRCMR4 Request to Channel Map Register for BTUART receive Request

0x4000 0114 DRCMR5 Request to Channel Map Register for BTUART transmit Request.

0x4000 0118 DRCMR6 Request to Channel Map Register for FFUART receive Request
0x4000 011C DRCMR7 Request to Channel Map Register for FFUART transmit Request
0x4000 0120 DRCMR8 Request to Channel Map Register for AC97 microphone Request
0x4000 0124 DRCMR9 Request to Channel Map Register for AC97 modem receive Request
0x4000 0128 DRCMR10 Request to Channel Map Register for AC97 modem transmit Request
0x4000 012C DRCMR11 Request to Channel Map Register for AC97 audio receive Request
0x4000 0130 DRCMR12 Request to Channel Map Register for AC97 audio transmit Request
0x4000 0134 DRCMR13 Request to Channel Map Register for SSP receive Request
0x4000 0138 DRCMR14 Request to Channel Map Register for SSP transmit Request
0x4000 013C DRCMR15 Request to Channel Map Register for NSSP receive Request
0x4000 0140 DRCMR16 Request to Channel Map Register for NSSP transmit Request
0x4000 0144 DRCMR17 Request to Channel Map Register for ICP receive Request
0x4000 0148 DRCMR18 Request to Channel Map Register for ICP transmit Request
0x4000 014C DRCMR19 Request to Channel Map Register for STUART receive Request
0x4000 0150 DRCMR20 Request to Channel Map Register for STUART transmit Request
0x4000 0154 DRCMR21 Request to Channel Map Register for MMC receive Request
0x4000 0158 DRCMR22 Request to Channel Map Register for MMC transmit Request
0x4000 015C DRCMR23 Request to Channel Map Register for ASSP receive Request
0x4000 0160 DRCMR24 Request to Channel Map Register for ASSP transmit Request
0x4000 0164 DRCMR25 Request to Channel Map Register for USB endpoint 1 Request
0x4000 0168 DRCMR26 Request to Channel Map Register for USB endpoint 2 Request
0x4000 016C DRCMR27 Request to Channel Map Register for USB endpoint 3 Request
0x4000 0170 DRCMR28 Request to Channel Map Register for USB endpoint 4 Request
0x4000 0174 DRCMR29 Request to Channel Map Register for HWUART receive Request

2-22 Inte l® PXA26x P rocesso r Family Deve loper’s Man ual

System Arch itecture

Table 2-8. Register Address Summary (Sheet 3 of 13)

Unit Address Register Symbol Register Description

0x4000 0178 DRCMR 30 Request to Channel Map Register for USB endpoint 6 Request
0x4000 017C DRCMR31 Request to Channel Map Register for USB endpoint 7 Request
0x4000 0180 DRCMR 32 Request to Channel Map Register for USB endpoint 8 Request
0x4000 0184 DRCMR 33 Request to Channel Map Register for USB endpoint 9 Request
0x4000 0188 DRCMR 34 Request to Channel Map Register for HWUART transmit Request
0x4000 018C DRCMR35 Request to Channel Map Register for USB endpoint 11 Request
0x4000 0190 DRCMR 36 Request to Channel Map Register for USB endpoint 12 Request
0x4000 0194 DRCMR 37 Request to Channel Map Register for USB endpoint 13 Request
0x4000 0198 DRCMR 38 Request to Channel Map Register for USB endpoint 14 Request
0x4000 019C DRCMR39 reserved
0x4000 0200 DDADR0 DMA Descriptor Address Register Channel 0
0x4000 0204 DSADR0 DMA Source Address Register Channel 0
0x4000 0208 DTADR0 DMA Target Address Register Channel 0
0x4000 020C DCMD0 DMA Command Address Register Channel 0
0x4000 0210 DDADR1 DMA Descriptor Address Register Channel 1
0x4000 0214 DSADR1 DMA Source Address Register Channel 1
0x4000 0218 DTADR1 DMA Target Address Register Channel 1
0x4000 021C DCMD1 DMA Command Address Register Channel 1
0x4000 0220 DDADR2 DMA Descriptor Address Register Channel 2
0x4000 0224 DSADR2 DMA Source Address Register Channel 2
0x4000 0228 DTADR2 DMA Target Address Register Channel 2
0x4000 022C DCMD2 DMA Command Address Register Channel 2
0x4000 0230 DDADR3 DMA Descriptor Address Register Channel 3
0x4000 0234 DSADR3 DMA Source Address Register Channel 3
0x4000 0238 DTADR3 DMA Target Address Register Channel 3
0x4000 023C DCMD3 DMA Command Address Register Channel 3
0x4000 0240 DDADR4 DMA Descriptor Address Register Channel 4
0x4000 0244 DSADR4 DMA Source Address Register Channel 4
0x4000 0248 DTADR4 DMA Target Address Register Channel 4
0x4000 024C DCMD4 DMA Command Address Register Channel 4
0x4000 0250 DDADR5 DMA Descriptor Address Register Channel 5
0x4000 0254 DSADR5 DMA Source Address Register Channel 5
0x4000 0258 DTADR5 DMA Target Address Register Channel 5
0x4000 025C DCMD5 DMA Command Address Register Channel 5
0x4000 0260 DDADR6 DMA Descriptor Address Register Channel 6
0x4000 0264 DSADR6 DMA Source Address Register Channel 6
0x4000 0268 DTADR6 DMA Target Address Register Channel 6
0x4000 026C DCMD6 DMA Command Address Register Channel 6
0x4000 0270 DDADR7 DMA Descriptor Address Register Channel 7
0x4000 0274 DSADR7 DMA Source Address Register Channel 7

Intel® PXA26x Processor Family Deve lo p er’s Manua l 2-23

System Ar ch itecture

Table 2-8. Register Address Summa r y (S h eet 4 of 13)

Unit Address Register Symbol Register Description

0x4000 0278 DTADR7 DMA Target Address Register Channel 7
0x4000 027C DCMD7 DMA Command Address Register Channel 7
0x4000 0280 DDADR8 DMA Descriptor Address Register Channel 8
0x4000 0284 DSADR8 DMA Source Address Register Channel 8
0x4000 0288 DTADR8 DMA Target Address Register Channel 8
0x4000 028C DCMD8 DMA Command Address Register Channel 8
0x4000 0290 DDADR9 DMA Descriptor Address Register Channel 9
0x4000 0294 DSADR9 DMA Source Address Register Channel 9
0x4000 0298 DTADR9 DMA Target Address Register Channel 9
0x4000 029C DCMD9 DMA Command Address Register Channel 9
0x4000 02A0 DDADR10 DMA Descriptor Address Register Channel 10
0x4000 02A4 DSADR10 DMA Source Address Register Channel 10
0x4000 02A8 DTADR10 DMA Target Address Register Channel 10
0x4000 02AC DCMD10 DMA Command Address Register Channel 10
0x4000 02B0 DDADR11 DMA Descriptor Address Register Channel 11
0x4000 02B4 DSADR11 DMA Source Address Register Channel 11
0x4000 02B8 DTADR11 DMA Target Address Register Channel 11
0x4000 02BC DCMD11 DMA Command Address Register Channel 11
0x4000 02C0 DDADR12 DMA Descriptor Address Register Channel 12
0x4000 02C4 DSADR12 DMA Source Address Register Channel 12
0x4000 02C8 DTADR12 DMA Target Address Register Channel 12
0x4000 02CC DCMD12 DMA Command Address Register Channel 12
0x4000 02D0 DDADR13 DMA Descriptor Address Register Channel 13
0x4000 02D4 DSADR13 DMA Source Address Register Channel 13
0x4000 02D8 DTADR13 DMA Target Address Register Channel 13
0x4000 02DC DCMD13 DMA Command Address Register Channel 13
0x4000 02E0 DDADR14 DMA Descriptor Address Register Channel 14
0x4000 02E4 DSADR14 DMA Source Address Register Channel 14
0x4000 02E8 DTADR14 DMA Target Address Register Channel 14
0x4000 02EC DCMD14 DMA Command Address Register Channel 14
0x4000 02F0 DDADR15 DMA Descriptor Address Register Channel 15
0x4000 02F4 DSADR15 DMA Source Address Register Channel 15
0x4000 02F8 DTADR15 DMA Target Address Register Channel 15
0x4000 02FC DCMD15 DMA Command Address Register Channel 15

Full Function
UART

0x4010 0000
0x4010 0000 FFRBR Receive Buffer Register (read only)

0x4010 0000 FFTHR Transmit Holding Register (write only)
0x4010 0004 FFIER Interrupt Enable Register (read/write)
0x4010 0008 FFIIR Interrupt ID Register (read only)
0x4010 0008 FFFCR FIFO Control Register (write only)

2-24 Inte l® PXA26x P rocesso r Family Deve loper’s Man ual

Table 2-8. Register Address Summary (Sheet 5 of 13)

Unit Address Register Symbol Register Description

0x4010 000C FFLCR Line Control Register (read/write)
0x4010 0010 FFMCR Modem Control Register (read/write)
0x4010 0014 FFLSR Line Status Register (read only)
0x4010 0018 FFMSR Modem Status Register (read only)
0x4010 001C FFSPR Scratch Pad Register (read/write)
0x4010 0020 FFISR Infrared Selection Register (read/write)
0x4010 0000 FFDLL Divisor Latch Low Register (DLAB = 1) (read/write)
0x4010 0004 FFDLH Divisor Latch High Register (DLAB = 1) (read/write)

Bluetooth
UART

I2C 0x4030 0000

I2S 0x4040 0000

0x4020 0000
0x4020 0000 BTRBR Receive Buffer Register (read only)

0x4020 0000 BTTHR Transmit Holding Register (write only)
0x4020 0004 BTIER Interrupt Enable Register (read/write)
0x4020 0008 BTIIR Interrupt ID Register (read only)
0x4020 0008 BTFCR FIFO Control Register (write only)
0x4020 000C BTLCR Line Control Register (read/write)
0x4020 0010 BTMCR Modem Control Register (read/write)
0x4020 0014 BTLSR Line Status Register (read only)
0x4020 0018 BTMSR Modem Status Register (read only)
0x4020 001C BTSPR Scratch Pad Register (read/write)
0x4020 0020 BTISR Infrared Selection Register (read/write)
0x4020 0000 BTDLL Divisor Latch Low Register (DLAB = 1) (read/write)
0x4020 0004 BTDLH Divisor Latch High Register (DLAB = 1) (read/write)

0x4030 1680 IBMR I2C Bus Monitor Register – IBMR
0x4030 1688 IDBR I2C Data Buffer Register – IDBR
0x4030 1690 ICR I2C Control Register – ICR
0x4030 1698 ISR I2C Status Register – ISR
0x4030 16A0 ISAR I2C Slave Address Register – ISAR

0x4040 0000 SACR0 Global Control Register
0x4040 0004 SACR1 Serial Audio I
0x4040 0008 — reserved
0x4040 000C SASR0 Serial Audio I
0x4040 0010 — reserved
0x4040 0014 SA IMR Serial Audio Interrupt Mask Register
0x4040 0018 SA ICR Serial Audio Interrupt Clear Register
0x4040 001C

through

0x4040 005C
0x4040 0060 SADIV Audio Clock Divider Register.

— reserved

2

S/MSB-Justified Control Register

2

S/MSB-Justified Interface and FIFO Status Register

System Arch itecture

Intel® PXA26x Processor Family Deve lo p er’s Manua l 2-25

System Ar ch itecture

Table 2-8. Register Address Summa r y (S h eet 6 of 13)

Unit Address Register Symbol Register Description

0x4040 0064

through

0x4040 007C
0x4040 0080 SADR Serial Audio Data Register (TX and RX FIFO access Register).

AC97 0x4050 0000

0x4050 0000 POCR PCM Out Control Register
0x4050 0004 PICR PCM In Control Register
0x4050 0008 MCCR Mic In Control Register

0x4050 000C GCR Global Control Register

0x4050 0010 POSR PCM Out Status Register
0x4050 0014 PISR PCM In Status Register
0x4050 0018 MCSR Mic In Status Register

0x4050 001C GSR Global Status Register

0x4050 0020 CAR CODEC Access Register
0x4050 0024

through

0x4050 003C
0x4050 0040 PCDR PCM FIFO Data Register
0x4050 0044

through

0x4050 005C
0x4050 0060 MCDR Mic-in FIFO Data Register
0x4050 0064

through

0x4050 00FC
0x4050 0100 MOCR Modem Out Control Register
0x4050 0104 — reserved
0x4050 0108 MICR Modem In Control Register
0x4050 010C — reserved

0x4050 0110 MOSR Modem Out Status Register

0x4050 0114 — reserved

0x4050 0118 MISR Modem In Status Register
0x4050 011C

through

0x4050 013C
0x4050 0140 MODR Modem FIFO Data Register
0x4050 0144

through

0x4050 01FC
0x4050 0200

through

0x4050 02FC

— reserved

— reserved

— reserved

— reserved

— reserved

— reserved

— Primary Audio codec Registers

2-26 Inte l® PXA26x P rocesso r Family Deve loper’s Man ual

Table 2-8. Register Address Summary (Sheet 7 of 13)

Unit Address Register Symbol Register Description

0x4050 0300

through

0x4050 03FC
0x4050 0400

through

0x4050 04FC
0x4050 0500

through

0x4050 05FC

UDC 0x4060 0000

0x4060 0000 UDCCR UDC Control Register
0x4060 0010 UDCCS0 UDC Endpoint 0 Control/Status Register
0x4060 0014 UDCCS1 UDC Endpoint 1 (IN) Control/Status Register
0x4060 0018 UDCCS2 UDC Endpoint 2 (OUT) Control/Status Register
0x4060 001C UDCCS3 UDC Endpoint 3 (IN) Control/Status Register
0x4060 0020 UDCCS4 UDC Endpoint 4 (OUT) Control/Status Register
0x4060 0024 UDCCS5 UDC Endpoint 5 (Interrupt) Control/Status Register
0x4060 0028 UDCCS6 UDC Endpoint 6 (IN) Control/Status Register
0x4060 002C UDCCS7 UDC Endpoint 7 (OUT) Control/Status Register
0x4060 0030 UDCCS8 UDC Endpoint 8 (IN) Control/Status Register
0x4060 0034 UDCCS9 UDC Endpoint 9 (OUT) Control/Status Register
0x4060 0038 UDCCS10 UDC Endpoint 10 (Interrupt) Control/Status Register
0x4060 003C UDCCS11 UDC Endpoint 11 (IN) Control/Status Register
0x4060 0040 UDCCS12 UDC Endpoint 12 (OUT) Control/Status Register
0x4060 0044 UDCCS13 UDC Endpoint 13 (IN) Control/Status Register
0x4060 0048 UDCCS14 UDC Endpoint 14 (OUT) Control/Status Register
0x4060 004C UDCCS15 UDC Endpoint 15 (Interrupt) Control/Status Register
0x4060 0060 UF NRH UDC Frame Number Register High
0x4060 0064 UF NRL UDC Frame Number Register Low
0x4060 0068 UBCR 2 UDC Byte Count Register 2
0x4060 006C UBCR4 UDC Byte Count Register 4
0x4060 0070 UBCR 7 UDC Byte Count Register 7
0x4060 0074 UBCR 9 UDC Byte Count Register 9
0x4060 0078 UBCR 12 UDC Byte Count Register 12
0x4060 007C UBCR14 UDC Byte Count Register 14
0x4060 0080 UDDR0 UDC Endpoint 0 Data Register
0x4060 0100 UDDR1 UDC Endpoint 1 Data Register
0x4060 0180 UDDR2 UDC Endpoint 2 Data Register
0x4060 0200 UDDR3 UDC Endpoint 3 Data Register
0x4060 0400 UDDR4 UDC Endpoint 4 Data Register
0x4060 00A0 UDDR5 UDC Endpoint 5 Data Register

— Secondary Audio codec Registers

— Primary Modem codec Registers

— Secondary Modem codec Registers

System Arch itecture

Intel® PXA26x Processor Family Deve lo p er’s Manua l 2-27

System Ar ch itecture

Table 2-8. Register Address Summa r y (S h eet 8 of 13)

Unit Address Register Symbol Register Description

0x4060 0600 UDDR6 UDC Endpoint 6 Data Register
0x4060 0680 UDDR7 UDC Endpoint 7 Data Register
0x4060 0700 UDDR8 UDC Endpoint 8 Data Register
0x4060 0900 UDDR9 UDC Endpoint 9 Data Register
0x4060 00C0 UDDR10 UDC Endpoint 10 Data Register
0x4060 0B00 UDDR11 UDC Endpoint 11 Data Register
0x4060 0B80 UDDR12 UDC Endpoint 12 Data Register
0x4060 0C00 UDDR13 UDC Endpoint 13 Data Register
0x4060 0E00 UDDR14 UDC Endpoint 14 Data Register
0x4060 00E0 UDDR15 UDC Endpoint 15 Data Register
0x4060 0050 UICR0 UDC Interrupt Control Register 0
0x4060 0054 UICR1 UDC Interrupt Control Register 1
0x4060 0058 USIR0 UDC Status Interrupt Register 0
0x4060 005C USIR1 UDC Status Interrupt Register 1

Standard
UART

ICP 0x4080 0000

RTC 0x4090 0000

0x4070 0000
0x4070 0000 STRBR Receive Buffer Register (read only)

0x4070 0000 STTHR Transmit Holding Register (write only)
0x4070 0004 STIER Interrupt Enable Register (read/write)
0x4070 0008 STIIR Interrupt ID Register (read only)
0x4070 0008 STFCR FIFO Control Register (write only)
0x4070 000C STLCR Line Control Register (read/write)
0x4070 0010 STMCR Modem Control Register (read/write)
0x4070 0014 STLSR Line Status Register (read only)
0x4070 0018 STMSR reserved
0x4070 001C STSPR Scratch Pad Register (read/write)
0x4070 0020 STISR Infrared Selection Register (read/write)
0x4070 0000 STDLL Divisor Latch Low Register (DLAB = 1) (read/write)
0x4070 0004 STDLH Divisor Latch High Register (DLAB = 1) (read/write)

0x4080 0000 ICCR0 ICP Control Register 0
0x4080 0004 ICCR1 ICP Control Register 1
0x4080 0008 ICCR2 ICP Control Register 2
0x4080 000C ICDR ICP Data Register
0x4080 0010 — reserved
0x4080 0014 ICSR0 ICP Status Register 0
0x4080 0018 ICSR1 ICP Status Register 1

0x4090 0000 RCNR RTC Count Register
0x4090 0004 RTAR RTC Alarm Register
0x4090 0008 RTSR RTC Status Register

2-28 Inte l® PXA26x P rocesso r Family Deve loper’s Man ual

Table 2-8. Register Address Summary (Sheet 9 of 13)

Unit Address Register Symbol Register Description

0x4090 000C RTTR RTC Timer Trim Register

OS Timer 0x40A0 0000

0x40A0 0000 OSMR<0>
0x40A0 0004 OSMR<1>
0x40A0 0008 OSMR<2>
0x40A0 000C OSMR<3>
0x40A0 0010 OSCR OS Timer Counter Register
0x40A0 0014 OSSR OS Timer Status Register
0x40A0 0018 OWER OS Timer Watchdog Enable Register
0x40A0 001C OIER OS Timer Interrupt Enable Register

PWM 0 0x40B0 0000

0x40B0 0000 PWM_CTRL0 PWM 0 Control Register
0x40B0 0004 PWM_PWDUTY0 PWM 0 Duty Cycle Register
0x40B0 0008 PWM_PERVAL0 PWM 0 Period Control Register

PWM 1 0x40C0 0000

0x40C0 0000 PWM_CTRL1 PWM 1Control Register
0x40C0 0004 PWM_PWDUTY1 PWM 1 Duty Cycle Register
0x40C0 0008 PWM_PERVAL1 PWM 1 Period Control Register

Interrupt
Control

GPIO 0x40E0 0000

0x40D0 0000
0x40D0 0000 ICIP Interrupt Controller IRQ Pending Register

0x40D0 0004 ICMR Interrupt Controller Mask Register

0x40D0 0008 ICLR Interrupt Controller Level Register
0x40D0 000C ICFP Interrupt Controller FIQ Pending Register
0x40D0 0010 ICPR Interrupt Controller Pending Register
0x40D0 0014 ICCR Interrupt Controller Control Register

0x40E0 0000 GPLR0 G PIO Pin-Level Register GPIO<31:0>

0x40E0 0004 GPLR1 G PIO Pin-Level Register GPIO<63:32>

0x40E0 0008 GPLR2 G PIO Pin-Level Register GPIO<80:64>
0x40E0 000C GPDR0 GPIO Pin Direction Register GPIO<31:0>

0x40E0 0010 GPDR1 GPIO Pin Direction Register GPIO<63:32>

0x40E0 0014 GPDR2 GPIO Pin Direction Register GPIO<80:64>

0x40E0 0018 GPSR0 GPIO Pin Direction Register GPIO<31:0>
0x40E0 001C GPSR1 GPIO Pin Output Set Register GPIO<63:32>

0x40E0 0020 GPSR2 G PIO Pin Output Set Register GPIO<80:64>

0x40E0 0024 GPCR0 GPIO Pin Output Clear Register GPIO<31:0>

0x40E0 0028 GPCR1 GPIO Pin Output Clear Register GPIO <63:32>
0x40E0 002C GPCR2 GPIO Pin Output Clear Register GPIO <80:64>

0x40E0 0030 GRER0 GPIO Rising-Edge Detect Register GPIO<31:0>

0x40E0 0034 GRER1 GPIO Rising-Edge Detect Register GPIO<63:32>

OS Timer Match Registers<3:0>

System Arch itecture

Intel® PXA26x Processor Family Deve lo p er’s Manua l 2-29

System Ar ch itecture

Table 2-8. Register Address Summa r y (S h eet 10 of 13)

Unit Address Register Symbol Register Description

0x40E0 0038 GRER2 GPIO Rising-Edge Detect Register GPIO<80:64>
0x40E0 003C GFER0 GPIO Falling-Edge Detect Register GPIO<31:0>
0x40E0 0040 GFER1 GPIO Falling-Edge Detect Register GPIO<63:32>
0x40E0 0044 GFER2 GPIO Falling-Edge Detect Register GPIO<80:64>
0x40E0 0048 GEDR0 GPIO Edge Detect Status Register GPIO<31:0>
0x40E0 004C GEDR1 GPIO Edge Detect Status Register GPIO<63:32>
0x40E0 0050 GEDR2 GPIO Edge Detect Status Register GPIO<80:64>
0x40E0 0054 GAFR0_L GPIO Alternate Function Select Register GPIO<15:0>
0x40E0 0058 GAFR0_U GPIO Alternate Function Select Register GPIO<31:16>
0x40E0 005C GAFR1_L GPIO Alternate Function Select Register GPIO<47:32>
0x40E0 0060 GAFR1_U GPIO Alternate Function Select Register GPIO<63:48>
0x40E0 0064 GAFR2_L GPIO Alternate Function Select Register GPIO<79:64>
0x40E0 0068 GAFR2_U GPIO Alternate Function Select Register GPIO 80

Power
Manager and
Reset
Control

SSP 0x4100 0000

0x40F0 0000

0x40F0 0000 PMCR Power Manager Control Register
0x40F0 0004 PSSR Power Manager Sleep Status Register
0x40F0 0008 PSPR Power Manager Scratch Pad Register
0x40F0 000C PWER Power Manager Wake-up Enable Register
0x40F0 0010 PRER Power Manager GPIO Rising-Edge Detect Enable Register
0x40F0 0014 PFER Power Manager GPIO Falling-Edge Detect Enable Register
0x40F0 0018 PEDR Power Manager GPIO Edge Detect Status Register
0x40F0 001C PCFR Power Manager General Configuration Register
0x40F0 0020 PGSR0 Power Manager GPIO Sleep State Register for GP[31-0]
0x40F0 0024 PGSR1 Power Manager GPIO Sleep State Register for GP[63-32]
0x40F0 0028 PGSR2 Power Manager GPIO Sleep State Register for GP[84-64]
0x40F0 002C — reserved
0x40F0 002C — reserved
0x40F0 0030 RCSR Reset Controller Status Register
0x40F0 0034 PMFWR Power Manager Fast Sleep Walk-up Configuration Register

0x4100 0000 SSCR0 SSP Control Register 0
0x4100 0004 SSCR1 SSP Control Register 1
0x4100 0008 SSSR SSP Status Register
0x4100 000C SSITR SSP Interrupt Test Register

0x4100 0010 SSDR (Write / Read) SSP Data Write Register/SSP Data Read Register

MMC
Controller

0x4110 0000
0x4110 0000 MMC_STRPCL Control to start and stop MMC clock

2-30 Inte l® PXA26x P rocesso r Family Deve loper’s Man ual

T able 2-8. Register Address Summary (Sheet 11 of 13)

Unit Address Register Symbol Register Description

0x4110 0004 MMC_STAT MMC Status Register (read only)
0x4110 0008 MMC_CLKRT MMC clock rate

0x4110 000C MMC_SPI SPI mode control bits

0x4110 0010 MMC_CMDAT Command/response/data sequence control
0x4110 0014 MMC_RESTO Expected response time out
0x4110 0018 MMC_RDTO Expected data read time out

0x4110 001C MMC_BLKLEN Block length of data transaction

0x4110 0020 MMC_NOB Number of blocks, for block mode
0x4110 0024 MMC_PRTBUF Partial MMC_TXFIFO FIFO written
0x4110 0028 MMC_I_MASK Interrupt Mask

0x4110 002C MMC_I_REG Interrupt Register (read only)

0x4110 0030 MMC_CMD Index of current command
0x4110 0034 MMC_ARGH MSW part of the current command argument
0x4110 0038 MMC_ARGL LSW part of the current command argument

0x4110 003C MMC_RES Response FIFO (read only)

0x4110 0040 MMC_RXFIFO Receive FIFO (read only)
0x4110 0044 MMC_TXFIFO Transmit FIFO (write only)

Clocks
Manager

Network SS P 0x4140 0000

Audio SSP 0x4150 0000

Hardware
UART

0x4130 0000

0x4130 0000 CCCR Core Clock Configuration Register

0x4130 0004 CKEN Clock Enable Register

0x4130 0008 OSCC Oscillator Configuration Register

0x4140 0000 NSSCR0 NSSP Control register 0

0x4140 0004 NSSCR1 NSSP Control register 1

0x4140 0008 NSSSR NSSP Status register
0x4140 000C NSSITR NSSP Interrupt Test register

0x4140 0010 NSSDR NSSP Data Write Register / Data Read register

0x4140 0028 NSSTO NSSP Time Out register
0x4140 002C NSSPSP NSSP Programmable Serial Protocol

0x4150 0000 AS SCR0 ASSP Control register 0

0x4150 0004 AS SCR1 ASSP Control register 1

0x4150 0008 ASSSR ASSP Status register
0x4150 000C ASSITR ASSP Interrupt Test register

0x4150 0010 AS SDR ASSP Data Write Register / Data Read register

0x4150 0028 AS STO ASSP Time Out register
0x4150 002C ASSPSP ASSP Programmable Seri al Protocol

0x4160 0000

0x4160 0000 HW RBR Receive Buffer register (read only)

System Arch itecture

Intel® PXA26x Processor Family Deve lo p er’s Manua l 2-31

System Ar ch itecture

Table 2-8. Register Address Summa r y (S h eet 12 of 13)

Unit Address Register Symbol Register Description

0x4160 0000 HWTHR Transmit Holding register (write only)
0x4160 0004 HWIER Interrupt Enable register (read/write)
0x4160 0008 HWIIR Interrupt ID register (read only)
0x4160 0008 HWFCR FIFO Control register (write only)
0x4160 000C HWLCR Line Control register (read/write)
0x4160 0010 HWMCR Modem Control register (read/write)
0x4160 0014 HWLSR Line Status register (read only)
0x4160 0018 HWMSR Modem Status register (read only)
0x4160 001C HWSPR Scratch Pad register (read/write)
0x4160 0020 HWISR Slow Infrared Select register (read/write)
0x4160 0024 HWFOR FIFO Occupancy register (read only)
0x4160 0028 HWABR Auto-Baud Control register (read/write)
0x4160 002C HWACR Auto-Baud Count register
0x4160 0000 HWDLL Divisor Latch Low Register (DLAB = 1) (read/write)
0x4160 0004 HWDLH Divisor Latch High Register (DLAB = 1) (read/write)

LCD
Controller

Memory
Controller

0x4400 0000
0x4400 0000 LCCR0 LCD Controller Control Register 0

0x4400 0004 LCCR1 LCD Controller Control Register 1
0x4400 0008 LCCR2 LCD Controller Control Register 2
0x4400 000C LCCR3 LCD Controller Control Register 3
0x4400 0200 FDADR0 DMA Channel 0 Frame Descriptor Address Register
0x4400 0204 FSADR0 DMA Channel 0 Frame Source Address Register
0x4400 0208 FIDR0 DMA Channel 0 Frame ID Register
0x4400 020C LDCMD0 DMA Channel 0 Command Register
0x4400 0210 FDADR1 DMA Channel 1 Frame Descriptor Address Register
0x4400 0214 FSADR1 DMA Channel 1 Frame Source Address Register
0x4400 0218 FIDR1 DMA Channel 1 Frame ID Register
0x4400 021C LDCMD1 DMA Channel 1 Command Register
0x4400 0020 FBR0 DMA Channel 0 Frame Branch Register
0x4400 0024 FBR1 DMA Channel 1 Frame Branch Register
0x4400 0038 LCSR LCD Controller Status Register
0x4400 003C LIIDR LCD Controller Interrupt ID Register
0x4400 0040 TRGBR TMED RGB Seed Register
0x4400 0044 TCR TMED Control Register

0x4800 0000
0x4800 0000 MDCNFG SDRAM Configuration Register 0

0x4800 0004 MDREFR SDRAM Refresh Control Register
0x4800 0008 MSC0 Static Memory Control Register 0
0x4800 000C MSC1 Static Memory Control Register 1

2-32 Inte l® PXA26x P rocesso r Family Deve loper’s Man ual

System Arch itecture

Table 2-8. Register Address Summary (Sheet 13 of 13)

Unit Address Register Symbol Register Description

0x4800 0010 MSC 2 Static Memory Control Register 2

0x4800 0014 MEC R
0x4800 001C SXCNFG Synchronous Static Memory Control Register

0x4800 0024 SXMRS MRS value to be written to SMROM

0x4800 0028 MCMEM0

0x4800 002C MCMEM1

0x4800 0030 MCATT0 Card interface Attribute Space Socket 0 Tim ing Configuration

0x4800 0034 MCATT1 Card interface Attribute Space Socket 1 Tim ing Configuration

0x4800 0038 MCIO0 Card interface I/O Space Socket 0 Timing Configuration
0x4800 003C MCIO1 Card interface I/O Space Socket 1 Timing Configuration

0x4800 0040 MDMRS MRS value to be written to SDRAM

0x4800 0044 BOO T_DEF

0x4800 0058 MDMRSLP Low-Power SDRAM Mode Register Set Configuration Register

0x4800 0064 SA1111CR SA1111 compatibility register

Expansion Memory (PCMCIA/Compact Flash) Bus Configuration
Register

Card interface Common Memory Space Socket 0 Timing
Configuration

Card interface Common Memory Space Socket 1 Timing
Configuration

Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL
values.

2.14 Memory Map

Figur e 2-3 on page 2-35 and Figure 2-2 on page2-34 show the fu ll processor memory map.

Any unused r e gister space from 0x4000 00 00 to 0x4BFF FFFF is reserved.

Note: Accessing reserved portions of the memory map gives unpredictable results.

The PCMCIA interface is divided into socket 0 and socket 1 space. These two partitions are each
subdivided into I/ O, memor y and attribute space. Each is allocated 128 MB of memory space.

Intel® PXA26x Processor Family Deve lo p er’s Manua l 2-33

System Ar ch itecture

Figure 2-2. Memory Map (Part One) — From 0x8000 0000 to 0xFFFF FFFF

0xFFFF FFFF
0xFC00 0000

0xF800 0000
0xF400 0000
0xF000 0000

0xEC00 0000

0xE800 0000
0xE400 0000

0xE000 0000

0xDC00 0000
0xD800 0000

0xD400 0000
0xD000 0000
0xCC00 0000
0xC800 0000

0xC400 0000
0xC000 0000

0xBC00 0000
0xB800 0000

0xB400 0000
0xB000 0000
0xAC00 0000

0xA800 0000
0xA400 0000

0xA000 0000

0x9C00 0000

0x9800 0000
0x9400 0000
0x9000 0000

0x8C00 0000

0x8800 0000
0x8400 0000

0x8000 0000

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)
Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

SDRAM Bank 3 (64 MB)

SDRAM Bank 2 (64 MB)
SDRAM Bank 1 (64 MB)
SDRAM Bank 0 (64 MB)

Reserved (64 MB)
Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)

Reserved (64 MB)
Reserved (64 MB)

2-34 Inte l® PXA26x P rocesso r Family Deve loper’s Man ual

Figure 2-3. Memory Map (Part Two) — From 0x0000 0000 to 0x7FFF FFFF

0x7FFF FFFF

0x7C00 0000

0x7800 0000
0x7400 0000

Reserved (64 MB)
Reserved (64 MB)

Reserved (64 MB)

System Arch itecture

0x7000 0000

0x6C00 0000

0x6800 0000
0x6400 0000

0x6000 0000

0x5C00 0000

0x5800 0000
0x5400 0000
0x5000 0000

0x4C00 0000

0x4800 0000
0x4400 0000

0x4000 0000

0x3C00 0000

0x3800 0000
0x3400 0000
0x3000 0000

Reserved (64 MB)
Reserved (64 MB)

Reserved (64 MB)
Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Memory Mapped registers (Memory Ctl)

Memory Mapped registers (LCD)

Memory Mapped registers (Peripherals)

PCMCIA/CF- Slot 1 (256 MB)

0x2C00 0000

0x2800 0000
0x2400 0000

0x2000 0000

0x1C00 0000

0x1800 0000
0x1400 0000
0x1000 0000

0x0C00 0000

0x0800 0000
0x0400 0000

0x0000 0000

Intel® PXA26x Processor Family Deve lo p er’s Manua l 2-35

PCMCIA/CF - Slot 0 (256MB)

Reserved (64 MB)

Reserved (64 MB)

Static Chip Select 5 (64 MB)

Static Chip Select 4 (64 MB)
Static Chip Select 3 (64 MB)
Static Chip Select 2 (64 MB)

Static Chip Select 1 (64 MB)
Static Chip Select 0 (64 MB)

System Ar ch itecture

2-36 Inte l® PXA26x P rocesso r Family Deve loper’s Man ual

Clocks and Power Manager 3

The clocks and power manager for the Intel® PX A26 x Processor Family controls the clock
frequency to each m odule and manages transitions between the different power manager operating
modes to opt imize both compu ting performance and power consumption.

The PXA26x processor family clocks and power manager supports 400-MHz run mode, and
CKEN bits for the NSSP, ASSP, and HWUART. Also, it includes nine new GPIOs that must be
defined in the Power Manager Sleep State registers.

3.1 Clock Manager Introduction

The clocks and power manager provides fixed clocks for each peripheral unit. Many of the devices’
peripher a l c locks can be disabled using the Clock Enable register (CKEN), or through bits in the
peripher al’s control regi ster s. To minimize p owe r co ns umpt ion , tur n o ff th e clo ck to a ny u nit tha t i s
not being u sed. The clocks and power manag e r a lso provides the programmable-frequency clocks
for the LCD controller , memory controller, and CPU. These clocks are related to each other
because they originate from th e same internal phase locked loop (PLL) clock sou rce. To program
the PLL’s frequency, follow these steps (for information on the factors L, M, and N, see

Section 3.6.1 , “Core Clock Configuration Register (CCCR)”):

1. Determine the fastest synchr onous memory requirement (SDRAM frequency).

2. If the SDRA M frequency is less tha n 99 . 5 MH z , th e me m o ry f re q ue ncy must be twice the
SDRAM frequency and the SDRAM clock ratio in the memory controller must be set to two.
If the SDRAM fre que ncy is 99.5 MHz, the memory freq ue ncy is equal to the SDRAM
frequency.

3. Round the memory frequenc y down to the nearest value of 99.5 MHz (L = 0x1B), 11 8.0 MHz
(L = 0x20), 132.7 MHz (L = 0x24), 147.5 MHz (L = 0x 28), or 165.9 MHz (L = 0x2D), and
program the value of L in the Core Clock Configuration Register (CCCR). This frequency (or
half, if the SDRA M c l ock ratio is 2) is the extern a l synchronous memory freque nc y.

4. Determine the r equ ire d cor e fre que nc y for n or mal (r un mod e) oper ati on. Use t his mode d ur ing
normal proces sing, when the a pplication must make occasi onal fetches to e xternal memory.
The possible values are one, two, or fo ur times the me mory frequen cy. Program this value (M)
in the Core Clock Configuration Register.

5. Determine the req uired core frequency for turbo mode operation. This mode is generally used
when the application runs entirely from the caches, because any fetches to external memory
slow the core’s performance. This value is a multiple (1.0, 1.5, 2.0, or 3.0) of the run mode
frequency. Program the value (N) in the Core Clock Configuration Register.

6. Configure the LCD controller and m emory co ntrol ler for the new memory frequency and ent er
the frequency change sequence (described in Secti o n 3.4.8, “Frequency Ch an g e Seq ue n c e ” ).

Note: Not all frequency combinations are vali d. See Section 3.3.3, “Core Phase Locked Loop” for valid

combinations.

Intel® PXA26x Processo r Family Develop er’s Manual 3-1

Clocks and Power Manager

3.2 Power Manager Introduction

The clocks and power manager can place the processo r in one of three resets.

• Hardware reset (nRESET asserted) is a nonmaskable total reset. Use hardware reset at power

up or when no system inform a t ion requires preservation.

• Watchdog reset is asserted through the watchdog timer and resets the system with the

exception of the clocks and power manag e r. Use his reset as a code monitor. If code fails to
complete a specified sequence, the processor assumes a fatal system error has occurred and
causes a watchdo g r eset.

• GPIO reset is enabled through the GPIO alternate function registers. Use GPIO reset as an

alternative to hardware reset that preserves the memory contr oller registers and a few critical
states in the clocks and power manager and the real time clock (RTC).

The clocks and power manager also controls the entry into a nd e xit from any of the low power or
special clocking modes on the processor. These mo des are:

• Turbo mode – the core runs at its peak freq ue ncy. In this mode , make very few external

memory accesses because the core must w ait on the external memory.

• Run mode – the core r uns at its normal frequency. In this mode, the core is assumed to be

doing frequent external memory acc e sses, so running slower is op timum for the be st power/
performance trade-off.

• Idle mode – the core is not being clocked, but th e res t of the system is fully operational. Use

this mode durin g brief lulls in activity, when the external system must continue operation but
the core is idle.

• Sleep mode – places the processor in its lowest power state but maintains I/O state, RTC, and

the clocks and power manag e r. Wa ke-up from sleep mode requires re -booting the system,
since most internal states were lost.

The clocks and power manager also controls the processor’s actions dur ing the frequency change
sequence. The frequency change sequence is a sequence that changes the core frequency (run and
turbo) and m e mory freque ncy from the previously stored values to the new values in the C ore
Clock Configuration Register. This sequenc e takes time to complete due to P L L relock time, but it
allows dynamic frequency changes without compromising external memory integrity. Any
peripherals that rely on the core or memor y controller must be configured to withstand a data flow
interruption.

3.3 Clock Manager

The processor’s clocking system incorporates five major clock sour ces :

• 32.768-KH z oscillator

• 3.6864-MHz oscillator

• Programmable frequenc y c ore PLL

• 95.85-MHz fixed frequenc y peripheral PLL

• 147.46-MHz fixed frequency PLL

The clocks manager also contains clock gating fo r power reduction.

3-2 Intel® PXA26x Processor Family Developer’s Manual

Figur e 3- 1 shows a functional repr e sentation of the c locking network. “L” is in the core PLL.

The PXbus is the internal bus between the core, the DMA/bridge, the LCD controller, and the
memory controller as shown in Figure 3-1. This bus is clocked at 1/2 the run mode frequen c y. For
optimal performance, th e PXbus sho uld be cloc ked as fast as possible. For example, if a tar get cor e
frequenc y of 2 00 MHz is desi re d us e 20 0- MHz run m ode i nst ead of 20 0-M Hz t ur bo mod e wi th r un
at 100 MHz. Increasing the PXbus frequency may help reduce the latenc y inv olved in accessing
non-cacheable memory.

Figure 3-1. Clocks Manager Block Diagram

Clocks and Power Manager

32.768 k
RTC

32.768

32.768 k

PWR_MGR

/1 /112

KHz

OSC

3.6864
MHz
OSC

RET AINS POWER IN SLEEP

USB

FICP

I2C

3.6864
PWM

100-400

MHz

PLL*

147.46
MHz

PLL

95.846
MHz

PLL

MMC

3.6864
SSP

3.6864
GPIO

UART s

/N

/4

DMA

Bridge

/

3.6864
OST

/2

AC97

CPU

CORE

MEM

Controller

/M

LCD

Controller

PXbus

I2S

47.923

* For the PXA26 x processor fami l y: 100-400 MHz.

Intel® PXA26x Processo r Family Develop er’s Manual 3-3

47.923

31.949

19.169

14.746

12.288

5.672

Clocks and Power Manager

3.3.1 32.768-KHz Oscillator

The 32.768-KHz osc illator is a low-power , low -frequenc y oscillato r that clocks the RTC and power
manager. The 32.768-KHz oscillator is disabled out of ha rdware rese t so the RTC and power
manager blocks us e the 3.68 64-MH z oscilla tor instead . Softwar e wr ites th e Oscill ator On bi t in the
Oscillator Configuration Register to enable the 32.768-KHz oscillator. This configures the RTC
and power manager to use the 32.768-KHz oscillator aft er it stabilizes.

32.768-KH z oscillator use is optional and pr ovides the lowest power cons umption during sleep
mode. In less power-sensitive applications, dis a ble the 32.768-KHz oscillator in the Oscillator
Configuration Register (OSCC) and leave the ex ternal pins floa ting (no external crystal required)
for cost savings. If the 32.768-KHz os c illator is not in the system, the frequen c y of the RTC and
power manage r will be 3.6864 MHz divided by 112 (32.914 KHz). In sleep, the 3.686 4-MHz
oscillator consumes hundred s of micr oam ps of extra power when it stays enabled. See

Section 3.5.2, “Power Ma na ger General Configuration Register (PCFR)” on pa ge 3-24 for

information on the Oscillator Power Down Enable (OPDE) bit, which determines if the 3.6864­MHz oscillator is enabled in sleep mode. No external capacitors are required.

3.3.2 3.6864-MHz Oscillator

The 3.6864-MHz oscillator provides the primary clock source for the processor. The on-chip PLL
frequency multipliers, S ynchronous Serial Port (SSP), Pulse Width Modula tor (PWM), and the
Operating System Timer (OST) use the 3.6864-MHz oscillator as a reference. Out of hardw are
reset, the 3.6 864-MHz oscillator also drives the RTC and power manager (PM). The u ser may then
enable the 32.768-KHz oscillator, which drives the RTC and PM after it is stabilized. The 3.6864­MHz oscillat or can be disab l e d during sleep mode by setting the OPDE bit (see Sectio n 3.5.2,

“Power Manage r General Confi guration Regis te r (PCFR)” on page 3-24) but only if the 32.768-

KHz oscillator is enabled and stabilized (both the OON and OOK bits in the OSCC s et). See

Section 3.6.3, “Oscillator Configuration Register (OSCC)” on page 3-39 for more information. No

external capacitors are requi red.

3.3.3 Core Phase Locked Loop

The core PLL is the clock source of the CPU co re, the memory controller, the LCD controller, and
DMA controller. The core PLL uses the 3.6864-MHz oscil lator as a reference and multiplies its
freque n c y by the following variables:

• L: crystal frequency to memory frequency multiplier, set to 27, 32, 36, 40, or 45.

• M: memory frequency to run mode frequency multiplier, set to 1, 2 or 4.

• N: run mode frequency to turbo mode frequency m ultiplier, set to 1.0 , 1.5, 2.0, or 3.0.

The output fre quency selections are shown in Table 3-1, on page 3-5. See Section 3.6.1, “Core

Clock Configuration Register (CCCR)” on page 3-35 for programming information on the L, M,

and N factors. See Section 3.6.1 for the hexadeci mal set tings.
Do not choose a combin ation that generate s a f requency that is not supported in the voltag e range

and package in which the processor is oper ating.
SDCLK must not be greater than 100 MHz for SDRAM and 66 MHz for intern a l Flash. If

MEMCLK is greater than 100 MHz, the SDCLK to MEMCL K ratio must be set to 1:2 in the
memory controller.

3-4 Intel® PXA26x Processor Family Developer’s Manual

T able 3-1. Core PLL Output Frequencies for 3.6864-MHz Crystal

Clocks and Power Manager

LM

27 1

32 1

36 1

40 1

45 1

27 2

32 2

36 2

40 2

45 2

27 4

Turbo Mode Frequency (MHz) for Values

Configuration Register (CCCR[15:0])

1.00

(Run)

99.5

@.85 V

118.0

@1.0 V

132.7

@1.0 V

147.5

@1.0 V

165.9

1.0 V

199.1

@1.0 V

235.9

@1.1 V

265.4

@1.1 V

294.9

@1.1 V

331.9

@1.3 V

398.1

@1.3 V

“N” and Core Clock

programming for Values of “N”:

1.50 2.00 3.00

—

—

—

—

—

298.6

@1.1 V

— — — 118 118.0 59.0

— — — 132.7 132.7 66

— — — 147.5 147.5 74

— — — 165.9 165.9 83

— — — 200 99.5 99.5

199.1

@1.0 V

235.9

@1.1 V

265.4

@1.1 V

294.9

@1.1 V

331.8

1.3 V

398.1

@1.3 V

298.6

@1.1 V

353.9

@1.3 V

398.1

@1.3 V

— 74 147.5 74

— 83 165.9 83

— 99.5 99.5 99.5

PXbus

Frequency

(MHz)

50 99.5 99.5

59 118.0 59.0

66 132.7 66

MEM, LCD
Frequency

(MHz)

SDRAM

max Freq

(MHz)

3.3.4 95.85-MHz Peripheral Phase Locked Loop

The 95.85-MHz PLL is the clock source for many of the peripheral blocks’ external interfaces.
These interfaces require: ~48 MHz for the UDC/USB,
~33 MHz for the I

2

C, and ~20 MHz for the MMC. The generated fr equency is not exactly the
required frequency due to the chosen crystal and the lack of a perfect least common multiple
between the units. The chosen frequencies keep each unit’ s clock frequency wi thin the unit’s clock
tolerance. If a crystal other than 3.6864 MHz is used, the clock freq uencies to the peripheral
blocks’ interfaces ma y no t yield the desired baud rates (or protocol’s rate).

Table 3-2. 95.85-MHz Peripheral PLL Output Freq uenc ies for 3.6864 -MH z Crystal

Unit Name Nominal Frequency Actual Frequency

USB (UDC) 48 MHz 47.923 MHz

FICP 48 MHz 47.923 MHz

2

I

C 33 MHz 31.949 MHz

MMC 20 MHz 19.169 MHz

Intel® PXA26x Processo r Family Develop er’s Manual 3-5

fast infrare d communications por t (FICP),

Clocks and Power Manager

3.3.5 147.46-MHz Peripheral Phase Locked Loop

The 147.46-MHz PLL is the clock source for many of the peripher al blocks’ external interfaces.
These interfaces require: ~14.75 MHz for the UARTs, 12.288 MHz for the AC97, and variable
frequenc ies for I
the choice of crystal and the lack of a pe rfect le ast common m ultipl e between t he units. The chosen
frequencies keep each unit’s clock frequency within the unit’s clock tolerance. If a crystal other
than 3.6864 MHz is used, the clock frequencie s to the periphe ral blocks’ interfaces may no t yield
the desired baud rates (or other protocol’s rate)

Table 3-3. 147.46-MHz Peri p h eral PLL Outpu t Fr equencies for 3 .6 864-MHz Crystal

Unit Name Nominal Frequency Actual Frequency

UARTs 14.746 M Hz 14.746 MHz

AC97 12.288 MHz 12.288 MHz

2

I

S 146.76 MHz 147.46 MHz

2

S. The gener a ted frequency may not exactly match the required frequency due to

3.3.6 Clock Gating

The clocks man a ger contains the CKEN register. This register conta ins configuration bits that c a n
disable the cl oc ks to individual units. The configuration bits are used when a module is not being
used. After a ha rdware reset, any module t ha t is not being used must have its clock disabled. If a
module is temporarily quiesc ent but does not have clock gating functionality, use the CKEN
register to disable the unit’s clock.

When a module’s clock is disabled, t he registers in that module are still readable and writable. The
AC97 is an exception and is completel y inaccessible if the clock is disabled .

3.4 Resets and Power Modes

The clocks and power manager unit determines th e processor’s resets, power se quences and power
modes. Each behaves differently during operation and has specific entry and exit sequences. The
resets and power modes are:

• Hard ware re se t

• Watchdog reset

• GPIO reset

• Run mode

• Turbo mode

• Idle mode

• Frequency change sequence

• Sleep mode

3-6 Intel® PXA26x Processor Family Developer’s Manual

3.4.1 Hardware Reset

To invoke a hardware reset and reset all units in the processor to a kno wn state, assert the nRESET
pin. Hardware reset is only intended to be us e d for power up and complete resets.

3.4.1.1 Invoking Hardware Reset

Hardware reset is invoked when the nRESET pin is pull ed low by an external source. The
processor does not provide a method of masking or disabling the propagation of the external pin
value. When the nRESET pin is ass e rted, a hardw are reset is invoked, regardle ss of the mode of
operation. The nRESET_OUT pin is asserted when the n RESET pin is asserted. To enter hardware
reset, nRESET must be held low for t
state to propagate. Refer to the I ntel® PXA26x Processor Family Electrical, Mecha nical, and
Thermal Specification for deta ils .

3.4.1.2 Behavior During Hardware Reset

During hardware reset, all internal registers and units are held at their defined reset conditions.
While the nRESET pin is asserted, nothing inside the processor is active except the 3.6864-MHz
oscillator. The internal clocks are stoppe d and the chip is static. All pins return to their reset
conditions and the nBATT_FAULT and nVDD_FAULT pins are ignored. Because the memory
controller receives a full reset, all dynamic RAM contents are lost duri ng ha rdware reset.

DHW_NRESET

Clocks and Power Manager

to allow the system to stabilize and the reset

3.4.1.3 Completing Hardware Reset

To complete a hardware reset, deassert the nRESET pin. All power supplies must be stabl e for
t

D_NRESET

Mechanical, and Thermal Spec ification for details. After the nRESET pin is deasserted, this
sequence occurs:

1. The 3.6864-MHz oscillator and internal PLL clo c k ge nerators wait for stabiliz a t ion.

2. The nRESET_OUT pin is deasserted.

3. The normal boot-up se quence begins. All proce ssor units return to their predefined reset

before nRESET is deasserted. Refer to the Intel® PXA26x Processor Family Electrical,

conditions. Software must ex a mine the Reset Controller Status Register (RCSR) to determine
the cause for the boot.

3.4.2 Watchdog Reset

Watchdog reset is invok e d when software fails to properly pre v e nt the watchdog time-out event
from occurring. It is assumed that wa tchdog resets are only generated whe n software is not
executing properly and has potenti ally destroyed data. In watchdog reset, all units in the processor
are reset except the clocks and power ma nager.

3.4.2.1 Invoking Watchdog Reset

Watchdog reset is invoked when the Watchdog Enable (WE) bit in the OS Timer Watchdog Match
Enable Register (OWER) is set and the OS T imer Match Register 3 (O SMR3) matches the OS
timer counter. When these conditions are met , they invoke watchdog reset, regardless of the
previo us m o de of operation. Watchdog reset asse rts nRESET _ OUT.

Intel® PXA26x Processo r Family Develop er’s Manual 3-7

Clocks and Power Manager

3.4.2.2 B ehavior During Watchdog Reset

During watchdog reset, all units except the real time clock and parts of the clocks and power
manager maintain their defined reset conditions. All pins except the oscillator pins assume their
reset conditio ns and the nBATT_F AULT and nVDD_FAULT pins are ignored. All dynamic RAM
contents are lost during watchdog reset because the memory controller receives a full reset.

Refer to Table 2-6, “Pin & Sig na l Descriptions for the PXA26x Proce ssor Family” on page 2-9 for
the pin states during watchdog and other resets.

3.4.2.3 Completing Watchdog Reset

W atchdog reset immediately reverts to a hardware reset when the nRESET pin is asserted.
Otherwise, the completion sequence for watchdog reset is:

1. The watchdog reset source is deasser te d a fter t
Processor Family Electrical, Mechanical, and Thermal Sp ecification.

2. The 3.6864 MHz oscillator and interna l phase locked loop clock generators wait for
stabilizatio n. The 32.768-KHz oscillator’s configuration and status are not af fected by
watchdog re set.

3. The nRESET_OUT pin is deasse rted. Refer to the I ntel® PXA26x Processor Family
Electrical, Mechanical, and Therm al Sp ecification.

4. The normal boot-up sequence begins. All processor units except the RTTR in the real time
clock and parts of the cloc ks and power manager retu rn to their pr e de fined reset conditions.
Software must examine the RCSR to det ermine the cause for the reboot.

3.4.3 GPIO Reset

GPIO reset is invoked when GP[1] is properly configure d as a reset source and is assert ed low for
greater than four 3.6864 MHz clock cycles.

time clock, parts of the clocks and power ma nager, and the memory controller return to their
predefined, known states.

3.4.3.1 Invoking GPIO Reset

T o use the GPIO reset function, configure it through the GPIO controlle r. The GP[1] pin m ust be
configured as an input and set to its alternate GPIO reset fun ction in the GPIO controller. The
GPIO reset alternate functi on is level-sens itive and not edge-t riggered. To ensure no spurious resets
are generated when the alternate GPIO rese t function is set, follo w these steps:

DHW_OUT

In GPIO reset all the processor units except the real

. Refer to the Intel® PXA26x

1. GP[1] must be set up as an output wi th its data register set to a 1.

2. Externally drive the GP[1] pin to a high state.

3. Configure GP[1] as an input.

4. Configure GP[ 1] for it s a lt ernate (reset) fu n ct i on .

The previous mode of operation does not affect a GPIO reset. When GPIO res e t is invoked,
nRESET_OUT is asserted.

processor may rem a in in its previous mo de or enter GPIO reset.

3-8 Intel® PXA26x Processor Family Developer’s Manual

If GP[1] is asserted for les s than four 3.6864 MHz clock cycles, the

GPIO reset doe s not functi on in sleep mode because all GPIO pins’ alternate function inputs are
disable d. External wake -up sources must be routed thr ough one of the enabled GPIO wake-up
sources (see Section 3.5.3, on page 3-25 for details) during sleep mode. GP[1] may be enabled as a
wake-up s o urce.

3.4.3.2 Behavior During GPIO Reset

During GPIO rese t, most, but not all, internal registers and processes are held at their defined reset
conditions. The exception s are the RTC, the clocks and power manager (unless otherwise noted),
and the memory controller. During GPI O reset, the clocks unit continues to opera te with its
previously programme d values, so the processor enters and exits GPI O reset with the same clock
configurations . Al l pins except the oscillator and memory controller pins return to their res et
conditio ns and the nBATT_FAUL T and nVDD_FAUL T pins are ignor e d.

GPIO reset doe s not reset the Me mory Controller Configuration registers. This creates the
possibility that the contents of external memories may be preserved if the external memories are
properly configured befo re GPIO reset is entered. To preserve SDRAM contents during a GPIO
reset, softwar e must corr ectly configu re the memory cont rol and th e time spent in GPIO res et must
be shorter than th e SDRAM refresh interval. The amount of time spent in GPIO reset depends on
the CPU mode before GPIO reset. See Section 6, “Memory Controller” for details.

Clocks and Power Manager

Refer to Table 2-6, “Pin & Signal Descr iptions for the PXA26x Processor Family” on page 2-9 for
the states of all the PXA26x processor fam ily pins during GPIO reset and other resets .

3.4.3.3 Completing GPIO Reset

GPIO rese t imm ediat ely re ver ts to har dw ar e r eset w hen the nRE SET pi n i s as sert e d. Ot her wi se, t he
complet ion s eq ue n c e for GPIO reset is:

1. The GPIO reset source is deasserted because the internal reset has propagated to the GPIO
controller and its registers, whi ch are driven to their reset states.

2. The nRESET_OUT pin is deasserted.

3. The normal boot-up se quence begins. All processor units except the real time clock, parts of
the clocks and power manager, and the memory controller return to their predef ined reset
conditions. Software must ex amine the RCSR to determine the cause for the reset.

3.4.4 Run Mode

Run mode is the processor’s normal operating mode. All power supplies are enabled and all
functionally enabled clocks are running. Run mode is en te red after any power mode, power
sequence , or reset c ompletes its sequence. Run mode is exited when any other power mode, power
sequence, or reset begins.

3.4.5 Turbo Mode

Turbo mode allows the user to clock the processor core at a higher frequency during peak
processi ng requirements. It allows a synchronous switch in frequencies witho ut disrupting the
memory controller, LCD controller, or any pe ripheral.

Intel® PXA26x Processo r Family Develop er’s Manual 3-9

Clocks and Power Manager

3.4.5.1 E nt ering Turbo Mode

The ratio be twe en the run mode processor clock frequency and the turbo mode process or clock
frequency is programmed in CCCR[N]. The value in CCCR[N], and any other ap propriate clock
configurations, must be programmed through the frequency change s equence. To simultaneously
change turbo mode and enter th e freq uency cha nge sequen ce, use the steps to change t he freq uency
change sequence.

Turb o mode is invoked when software sets the TURBO bit in the Core Clock Config uration
Register (CCLKCFG) (See Se c tion 3.7.1). After software sets the T URBO bit, the CPU waits for
all instructions current ly in the pipeline to complete. When the instructions are comple ted, the CPU
resumes op e ra tion at the higher turbo mode frequency.

Software can set or clear other bits in the CCLKCFG in the same write that s ets the TURBO bit.
The other bits in the register take precedence over turbo mode, so, if another bit is set, that mode’s
sequence is followed before the CPU enters turbo mode. When the CPU exits the other mode, it
enters either run or turbo mode, based on the state of the CCLKCFG [TURBO] bit.

Do not confuse the CCLKCFG Register, which is in Coprocessor 14, with the CCCR (See

Section 3.6. 1), which is in t he processor’s clocks and power manage r.

3.4.5.2 B ehavior in Turbo Mode

The processor’s behavior in turbo m ode is identical to its behavior in run mode, exce pt that the
processor’s clock fr equency relative to the memory and pe rip herals is increased by N, the value in
the CCCR (see Section 3.6.1). Turbo mode is intended for use during peak processin g, when there
are very few accesses to external memory. The higher core to external memory clock ratio
increases the relative delay for each external memory access. This incr eased delay lowers the
processor’s power efficiency. For optimum performance, software must load applications in the
caches in run mode and execute them in turbo mode.

3.4.5.3 E xiting Turbo Mode

To exit turbo mode, software clears the TURBO bit in the CCLKCFG Register. After software
clears the TURBO bit, the CPU waits for all ins tructions in the pipeline to comp lete. When the
instructions ar e completed, the CPU enters run mode.

Other bits in the CCL KCFG may be set or cleared in th e write that clears CCLKCFG [TURBO].
All other bits in the register take pr ecedence over turbo mode, so the new mode’s proper sequence
is followed.

Idle, sleep, frequency change sequence, and reset have precedence over turbo mode and cause the
processor to exit turbo mode. When the CPU exits of one of these modes , it enters either run or
turbo mode, based on the state of CCLKCFG [TURBO].

3.4.6 Idle Mode

Idle mode allows the user to stop the CPU core clock during periods of processor inactivity and
continue to monitor on- and off-chip interrupt service requests. Idle mode does not change clock
generation, so when an interru pt occurs the CPU is quickly reactivated in the state that preceded
idle mode.

3-10 Intel® PXA26x Processor Family Developer’s Manual

During idle mode these resources are active:

• System unit modules (real-time clock, operating sys tem timer, interrupt controlle r, general-

purpose I/O, a n d the clocks and power man a ge r)

• Peripheral unit modules (DMA controller, LCD controller, and all other peripheral units)

• Memory controller resources

3.4.6.1 Entering Idle Mode

During idle m ode, the clocks to the CPU core stop. All critical a pplications must be finished a nd
peripher als m ust be set up to gen era te inte rrupt s when t h ey re qui re CPU a tt enti on. To enter the idle
mode, software selects idle mode in PWRMODE[M] (See Se c ti o n 3.7.2). An interr upt imm edi atel y
aborts idle mode and normal processing resumes. Afte r software selects idle mode, the CPU waits
until all instru ctions in the pipeline are completed. When the instructions are completed, the CPU
clock stops and idle mode beg ins. In idle mode, interrupts are recognized as wake-up sources.

3.4.6.2 Behavior in Idle Mode

In idle mo de the CPU clo cks ar e st opp ed, but t he r em ain der of th e pr oc esso r ope rate s norm ally. For
example, the LCD cont ro ller can continue ref reshing the screen with the s ame frame buffer data in
memory.

Clocks and Power Manager

When ICCR[DIM] is cleared , any enabled interrupt w akes up the processor. When ICCR[DIM] is
set, only unmasked inte rrupts cause wa ke-up.

Enabled inter rupts are those interrupts that are allowed at the unit level. The value in the Interrupt
Controller Mask Register prevents masked interrupts are from interrupting the c ore.

3.4.6.3 Exiting Idle Mode

Idle mode exits when any reset is as serted. Reset entry and exit sequences take precedence over
idle mode. Wh en the r ese t exit s eque nce is compl eted, t he CP U is no t in id le mod e. If th e wa tchdog
timer is enabled, softw are must set the Watchdog Match Registers before it se ts idle mode to ensure
that another in terrupt brings the processor out of idle mode bef ore the watchdog rese t is asserted.
Use an RTC alarm or another OS timer channel for this purpose.

Any enabled interrupt causes idle mod e to exit. When ICCR[DIM] is cleared, the Interrupt
Controller Mask Register (ICMR) is ignor e d during idle mode. This mean s that an interrupt does
not have to be unma sk ed to cause idle mode to exit. The idle mode exit sequ ence is:

1. A valid, enabled interrupt asserts

2. The CPU clocks restart

3. CPU resumes operation a t the state indic ated by CCLKCFG [TURBO]

Idle mode also exits when the nBATT_FAULT or nVDD_FAULT pin is asserted. When ei ther pin
is asserted, idle mode exits in this sequence:

1. The nBATT_FA ULT or nVDD_ FAULT pin is asserted.

2. If the Imprecise Da ta Abort Enable (IDAE) bit in the P ower Manager Control Register
(PMCR) is clear (not recommended), the proces s or enters sleep mode immediately.

3. If the IDAE bit is set, the nBATT_FAULT or nVDD_FAULT asse rti on is treated as a valid
interrupt to the cl ocks m odu le and idle mode e xits using its norm al, i nterr upt -d rive n sequ ence .

Intel® PXA26x Processo r Family Develop er’s Manual 3-11

Clocks and Power Manager

Software must then shut down the system and enter sleep mode. See Section 3.4.9.3, “Entering

Sleep Mode” for more details.

3.4.7 33-MHz Idle Mode

33-MHz id le mode has th e lo we s t pow e r c on s u mption of an y id l e mo de . The run mode fre q u e nc y
selected in the Core Clock Conf igura tion Regist er (CCCR) dir ectly af f ects the processor id le mode
power consumption. Fas ter run mode frequencies consume more power. 33-MHz idle mode places
the processor a sp ecial low speed r un mo de before enterin g idle. This is simila r t o normal idle sin ce
the CPU core clo c k c an be stopped during periods of processor inactivity and continue to monitor
on- and off-ch ip interrupt service re quests. 33-MHz idle limitations are:

• Peripherals will not function correctly and should be disabled befor e e ntering this mode.

• A Frequency Change Sequence mu st be performed upon entry to and exit from 33-MHz idle

mode.

• SDRAM is placed in self refresh before entering 33- MHz idle mode, because SDRAM cannot

be refreshed correctly in 33-MHz idle mode. Car efully consider the processor interrupt
behavior when the SDRAM in sel f refresh. To allow the interrupts to occur while SDRAM is
in self refresh, set the I and F bits in the CPSR. This allows interrupts to wake the processor
from idle mode without jumping to the inter rupt handler. When the system’s SDRAM is no
longer in self refresh, the I and F bits can be cleared and the interrupt is handled.

• Because nBATT_FAULT and nVDD_FAU LT can cause a data abort interrupt, the function of

these pins in 33-MHz idle mode also needs special consideratio n. Either the Imprecise Data
Abort Enable (IDAE) bit in the Power Manage r Control Register (PMCR) mu st be clear,
(causing the processor to immediately enter sleep mode if either nBATT_FAULT or
nVDD_FAUL T a re asserted) or take softw a re precautions to avoid starting execution in or
trying to use SDRA M while it is in self refresh.

During 33-Mhz idle mode these system uni t modules are func tional:

• Real-time clock

• Operating system timer

• Interru p t c on t ro lle r

• General purpo se I/O

• Clocks and power manager

• Flash ROM/SRAM

Unlike norm al id le mode, in 33-MH z idl e mo de al l ot her periph era l un its c annot be us ed , inc ludin g
SDRAM, LCD and DMA controllers.

3.4.7.1 Entering 33-MHz Idle Mode

During idle mode, the processor core clocks stop. Before the clocks stop, all critical applicat ions
must be fi nish ed an d pe ri phe ral s tur ned of f. I f s oft war e i s e xecu tin g fro m SDRAM, t he l as t th ree of
the following steps must b e loaded into the cache before being performed.

1. Set the I and F bits in the CPSR register to mask all interrupts

2. Place the SDRAM into self refresh mode

3-12 Intel® PXA26x Processor Family Developer’s Manual

3. Perform a frequency change seq uence to 33MHz mode. The CCCR value for this mode is
0x13F

4. Enter idle mode by selecting the PWRMO DE[M] bit (refer to Section 3.7.2)

3.4.7.2 Behavior in 33-MHz Idle Mode

In 33-MHz idle mode the CPU clocks are stopped. While in 33-MHz idle mode these features of
the processor al l oper ate normall y: the RTC timer, th e OS ti mers in cluding the watc hdog ti mer, and
the GPIO interrupt capabilities.

When ICCR[DIM] is cleared , any enabled interrupt w akes up the processor. When ICCR[DIM] is
set, only unmasked inte rrupts cause wa ke-up.

Enabled interrupts are interrupts that are allowed at the unit level. Masked inter rupts are interrupts
that are prevented from interrupting the core based on the Interr upt Controller Mask Register
(ICMR).

3.4.7.3 Exiting 33-MHz Idle Mode

The 33-MHz idle mode exit procedur e is the same as the exit procedure for normal idle mode.
However, because the I and F bits are set in the CPSR, the processor does not immediatel y jump to
the interrupt vector. Instead processing continues wit h the instruction following th e last executed
instructi on bef ore 33-M Hz idle m ode was en ter ed. I f exe c ution o cc urs fro m SD RAM, s t eps 1 and 2
must have been previously lo aded into the instruction cache. The steps bel ow are then taken:

1. Perform a frequency change to a supported run mode frequency, greater or equal to 100 MHz.

Clocks and Power Manager

2. Take the SDRAM out of self refresh.

3. Clear the I and F bits in the CPSR. Execution immediately jumps to the pending interrupt
handler.

3.4.8 Frequency Change Sequence

Use the frequency change sequence t o chan ge the proces sor clock fr equency. During the frequency
change sequence, the CPU, memory contro ller, LCD controller, and DMA clocks stop. The other
periphera l units continue to function dur ing the frequency change sequ e nc e . Use this mode to
change the frequency from the default c ondition at initial boot-up . It may also be used as a power­saving fea ture that lets the processor run at the minimum required frequenc y when the software
requires major changes in frequency.

3.4.8.1 Preparing for the Frequency Change Sequence

Software must complete these steps before it initiates the frequency change sequence:

1. Configure the memory controller to ensure SDRAM contents are maintained during the
frequency change sequence. The memory controller’s refresh timer must be programmed to
match the maxi mum refresh time a ssociated with the slower of two frequen c ie s (current a nd
desired). The SDRAM divide by two must be set to a value tha t prevents the SDRA M
frequency from exceeding the specified f requency . For example, to change from 100/100 to
133/66, the SDRAM bus must be set to divide by two before the frequency change. To change
from 133/66 to 100/100, the SDRAM must be set to one -to-one after the frequency change
sequence is completed. See Sec tion 6, “Memory Controller” for more details.

Intel® PXA26x Processo r Family Develop er’s Manual 3-13

Clocks and Power Manager

2. Disable the LCD controller or configure it to avoid the effects of an interruption in the LCD
clocks and data from the processor.

3. Configure peripheral units to han dle a lack of DMA service for up to 500
unit can not function for 500

4. Disable peripheral units that can not accommodate a 500
generated during the frequency change sequence are serviced when the sequence exits .

5. Program the CCCR (Section 3.6.1, “Core Clock Configuration Register (CCCR)”) to reflect
the desired frequency.

µs without DMA ser vice, disable it.

3.4.8.2 Starting the Frequency Change Sequence

T o start the frequency change sequence, software must se t the Frequency Change Sequence bit
(FCS) in the CCLKC FG (See Sectio n 3.7.1). When software sets FCS, it may also set or clear other
bits in CCLKCFG. If software sets the TURBO bit in the same writ e, the CPU enters turbo m ode
when the frequency change sequence exits.

After soft wa re se ts the FC S:

1. The CPU clock stops and CPU interrupts are gated.

2. The memory controller completes all outs tanding tr ansact ions in it s buf fe rs and fro m the CPU.
New transa c t ions from the LCD or DMA cont rollers are ignored.

3. The memory controller places the SD RAM in self-ref resh mode.

Note: Program the memory controller to ensure the cor rect self-refresh time for SDRA M, gi ven the

slower of the current and des i red clock frequencies.

µs. If a peripheral

µs interrupt latency. The interrupts

3.4.8.3 B ehavior During the Frequency Change Sequence

In the frequency change sequence, the processor’s PLL cl oc k generator is in the process of locking
to the correct frequency and ca nnot be used. This means that int e rrupts cannot be processed.
Interrupts that occur durin g the frequency change sequence are serviced af ter the processor’s PLL
has locked. The 95.85 MHz and 147.46 MHz PLL clock generators are active and peripherals
(except memory contr oller, LCD contr oller , and DMA) may continu e to operate normally, provided
they can accommodate the inability to process DMA or interrupt requests. DMA or interrupt
requests are not recognize d unt il the frequency change sequence is com plete.

The imprecise da ta abort is also not recognized and if nVDD_FAULT or nBATT_FAULT is
asserted, the assertion is ignor ed until the frequency change seque nce exits. This means that the
processor does not enter sleep mod e until the frequency change sequence is complete.

3.4.8.4 Completing the Frequency Change Sequence

The fr e quency change sequen c e exits when any rese t is asserted. In ha rdware and watchdog resets,
the reset entry and exit sequences take precedence over the frequency change sequence and the
PLL resumes in its reset condition. I n GPIO reset, the reset exit sequence is delayed while the PLL
relocks an d the frequency is set to the des ired frequency of the frequency change sequence.

If the watchd og timer is enabled during the frequency change sequence, set the Watchdog Match
Register to ensure that the frequency change sequence completes before the wat chdo g reset is
asserted.

3-14 Intel® PXA26x Processor Family Developer’s Manual

Clocks and Power Manager

If hardware or watchdog reset is asserted during the frequency change sequence, the DRAM
contents are lost becaus e all s tates, including memory contro ller configuration and information
about the previous frequency chang e se quence, are reset. If GPIO reset is asserted during th e
frequency change sequence, the SDRAM contents are lost during the GPIO reset exit sequence if
the SDRAM is not in self-refresh mode and the exit sequence exceeds the refresh interval.

Normally, the frequency change sequence exits in this sequence:

1. The processor’s PLL clock generator is reprogr ammed with the desired values (in the CCCR)
and begins to relock to those value s.

Note: The frequency change sequence occurs even if the before and after frequ encies are the same.

2. The internal PLL clock generator for the processor clock waits for st abilization. Refer to the
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification for
details.

3. The CPU clocks restart and the CPU resumes operation at the state indicated by the TURBO
bit (either run or turbo mode). Interrupts to the CPU are no longer gated.

4. The FCS bit is not automatically cleared. To prevent an accidental return to the frequency
change sequence, software must not immediat ely clear the FCS bit. The bit must be cleared o n
the next required write to the reg is ter.

5. Values may be written to th e CCCR, but they are ignored until the frequency change se quence
is re-ent er ed.

6. The SDRAM must transition out of self-refresh mode and into its idle state. See Chapter 6,

“Memory Controller” for details on configuring the SDRAM interface .

3.4.9 Sleep M ode

Sleep mode offers lower pow er consumption at the expense of the loss of most of th e internal
processor state. In sleep mode, the processor goes through an orderly shut-down sequence . The
PXA26x process or family supports tw o sleep mode configurations: one that minimizes power
consumption and one that minimi zes sl eep exit latency .

To minimize power consumption during sleep, drive the VCC and PLL_VCC supplies to ground
when PWR_EN deasserts. To minimize sleep exit latency:

• VCC and PLL_VCC power supplies must remain enabled during sleep

• Software must disable the power supply st a bilization delay during the wa ke-up sequence

When in sleep mo de, the power manager watches for a wake-up event and, after it receive s one, re­establishes power (if needed) and goes through a reset sequence. During sleep mode, the RTC and
power mana ger continue to function. Pin s t a tes can be controlled throughout sleep mode and
external SDRAM is preserved because it is in self-refresh mode.

Because all processor act ivity (except the RTC) stops when sleep mode starts, peripherals must be
disabled to allow an orderly s hut dow n. When sleep mode exits, the processor’s s tate resets and
processing resumes in a boot-up mode.

3.4.9.1 Sleep Mode External Voltage Regulator Requirements

For maximum f lexibil ity wit h the im pl ementat ion of sleep m ode , the externa l po wer supp ly sy stem
must have these character is tics:

Intel® PXA26x Processo r Family Develop er’s Manual 3-15

Clocks and Power Manager

• A power enable input pin that enables the primary supply output connected to VCC a nd

PLL_VCC. This pin must be connected to the processor’s PWR_EN pin. To support fast sleep
wake up by maintaining power during sleep, the regulator should be software configurable to
ignore PWR_EN. When PWR_EN is not used, VCC and PLL_VCC may be powered on
before or simultaneously with VCCN and VCCQ. In this configuration, when PWR_EN is
deasserted the core regulator must be able to maintain regulation when the load power is as
little as 0.5 mW. Core supply current during sleep varies with voltage and temperature.

• When core power is enabled during sleep, the power management IC or logic that generates

nVDD_FAUL T must assert this signal when any supply including VCC and PLL_VCC falls
below the lower-regulation limit during sleep. nVDD_FAULT must not b e deasserted until all
supplies are a gain in regulation since ther e is no power-supply-stabilization-delay during the
fast-sleep-wake-up sequence. If nVD D_FAUL T is assert ed during fas t-sleep wake up, th en the
processor returns to sleep mode.

• When configured to sa ve power dur ing sleep by dis ablin g the supply, drive the core regulato r’ s

output to ground when PWR_EN goes low.

• Higher-voltage outputs c onnected to VCCQ and VCCN are cont inuously driven and do not

change when the PWR_EN pin is asserted.

3.4.9.2 Preparing for Sleep Mode

To prepare for sleep mode, software must:

1. Configure the memory controller to ensure SDRAM contents are maintained during sleep
mode. See Chapter 6, “Memory Controller” for details.

2. If a graceful shutdown is required for a peripheral, disable the peripheral before sleep mode
asserts. This includes monitoring DMA transfers to and from per ipherals or memories to
ensure they are completed. All ot her peripherals need not be disabled, since they are held in
their reset state s in ternally during sleep mode.

3. Set up these power manager (PM) registers for proper sleep entry and exit:

— PM GPIO Sleep S tate r egist ers (P GSR0, PGS R1, PGSR2) . To avoid contention on th e bus

when the processor att empts to wake up , ensur e that t he c hip s elects are not set to 0 durin g
sleep mode. If a GPIO is used as a n input, it must not be a llowed to float during sleep
mode. The GPIO can be pulled up or down externa lly or changed to an output and driven
with the unasserted value.

— PM General Configu rat ion Register Flo at bit s [FS/ FP]. Con fi gure the se bi ts appropr iat ely

for the system . The General Configu ration Regis ter Flo at b its must b e clear ed on wake u p.
To avoid contention on the bus when the processor attempts to wake up, ensure that the
chip selects are not set to 0 during sleep mode. The PCFR[OPDE] bit must be cleared to
leave the 3.6864 MHz enabled dur ing sleep if the fast-wake-up-sleep configuration is
selected using the PMFWR[FWAKE] bit.

— PMFWR configuration re gister. Set this register to select b etween the standard and fast-

sleep-wa ke-up confi gurati ons. If power is maint ained dur ing sl eep, se t PMFW R[FWAKE]
to 1 to disable the 10 ms power supply stabilization delay during sleep wake up. This
configuration redu ces the s leep wake up time to approximately 650

µs.

4. Before the IDAE bit is set, software must configure an i mprecise dat a a bort exception handler
to put the processor into sleep mode. This is necessar y when a data abort occurs in re sponse to
nVDD_FAULT or nBATT_FAULT assertion. This abort exception event indicates that the
processo r is in peril of losing its main power supply.

5. Set up these power manager registers to detect wake-up sources a nd oscillator activity:

3-16 Intel® PXA26x Processor Family Developer’s Manual

— PM GPIO Sleep State registers (PGSR0, PGSR,1 and PGSR2)
— PM Wake-up Enable regi s ter (PWE R )
— PM GPIO Falling-edge Detect Enable and PM GPIO Rising-edge Detect Enable r egisters

(PFER and PR ER)
— OPDE bit in the Pow e r Ma nager Configuration Registe r (PCFR)
— IDAE bit in PMCR

Note: Clear the PCFR[OPDE] bit t o en able the 3.6 864-M Hz osc illa tor du rin g slee p when f as t-sleep wake

up is selected using the PMFWR[FWAKE] bit.

3.4.9.3 Entering Sleep Mode

Software uses the PWRMODE register to enter sl eep m ode (See Section 3.7.2).
If the external volt age regul ator is fail ing or the main ba ttery is low or missi ng, s ome syst ems must

enter sleep mode quickly. When nBA TT_FAULT or nVDD_FAULT is asserted, the system is
required to s hut down immediately.

To allow the assertion of nVDD_FAULT or nBATT_FAULT to cause an imprecise data abort, set
the Imprecise Da ta Abort Enable (IDAE) bit in the PMCR. Setting the ID AE bit in the PMCR
results in software executing the data abort handler routine as part of entering sleep mode. If the
IDAE bit is cle ar , th e process or en ters sleep mode im mediat ely wit hout ex ecuting the abor t handl er
routine.

Clocks and Power Manager

Note: Use an exception handler to invoke sleep i n re sp onse to a power fault event. Becaus e s oftware can

clear the PMFWR[FWAKE] bit and configure the power management IC to use PWR_EN to
disable t he cor e po wer su ppl y du ring s leep and th us minim ize pow er con sum pti on fro m a cr iti cally
low battery.

PSSR[VFS] and PSSR[BFS] can not be used prior to entering sleep mode to determine which type
of fault oc c urred, VDD fault or battery fault, res pectively. If either nVDD_FAULT or
nBATT_FAULT signals are asserted or if both are asserted at the same time (and the IDAE bit of
the PMCR is set), the software data abort handler is called. Since there is only one common data
abort han dler, software must f i rst determine if one of the two nVDD_FAULT or nBATT_FAULT
assertion events resulted in an imprecise data abort by reading Coprocessor 7, Register 4, Bit 5
(PSFS). If the PSFS bit is cleared, neith er a nVDD_FAULT or nBATT_FAULT assertion occurred
and the data abort handler was called for so me other reason. If the PSFS bit is set, this indicates
either a nVDD_FAULT or nBATT_FAULT assertion occurred, but it is not possible to determine
which of the two faults was asserted. F or either case, nVDD_FAULT or nBATT_FAULT a sser tion,
software should shut down the system as quickly as pos sible by perf orming the steps outlined
below to enter sleep mode.

Note: All addresses (data and instruction ) used in the abort handler routines should be resident and

accessible in the memory page tables, that is system software developers should ensure no furth e r
aborts occur while executing an abort handler . The processor does not supp ort recursiv e (nested)
aborts. The system must not assert nBATT_F AU LT or nVDD_FAULT signals more than once
before nRESET_OUT is asserted. System software can not return to normal execution following a
nBATT_FAULT or nVDD_FAULT. If a battery or VDD fault occurs while executing in the abor t
mode, the abort h andler is re enter ed. Th is condit ion of a recur sive abor t occur rence ca n be dete cted

Intel® PXA26x Processo r Family Develop er’s Manual 3-17

Clocks and Power Manager

in software by reading the Saved Program Status Register (SPS R) to see if the previous context
was executing in abort mode.

To enter sleep mode, software must complete this sequence:

1. Software uses external memory and the Power Manager Scratch Pad Register (PSPR) to
preserve critical states.

2. Software sets s leep m ode in PW RMO DE[M]. A n i nte rrupt im media te ly a bort s sleep m ode and
normal processing resumes.

3. The CPU waits until all instructions in the pipeline are complete.

4. The memory controller complete s outstanding trans actions in its buffers and from the CPU .
New transa c t ions from the LCD or DMA cont rollers are ignored.

5. The memory controller places the SD RAM in self-ref resh mode.

6. The power manager switches the GPIO output pins to their sleep state. This sleep state is
programme d in a dvance by loading the Power Ma nager GPIO Sleep State registers ( PGSR0,
PGSR1, and PGSR2). To avoid contention on the bus when the processo r at tempts t o wake up,
ensure that the chip selec ts are not set to 0 during sleep mode.

7. The CPU clock stops and power is removed from the Core.

8. PWR_EN is deasserted.

When the power manger gets the indication from the memory controller that it has finished its
outstanding transact ions and has p ut the SDRAM int o self- refresh , there ar e e ight co re clock cycles
before the GPIOs latch the PGSR values and four core clo ck cycles after that, nRESET_OUT
asserts low.

In some systems the imprecise data abort latency lasts longer than the residual charge in the failed
power supply can sustain operation. This normally only occurs when the processor is in a power
mode or sequence that requires that the processor exit before sleep mode starts. Frequency change
sequence is an example of such a pow er sequence. In th es e power modes and se quen ces, the IDAE
bit must not be set. This allows the processor to enter sleep mode immediately but any critical
states in the processor are lost.

If the IDAE bi t is not set and the nVDD_FAULT or nBATT_FAULT pin is asserted, the sleep
sequence begins at step 4 in the list above.

3.4.9.4 Behavior in Sleep Mode

In sleep mode, all processor and peripheral clocks (except the RTC) are disabled. The processor
does not recogn ize in ter ru pts or exte rn al pin trans iti ons exc e pt val id wa ke-up sig nal s, re set si gnal s,
and the nBATT_FAULT signal.

If the nBATT_FAULT signal is asserted while in sleep mode, GPIO[1:0] are set as th e only valid
wake-up s i gnals.

The power manage r watc hes for wake up even ts pro gr ammed by the CPU before slee p mode st art s
or set by th e p ower man ager i t d etect s a fau lt cond ition . In order t o detec t a GP I O pin r i sing -ed ge or
falling-e dge, the rising- or falling- e dge must b e held for more than on e full 32.768-KHz-clock
cycle. The power manager takes three 32.768-KHz- clock cycles to acknowledge the GPIO edge
and begin the wake up sequence.

3-18 Intel® PXA26x Processor Family Developer’s Manual

Refer to Table 2-6, “Pin & Signal Descr iptions for the PXA26x Processor Family” on page 2-9 for
the PXA26x processor family pin sta t e s during sleep mode reset and other rese ts.

3.4.9.5 Exiting Sleep Mode

Sleep mode exits when h ardware reset is asserted. Hardware rese t entr y and exit sequences take
precedence over sleep mode.

Note: If hardware reset is asserted during sleep mode, the DRAM contents are lost because all states,

including memory contr oller configuration and information about the previous sl eep m ode, are
reset.

Normally, sleep mode exits in the sequence below . Any time the nBATT_FAULT pin is asserted,
the processor returns to sleep mode.

1. A pre-programmed wake up event from an enabled GPIO or RTC source occurs. If the
nBATT_FAULT pin is asserted, the wa ke up source is ignored.

2. The PWR_EN signal is asserted and the power manage r waits for th e external po wer supp ly to
stabilize if PMFWR [F WAKE] is cleared. After this, if nVDD_FAULT is as serted the
processor returns to sleep mode.

3. If PCFR[OPDE] and OSCC[OON] were set when sleep mode started, the 3.6864 MHz
oscillator is enabled and stabilizes . Otherwise, the 3.6864 MHz oscillator is already stable and
this step is bypassed.

Clocks and Power Manager

4. The processor’s PLL clock generator is reprogr ammed with the values in the CCCR and
stabilizes.

5. The sleep mode configuration in PWRMODE[M] is cleared.

6. The processor’ s int ern al rese t is de asser ted an d th e CP U be gins a n orma l bo ot seque nc e. W hen
the normal boot sequence begins, all of the pro c e ssor’s units (except the RTC and portions of
the clocks and power manager and the memo ry controller) return to their predefined reset
settings.

7. The nRESET_OUT pin is deasserted. This indicates that the process or is about to perform a
fetch from the reset vector.

8. Clear PSSR[PH] before accessing GPIOs, this includes chip selects that are muxed wi th
GPIOs.

9. Clear PCFR[FS] and PCFR[FP] if either was set before sleep mode was triggered.

10. The SDRAM must transition out of self-refresh mode and into its idl e st ate. See Chapter 6,

“Memory Controller” for details on configuring the SDRAM interface .

11. Software must examine the RCSR, to determine what caused the reboot, and the Power
Manager Sleep Status Register (PSSR), to determine what triggered sleep mode.

12. If the PSPR was used to preserve any critical states during sleep mode, software can now
recover the information.

If the nVDD_FAULT or nBATT_FAULT pin is asserted during the sleep mode exit sequence, the
system re-enters sleep mode in this sequence:

1. Regardless of the state of the IDAE bit:
— All GPIO edge detects and the RTC alarm interrupt are cleared.

Intel® PXA26x Processo r Family Develop er’s Manual 3-19

Clocks and Power Manager

— The power manager wake-up source re gisters (PWER, PRER, an d PFER) are loaded with

0x0000 0003, their wake-up default stat e . This limits the potential wake-up sources to a
rising or falling edge on GPIO[0] or GPIO[1]. The wake-up fault state prevents spurious
events from causing an unwanted wake-up while the battery is low or the power supply is
at risk. The fault state is also the default state after a hardwar e res et.

2. The PLL clock generators are disabled.

3. If the OPDE bit in the PCFR is set and the OON bit in the OSCC is set, the 3.6864 MHz
oscillator is disabled. If the oscillator is disabled, sle e p mode consumes le ss power. If it is
enabled, sleep mode exits more qui ckly.

4. An internal reset is generated to the core and most perip heral modules. This res e t as serts the
nRESET_OUT pin.

5. The PWR_EN pin is deasserted. If PMFWR[FWAKE] is cleared, the system must respond by
grounding the VCC and PLL_VCC power supplies to minimize powe r consumption.

3.4.10 Power Mode Summ ary

Table 3-4 shows the actions that occur when a power mode is entered. Table 3-5 shows the actions

that occur when a power mode is exited. In the tables, an empty cell means that the powe r mode
skips that step. Table 3-6 shows the expected behavior for power supplies in each power mode.

Table 3-4. Power Mode Entry Sequence T able

Step

1 Software writes a bit in CP14 x x x x x
2 The CPU waits until all instructions to be completed x x x x x
3 Wake up sources are cleared and limited to GP[1:0] x
4 The power manager places GPIOs in their sleep states x x
5 The memory controller finishes all outstanding transactions x x x
6 The memory controller places SDRAMs in self-refresh x x x
7 The PLL is disabled x x x
8 If OPDE and OOK bits are set, disable 3.6864 MHz oscillator x x
9 Internal reset to most modules. nRESET_OUT asserted x x

10 PWR_EN is deasserted. x x

NOTE: 1. Fault sleep mode starts if IDAE is clear and nBATT_FAULT or nVDD_FAULT is asserted.

Description of Action

Sleep

Turbo

Idle

Freq Change

Run (from Turbo)

1

Sleep

Fault

3-20 Intel® PXA26x Processor Family Developer’s Manual

.

Table 3-5. Power Mode Exit Sequ en ce Table

Clocks and Power Manager

Step

Description of Action

Turbo

Idle

Sleep

Freq Change

Run (from Turbo)

1 Wake up source or interrupt is received x x x
2 Power to I/O pins restored
3 PWR_EN is asserted x x
4 External power ramp (if core supply was disabled in sleep) x x
5 Enable 3.6864 MHz oscillator if OPDE and OOK are set x x

Wait for 3.6864 MHz oscillator to stabilize if OPDE and OOK

6

are set

xx

7 Enable PLL with new frequency x x x
8 Wait for PLL stabilization x x x

9 Wait for internal stabilization x x
10 Clear CP14 bit x x
11 Deassert nRESET_OUT x x
12 Restart CPU clocks, enable interrupts x x x x x x

NOTE: 1. Fault sleep mode starts if IDAE is clear and nBATT_FAULT or nVDD_FAULT is asserted.

Sleep

1

Fault

Intel® PXA26x Processo r Family Develop er’s Manual 3-21

Clocks and Power Manager

Table 3-6. Power and Clock Supply Sources and States During Power Modes

Power Mode

Module

Supply Source

Turbo Run Idle

Pw Ck Pw Ck Pw Ck Pw Ck Pw Ck Pw Ck

Freq

Change

Sleep

CPU,
Caches,
Buffers

Memory
Controller

LCD
Controller

DMA
Controller

General
Periphs.

OS timer
Interrupts
Real Time

Clock
Power

Manager
GP[3:0], PM

pads, Osc
pads

General IO H
KEY:

T – Turbo clock
R – Run clock
V – Module powered off VCC.
I – Module powered off internal regulator
H – Module powered off VCCQ or VCCN
D – Module is dynamic or actively clocked
S – Module is static or clocks are gated.

VCC

VCC/

Reg

(V/R)

HV/
Batt

(H/B)

Run/

Turbo
(R/T)

Mem

PLL

3.686-

MHz Osc

32.768-

KHz Osc

Dynamic/

Static
(D/S)

T

On

On On On

VOnVOnVOnVOnI On

HDHDHDHDHS

On

R

On

Off

On

changing

Off Off

On

3.5 Power M anager Registers

This section des c ribes the 32-bit registers that control th e power manager.

3-22 Intel® PXA26x Processor Family Developer’s Manual

3.5.1 Power Manager Control Register (PMCR)

Use the PMCR, refer to Table 3 -7 , to select how sleep mode is ent ere d whe n t he nV DD_FAULT or
the nBATT_FAULT pin is asserted low. When the IDAE bit is set, an imprecise data abort
indication is sent to the CPU. The CPU then performs an abort routine. Sof twar e mu s t ensure that
the abort routine sets th e s leep mode configuration in the PWRMODE register (see Section 3.7.2,

“Power Mode Regis ter (PW RMODE)”) . The IDA E bit is clear ed in an y reset a nd when sleep m ode

exits. Software may a lso cl ear the IDA E bit wh en necessary. The PMCR must be protected throu gh
Memory Management Unit (MM U) permis sions.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-7. PMCR Bit Definitions

0x40F0_0000 PMCR Clocks and Power Manager

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Clocks and Power Manager

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31:1] — Reserved

Imprecise Data Abort Enable.
0 – Allow immediate entry to sleep mode when nVDD_FAULT or nBATT_FAULT is

0IDAE

asserted.

1 – Force imprecise data abort signal to CPU to allow software to enter sleep mode

when nVDD_FAULT or nBATT_FAULT is asserted. Recommended mode.

Cleared on hardware, watchdog, and GPIO reset, or when sleep mode exits.

IDAE

Intel® PXA26x Processo r Family Develop er’s Manual 3-23

Clocks and Power Manager

3.5.2 Power Manager General Configuration Register (PCFR)

Use the PCFR, refer to Table 3-8, to co nf igu re po wer m anag er f u nct ion s in th e pr oc esso r. When the
OPDE bit is set, it allows the 3.6864-MHz oscil la t or to be disabl e d during sleep mode. The OPDE
bit is cleared in hardware, watchdog, and GPIO rese ts. The Float PCMCIA (FP) and Fl oa t Static
Memory (FS) bits control the state of the PCMCIA control pins and the static memory con trol pins
during sleep m ode.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-8. PCFR Bit Definitions

0x40F0_001C PCFR Clocks and Power Manager

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31:3] — Reserved

Float Static Chip Selects during sleep mode.
0 – Static chip select pins are not floated in sleep mode. nCS[5:1] are driven to the state

2FS

1FP

0OPDE

of the appropriate PGSR register bits. nCS[0], nWE, and nOE are driven high.

1 – Static chip select pins are floated in sleep mode. The pins nCS[5:0], nWE, and nOE

are affected.

Cleared on hardware, watchdog, and GPIO resets.
Float PCMCIA controls during sleep mode.

0 – PCMCIA pins are not floated in sleep mode. They are driven to the state of the

appropriate PGSR register bits.

1 – The PCMCIA signals: nPOE, nPWE, nPIOW, nPIO R, and nPCE[2:1] are floated in

sleep mode. nPSKTSEL and nPREG are derived from address signals and assume
the state of the address bus during sleep mode.

Cleared on hardware, watchdog, and GPIO resets.

3.6864 MHz oscillator power-down enable.
If the 32.7686-KHz crystal is disabled because the OON bit in the Oscillator

Configuration Register is 0, OPDE is ignored and the 3.6864 MHz oscillator is not
disabled.

0 – Do not stop the oscillator during sleep mode.
1 – Stop the 3.6864 MHz oscillator during sleep mode.
Cleared on hardware, watchdog, and GPIO resets.

FS

FP

OPDE

3-24 Intel® PXA26x Processor Family Developer’s Manual

Clocks and Power Manager

3.5.3 Power Manager Wake-Up Enable Register (PWER)

PWER, refer to Table 3-9, shows the location of all wake up source enable bits. If a GPIO is used
as a sleep-mode wake up source, program it as an input in the GPDR and set either on e or both of
the corresponding bits in the PRER and PFER. When the IDAE bit is zero and a fault condition is
detected on the nVDD_FAULT or nBATT_FAULT pin, PWER is se t to 0x0000 0003 and only
allows GP[ 1:0] as wake-up sources. When the IDAE bit is set, fault conditions on the
nVDD_FAULT or nBATT_FAULT pins do not affect wake-up sources . PWER is also set to
0x0000 0003 in hardware, watchdog, or GPIO rese ts.

Software should enable wake ups only for those GPIO pins that are configured as inputs during
sleep. Any GPIO pins that are configur ed as outputs during s leep, should have their associated
wake enable bits set to logic zero in all three PMU wake enable registers (PWER, PRER, and
PFER).

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-9. PWER Bit Definitions

0x40F0_000C PWER Clocks and Power Manager

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

Reserved

WERTC

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

RTC SLEEP MODE WAKE UP ENABLE:

31 WERTC

[30:16] — Reserved

[15:0] WEx

0 – Wake up due to RTC alarm disabled.
1 – Wake up due to RTC alarm enabled.
Cleared on hardware, watchdog, and GPIO resets.

SLEEP MODE WAKE UP ENABLE:
0 – Wake up due to GPx edge detect disabled.
1 – Wake up due to GPx edge detect enabled.
Set to 0x 0003 on hardware, watchdog, and GPIO resets.

WE15

WE14

WE13

WE12

WE9

WE8

WE7

WE6

WE5

WE4

WE3

WE2

WE11

WE10

WE1

WE0

Intel® PXA26x Processo r Family Develop er’s Manual 3-25

Clocks and Power Manager

3.5.4 Power Manager Rising-Edge Detect Enable Register (PRER)

The PRER, refer to Table 3-10, determines whether the GPIO pin enabled via the PWER register
causes a sleep-mo de wake up on the GPIO pin’s rising edge. When the IDAE bit is zero and a fault
condition is detected on the nVDD_FAULT or nBATT_ FAULT pin, PRER is set to 0x0000 0003.
This enables risi ng edges on GP[1:0] to act as wake up sources. Wh en the IDAE bit is set, fault
condition s on the nVDD_FAULT or nBATT_FAU LT pins do n ot a ffect wake-up sourc e s. PRER is
also set to 0x0000 0003 in hardware, watchdog, and GPIO resets.

Software shoul d enable wake ups only for those GPIO pins that are configured as inputs during
sleep. Any GPIO pins th at are configured as outputs during sleep, should have their associated
wake enable bits set to logic zero in all three PMU wake enable registers (PWER, PRER, and
PFER).

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-10. PRER Bit Definitions

0x40F0_0010 PRER Clocks and Power Manager

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

[31:16] — Reserved

SLEEP MODE R I SING-EDGE WAKE-UP ENAB LE:

[15:0] REx

0 – Wake up due to GPx rising-edge detect disabled.
1 – Wake up due to GPx rising-edge detect enabled.
Set to 0x 0003 on hardware, watchdog, and GPIO resets.

RE15

RE14

RE13

RE12

RE9

RE8

RE7

RE6

RE5

RE4

RE3

RE2

RE11

RE10

RE1

RE0

3-26 Intel® PXA26x Processor Family Developer’s Manual

Clocks and Power Manager

3.5.5 Power Manager Falling-Edge Detect Enable Register (PFER)

The PFER, refer to Table 3-11, determines if the GPIO pin enabled via the PWER register cause s a
sleep-mode wake up on the GPIO pin’s falling edge. When the IDAE bit is zero and a fault
condition is detected on the nVDD_FAULT or nBATT_F AULT pin, PFER is set to 0x0000 0003.
This enables falling edges on GP[1:0 ] to act as wake up sources. When the IDAE bit is set, fault
conditio ns on the nVDD_FAULT or nBATT_FAULT pins do not affect wake-up sources . PFER is
also set to 0x0000 0003 in ha rdware, watchdog, and GPIO re sets.

Software should enable wake ups only for those GPIO pins that are configured as inputs during
sleep. Any GPIO pins that are configur ed as outputs during s leep, should have their associated
wake enable bits set to logic zero in all three PMU wake enable registers (PWER, PRER, and
PFER).

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-11. PFER Bit Definitions

0x40F0_0014 PFER Clocks and Power Manager

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

[31:16] — Reserved

SLEEP MODE FALLING-EDGE WAKE-UP ENABLE:

[15:0] FEx

0 – Wake up due to GPx falling-edge detect disabled.
1 – Wake up due to GPx falling-edge detect enabled.
Set to 0x0003 on hardware, watchdog, and GPIO resets.

FE15

FE14

FE13

FE12

FE9

FE8

FE7

FE6

FE5

FE4

FE3

FE2

FE11

FE10

FE1

FE0

Intel® PXA26x Processo r Family Develop er’s Manual 3-27

Clocks and Power Manager

3.5.6 Power Manager GPIO Edge Detect Status Register (PEDR)

The PEDR , refer to Table 3-12, indicates which of the GPIO pins enabled via th e PW ER, PRER,
and PFER registers caused a sleep-mode wake up. The bits in PEDR can only be set on a rising or
falling edg e on a gi ven GPIO p in. If PR ER is set , th e bit s in PED R ca n only b e set on a r is ing e dge .
If PFER is set, the bits in PE DR can only be set on a falling edge. To reset a bit in PEDR to zero ,
write a 1 to it. The PEDR bi ts are reset to zero in hard ware, watchdog, and GPIO resets.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-12. PEDR Bit Definitions

0x40F0_0018 PEDR Clocks and Power Manager

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31:16] — Reserved

SLEEP MODE EDGE DETECT STATUS:

[15:0] EDx

0 – Wake up on GPx not detected.
1 – Wake up due to edge on GPx detected.
Cleared by hardware, watchdog, and GPIO resets. Cleared by writing a 1.

ED15

ED14

ED13

ED12

ED9

ED8

ED7

ED6

ED5

ED4

ED3

ED2

ED11

ED10

ED1

ED0

3-28 Intel® PXA26x Processor Family Developer’s Manual

Clocks and Power Manager

3.5.7 Power Manager Sleep Status Register (PSSR)

The PSSR, refe r to Table 3-13, contains these status flags:

• Read Disable Hold (RDH) bit is set by hardware, watchdog, and GPIO resets and sleep mode.

The

RDH bit indicates th at all the pro cessor’ s GPIO inpu t pat hs ar e disabl ed. To allow a GPIO
input pin to be enabled, software mu st reset the RDH bit by writing a one to it. Clearing RDH
also disables the 10 K to 60 K GPIO pullup resist ors that are present during and after
hardware, GPIO and watchdog reset. Sleep mode disables t he GPIO input path, but the pullup
resisters are not re -enabled in this case .

• Peripheral Control Hold (PH) bit is set when sleep mode starts and indicat es that the GPIO

pins are retaining their sleep mode s tate values.

• VDD Fault Status (VFS) bit is set after wake up when the nVDD_FAUL T pin is asserted and

causes the processor to enter sleep mode. The VFS bit is not set if software starts the sleep
mode and then the nVDD_FAULT pin is asserted.

• Battery Fault S tat us (BF S) bit is set af ter wake u p any ti me the nBATT_FAULT pin is asserted

(even when the processor is already in sleep m ode).

• Software Sleep Status (SSS) flag is set wh en the sleep mode configuration in the PWRMODE

register is set and sleep mode starts (see Section 3.7.2, “Power Mode R e gister

(PWRMODE)”).

To clear a status flags write a 1 to it. Writing a 0 to a status bit has no effect. Hardware, watchdog,
and GPIO resets clear or set the PSSR bits.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-13. PSSR Bit Definitions (Sheet 1 of 2)

0x40F0_0004 PSSR Clocks and Power Manager

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PH

VFS

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

[31:6] — Reserved

Read Disable Hold.
0 – GPIO pins are configured according to their GPIO configuration

5RDH

4PH

3—Reserved

1 – Receivers of all GPIO pins that can act as inputs are disabled and following a

hardware, GPIO, or watchdog reset, internal GPIO pull-ups are active. Must be
cleared by the processo r after the peripheral and GPIO interfac es are con f igured but
before they are used.

Set by hardware, watchdog, and GPIO resets and sleep mode. Cleared by writing a 1.
Peripheral Control Hold.

0 – GPIO pins are configured according to their GPIO configuration
1 – GPIO pins are being held in their sleep mode state. Set when sleep mode starts.

Must be cleared by the processor after the peripheral interfaces have been
configured but before they are actually used by the processor.

Cleared by hardware, watchdog, and GPIO resets. Cleared by writing a 1.

RDH

BFS

Reserved

SSS

Intel® PXA26x Processo r Family Develop er’s Manual 3-29

Clocks and Power Manager

Table 3-13. PSSR Bit Definitions (Shee t 2 of 2)

0x40F0_0004 PSSR Clocks and Power Manager

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PH

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

VDD Fault Status.
0 – nVDD_FAULT pin has not been asserted since it was last cleared by a reset or the

CPU.

2VFS

1BFS

0SSS

1 – nVDD_FAULT pin was asserted in run or idle mode and caused the chip to enter

sleep mode; bit is set only after wake up.
This bit is not set when nVDD_FAU LT is asserted while in sleep mode.
Cleared by hardware, watchdog, and GPIO resets.

Battery Fault Status.
0 – nBATT_FAULT pin has not been asserted since it was last cleared by a reset or the

CPU.
1 – nBATT_FAULT pin has been asserted; bit is set only after wake up.
This bit can be set when nBATT_FAULT is asserted while in sleep mode.
Cleared by hardware, watchdog, and GPIO resets.

Software Sleep Status.
0 – Software has not entered sleep mode th rough the sleep mode bit sin ce the SSS was

last cleared by a reset or the CPU.
1 – Chip was placed in sleep mode by setting the sleep mode bit.
Cleared by hardware, watchdog, and GPIO resets.

RDH

VFS

Reserved

BFS

SSS

3.5.8 Power Manager Scratch Pad Register (PSPR)

The power manager contains a 32-bit register that can be used to save processor configuration
information in any desired format. The PSPR, shown in Table 3-14, is a holding register that is
powered during sleep mode and is rese t by hardware, watchdog, and GPIO resets. During run and
turbo modes, any value can be written to PSPR. The value can be read after sleep mode exits. The
value in PSPR can be use d to repr es ent th e proc ess or’s configurati on be for e sl ee p mode is invo ked.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-14. PSPR Bit Definitions

0x40F0_0008 PSPR Clocks and Power Manager

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

SP

Reset

3-30 Intel® PXA26x Processor Family Developer’s Manual

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Scratch Pad

[31:0] SP

32-bit word is preserved in sleep mode.
Cleared by hardware, watchdog, and GPIO resets.

Clocks and Power Manager

3.5.9 Power Manager Fast Sleep Wake Up Configuration Register (PMFWR)

Table 3-15. PMFWR Register Bitmap and Bit Definitions

0x40F0 0034

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31:3] —

[1] FWAKE

[0] —

Reserved.
Read undefined and must always be written with zeroes.

FAST WAKE UP ENABLE:
0 – Selects the standard-sleep-wake-up sequence with a 10 ms power supply stabili-

1 – Selects the fast-sleep-wake-up sequence without a power supply stabilization delay

Cleared by hardware reset.
Reserved.

Read undefined and must always be written with zeroes.

Power Manager Fast Sleep Wake

Up Configuration Register

(PMFWR)

Reserved

zation delay when power is disabled during sleep.

when power is maintained during sleep.

Power Manager

FWAKE

The power manager contains a 32-bit re gister that configures the processor sl eep- wake-up
sequence. The PMFWR, refer to Tab le 3-15, contains a single config urable bit: FWAKE. Use the
PMFWR[FWAKE] bit to select between the standard and fast-sleep-wake-up sequences. The
PMFWR register is reset by a h a rdware reset, but is not cleared by the sleep-wake-up sequence.
Using an exception handler to enter sleep in response to a power-f ault event is advantageous
because software can clear the PMFW R[F WAKE] bit and configure the power management IC to
use PWR_EN to disable the core power supply during sleep. Thus minimizing power consumption
from a criticall y low batter y. Also, the PCFR[OPDE] bit must be c leared to enab le the 3 .6864-M Hz
oscillator during sleep when fa st-sleep wake up is selected.

Reserved

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

3.5.10 Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2)

PGSR0, PGSR1, and PGSR2, shown in Table 3-16, Ta ble 3-17 , and T a ble 3-18 let software select
the output state of each GPIO pin when the pr ocess or goes into sleep mode. When a transition to
sleep mode is required (t hrough software or the nBATT_FAULT or nVDD_FAULT pin), the
contents of the PGSR regist ers are loaded into the GPIO output data regi st ers. Software normally
controls this through GPSR and GPCR. Only pins that are already config ured as outputs reflect the
new state. All bits in the output registers are loaded. When the pro ces so r r e-enters the run mode,
these GPIO pins retain the p rogrammed sleep state until soft war e resets the PSSR[PH] bit. If a pin
is reconfigured from an input to an ou tput, the register’s last co ntents are driven onto the pin.

Intel® PXA26x Processo r Family Develop er’s Manual 3-31

Clocks and Power Manager

Warning: Because GPIO[89:86] were previously dedicated pins, they only reflect their PGSR value if their

GPIO function is selected. Other wise they drive their dedicated pin’s sleep state.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-16. PGSR0 Bit Definitio ns

0x40F0_0020 PGSR0 Clocks and Power Manager

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SS9

SS8

SS7

SS6

SS5

SS4

SS3

SS31

SS30

SS29

SS28

SS27

SS26

SS25

SS24

SS23

SS22

SS21

SS20

SS19

SS18

SS17

SS16

SS15

SS14

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SLEEP STATE OF GPx – If programmed as an output:

[31:0] SSx

0 – Pin is driven to a zero during sleep mode
1 – Pin is driven to a one during sleep mode
Cleared by hardware, watchdog, and GPIO resets.

SS11

SS13

SS12

SS10

SS2

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

SS1

SS0

Table 3-17. PGSR1 Bit Definitio ns

0x40F0_0024 PGSR1 Clocks and Power Manager

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

SS63

SS62

SS61

SS60

SS59

SS58

SS57

SS56

SS55

SS54

SS53

SS52

SS51

SS50

SS49

SS48

SS47

SS46

SS45

SS44

SS43

SS42

SS41

SS40

SS39

SS38

SS37

SS36

SS35

SS34

SS33

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SLEEP STATE OF GPx – If programmed as an output:

[31:0] SSx

0 – Pin is driven to a zero during sleep mode
1 – Pin is driven to a one during sleep mode
Cleared by hardware, watchdog, and GPIO resets.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-18. PSPR Bit Definitions

0x40F0_0008 PSPR Clocks and Power Manager

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

SP

Reset

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCRATCH PAD:

[31:0] SP

32-bit word is preserved in sleep mode.
Cleared by hardware, watchdog, and GPIO resets.

SS32

3-32 Intel® PXA26x Processor Family Developer’s Manual

3.5.11 Reset Controller Status Register (RCSR)

The CPU uses the RCSR, refer to Table 3-19, to determine wha t caused the last reset. The
processor can be reset in four ways:

• GPIO reset

• Sleep mode

• Watchdog reset

• Hardware reset

Refer to Table 2-4, “Eff ect of Eac h Type of Res et o n Inte rnal Reg is ter S tate ” on p age 2-7 for de tail s
of the behavior of different modules during each type of res et.

Each RCSR status bit is set by a differe nt reset sour ce and can be cleared by writi ng a 1 back to the
bit. The RCSR status bits for watchdog res e t, s l e ep mode, and GPIO resets hav e a ha rdware reset
state of zero.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Clocks and Power Manager

Intel® PXA26x Processo r Family Develop er’s Manual 3-33

Clocks and Power Manager

Table 3-19. RCSR Bit Definitions

0x40F0_0030 R CS R Clocks and Power Manager

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GPR

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

[31:4] — Reserved

GPIO RESET:
0 – GPIO reset has not occurred since the last time the CPU or hardware reset cleared

3GPR

2SMR

1WDR

0HWR

this bit.

1 – GPIO reset has occurred since the last time the CPU or hardware reset cleared this

bit.

Cleared by hardware reset and by setting to a 1.
SLEEP MODE:

0 – Sleep mode has not occurred since the last time the CPU or hardware reset cleared

this bit.

1 – Sleep mode has occurred since the last time the CPU or hardware reset cleared this

bit.

Cleared by hardware reset and by setting to a 1.
WATCHDOG RESET:

0 – Watchdog reset has not occurred since the last time the CPU or hardware reset

cleared this bit.

1 – Watchdog reset has occurred since the last time the CPU or hardware reset cleared

this bit.

Cleared by hardware reset and by setting to a 1.
HARDWARE RESE T:

0 – Hardware reset has not occurred since the last time the CPU cleared this bit.
1 – Hardware reset has occurred since the last time the CPU cleared this bit.
Set by hardware reset. Cleared by setting to a 1.

SMR

WDR

HWR

3.5.12 Power Manager Register Locations

T a ble 3-20 shows the registers associated w ith the power manager and the physical addresses us ed

.

Table 3-20. Power Manager Register Locations (Sheet 1 of 2)

3-34 Intel® PXA26x Processor Family Developer’s Manual

to access them.

Address N ame Description

0x40F0 0000 PMCR Power Manager Control Register
0x40F0 0004 PSSR Power Manager Sleep Status Register
0x40F0 0008 PSPR Power Manager Scratch Pad Register

0x40F0 000C PWER Power Manager Wake-up Enable Register

0x40F0 0010 PRER Power Manager GPIO Rising-edge Detect Enable Register
0x40F0 0014 PFER Power Manager GPIO Falling-edg e Detect Enable R egis ter
0x40F0 0018 PEDR Power Manager GPIO Edge Detect Status Register