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17-10FCR Bit Defin iti o ns..................... ...........................................................................................17-15
17-11FOR Bit Definitions................................................................................................................17-16
17-12ABR Bit Definiti ons........................................................................................... .....................17-17
17-13ACR Bit Definitions................................................................................................................17-18
17-14LCR Bit Definitions ................................................................................................................17-18
17-15LSR Bit Definitions................................................................................................................. 17-20
17-16MCR Bit Definitions............................................................................................................... 17-22
17-17MSR Bit Definit ion s........ ........................... .............................................................................17-23
17-18SCR Bit Definitions................................................................................................................17-24
17-19ISR Bit Definitions..................................................................................................................17-25
17-20HWUART Registe r Loca ti o ns............ .................................................. ..................................17-25
Contents
Intel® PXA255 Processor Developer’s Manualxxiii
Contents
Revision History
DateRevisionDescription
March 2003-001Initial release
xxivIntel® PXA255 Processor Developer’s Manual
Introduction1
This document applies to the Intel® PXA255 Processor (PXA255 pro ces sor). It is an application
specific standard product (ASSP) that provides i ndustry-leading MIPS/mW performance for
handheld computing appli cations. The processor is a highly integrated system on a chip and
includes a high-performance low-power Intel® XS cale™ microarchitecture with a variety of
different system peripherals.
The PXA255 proc esso r is a 17x17mm 256-pin PBG A package config uration fo r high per forma nce.
The 17x17m m package has a 32-bit memory da ta bus and the full assortment of peripherals.
1.1Intel® XScale™ Microarchitecture Features
The Intel® XScale™ microarchitecture provides these f eatures:
• ARM* Architecture Version 5TE ISA compliant.
— ARM* Thumb Instruction S upport
— ARM* DSP Enhance d Instructions
• Low power cons umption and high performance
• Intel® Media Processing Technology
— Enhanced 16-bit Multiply
— 40-bit Accumulator
• 32-KByte Instruction Cache
• 32-KByte Data Cache
• 2-KByte Mini Data Cache
• 2-KByte Mini Instruction Cache
• Instruction and Data Memor y Ma nagement Units
• Branch T arget Buffer
• Debug Capability via JTAG Port
Refer to the Int e l® XScale™ Micr oarchitecture for the Intel® PXA255 Processor User’s Manual
for more detai l s.
1.2System Integration Features
The processor integrat es the In tel® XScale™ microarchitectur e with this peripheral set:
• Memory Controller
• Clock and Power Controllers
• Universal Serial Bus Client
Intel® PXA255 Processor Developer’s Manual1-1
Introduction
• DMA Controller
• LCD Controller
• AC97
2
• I
S
• MultiMediaCard
• FIR Communication
• Synchronous Serial Pro t oc ol Port
2
• I
C
• General Purp ose I/O pins
• UARTs
• Real-Time Clock
• OS Timers
• Pulse Width Modulation
• Interru p t C on t ro l
1.2.1Memory Controller
The Memory Con troller provides glueless control s i gnals with programmable tim ing for a wide
assortment of mem ory-chip types and organizations. It supports up to four S DRAM partitions; six
static chip s elects for SRA M, S SRAM, F lash , ROM , SROM, and compa nion chip s; su pport for two
PCMCIA o r Compa ct Flas h slots
1.2.2Clocks and Power Controllers
The processor functional blocks are dr iven by clocks that are deri ve d from a 3.6864-MHz crystal
and an optional 32.768-kHz crystal.
The 3.6864-MHz crystal drives a core Phase Lock ed Loo p ( PLL) and a Per iph eral PLL. The PLLs
produce selec t ed clock frequencies to run particular functional blocks.
The 32.768-kHz crystal provides an optional clock source that must be selected after a hard reset.
This clock drive s the Real Time Clock (RTC), Power Management Controller, and Interrupt
Controller. The 32.768-kHz crystal is on a separate power island to provide an active clock while
the processor is in s leep mode.
Power management controls the transition between the turbo/run, idle, and sleep operating m ode s.
1.2.3Unive rsal Serial Bus (USB) Client
The USB Client Module is bas ed on the Universal Serial Bus Specification, Revisio n 1.1. It
supports up to s ixteen endpoints and it provides an interna lly generated 48-MHz clock. The USB
Device Controller provides FIFOs with DMA access to or from memory.
1-2 Intel® PXA255 Process or Developer’s Manual
1.2.4DMA Controller (DMAC)
The DMAC provide s sixteen prioritized channels to service transfer requests from internal
peripherals and up to two dat a transfer requests from external companion chips. The DMAC is
descriptor-based to allow comma nd c haining and looping constructs.
The DMAC op e ra t e s in Fl ow-Throu gh Mo de wh e n pe rf orming peri p he r a l- to -memory, memory- to peripheral, and memory- to- memory transfers. The DMAC is compatibl e with peripherals that use
word, half-word, or byte data sizes.
1.2.5LCD Controller
The LCD Controller supports both passi ve (DSTN) and active (TFT) flat-panel displays with a
maximum supported resolution of 640 x480x16-bit/pixel. An internal 256 entry palette expa nds 1,
2, 4, or 8-bit encoded pixels. Non-encoded 16-bit pixels bypass the palette.
Two dedicated DMA channels a l low the LCD Controller to support single- and dual-panel
displays . P a ssive monochrome mode supp orts up to 256 gra y-scale levels and passive color mode
supports up to 64K colors. Active color mode supports up to 64K colors.
1.2.6AC97 Controller
Introduction
The AC97 Controller supports AC97 Revision 2.0 CODECs. These CODECs can operate at
sample rates up to 48 KHz. The controller provid es independent 16-bit channels for Stereo PCM
In, Stereo PCM Out, Modem In , Mod em Out, and mono Microphone In. Each channel includes a
FIFO that supports DMA access to memory.
1.2.7Inter-IC Sound (I2S) Controller
The I2S Controller provides a serial link to standard I2S CODECs for digital stereo sound. It
supports both the Normal-I
connectio n to a n I
The controller includes FIFOs that support DMA access to memory.
2
S CODEC. I2S Controller signals are multiplexed with AC97 Controller pins.
2
S and MSB-Justif ied I2S formats, and provides four signals for
1.2.8Multimedia Card (MMC) Controller
The MMC Controller provide s a serial i nterface to sta ndard me mory cards . The controller suppor ts
up to two cards in e ither MMC or SPI modes with serial da ta transfers up to 20 Mbps. Th e MMC
controller has FIFOs that support DMA access to and from memory.
1.2.9Fast Infrared (FIR) Communication Port
The FIR Com munication Port is based on the 4-Mbps Infrared Data Association (IrDA)
Specification. It operates at half-duplex and has FIFOs with DMA access to memory. The FIR
Communication Port uses the STUART’s transmit and receive pins to directly connect to external
IrDA LED transceivers.
Intel® PXA255 Processor Developer’s Manual1-3
Introduction
1.2.10Synchronous Serial Protocol Controller (SSPC)
The SSP Port provides a full-duplex synchronous serial interface th at operates at bit rates from
7.2 kHz to 1.84 MHz. It supports National Semico nductor’s Microwire*, Texas Instruments’
Synchronous Serial Protocol*, and Motorola’s Serial Peripheral Interface*. The SSPC has FI FO s
with DMA access to memory.
1.2.11Inter-Integrated Circuit (I2C) Bus Interface Unit
The I2C Bus Interface Unit provides a general purpose 2-pin serial communication port.The
interface uses one pin for data and address and a second pin for clocking.
1.2.12GPIO
Each GPIO pin can be individually programmed as an output or an input. Inputs can cau se
interrupts on rising or falling edge s. Primary GPIO pins are not shared with peripherals while
secondary GPIO pins have alternate functions which can be mapped to the peripherals.
1.2.13UARTs
The processor provides three Univers al Asynchronous Receiver/Transmitters. Each UART can be
used as a slow infrared (SIR) transmitter/receiver based on the Infrared Data Associatio n Serial
Infrar ed (SIR) Physical Layer Link Specification.
1.2.13.1Full Function UART (FFUART)
The FFUART baud rate is pr og ramm abl e up to 2 30 Kbps. The FFUART provides a c omp lete se t of
modem control pins: nCTS, nRTS, nDSR, nDTR, nRI, and nDCD. It has FIFOs with DMA access
to or from memory.
1.2.13.2Bluetooth UART (BTUART)
The BTUART baud rate is programma ble up to 921 Kbps. The BTUART provide s a partial set of
modem control pins: nCTS and nRTS. Other modem control pi ns can be implemented via GPIOs.
The BTUART has FIFOs wi th DMA access to or from memory .
1.2.13.3Standard UART (STUART)
The STUART baud rate is pr og rammab le up to 230 Kbps. The S TUART does not prov ide any
modem control pins. The mode m control pins can be impleme nted via GPIOs. The STUART has
FIFOs wit h DM A a c ces s to or from memory.
The STUART’s transmit and receive pins are multipl exed with the Fast Infrared Communication
Port.
1-4 Intel® PXA255 Process or Developer’s Manual
1.2.13.4Hardware UART (HWUART)
The PXA255 processor has a UART with hardware flow control. The HWUART provides a partial
set of modem contr ol pins: nCTS and nRTS. These modem control pi ns pr ovi de full hardwar e f low
control. Other modem control pins can be implemented via GPIOs. The HWUART baud rate is
programmable up to 921.6 Kbps.
The HWUART’ s pins are multiplexed with the PCMCIA contr ol pins. Because of this, these
HWUART pins operate at the same voltage as the memory bus. Also, since the PCMCIA pin
nPWE is used for variable-latency input/output (VLIO), while using these pins for the HWUAR T,
VLIO is unavailabl e. The HWUART pins are also available over the BTUART pins. When
operating over the BTUART pins, the HWUART pins operate at the I/O voltage.
1.2.14Real-Time Clock (RTC)
The Real-Time Clock can be clocked from either crys tal. A system with a 32.768-KHz cry st al
consumes le ss p owe r d ur ing Sl eep v ers u s a s ystem usi ng o nly th e 3.68 64- MHz crys tal. Th is cr ysta l
can be remov e d to save syst e m cost. The RTC provides a consta nt frequenc y output with a
programmable alarm regis ter. This alarm register can be used t o wake up the processor from Sleep
mode.
Introduction
1.2.15OS Timers
The OS Timers can be used to prov ide a 3.68-MHz reference counter with four match registers.
These registers can be config ured to cause interrupts when equal to th e ref erence counter. One
match register can be used to cause a watch dog reset.
1.2.16Pulse-Width Modulator (PWM)
The PWM has two independent outputs that can be progra mmed to drive two GPIOs. The
frequency and duty cycle are ind ependently programmable. For example, one GPIO can control
LCD contrast and the other LCD brigh t ne ss.
1.2.17Interrupt Control
The Interrupt Controller directs the processor interrupts into the core’s IRQ and FIQ inputs . The
Mask Register enables or dis a bles individual interrupt sources.
1.2.18Network Synchronous Serial Protocol Port
The PXA2 5 5 pr oc e s so r ha s a n SSP port optim iz e d f or con n e c ti o n to ot he r ne t work ASICs . T hi s
NSSP adds a Hi-Z function to TXD, the ability to control when Hi-Z occur s, and swapping the
TXD/RXD pins.
This port is not multiplexed with other interfaces.
Intel® PXA255 Processor Developer’s Manual1-5
Introduction
1-6 Intel® PXA255 Process or Developer’s Manual
System Architecture2
2.1Overview
The PXA255 processor is an integrated system-on-a-chip microprocessor for high performance,
low power portable handheld and handset devices. It incorporates the Intel® XScale™
microarchitecture with on-the-fly frequency s c a ling and sophisticated power m a na gement to
provide industry leading MIPs/mW performance. The PXA255 processor is ARM* Architecture
Version 5TE instruction set compliant (excluding flo a ting point instructions) and follows the
ARM* programmer’s model.
The processor’s memor y interface supports a variety of memory types to allow desig n fl exibility.
Support for th e conne ction o f two companion chips permits a glu eless inter face to extern al de vices.
An integra te d LCD display controller provides support for displays up to 640x480 pixels, and
permits 1-, 2-, 4-, and 8-bit grayscale and 8- or 16-bit color pixels . A 256 en try/512 byte palette
RAM provides flexibility in color mapping.
A set of serial devices and gener al s ys tem res ources provide comput ational and connectivit y
capability for a variety of applications. Refer to Figure 2-1 for an overview of the microprocessor
system architecture.
The processor inco rpo rates the Intel® XScale™ microarch itecture which is described in a separate
document. This core contains impleme nta tion options which an Applic a tion Specific Standard
Product (ASSP) may elect to implement or omit. This section des c ribes those options.
Most of these options are specifi ed within the coprocessor register space. The processor does not
implement any coprocessor registers beyond those de fined in the Intel® XScale™
microarchitecture. The coprocessor registers which are ASSP specific, as stated in the Intel® XScale™ Microarchitecture for the Intel® PXA255 Processor User’s Manual, order number
278793, are defined in the following sections.
2.2.1Coprocessor 7 Register 4 - PSFS Bit
Bit 5 of thi s re gis ter i s def ined as t he P owe r So ur ce F ault St atu s bit or P SFS bit. This bit is set when
either nVDD_FAULT or nBATT_FA ULT pins are asserted and the Imprecise D ata Abort Enable
(IDAE) bit in the Pow e r Manager Control Register (PMCR) is set.
This is a read-only register. Ignore reads from reserved bits.
2-2 Intel® PXA255 Process or Developer’s Manual
Table 2-1. CPU Core Fault Register Bit Definitions
The proces sor does not define any performance monitoring features beyond those called out in the
Intel® XScale™ Micr oarch itectur e for the Intel® PXA255 Pr ocessor User’s Manual, order n umbe r
278793. The interrupt generated by pe rformance monitoring eve nts is defined in Chapter 4,
“System Integration Unit”. The ASSP define d performance monitor i ng events (events 0x10 -
0x17), defined through the PMNC register are reserved for the processor.
2.2.3Coprocessor 14 Register 6 and 7- Clock and Power
Management
These registers all ow software to use the clocking and power management modes. Th e va lid
operations are d escri bed in Table 3-23, “Coproc essor 14 Cloc k and Power Mana geme nt Summary”
on page 3-39.
2.2.4Coprocessor 15 Register 0 - ID Register Definition
This register may be read by software to determin e the dev ice type and revision. The contents of
this registe r for the Intel ® PXA255 Proces sor is def ined in the t able b elow. Combined, this reg ister
must read as 0x6905 2X0R where R = 0b0000 for the first stepping and then increments for
subsequent steppings, and X is the revision of the Intel® XScale ™ micr oar chitecture present.
Please see the Inte l Developer Homepage at http://devel oper.intel.com for updates.
0x05
This field is updated when new sets of features are added to the core. This
allows software that is dependant on core features to target a specific core.
Core generation:
– Intel® XScale™ core
0b001
This field is updated each time a core is revised. Differences m a y include
errata, software workarounds, etc.
Core revision:
0b000
– First version of the core.
0b010
– Third version of the core.
0b011
– Fourth version of the core.
Product Number
0b010000 – PXA255 processor
This field tracks the different steppings for each ASSP.
Product Revision
– A0 Stepping
0b0110
Core
generation
Core
Revision
Product
Number
Product
Revision
Table 2-3. PXA255 Processor ID Values
Stepping ARM IDJTAG ID
A00x6905_2D060x6926_4013
2.2.5Coprocessor 15 Register 1 - P-Bit
Bit 1 of this regi ster is defined a s the Page Table Memory Attribute bit or P-bit. I t is not
implemented in the processor and must be written as zero. Similarly, the P-bit in the page table
descriptor in the MMU is not implemented and must be written to zero.
2-4 Intel® PXA255 Process or Developer’s Manual
2.3I/O Ordering
The processor uses queues that accept memory requests from the three internal mast ers: core,
DMA Controller , and LCD Controller. Operations issued by a master are completed in the order
they were received. Operations from one master may be interrupted by oper ations from another
master. The processor does not provide a method to regulate the order of operations from dif fer ent
masters.
Loads and stores to internal addr es ses are generally completed more quickly than those is s ued to
external addresses. The difference in completion time allows one operation to be received before
another operation, but completed after the second operation.
In the following sequen ce, the store to the address in r4 is compl eted before the stor e to the addres s
in r2 because the first store waits for memory in the queue whi le the second is not delayed.
str r1, [r2]; store to external memory address [r2].
str r3, [r4]; store to internal (on-chip) memory address [r4].
If the two stores are contr ol o peratio ns that must be comple ted i n ord er, the recommended sequence
is to inser t a l oa d to an unbuffered, uncached memor y pa ge follow e d by an operation that depends
on data from the load:
System Arch itecture
str r1, [r2]; first store issued
ldr r5, [r6]; load from external unbuff ered, uncached address ([r2] if po ssible)
mov r5, r5; nop stalls until r5 is loaded
str r3, [r4]; second store completes in program order
2.4Semaphores
The Swap (SWP) and Swap Byte (SWPB) instructions, as described in the ARM* Architecture
reference, may be used for semaphore manipulation. No on-chip master or process can access a
memory loca tion between the load and store portion of a SWP or SWPB to the same location.
Note:Semaphore coherency may be interrupted because an external companion chip that uses the
MBREQ/MBGNT handshake can take ownership of the bus during a locked sequence. To allow
semaphor e manipulation by external com pa nion chips, the software must manage coherency.
2.5Interrupts
The int e rr u p t c ontroll e r is descri be d in de tail in Sect ion 4.2, “Int e rr upt Controller”. All on-chip
interrupts are enabled, masked, and routed to the core FIQ or IRQ. Each in terrupt is enabled or
disabled at the source through an interrupt mask bit. Generally, all interrupt bits i n a unit are ORed
together and present a single value to the interrupt controller.
Intel® PXA255 Processor Developer’s Manual2-5
System Ar ch itecture
Each interrupt goes through the I nterrupt Controller Mask Register and then the Interrupt
Controller Level Register directs the interrupt into either the IRQ or FIQ. If an interrupt is taken,
the software may read the Interrupt Controller Pending Register to identif y the source. Afte r it
identifies the interrupt source, software is responsible for servicing the inter rupt and clearing it in
the source un it before exiting the service routine.
Note:Clearing interrupts may take a delay . To allow the status bit to c l e ar before returning fr om an
interrupt serv ice routine (ISR), clear the interrupt early in the routine.
2.6Reset
The processor can be reset in any of three ways: Hardware, Watchdog, and GPIO resets. Each is
described in m ore detail in Section 3.4, “Resets and Power Modes” on page 3-6.
• Hardware reset results from asserting the nRESET pin and f orces all units into rese t state.
• Watchdog reset results fr om a time-out in the OS Timer and ma y be used to reco ve r from
runaway code . Watchdog reset is disable d by default a nd must be enabled by software.
• GPIO reset is a “soft reset” that is less destr uctive than Hardware and Watchdog resets.
Each type of reset aff ects th e state o f the proc essor p ins. Table 2-4 shows each pin’s state aft er each
type of reset.
Leaving Sleep Mode causes a Sleep Mode reset. Unlike other resets, Sleep Mode resets do not
change the state of the pins.
The Reset Controller S tatus Register (RCSR) cont ains information on the type of res et, including
Sleep Mode resets.
Table 2-4. Effect of Each Type of Reset on Internal Regist er State (Sh eet 1 of 2)
UnitSleep ModeGPIO ResetWatchdog ResetHard Reset
Coreresetresetresetreset
Memory Controllerresetpreservedresetreset
LCD Controllerresetresetresetreset
DMA Controllerresetresetresetreset
Full Function UARTresetresetresetreset
Bluetooth UARTresetresetresetreset
Standard UARTresetresetresetreset
Hardware UARTresetresetresetreset
2
I
Cresetresetresetreset
2
I
Sresetresetresetreset
AC97resetresetresetreset
USBresetresetresetreset
ICPresetresetresetreset
RTCpreservedpreservedreset (except RTTR)reset
OS Timerresetresetresetreset
2-6 Intel® PXA255 Process or Developer’s Manual
System Arch itecture
Table 2-4. Effect of Each Type of Reset on Internal Register State (Sheet 2 of 2)
All internal regist ers are mapped in physical memory spac e on 32 -bit address boundaries. Use
word access lo ads and stores to access internal r egisters. Interna l register space must be mapped as
non-cacheable.
Byte and halfword accesses to internal registers are not permitted and yield unpredictable results.
Register space where a register is not specifically mapped is defined as rese rved space. Reading or
writing reserved sp ace cause s unpredictable result s.
The processor does not use all register bit locations. The unused bit locations are marked reserved
and are allocated for futur e use. W r ite re ser ve d bit locat ions as zeros. Igno re the values of t hese bits
during reads because they are unpredictable.
2.8Selecting Peripherals vs. General Purpose I/O
Most peripherals conn ect to the external pins through GPIOs. To use a peripheral connected
through a GP IO , th e so ft wa r e mu st firs t configure the GPIO so that the desi re d peri pheral is
connected to its pins. The default state of the pins is GPIO inputs.
To allocate a peripheral to a pin, disable the GPIO function for that pin, then map the peripheral
function onto the pin by selecting the pro pe r alternate function fo r the pin. Some GPIOs have
multiple alternate functions. After a function is selected for a pin, all other functions are excluded.
For this reason some peripherals are mapped to multiple GPIOs, as shown in Section 4.1.2, “GPIO
Alternate Functions” on pa ge4-2. Multiple mapping does not mean multiple instance s o f a
peripher a l - only that the pe ripheral is connected to the pins in several ways.
Intel® PXA255 Processor Developer’s Manual2-7
System Ar ch itecture
2.9Power on Reset and Boot Operation
Before the device that uses the processor is powered on, the system must assert nRESET and
nTRST. To allow the internal clocks to stabilize, all power supplies must be stable for a specified
period before nRESET or nTRST are deasserted. When nRESET is asserted, nRESET_OUT is
driven active and can be used to res et other devices in the system. For additional informati on, see
the Intel® PXA255 Processor Design Guide.
When the system deasserts nRESET and nTRST, the processor deasserts nRESET_OUT a
specified time later and the device attemp ts to boot from physical address locatio n 0x0000_0000.
The BOOT_SEL[2:0] pins are sampled when reset is deas serted and let the user specify the type
and width of memory device from which the processor attempts to boot. The sof tware can read the
pins as described in Section 6.10.2, “Boot Time Defaults” on page 6-72.
2.10Power Management
The processor offers a number of modes to manage pow er in the system . These range widely in
level of power savings and le ve l of functionality. The following modes are s upported:
• Turbo Mode : low latency (nanoseconds) switch between two preprogrammed fre que ncies.
• Run Mode: normal full function mode.
• Idle Mode: core clocks are stopped - resume through an interrupt.
• Sleep Mode: low power mode that does not save state but keeps I/Os powered. The RTC,
Power Manager, and Clock modules are saved, excep t for Coprocessor 14.
Note:In low power modes, en sure that input pins are not floatin g a nd output pins are not driven by a n
external device that opposes how the processor is driving that pin. In either case, the system w ill
draw excess current. Current dr aw that varies in sleep mode or varies greatly between parts is
typically a sign of floating pins.
Section 3.4, “Reset s and Pow er Mo des” describes the modes in detail.
2.11Pin List
Some of the proces s or pins can be connected to m ultiple signal s. The signal connect ed to the pi n is
determine d by the GPIO Alternate Function Select Registe rs (GAFRn m). Some signa ls can go to
multiple pins. The s ignal must be routed to only one pin by using the GAFRn m registe rs . Because
this is true, some pins are listed twice, once in each unit that can use the pin.
Table 2-6. Pin & Signal Descriptions for th e P XA255 Processor (Sheet 1 of 9)
Pin NameTypeSignal DescriptionsReset StateSleep State
Memory Controller Pins
MA[25:0]OCZ
MD[15:0]ICOCZ
MD[31:16]ICOCZ
nOEOCZ
nWEOCZ
nSDCS[3:0]OCZ
DQM[3:0]OCZ
nSDRASOCZ
nSDCASOCZ
SDCKE[0]OC
SDCKE[1]OC
SDCLK[0]OC
Memory address bus. (output) Signals the address
requested for memory accesses.
Memory data bus. (input/output) Lower 16 bits of the
data bus.
Memory data bus. (input/output) Used for 32-bit
memories.
Memory output enable. (output) Connect to the output
enables of memory devices to control data bus drivers.
Memory write enable. (output) Connect to the write
enables of memory devices.
SDRAM CS for banks 3 through 0. (output) Connect to
the chip select (CS) pins for SDRAM. For the PXA255
processor nSDCS0 can be Hi-Z, nSDCS1-3 cannot.
SDRAM DQM for data bytes 3 through 0. (output)
Connect to the data output mask enables (DQM) for
SDRAM.
SDRAM RA S. (output) Connect to the row address
strobe (RAS) pins for al l banks of SDRAM.
SDRAM CA S. (output) Connect to the column address
strobe (CAS) pins for al l banks of SDRAM.
Synchronous Static Memory clock enable. (output)
Connect to the CKE pins of SMROM. The memory
controller provides control register bits for deassertion.
SDRAM and/or Synchronous Static Memory clock
enable. (output) Connect to the clock enable pins of
SDRAM. It is deasserted during sleep. SDCKE[1] is
always deasserted upon reset. The memory controller
provides control register bits for deassertion.
Synchronous Static Memory clock. (output) Conne ct to
the clock (CLK) pins of SMROM. It is driven by either the
internal memory controller c lock, or the internal memory
controller clock divided by 2. At reset, all clock pins are
free running at the divide by 2 clock speed and may be
turned off via free running control register bits in the
memory controller. The memory controller also provides
control register bits for clock division and deassertion of
each SDCLK pin. SDCLK[0] control register assertion bit
defaults to on if the boot-time static memory bank 0 is
configured for SMROM.
Driven LowDriven Low
Hi-Z Driven Low
Hi-ZDriven Low
Driven HighNote [4]
Driven HighNote [4]
Driven HighNote [5]
Driven LowDriven Low
Driven HighDriven High
Driven HighDriven High
Driven LowDriven Low
Driven LowDriven Low
Intel® PXA255 Processor Developer’s Manual2-9
System Ar ch itecture
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Shee t 2 of 9)
Pin NameTypeSignal DescriptionsReset StateSleep State
SDCLK[1]OCZSDRAM Clocks (output) Connect SDCLK[1] and
SDCLK[2]OCDriven LowDriven Low
nCS[5]/
GPIO[33]
nCS[4]/
GPIO[80]
nCS[3]/
GPIO[79]
nCS[2]/
GPIO[78]
nCS[1]/
GPIO[15]
nCS[0]IC OCZ
RD/nWROCZ
RDY/
GPIO[18]
L_DD[8]/
GPIO[66]
L_DD[15]/
GPIO[73]
MBGNT/
GP[13]
MBREQ/
GP[14]
PCMCIA/CF Control Pins
nPOE/
GPIO[48]
nPWE/
GPIO[49]
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
SDCLK[2] to the clock pins of SDRAM in bank pairs 0/1
and 2/3, respectively. They are driven by either the
internal memory controller clock, or the internal memory
controller clock divided by 2. At reset, all clock pins are
free running at the divide by 2 clock speed and may be
turned off via free running control register bits in the
memory controller. The m emory controller also provides
control register bits for clock division and deassertion of
each SDCLK pin. SDCLK[2:1] control register assertion
bits are always deasserted upon reset.
Static chip selects. (output) Chip selects to static
memory devices such as ROM and Flash. Individually
programmable in the memory configuration registers.
nCS[5:0] can be used with variable latency I/O devices.
Static chip select 0. (output) Chip select for the boot
memory. nCS[0] is a dedicated pin.
Read/Write for static interface. (output) Signals that the
current transaction is a read or write.
Variable Latency I/O Ready pin. (input) Notifies the
memory controller when an external bus device is ready
to transfer data.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
Memory Controller alternate bus mast er request.
(input) Allows an external device to request the system
bus from the Memory Controller.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
Memory Controller grant. (output) Notifies an external
device that it has been granted the system bus.
Memory Controller grant. (output) Notifies an external
device that it has been granted the system bus.
Memory Controller alternate bus mast er request.
(input) Allows an external device to request the system
bus from the Memory Controller.
PCMCIA output enable. (output) Reads from PCMCIA
memory and to PCMCIA attribute space.
PCMCIA write enable. (output) Performs writes to
PCMCIA memory and to PCMCIA attribute space. Also
used as the write enable signal for Variable Latency I/O.
Driven LowDriven Low
Hi-Z - Note [1]Note [4]
Driven HighNote [4]
Driven LowHolds last state
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [5]
Hi-Z - Note [1]Note [5]
2-10 Intel® PXA255 Process or Developer’s Manual
System Arch itecture
Table 2-6. Pin & Signal Descriptions for th e P XA255 Processor (Sheet 3 of 9)
Pin NameTypeSignal DescriptionsReset StateSleep State
PCMCIA card enable 2. (output) Selects a PCMCIA
card. nPCE[2] enables the high byte lane and nPCE[1]
enables the low byte lane.
MMC clock. (output) Clock signal for the MMC
Controller.
PCMCIA card enable 1. (outputs) Selects a PCMCIA
card. nPCE[2] enables the high byte lane and nPCE[1]
enables the low byte lane.
IO Select 16. (input) Acknowledge from the PCMCIA
card that the current address is a valid 16 bit wide I/O
address.
PCMCIA wait. (input) Driven low by the PCMCIA card to
extend the length of the transfers to/from the PXA255
processor.
PCMCIA socket select. (output) Used by external
steering logic to route control, address, and data signals
to one of the two PCMCIA sockets. When PSKTSEL is
low, socket zero is selected. When PSKTSEL is high,
socket one is selected. Has the same timing as the
address bus.
PCMCIA Register select. (output) Indicates that the
target address on a memory transaction is attribute
space. Has the same timing as the address bus.
LCD display data. (outputs) Transfers pixel information
from the LCD Controller to the external LCD panel.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
Memory Controller alternate bus master request.
(input) Allows an external device to request the system
bus from the Memory Controller.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
MMC chip select 0. (output) Chip select 0 for the MMC
Controller.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
MMC chip select 1. (output) Chip select 1 for the MMC
Controller.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
MMC clock. (output) Clock for the MMC Controller.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
RTC clock. (output) Real time clock 1 Hz tick.
Hi-Z - Note [1]Note [5]
Hi-Z - Note [1]Note [5]
Hi-Z - Note [1]Note [5]
Hi-Z - Note [1]Note [5]
Hi-Z - Note [1]Note [5]
Hi-Z - Note [1]Note [5]
Hi-Z - Note [1]Note [5]
Hi-Z - Note [1]Note [5]
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [3]
Intel® PXA255 Processor Developer’s Manual2-11
System Ar ch itecture
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Shee t 4 of 9)
Pin NameTypeSignal DescriptionsReset StateSleep State
L_DD[13]/
GPIO[71]
L_DD[14]/
GPIO[72]
L_DD[15]/
GPIO[73]
L FCLK/
GPIO[74]
L LCLK/
GPIO[75]
L PCLK/
GPIO[76]
L BIAS/
GPIO[77]
Full Function UART Pins
FFRXD/
GPIO[34]
FFTXD/
GPIO[39]
FFCTS/
GPIO[35]
FFDCD/
GPIO[36]
FFDSR/
GPIO[37]
FFRI/
GPIO[38]
FFDTR/
GPIO[40]
FFRTS/
GPIO[41]
Bluetooth UART Pins
BTRXD/
GPIO[42]
BTTXD/
GPIO[43]
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZFull Function UART Clear-to-Send. (input)Hi-Z - Note [1]Note [3]
ICOCZFull Function UART Data-Carrier-Detect. (input)Hi-Z - Note [1]Note [3]
ICOCZFull Function UART Data-Set-Ready. (input)Hi-Z - Note [1]Note [3]
ICOCZFull Function UART Ring Indicator. (input)Hi-Z - Note [1]Note [3]
ICOCZFull Function UART Data-Terminal-Ready. (output)Hi-Z - Note [1]Note [3]
ICOCZFull Function UART Request-to-Send. (output)Hi-Z - Note [1]Note [3]
IrDA receive signal. (input) Receive pin for the FIR
ICOCZ
ICOCZ
ICOCZHardware UART Transmit Data.
ICOCZHardware UART Receive Data.
ICOCZHardware UART Clear-To-Send.
ICOCZHardware UART Request-to-Send.
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
function.
Standard UART receive. (input)
IrDA transmit signal. (output) Transmit pin for the
Standard UART, SIR and FIR functions.
Standard UART transmit. (output)
PCMCIA card enable 2. (outputs) Selects a PCMCIA
card. Bit one enables the high byte lane and bit zero
enables the low byte lane.
MMC clock. (output) Clock signal for the MMC
Controller.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
MMC chip select 0. (output) Chip select 0 for the MMC
Controller.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
MMC chip select 1. (output) Chip select 1 for the MMC
Controller.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
MMC clock. (output) Clock for the MMC Controller.
Full Function UART Receive. (input)
MMC chip select 0. (output) Chip select 0 for the MMC
Controller.
Full Function UART Transmit. (output)
MMC chip select 1. (output) Chip select 1 for the MMC
Controller.
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [3]
Pulled High
Note [1]
Pulled High
Note [1]
Pulled High
Note [1]
Pulled High
Note [1]
Hi-Z - Note [1]Note [5]
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Intel® PXA255 Processor Developer’s Manual2-13
System Ar ch itecture
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Shee t 6 of 9)
Pin NameTypeSignal DescriptionsReset StateSleep State
MMCCLK/
GP[6]
MMCCS0/
GP[8]
MMCCS1/
GP[9]
ICOCZ
ICOCZ
ICOCZ
MMC clock. (output) Clock signal for the MMC
Controller.
MMC chip select 0. (output) Chip select 0 for the MMC
Controller.
MMC chip select 1. (output) Chip select 1 for the MMC
Controller.
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [3]
SSP Pins
SSPSCLK/
GPIO[23]
SSPSFRM/
GPIO[24]
SSPTXD/
GPIO[25]
SSPRXD/
GPIO[26]
SSPEXTCLK/
GPIO[27]
ICOCZSynchronous Serial Port Clock. (output)Hi-Z - Note [1]Note [3]
ICOCZSynchronous Serial Port Frame. (output)Hi-Z - Note [1]Note [3]
ICOCZSynchronous Serial Port Transmit. (output)Hi-Z - Note [1]Note [3]
ICOCZSynchronous Serial Port Receive. (input)Hi-Z - Note [1]Note [3]
ICOCZSynchronous Serial Port External Clock. (input) Hi-Z - Note [1]Note [3]
Network SSP p ins
NSSPSCLK/
GPIO[81]
NSSPSFRM/
GPIO[82]
NSSPTXD/
GPIO[83]
NSSPRXD/
GPIO[84]
ICOCZNetwork Synchronous Serial Port Clock.
ICOCZNetwork Synchronous Serial Port Frame Signal.
ICOCZNetwork Synchronous Serial Port Transmit.
ICOCZNetwork Synchronous Serial Port Receive.
Pulled High
Note [1]
Pulled High
Note [1]
Pulled High
Note [1]
Pulled High
Note [1]
Note [3]
Note [3]
Note [3]
Note [3]
USB Client Pins
USB PIAOAZUSB Client Positive. (bidirectional)Hi-ZHi-Z
USB NIAOAZUSB Client Negative pin. (bidirectional)Hi-ZHi-Z
AC97 Controller and I2S Controller Pins
AC97 Audio Port bit clock. (input) AC97 clock is
generated by Codec 0 and fed into the PXA255
processor and Codec 1.
BITCLK/
GPIO[28]
ICOCZ
AC97 Audio Port bit clock. (output) AC97 clock is
generated by the PXA255 proce ssor.
2
I
S bit cl ock. (input) I2S clock is generated externally
Hi-Z - Note [1]Note [3]
and fed into PXA255 processor.
2
I
S bit cl ock. (output) I2S clock is generated by the
PXA255 processor.
SDATA_IN0/
GPIO[29]
SDATA_IN1/
GPIO[32]
ICOCZ
ICOCZ
AC97 Audio Port data in. (input) Input line for Codec 0.
2
I
S data in. (input) Input line for the I2S Controller.
AC97 Audio Port data in. (input) Input line for Codec 1.
2
S system clock. (output) System clock from I2S
I
Controller.
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [3]
2-14 Intel® PXA255 Process or Developer’s Manual
System Arch itecture
Table 2-6. Pin & Signal Descriptions for th e P XA255 Processor (Sheet 7 of 9)
Pin NameTypeSignal DescriptionsReset StateSleep State
SDATA_OU T/
GPIO[30]
ICOCZ
AC97 Audio Port data out. (output) Output from the
PXA255 processor to Codecs 0 and 1.
2
I
S data out. (output) Output line for the I2S Controller.
NOTE: This clock is only generated when the USB unit
Hi-Z - Note [1]Note [3]
clock enable is set.
Intel® PXA255 Processor Developer’s Manual2-15
System Ar ch itecture
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Shee t 8 of 9)
Pin NameTypeSignal DescriptionsReset StateSleep State
RTCCLK/
GP[10]
3.6MHz/GP[11] ICOCZ
32kHz/GP[12]ICOCZ32 kHz clock. (output) Output from the 32 kHz oscillator. Hi-Z - Note [1]Note [3]
Miscellaneous Pins
BOOT_SEL
[2:0]
PWR_ENOC
nBATT_FAULTIC
nVDD_FAULTIC
nRESETIC
nRESET_OUTOC
JTAG and Test Pins
nTRSTIC
TDIIC
TDOOCZ
TMSIC
ICOCZ
ICBoot select pins. (input) Indicates type of boot device.InputInput
Real time clock. (output) 1 Hz output derived from the
32kHz or 3.6864MHz output.
3.6864 MHz clock. (output) Output from 3.6864 MHz
oscillator.
Power Enable for the power supply. (output) When
negated, it signals the power supply to remove power to
the core because the system is entering sleep mode.
Main Battery Fault. (input) Signals that main battery is
low or removed. Assertion causes PXA255 processor to
enter sleep mode or force an Imprecise Data Exception,
which cannot be masked. PXA255 processor will not
recognize a walk-up event while this signal is asserted.
Minimum assertion time for nBATT_FAULT is 1 ms.
VDD Fault. (input) Signals that the main power source is
going out of regulation. nVDD_FAULT causes the
PXA255 processor to enter sleep mode or force an
Imprecise Data Exception, which cannot be masked.
nVDD_FAULT is ignored after a walk-up event until the
power supply timer completes (approximately 10 ms).
Minimum assertion time for nVDD_FAULT is 1 ms.
Hard reset. (input) Level sensitive input used to start the
processor from a known address. Assertion causes the
current instruction to terminate abnormally and causes a
reset. When nRESET is driven high, the processor starts
execution from address 0. nRESET must remain low until
the power supply is stable and the internal 3.6864 MHz
oscillator has stabilized.
Reset Out. (output) Asserted when nRESET is asserted
and deasserts after nRESET is deasserted but before the
first instruction fetch. nRESET_OUT is also as serted for
“soft” reset events: sleep, watchdog reset, or GPIO reset.
JTAG Test Interface Reset. Resets the JTAG/Debug
port. If JTA G/Debug is used, drive nTRST from low to
high either before or at the same time as nRESET. If
JTAG is not used, nTRST must be either tied to nRESET
or tied low.
JTAG test data input. (input) Data from the JTAG
controller is sent to the PXA255 processor using this pin.
This pin has an internal pull-up resistor.
JTAG test data output. (output) Data from the PXA255
processor is returned to the JTAG controller using this
pin.
JTAG test mode select. (input) Selects the test mode
required from the JTAG controller. This pin has an
internal pull-up resistor.
Hi-Z - Note [1]Note [3]
Hi-Z - Note [1]Note [3]
Driven low while
Driven High
InputInput
InputInput
Input
Driven low during
any reset sequence
- driven high prior to
first fetch.
InputInput
InputInput
Hi-ZHi-Z
InputInput
entering sleep
mode. Driven high
when sleep exit
sequence begins.
Input. Driving low
during sleep will
cause normal
reset sequence
and exit from sleep
mode.
Driven Low
2-16 Intel® PXA255 Process or Developer’s Manual
System Arch itecture
Table 2-6. Pin & Signal Descriptions for th e P XA255 Processor (Sheet 9 of 9)
Pin NameTypeSignal DescriptionsReset StateSleep State
TCKIC
TESTICTest Mode. (input) Reserved. Must be grounded. InputInput
TESTCLKICTest Clock. (input) Reserved. Must be grounded.InputInput
Power and Ground Pins
VCCSUP
VSSSUP
PLL_VCCSUP
PLL_VSSSUP
VCCQSUP
VSSQSUP
VCCNSUP
VSSNSUP
JTAG test clock. (input) Clock for all transfers on the
JTAG test interface.
Positive supply for internal logic. Must be connected
to the low voltage supply on the PCB.
Ground supply for internal logic. Must be connected to
the common ground plane on the PCB.
Positive supply for PLLs and oscillators. Must be
connected to the common low voltage supply.
Ground supply for the PLL. Must be connected to
common ground plane on the PCB.
Positive supply for all CMOS I/O except memory bus
and PCMCIA pins. Must be connected to the common
3.3v supply on the PCB.
Ground supply for all CMOS I/O except memory bus
and PCMCIA pins. Must be connected to the common
ground plane on the PCB.
Positive supply for memory bus and PCMCIA pins.
Must be connected to the common 3.3v or 2.5v supply on
the PCB.
Ground supply for memory bus and PCMCIA pins.
Must be connected to the common ground plane on the
PCB.
InputInput
PoweredNote [6]
GroundedG rounded
PoweredNote [6]
GroundedG rounded
PoweredNote [7]
GroundedG rounded
PoweredNote [7]
GroundedG rounded
Table 2-7. Pi n Description No tes (Sheet 1 of 2)
NoteDescription
GPIO Reset Operation: Configured as GPIO inputs by default after any reset. The input buffers for these pins
are disabled to prevent current drain and the pins are pulled high with 10K to 60K internal resistors. The input
[1]
paths must be enabled and the pullups turned off by clearing the Read Disable Hold (RDH) bit described in
Section 3.5.7, “Power Manager Sleep Status Register (PSSR)” on page 3-29. Even though sleep mode sets the
RDH bit, the pull-up resistors are not re-enabled by sleep mode.
Crystal oscillator pins: These pins are used to connect the external crystals to the on-chip oscillators. Refer to
[2]
Section 3.3.1, “32.768 kHz Oscillator” on page 3-4 and Section 3.3.2, “3.6864 MHz Oscillator” on page 3-4 for
details on Sleep Mode operation.
GPIO Sleep operation: During the transition into sleep mode, the state of these pins is determined by the
corresponding PGSRn. See Section 3.5.10, “Power Manager GPIO Sleep State Registers (PGSR0, PGSR1,
PGSR2)” and Section 4.1.3.2, “GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)” on page 4-8. If
[3]
selected as an input, this pin does not drive during sleep. If selected as an output, the value contained in the
Sleep State Register is driven out onto the pin and held there while the PXA255 processor is in Sleep Mode.
GPIOs configured as inputs after exiting sleep mode cannot be used until PSSR[RDH] is cleared.
Static Memory Control Pins: During Sleep Mode, these pins can be programmed to either drive the value in the
Sleep State Register or to be placed in Hi-Z. To select the Hi-Z state, software must set the FS bit in the Power
Manager General Configuration Register. If PCFR[FS] is not set, then during the transition to sleep these pins
[4]
function as described in [3], above. For nWE, nOE, and nCS[0], if PCFR[FS] is not set, they are driven high by
the Memory Controller before entering sleep. If PCFR[FS] is set, these pins are placed in Hi-Z.
Intel® PXA255 Processor Developer’s Manual2-17
System Ar ch itecture
Table 2-7. Pin Description Notes (Sheet 2 of 2)
NoteDescription
PCMCIA Control Pins: During Sleep Mode: Can be programmed either to drive the value in the Sleep State
[5]
Register or to be placed in Hi-Z. To select the Hi-Z state, sof tware must set PCFR[FP]. If it is not set, then during
the transition to sleep these pins function as described in [3], above.
[6]During sleep, this supply may be driven low. This supply must never be high impedance.
[7]Remains powered in sleep mode.
2.12Memory Map
Figure 2-2 and Figure 2-3 show the full proc es so r me mo ry map.
Any unused register space from 0x4000_0000 to 0x4BFF_F FFF is reserved.
Note:Accessing rese rved portions of the memory map will give unpredictable resul t s.
The PCMCIA interface is divided into Socket 0 and Socket 1 space. These two sockets are each
subdivided into I/O, memory and attrib ute space. Each socket is all ocated 256 MB of memory
space.
2-18 Intel® PXA255 Process or Developer’s Manual
Figure 2-2. Memory Map (Part One) — From 0x8000_0000 to 0xFFFF FFFF
T able 2-8. System Architecture Register Address Summary (Sheet 1 of 12)
UnitAddressRegister SymbolRegister Description
DMA
Controller
0x4000_0000
0x4000_0000DCSR0DMA Control / Status Register for Channel 0
0x4000_0004DCSR1DMA Control / Status Register for Channel 1
0x4000_0008DCSR2DMA Control / Status Register for Channel 2
0x4000_000CD CSR3DMA Control / Status Register for Channel 3
0x4000_0010DCSR4DMA Control / Status Register for Channel 4
0x4000_0014DCSR5DMA Control / Status Register for Channel 5
0x4000_0018DCSR6DMA Control / Status Register for Channel 6
0x4000_001CD CSR7DMA Control / Status Register for Channel 7
0x4000_0020DCSR8DMA Control / Status Register for Channel 8
0x4000_0024DCSR9DMA Control / Status Register for Channel 9
0x4000_0028DCSR10D MA Control / Status Register for Channel 10
0x4000_002CDCSR11DMA Control / Status Register for Channel 11
0x4000_0030DCSR12D MA Control / Status Register for Channel 12
0x4000_0034DCSR13D MA Control / Status Register for Channel 13
0x4000_0038DCSR14D MA Control / Status Register for Channel 14
0x4000_003CDCSR15DMA Control / Status Register for Channel 15
0x4000_00f0DINTDMA Interrupt Register
0x4000_0100DRCMR0Request to Channel Map Register for DREQ 0
0x4000_0104DRCMR1Request to Channel Map Register for DREQ 1
0x4000_0108DRCMR2Request to Channel Map Register for I2S receive Request
0x4000_010CDRCMR3Request to Channel Map Register for I2S transmit Request
0x4000_0110DRCMR4Request to Channel Map Register for BTUART receiv e Request
0x4000_0114DRCMR5Request to Channel Map Register for BTUART transmit Request.
0x4000_0118DRCMR6Request to Channel Map Register for FFUART receive Request
0x4000_011CDRCMR7Request to Channel Map Register for FFUART transmit Request
0x4000_0120DRCMR8Request to Channel Map Register for AC97 microphone Request
0x4000_0124DRCMR9Request to Channel Map Register for AC97 modem receive Request
0x4000_0128DRCMR10Request to Channel Map Register for AC97 modem transmi t Request
0x4000_012CDRCMR11Request to Channel Map Register for AC97 audio receive Request
0x4000_0130DRCMR12Request to Channel Map Register for AC97 audio transmit Request
0x4000_0134DRCMR13Request to Channel Map Register for SSP receive Request
0x4000_0138DRCMR14Request to Channel Map Register for SSP transmit Request
0x4000_013CDRCMR15Request to Channel Map Register for NSSP receive Request
0x4000_0140DRCMR16Request to Channel Map Register for NSSP transmit Request
0x4000_0144DRCMR17Request to Channel Map Register for ICP receive Request
0x4000_0148DRCMR18Request to Channel Map Register for ICP transmit Request
System Arch itecture
Intel® PXA255 Processor Developer’s Manual2-21
System Ar ch itecture
Table 2-8. System Archi tecture Regi ster Address Summary (Sheet 2 of 12)
UnitAddressRegister SymbolRegister Description
0x4000_014CDRCMR19Request to Channel Map Register for STUART receive Request
0x4000_0150DRCMR20Request to Channel Map Register for STUART transmit Request
0x4000_0154DRCMR21Request to Channel Map Register for MMC receive Request
0x4000_0158DRCMR22Request to Channel Map Register for MMC transmit Request
0x4000_015CDRCMR23Reserved
0x4000_0160DRCMR24Reserved
0x4000_0164DRCMR25Request to Channel Map Register for USB endpoint 1 Request
0x4000_0168DRCMR26Request to Channel Map Register for USB endpoint 2 Request
0x4000_016CDRCMR27Request to Channel Map Register for USB endpoint 3 Request
0x4000_0170DRCMR28Request to Channel Map Register for USB endpoint 4 Request
0x4000_0174DRCMR29Request to Channel Map Register for HWUART receive Request
0x4000_0178DRCMR30Request to Channel Map Register for USB endpoint 6 Request
0x4000_017CDRCMR31Request to Channel Map Register for USB endpoint 7 Request
0x4000_0180DRCMR32Request to Channel Map Register for USB endpoint 8 Request
0x4000_0184DRCMR33Request to Channel Map Register for USB endpoint 9 Request
0x4000_0188DRCMR34Request to Channel Map Register for HWUART transmit Request
0x4000_018CDRCMR35Request to Channel Map Register for USB endpoint 11 Request
0x4000_0190DRCMR36Request to Channel Map Register for USB endpoint 12 Request
0x4000_0194DRCMR37Request to Channel Map Register for USB endpoint 13 Request
0x4000_0198DRCMR38Request to Channel Map Register for USB endpoint 14 Request
0x4040_0080SADRSerial Audio Data Register (TX and RX FIFO access Register).
AC970x4050_0000
0x4050_0000POCRPCM Out Control Register
0x4050_0004PICRPCM In Control Register
0x4050_0008MCCRMic In Control Register
0x4050_000CGCRGlobal Control Register
0x4050_0010POSRPCM Out Status Register
0x4050_0014PISRPCM In Status Register
0x4050_0018MCSRMic In Status Register
0x4050_001CGSRGlobal Status Register
0x4050_0020CARCODEC Access Register
0x4050_0024
through
0x4050_003C
0x4050_0040P CDRPCM FIFO Data Register
0x4050_0044
through
0x4050_005C
0x4050_0060MCDRMic-in FIFO Data Register
0x4050_0064
through
0x4050_00FC
0x4050_0100MOCRModem Out Control Register
0x4050_0104—Reserved
0x4050_0108MICRModem In Control Register
0x4050_010C—Reserved
0x4050_0110MOSRModem Out Status Register
—Reserved
—Reserved
—Reserved
—Reserved
—Reserved
2
S/MSB-Justified Control Register
2
S/MSB-Justified Interface and FIFO Status Register
System Arch itecture
Intel® PXA255 Processor Developer’s Manual2-25
System Ar ch itecture
Table 2-8. System Archi tecture Regi ster Address Summary (Sheet 6 of 12)
UnitAddressRegister SymbolRegister Description
0x4050_0114—Reserved
0x4050_0118MISRModem In Status Register
0x4050_011C
through
0x4050_013C
0x4050_0140MODRModem FIFO Data Register
0x4050_0144
0x4060_0080UDDR0UDC Endpoint 0 Data Register
0x4060_0100UDDR1UDC Endpoint 1 Data Register
0x4060_0180UDDR2UDC Endpoint 2 Data Register
0x4060_0200UDDR3UDC Endpoint 3 Data Register
0x4060_0400UDDR4UDC Endpoint 4 Data Register
0x4060_00A0UDDR5UDC Endpoint 5 Data Register
0x4060_0600UDDR6UDC Endpoint 6 Data Register
0x4060_0680UDDR7UDC Endpoint 7 Data Register
0x4060_0700UDDR8UDC Endpoint 8 Data Register
0x4060_0900UDDR9UDC Endpoint 9 Data Register
0x4060_00C0UDDR10U DC Endpoint 10 Data Register
0x4060_0B00UDDR 11U DC Endpoint 11 Data Register
0x4060_0B80UDDR12UDC Endpoint 12 Data Register
0x4060_0C00UDDR13UDC Endpoint 13 Data Register
0x4060_0E00UDDR14UDC Endpoint 14 Data Register
0x4060_00E0UDDR15UDC Endpoint 15 Data Register
0x4060_0050UICR0UDC Interrupt Control Register 0
0x4060_0054UICR1UDC Interrupt Control Register 1
0x4060_0058USIR0UDC Status Interrupt Register 0
0x40F0_001CPCFRPower Manager General Configuration Register
0x40F0_0020PGSR0Power Manager GPIO Sleep State R egister for GP[31-0]
0x40F0_0024PGSR1Power Manager GPIO Sleep State Register for GP[63-32]
0x40F0_0028PGSR2Power Manager GPIO Sleep State Register for GP[84-64]
0x40F0_002C—Reserved
System Arch itecture
Intel® PXA255 Processor Developer’s Manual2-29
System Ar ch itecture
Table 2-8. System Architecture Register Address Summary (Sheet 10 of 12)
UnitAddressRegister SymbolRegister Description
0x40F0_002C—Reserved
0x40F0_0030RCSRReset Controller Status Register
SSP0x4100_0000
0x4100_0000SSCR0SSP Control Register 0
0x4100_0004SSCR1SSP Control Register 1
0x4100_0008SSSRSSP Status Register
0x4100_000CSSITRSSP Interrupt Test Register
0x4100_0010SSDR (Write / Read)SSP Data Write Register/SSP Data Read Register
MMC
Controller
Clocks
Manager
Network SSP0x4140_0000
0x4110_0000
0x4110_0000MMC_STRPCLControl to start and stop MMC clock
0x4110_0004MMC_STATMMC Status Register (read only)
0x4110_0008MMC_CLKRTMMC clock rate
0x4110_000CMMC_SPISPI mode control bits
0x4110_0010MMC_CMDATCommand/response/data sequence control
0x4110_0014MMC_RESTOExpected response time out
0x4110_0018MMC_RDTOExpected data read time out
0x4110_001CMMC_BLKLENBlock length of data transaction
0x4110_0020MMC_NOBNumber of blocks, for block mode
0x4110_0024MMC_PRTBUFPartial MMC TXFIFO FIFO written
0x41 10_0028MMC_I_MASKInterrupt Mask
0x4110_002CMMC_I_REGInterrupt Register (read only)
0x4110_0030MMC_CMDIndex of current command
0x4110_0034MMC_ARGHMSW part of the current command argument
0x4110_0038MMC_ARGLLSW part of the current command argument
0x4110_003CMMC_RESResponse FIFO (read only)
0x4110_0040MMC_RXFIFOReceive FIFO (read only)
0x4110_0044MMC_TXFIFOTransmit FIFO (write only)
0x4160_0000HWTHRTransmit Holding Register (write only)
0x4160_0004HWIERInterrupt Enable Register (read/write)
0x4160_0008HWIIRInterrupt ID Register (read only)
0x4160_0008HWFCRFIFO Control Register (write only)
0x4160_000CHWLCRLine Control Register (read/write)
0x4160_0010HWMCRM odem Control Register (read/write)
0x4160_0014HWLSRLine Status Register (read only)
0x4160_0018HWMSRModem Status Register (read only)
0x4400_003CLIIDRLCD Controller Interrupt ID Register
0x4400_0040TRGBRTMED RGB Seed Register
0x4400_0044TCRTMED Control Register
0x4800_0000
System Arch itecture
Intel® PXA255 Processor Developer’s Manual2-31
System Ar ch itecture
Table 2-8. System Architecture Register Address Summary (Sheet 12 of 12)
UnitAddressRegister SymbolRegister Description
0x4800_0000MDCNFGSDRAM Configuration Register 0
0x4800_0004MDREFRSDRAM Refresh Control Register
0x4800_0008MSC0Static Memory Control Register 0
0x4800_000CMSC1Static Memory Control Register 1
0x4800_0010MSC2Static Memory Control Register 2
0x4800_0014MECR
0x4800_001CSXCNFGSynchronous Static Memory Control Register
0x4800_0024SXMRSMRS value to be written to SMROM
0x4800_0028MCMEM0Card interface Common Memory Space Socket 0 T im ing Co nfiguration
0x4800_002CMCMEM1Card interface Common Memory Space Socket 1 Tim ing Co nfiguration
0x4800_0030MCATT0Card interface Attribute Space Socket 0 Timing Configuration
0x4800_0034MCATT1Card interface Attribute Space Socket 1 Timing Configuration
0x4800_0038MCIO0Card interface I/O Space Socket 0 Timing Configuration
0x4800_003CMCIO1Card interface I/O Space Socket 1 Timing Configuration
0x4800_0040MDMRSMRS value to be written to SDRAM
0x4800_0044BOOT_DEF
0x4800_0058MDMRSLPLow Power SDRAM Mode Register Set Configuration Register
0x4800_0064SA1111CRSA1111 Compatibility Register
Expansion Memory (PCMCIA/Compact Flash) Bus Configuration
Register
Read-only Boot-Time Register. Contains BOOT_SEL and PKG SEL
values.
2-32 Intel® PXA255 Process or Developer’s Manual
Clocks and Power Manager3
The Clocks and Power Manager for the PXA255 pr ocessor controls the clock frequency to each
module and manages transitions between the diffe rent power manager (PM) operating modes to
optimize both computing performance a nd power consumption.
3.1Clock Manager Introduction
The Clocks and Power Mana ger provides fixed clocks for each per i pheral unit. Many of the
devices’ pe ripheral clocks can be di sabled using the Clock Enable R e gister (CKEN), or throu gh
bits in the peripheral’s control registers. To m i nimize p ower consumption, turn off the clock to any
unit that is not being used. The Clocks and Power Manager also provides the programmablefrequency c locks for the LCD Cont roller , Memory Contr oller , and CPU. The se clocks a re relate d to
each other because they come from the same internal Phase Locked Loop (PLL) clock source. To
program the PLL’ s frequency, follow these steps (for information on the factors L, M, and N, see
Section 3.6.1, “Core Clock Configuration Register (CCCR)” on page 3-34):
1. Determine the fastest synchronous memory requireme nt (SDRAM frequency).
2. If the SDRAM frequency is less than 99.5 MHz, the Memory Frequency must be twice the
SDRAM Frequency and the SDRAM clock rat io in the Memor y Contr oller must be se t to two.
If the SDRAM fre que ncy is 99.5 MHz, the Memory Frequency is equal to the SDRAM
frequency.
3. Round the Memory Fr equ ency do wn to the nea res t v alue of 99.5 MHz (L = 0x1B ), 1 1 8.0 MHz
(L = 0x20), 132.7 MHz (L = 0x24), 147.5 MHz (L = 0x28), or 165.9 MHz (L = 0x2D), and
program the v alu e of L in t he Co re Cl ock Conf ig ura tion r egi st er. This frequency ( or hal f, if the
SDRAM clock ra tio is 2) is the External Synchronous Memor y Frequency.
4. Determine the req uired Core Frequency for normal (Run Mo de ) operatio n. This mode is us e d
during norma l processing, when the application must make occasional fe tches to external
memory. The possibl e values are one, two, or four times the Memory Frequency. Program this
value (M) in the Core Clock Configuration register.
5. Determine the required Core F requency for Turbo Mode operation. This mode is generally
used when the application runs ent irely from the caches, because any fetches to external
memory slow t he Co re’s performance . Thi s valu e is a mul tipl e ( 1.0, 1.5, 2. 0, or 3.0) of the Run
Mode Frequenc y. Program the va lue (N) in the Core Clock Configuration register.
6. Configure the LCD Controller and Memory Controller for the new Memor y Frequency a nd
enter the Frequency Change Sequence (described in Section 3.4.7, “Frequency Change
Seque n ce ” on pa ge 3 -11).
Note:Not all frequency comb inations are valid. See Section 3.3.3, “Core Phase Locked Loop” for valid
combinations.
Intel® PXA255 Processor Developer’s Manual3-1
Clocks and Power Manager
3.2Power Manager Introduction
The Clocks and P ower Manager can place the proc e ssor in one of three resets.
• Hardware Reset (nRESET asserted) is a nonmaskable total reset. It is used at power up or
when no system informa tion requires preser va tion.
• Watchdog Reset is asserted thro ugh the Watchdog Timer and resets the system except the
Clocks and Power Mana ger. This reset is used as a code monitor. If code fails to complete a
specified sequence, the processor assumes a fatal system error has occurred and causes a
Watchdog Res et.
• GPIO Reset is enabled through the GPIO alternate function regist ers. It is used as an
alternative to Hardware Reset that preserves the Mem ory Controlle r registers and a few critical
states in the Clocks and Power Manager and the Real Time Clock (RTC).
The Clocks and Power Manage r also cont rols the entry into and exit from any of the lo w power or
special clocking modes on processor. These modes are:
• Turbo Mode: the Core runs at its peak frequency. In this mode, make very few external
memory accesses because the Core must wait on the external memory.
• Run Mode: the Core runs at its normal frequency. In this mode, the Core is assumed to be
doing frequent external memory acc e sses, so running slowe r is optimum for the best power/
performance trade-off.
• Idle Mode: the Core is not bei ng clocked, but the rest of the system is fully operational. This
mode is used during brief lulls in activity, when the external s ys tem must contin ue operation
but the Core is idle.
• Sleep Mode: places the processor in its lowest power state but maintains I/O state, RTC, and
the Clocks and Power Manager. Wake-up from Sleep Mode requires re-booting the system,
since most interna l state wa s lost . The co re power must be grou nded in s leep to preven t current
leakage.
The Clocks an d P owe r Ma nag er al so c ontr ols t he proc es sor’s actions during the F reque nc y Cha nge
Sequence. The Frequency Change Sequence is a sequen ce that changes the Core Frequency (Run
and T urb o) a nd Me mo ry Freq uenc y f ro m the pr evi ousl y s to red va lue s to the new val ues i n t he C or e
Clock Configuration register. This sequence takes time to complete due to PLL relock time, but it
allows dynamic frequency changes without compromising external memory integrity. Any
periphera ls t hat rel y on the Core or Mem ory Con tro lle r mu st b e c onf igu red to w ith stand a data f low
interruption.
3.3Clock Manager
The processor’s clocking system incorporates five major clock so ur ces:
• 32.768 kHz Oscillator
• 3.6864 MHz Oscillator
• Programmable Frequency Core PLL
• 95.85 MHz F ixed Frequency Peripheral PLL
• 147.46 MHz Fixed Frequency PLL
3-2 Intel® PXA255 Process or Developer’s Manual
The clock s m a na ger also contains cloc k ga ting for power reduction.
Figure 3-1 shows a functional representation of the c l ocking network. “L” is in the core PLL.
The PXbus is the internal bus between the Core, the DMA/Bridge, the LCD Controller, and the
Memory Controller as shown in Figure 3-1. This bu s is clocked at 1/2 the run mode frequency. For
optimal performance, th e PXbus sho uld be cloc ked as fast as possible. For example, if a tar get cor e
frequenc y of 200 MHz is des ire d use 200 MHz run mo de inst ea d of 200MHz turbo mode with run
at 100 MHz. Increasing the PXbus frequency may help reduce the latency involved in accessing
non-cacheable memory.
Figure 3-1. Clocks Manager Block Diagram
Clocks and Power Manager
32.768k
RTC
32.768
32.768 k
PWR_MGR
/1/112
kHz
OSC
3.6864
MHz
OSC
RETAINS POWER IN SLEEP
USB
FICP
I2C
3.6864
PWM
100-400
MHz
PLL*
147.46
MHz
PLL
95.846
MHz
PLL
MMC
3.6864
SSP
3.6864
GPIO
UARTs
/N
/4
DMA
Bridge
/
3.6864
OST
/2
AC97
CPU
CORE
MEM
Controller
/M
LCD
Controller
PXbus
I2S
47.923
Intel® PXA255 Processor Developer’s Manual3-3
47.923
31.949
19.169
14.746
12.288
5.672
Clocks and Power Manager
3.3.132.768 kHz Oscillator
The 32.768 kHz oscillator is a low p ower, low frequency oscillator that clocks the RTC and Power
Manager. This oscillator is disa bled out of Hardware Reset and the RTC and Power Manager
blocks use the 3.6 864MHz oscillator instead. Software wr ites the Oscillator On bit in the
Oscillator Configurati on Register to enable the 32.768 kHz.This configures the RT C and Power
Manager to use the 32.768 kHz oscillator after it stabilizes.
32.768 kHz oscillator use is optional and provides the lowest power consumption during Sleep
Mode. In less power-s ens itive applications , disable the 32.768 kHz oscillator in the Oscillator
Configuration Register (OS CC) and leave the external pins floating (no external crystal required)
for cost savings. If the 32.768 kHz oscillator is not in the system, the frequency of the RTC and
Power Manag e r will be 3.6864 MHz divided by 112 (32.914 kHz). In Sleep, the 3. 6864 MHz
oscillator consumes hundred s of micr oam ps of extra power when it stays enabled. See
Section 3.5.2, “Power Manager General Configuration Register (PCFR)” on page 3-24 for
information on The Oscillator Power Down Enable (OPDE) bit, which determ ines if the
3.6864 MHz oscillator is enabled in Sleep Mode. No external capacito rs are required.
3.3.23.6864 MHz Oscillator
The 3.6864 MHz oscillator provides the primary clock source for the processor. The on-chip PLL
frequency multipliers, Synchronous Serial Port (SSP), Pulse Width M odulator (PWM), and the
Operating System Timer (OST) use the 3.6864 MHz oscillator as a reference. Out of Hardware
Reset, the 3.6864 MHz oscillator also drives the RTC and Power Manager (PM). The user may
then enable the 32.768 kHz oscillator, which will drive the RTC and PM after it is stabilized. The
3.6864 MHz oscillator can be disabled dur ing Sleep Mode b y settin g the OPDE (s ee Section 3.5.2)
bit but only if the 3 2.768 kHz oscillator is enabled and stabilized (both the OON and OOK b its in
the OSCC set). See Section 3.6.3 for more information. No external capacitor s are required.
3.3.3Core Phase Locked Loop
The Core PLL is the clock source of the CPU Core, the Memory Contr oller, the LCD Controller,
and DMA Controller. The Core PLL uses the 3.6864 MHz oscillator as a reference and multiplies
its fre q ue n c y by the follo wi n g va riables:
• L: Crystal Frequency to Memory Frequency Multiplier , set to 27, 32, 36, 40, or 45.
• M: Memory Frequency to Ru n Mode Frequency Multiplier, set to 1 or 2.
• N: Run Mode Frequenc y to Turbo Mode Fre que ncy Multiplier, set to 1.0, 1.5 , 2.0, or 3.0.
The output fre quency selections are shown in Table 3-1, “Core PLL Output Frequencies for
3.6864 MHz Crystal”. See Section 3.6.1 for programming in formation on the L, M, and N factors.
See Section 3.6.1, “Cor e Clock Configuration Register (CCCR)” for the hexadecimal settings.
Do not choose a combin ation that generates a frequency that is not supported in the voltage range
and package in which the processor is oper ating.
SDCLK must not be greater than 100 MHz. If MEMCLK is greater than 100 MHz, the SDCLK to
MEMC L K ra t i o m ust be set to 1: 2 in the Mem ory Contr o ll er.
3-4 Intel® PXA255 Process or Developer’s Manual
Table 3-1. Core PLL Output Frequencies for 3.6864 MHz Crystal
Clocks and Power Manager
LM
271
361
272
362
452
274
Turbo Mode Frequency (MHz) for Values
Configuration Register (CCCR[15:0])
1.00
(Run)
99.5
@1.0 V
132.7
@1.0 V
199.1
@1.0 V
265.4
@1.1 V
331.8
@1.3 V
398.1
@1.3 V
“N” and Core Clock
programming for Values of “N”
1.502.003.00
—
———66132.766
298.6
@1.1 V
———132.7132.766
———165.9165.983
———19699.599.5
199.1
@1.0 V
398.1
@1.3 V
298.6
@1.1 V
PXbus
Frequency
(MHz)
5099.599.5
—99.599.599.5
3.3.495.85 MHz Peripheral Phase Locked Loop
The 95.85 MHz PLL is the clock source for many of th e peri pheral blocks’ external interfaces.
These interface s req uire ~48 MHz (UDC/USB, FICP), ~3 3 MHz (I
generated frequency is not exactly the required frequency due to the chosen crystal and the lack of
a perfect Least Common Multiple betw een the units. The chosen freque ncies keep each unit’ s clock
frequency within the unit’ s clock toleranc e. If a crystal other than 3.6864 MHz is used, the clock
frequencie s to the peripheral blocks’ interfaces may not yield the desired ba ud rates (or protocol’ s
rate).
2
MEM, LCD
Frequency
(MHz)
SDRAM
max
Frequency
(MHz)
C), and ~20 MHz (MMC). The
Table 3-2. 95. 85 MHz Peripheral PLL Output Frequenc ies for 3.6864 M Hz Crystal
Unit NameNominal FrequencyActual Frequency
USB (UDC)48 MHz47.923 MHz
FICP48 MHz47.923 MHz
2
I
C33 MHz31.949 MHz
MMC20 MHz19.169 MHz
3.3.5147.46 MHz Peripheral Phase Locked Loop
The 147.46 MHz PLL is the clock source for many of the peripheral blocks’ external interfaces.
These interfaces requir e ~14.75 MHz (UARTs), 12.288 MHz (AC97), and variable frequencies
2
(I
S). The generated frequency may not exact ly match the required frequency due to the ch oice of
crystal and t he lack of a perfe ct Least Common Multip le between the units. The cho sen f requen cies
keep each unit’s clock frequency within the unit’s clock toleranc e. I f a crystal other than
3.6864 MHz is used, the clock frequencies to the periphera l blocks’ interfaces may not yield the
desired baud rates ( or other protocol’s rate)
Intel® PXA255 Processor Developer’s Manual3-5
Clocks and Power Manager
Table 3-3. 147.46 MHz Peripheral PLL Output F requencies for 3.6864 MHz Crystal
Unit NameNominal FrequencyActual Frequency
UARTs14.746 MHz14.746 MHz
AC9712.288 MHz12.288 MHz
2
I
S146.76 MHz147.46 MHz
3.3.6Clock Gating
The Clocks Manager contains the CKEN register. This register contains co nfi guration bits that can
disable the cl oc ks to individual units. The c onfiguration bits are used when a module is not being
used. After Hardware Reset, any module that is not being used must have its clock disabled. If a
module is temporarily quiescent but does not have clock gating functiona lity, the CKE N register
can be used to disable the unit’s clock.
When a module’s clock is disabled, the registers i n that module are s till readable and writable. The
AC97 is an exception and is completel y inaccessible if the clock is disabled.
3.4Resets and Power Modes
The Clocks and P ower Manager Unit determines the processor’s Res e ts, Power Sequences and
Power Modes . E ach b ehav es di f fe ren tly d ur ing ope ratio n a nd has sp ecif ic entr y and ex it s equen ces .
The resets and power modes are:
• Hardware Reset
• Watchdog Reset
• GPIO Reset
• Run Mode
• Turbo Mode
• Idle Mode
• Frequency Chan ge Sequence
• Sleep Mode
3.4.1Hardware Reset
To invoke the Hardware Res et and reset all units in the processor to a known state, assert the
nRESET pin. Hardware Reset is only intended to be used for power up and complete resets.
3.4.1.1I nvoking Hardware Reset
Hardware Reset is invoked when the nRESET pin is pulled low by an exter nal s ource. The
processor doe s not provide a method of masking or disabling the propagation of the external pin
value. When the nRESET pin is asserted, Hardware Reset is invoked, regardless of the mode of
operation. The nRESET_OUT pin is asserted when the nRESET pin is asserted. T o ente r Hardware
3-6 Intel® PXA255 Process or Developer’s Manual
Clocks and Power Manager
Reset, nRESET must be held low for t
state to propagate. Refer to the I ntel® PXA255 Processor Electrical, Mech anical, and Thermal Specification for details.
DHW_NRESET
3.4.1.2Behavior During Hardware Reset
During Hardwar e Reset, all internal re gisters and units are held at their defined reset conditions .
While the nRESET pin is asserted, nothing inside the processor is activ e except the 3.6864 MHz
oscillator. The internal clocks are stopp ed and the chip is static. All pins return to their reset
conditions and the nBATT_FAULT and nVDD_FAULT pins are ignored. Because the memory
controller receives a full reset, all dynamic RAM con tents are lost during Hardware Reset.
3.4.1.3Completing Hardware Reset
To complete Hardware Reset, deassert the nRESET pin. All power supplies mu st be stable for
t
D_NRESET
Mechanical, and Thermal Specification for details . After the nRESET pin is deasserted, the
followi n g s e qu e n ce oc c u rs:
1. The 3.6864 MHz oscillator and internal PLL cl oc k ge nerators wait for stabiliza tion.
2. The nRESET_OUT pin is deasserted.
3. The normal boot-up s e quence begins. All process or units retur n to their pr e de fined reset
before nRESET is deasserted. Refer to the Intel® PXA255 Processor Electrical,
conditions. Software mus t e xamine the Reset Controller Status register (RCSR) to determin e
the cause for the boot.
to allow the system to stabilize and the reset
3.4.2Watchdog Reset
Watchdog Reset is invoked when software fails to properly prevent the Watchdog Time-out Event
from occur ring. It is assumed that Watchdog Resets are only generated when software is not
executing properly and has potentially destroyed data. In Watchdog Reset all units in the are reset
except the Clocks and Power Manager.
3.4.2.1Invoking Watchdog Reset
Watchdog Reset is invoked when the Watchdog Enable bit (WE) in the OWER is set and the
OSMR[3] matches the OS timer counter. When these conditions ar e met, they invoke Watchdog
Reset, regardless of the pre vious mode of operation. Watchdog Reset asserts nRESET_OUT.
3.4.2.2Behavior During Watchdog Reset
During Watchdog Reset, al l units excep t the Re al Tim e Clock and parts of the Clocks and Pow er
Manager maintain their defined reset conditions. All pins except the oscillator pi ns a ssume their
reset co nd i ti o ns a nd th e nB ATT_FAULT and nVDD_FAULT pi n s are ig n ored. All dyn a mic RAM
contents are lost during Watchdog Reset beca use the memory c ontroller receives a full reset.
Refer to Table 2-6, “P in & Sign al De scr ip tio ns fo r t he P XA2 55 Pr oce ss or” fo r the pi n stat e s dur ing
Watchdog and other Resets.
Intel® PXA255 Processor Developer’s Manual3-7
Clocks and Power Manager
3.4.2.3Completing a Watchdog Reset
Watchdog resets immediately re vert to hardware resets when the nRESET pin is asserted.
Otherwise, the completion sequence for watchdog reset is :
1. The 3.6864 MHz oscillator and internal PL L clock generators wait for s tabilization. The
32.768 kHz oscil lator’s configuration and status are not af fected by watchdog reset.
2. The nRESET_OUT pin is deasserted a fter t
Electrical, Mechanical, and Therm al Sp ecification.
3. The normal boot-up sequence begins. All processor units except the R T TR in the RTC and
parts of the Clocks and Power Man ager return to their predefi ned r eset conditions. Soft war e
must examine the RCSR to determin e the cause for the reboot.
3.4.3GPIO Reset
A GPIO Reset is inv oked when GP[1] is pro perly configured as a reset source and is asserted low
for greater than four 3.6864-MHz clock cycl es.
parts of the Clocks and Power Ma nager, and the Memory Controller re turn to their predefined,
known states.
3.4.3.1I nvoking GPIO Reset
T o use the GPIO Rese t functio n, set it up through the GPIO Controller. The GP[1] pin must be
configured as an input and set to its alternate GPIO Reset function in the GPIO Con troller. The
GPIO Reset alternate function is level-sensitive and not edge-tri ggered. To ensure no s purious
resets are generat e d when the alternate GPIO Reset function is set, follow these ste ps:
1. GP[1] must be set up as an output with its data register set to a 1.
2. Externally drive the GP[1] pin to a high state.
3. Configure GP[1] as an input.
4. Configure GP[1] for its Al ternate (Reset) Function.
DHW_OUT
In GPIO Reset all processor units ex cept the RTC,
. Refer to the Intel® PXA255 Processor
The previous mode of operation does not affect a GPIO Reset. When performing a GPIO Reset,
nRESET_OUT is asserted.
processor may rema in in its previous mode or enter into a GPIO reset.
GPIO Reset does not function in Sleep Mode beca use all GPIO pin s’ Altern ate Funct ion Inputs are
disabled. E xte rnal wake-up sources mus t be routed through one of the enabled GPIO wake-up
sources (see Section 3.5.3 for details) during Sleep Mode. GP[1] may be enabled as a wake-up
source.
If GP[1] is asserted for less than four 3.6864-MHz clock cycles, the
3.4.3.2B ehavior During GPIO Reset
During GPIO Reset , most , but n ot a ll, in ternal r egi ster s and p roces ses are h eld at their def ined r eset
conditions. The exceptions are the RT C, the Clocks and Power Manager ( unless otherwise noted),
and the Memory Contro ller. During GPIO Reset, the clocks unit contin ues to operate with its
previously programmed values, so the processor ent ers and exits GPIO Reset with the same clock
configurations. All pins except the os cillator and Memory Controller pins return to their reset
condition s and the nBATT_FAULT and nVDD_FAULT pins are ignored.
3-8 Intel® PXA255 Process or Developer’s Manual
GPIO Reset does not reset the Memory Controller Configu ration registers. This creates the
possibility that the con tents of external memories may be preserved if the external memories are
properly configured before GPIO Reset is entered. To preserve SDRAM contents during a GPIO
Reset, software must correctly configure the Memor y Control and the time spent in GPIO Rese t
must be shorter than the SDR AM refresh interval. The amount of ti me spent in GPIO Reset
depends on the C PU’s mode before GPIO Re se t. See Section 6, “Memory Con troller” for details.
Refer to Table 2-6, “Pin & Signal Descriptions for the PXA255 Processor” for the states of all the
PXA255 processor pins during GPIO reset and other resets .
3.4.3.3Completing GPIO Reset
GPIO Reset immediately reverts to Hardware Reset when the nRESET pin is asserted. Otherwise,
the completion sequen ce for GPIO Reset is:
1. The GPIO Reset Source is deasserted because the internal reset has propagated to the GPIO
Controller and its registers, which are set back to their reset sta tes.
2. The nRESET_OUT pin is deasserted.
3. The normal boot-up sequence begins. All processor units exce pt the Real Time Clock, parts of
the Clocks and Power Manager, and the Memory Controller return to their predefined reset
conditions. Software must ex amine the RCSR to determine the cause fo r the reset.
Clocks and Power Manager
3.4.4Run Mode
Run Mode is the processor’ s normal ope rating mode. All power supplies are enabled a nd a ll
functionally enabled clocks are runnin g. Run Mode is entered after any powe r mode, power
sequence , or rese t compl etes its seq uen ce. Run Mode is e xite d whe n any ot her powe r mo de, powe r
sequence, or reset begins.
3.4.5Turbo Mode
Turbo Mode all ows the user to clock the processor cor e at a higher f requency during peak
processi ng requirements. It allows a synchronous s witch in frequencies without disrupting the
Memory Controller, LCD Controller, or any peripheral.
3.4.5.1Entering Turbo Mode
Turbo Mode is invoked when software se ts the TURBO bit in the Clock Config (CCLKCFG)
Register (See Section 3.7.1). After softw are sets the TURBO bit, the CPU waits for all instructi ons
currently in the pipeline to complete. When the instructions are complet ed, the CPU resumes
operation at the higher Turbo Mode Frequency.
Software can set or clear other bits in the CCLKCFG in the same write that sets the TURBO bit.
The other bits in the regis ter take preceden ce over T urb o Mode, so, if another bit is set , that mod e’s
sequence is followe d bef ore the CPU enters Tu rbo Mode. When the CPU exits the othe r mode, it
enters either Run or Turbo Mode, based on the state of the CCLKCFG [TURBO] bit.
Do not confuse the CCLKCFG Register, which is in Coprocessor 14, with the CCCR (See
Section 3.6.1), which is in the proces sor’s Clocks and Power Manager.
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Clocks and Power Manager
3.4.5.2B ehavior in Turbo Mode
The processor’s behavior in Turbo Mode is identical to its behavior in Run Mode , except that the
processor’s clock fr equency relative to the memor y and pe rip herals is increased by N, the value in
the CCCR (see Section 3.6.1). Turbo mode is intended for use during peak processing, when there
are very few acces ses to external memory. The higher Core to external memory clock ratio
increases the relative delay for each external memory access. Th is increased delay lowers t he
processor’s power efficiency. For optimum performance, software must load app lications in the
caches in Run Mode and execute them in Turbo Mode.
3.4.5.3Exiting Turbo Mode
To exit Turbo Mod e, software clears the TURBO bit in the CCLKCFG Reg ister. Af ter software
clears the TURBO bit, the CPU waits for all ins tructions in the pipeline to complete. When the
instructions are completed, the CPU enters Run Mode.
Other bits in the CCL KCFG may be set or cleared in the write that clears CC L KCFG [TURBO].
All other bi ts in th e reg is ter take p rece denc e over Turbo Mode, so the new mode’s proper sequ ence
is followed.
Idle, Sleep, Frequency Change Sequ ence, and Reset have precedence over Turbo Mode and cause
the processor to exit Turbo Mode. When the CPU exits of one of these modes, it enters either Run
or Turbo Mode, based o n the state of CCLKCFG [TURBO].
3.4.6Idle Mode
Idle Mode allows the user to s top the CPU cor e c loc k during pe riods of processor inactivity and
continue to monitor on- and off-chip in terrupt service requests. Idle mode does not change clock
generation, so when an interru pt occurs the CPU is quickly reactivated in the state that preceded
Idle Mode.
During Idle mode these resource s are active:
• System unit modules (real-time clock, operating system timer, interrupt controller, general-
purpose I/O, and clocks and power manager)
• Peripheral un it modules (DMA controller, LCD con t roller, and all othe r pe ripheral units)
• Memory Controller resources
3.4.6.1Entering Idle Mode
During Idle Mode, the clocks to the CPU co re s top. All critic al applications must be finished and
peripherals must be set up to ge ner ate in ter rupts when th ey require CP U attent ion. To enter the Idle
Mode, software selects Idle Mode i n PWRMODE[M] (See Section 3.7.2). An interrupt
immediately a borts Idle Mode and normal pr oc e ssing resume s. After software selects Idle Mode,
the CPU waits unt il all instructions in the pipeline are completed. When the instructions are
completed, the CPU clock st ops and Idle Mode begins. In Idle Mode, interrupts are rec ognized as
wake-up s ources.
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3.4.6.2Behavior in Idle Mode
In Idle Mode the CPU clocks are stopped, but the remainder of the processor operates norm a lly.
For example, the LCD controller can continue refreshing the screen with the same frame buffer
data in memory.
When ICCR[DIM] is cleared , any enabled interrupt wakes up the processor. When ICCR[DIM] is
set, only unmasked int e rrupts cause wake-up.
Enabled interrupts are interru pts that are allowed at the unit level. Masked interrupt s are interrupts
that are prevented from interrupting the core based on the Interrupt Controller Mask Regi ster .
3.4.6.3Exiting Idle Mode
Idle Mode exits when any Reset is asser ted. Res et entry and exit sequences take preced ence ov er
Idle Mode. When the Reset exit sequence is completed, the CPU is not in Idle Mode. If the
Watchdog Timer is enabled, software must set the Watchdog Match Registers before it sets Idle
Mode to ensure that another interru pt will bring the processor out of Idle Mode before the
Watchdog Reset is asserted. Use an RT C alarm or another OS timer channel for this purpose.
Any enabled interrupt causes Idl e Mode to exit. When ICCR[DIM] is cleared , the Interrupt
Controller Mask register (ICMR) is ignored during Idle Mode. This means that an interrupt does
not have to be unma sk ed to cause Idle Mode to exit. Idle Mode exits in the following sequence:
Clocks and Power Manager
1. A valid, enabled Interrupt asserts.
2. The CPU clocks restart and the CPU resumes operation at the state indicated by CCLKCFG
[TURBO].
Idle Mode als o exits whe n the nBATT_FAULT or nVDD_FAULT pin is asserted. When either pin
is asserted, Idle Mode exits in the following sequence:
1. The nBATT_FAULT or nVDD_FAULT pin is asser te d.
2. If the Imprecise Data Abort Enable (IDAE) bit in the Power Manager Control Register
(PMCR) is clear (not recommended), the pr ocessor enters Sleep Mode immediately.
3. If the IDAE bit is set, the nBATT_FAULT or nVDD_FAULT assertion is treated as a valid
interrupt to the clo cks mod ule and Id le Mo de exits usin g it s no rmal, in ter rupt- driv en se quenc e.
Software must then shut down the system and enter Sleep Mode. See Section 3.4.9.3,
“Entering Sleep Mode” fo r more details.
3.4.7Frequency Change Sequence
The Frequency Change Sequence is used to change the processor clock frequency. During the
Frequency Change Sequence, the CPU, Mem ory Controller, LCD Control le r, and DMA clocks
stop. The other peripheral units continue to function during the Frequency Change Sequence. This
mode is int ende d to be used t o cha nge the freq uenc y fr om th e def ault cond iti on at ini tial boo t-up. It
may also be used as a power-saving feature used to allow the process or to run at the minimum
required frequency when the software requires major changes in frequency.
3.4.7.1Preparing for a Frequency Change Sequence
Software must complete the following steps before it initiates the Frequency Change Sequence:
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Clocks and Power Manager
1. Configure the Memory Controller to ensure SDRAM contents are maintained during the
Frequency Change Sequence. The Memory Controller’s refresh timer must be programmed to
match the maximum refresh time asso ciated with the slower of two frequencies (current and
desired). The SDRAM divid e by two must be set to a va lue that prevents the SDRAM
frequency from exceeding the speci fied frequency. For example, to change from 100/100 to
133/66, th e SDRAM bus must be set to divide by two before the f requency c hange. To ch a nge
from 133/66 to 100/100, the SDRAM must be set to one -to-one after the frequency cha nge
sequence is completed. See S ection 6, “Memory Controller” for more detail s.
2. Disable the LCD Controller or configure it to avoid the effects of an interruption in the LCD
clocks and data from the processor.
3. Configure peripheral units to handle a lack of DMA s e rvice for up to 500
unit can not function for 500
4. Disable peripheral units that can not accommodate a 500
generated during the Frequency Change Sequence are serviced when the sequen ce exits.
5. Program the CCCR (Section 3.6.1, “Core Clock Config uration Register (CCCR)”) to reflect
the desired frequency.
µs without DMA service, it must be disabled.
3.4.7.2I nvoking the Frequency Change Sequence
To invoke the Frequency Change Sequen ce, software must set FCS in the CCLKCFG (See
Section 3.7.1). When software sets FCS, it may also set or clear other bits in CCLKCFG. If
software sets the TURBO bit in the same write, the CP U enters Turbo Mode when the Frequency
Change Sequence exits.
After soft wa re se ts the FC S:
1. The CPU clock stops and interrupts to the CPU are gated .
2. The Memory Controller completes all outs tanding transactions in its buffers and from the
CPU. New transactions from the LCD or DMA controllers are ignored.
3. The Memory Controller places the SDRAM in self-refresh m ode.
Note:Program the Memory Controller to ensure the correct self-refresh time for SDRAM, given the
slower of the current and desired clock frequencies.
µs. If a peripheral
µs interrupt latency. The interrupts
3.4.7.3B ehavior During the Frequency Change Sequence
In the frequency c ha nge sequence, the processor’s PLL clock generator is in the pro c e ss of locking
to the correct frequency and cannot be used. This means th a t interrupts cannot be processed.
Interrupts that occur durin g the frequency change sequence are servi ced after the processor’ s PL L
has locked. The 95.85 MHz and 147.46 MHz PLL clock generators are active and peripherals,
except the memory, LCD, and DMA controllers, may continue to operate no rmally, provided they
can accommodate the inab ility to process DMA or interrupt requests. DMA or interrupt requests
are not recognized until the freq uency change sequence is complete.
The Imprecise Data Abort is also not recognized and if nVDD_FAULT or nBATT_FAULT is
asserted, the assertion is ignor ed until the Frequency Change Seq uence exits. This means that the
processor does not enter Sle e p Mode until the Frequency Change Sequence is complete.
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3.4.7.4Completing the Frequency Change Sequence
The Frequency Change Sequence exits when any Reset is a sserted. In Hardwar e a nd Watchdog
Resets, the Reset entry and exit sequences take precede nce over the Frequency Change Sequence
and the PLL resumes in its Reset condition. In GPIO Reset, the Reset exit sequence is delayed
while the PLL relocks and the frequency is set to the desired fr equency of the Frequency Change
Sequence.
If the Watchdog T im er i s enab led dur ing th e F req uenc y Ch ange Seque nc e, se t th e Watchdog Match
Register to ensure that the Frequency Change Sequence completes before the Watchdog Reset is
asserted.
If Hardware or Watchdog Reset is asserted during the F requency Change Sequence, the DRAM
contents are lost becaus e all s tates , including Memory Controller configuration and information
about the previous Frequency Chang e Seq uence, are reset. If GPIO Reset is asserted dur ing the
Frequency Change Sequence, the SDRAM cont e nts will be lost during the GPIO Reset e xit
sequence if the SDRAM is not in self- refresh mode and the exit sequence exceeds the refresh
interval.
Normally, the Frequency Change Sequence exits in the following seq uence:
1. The processor’s PLL clock ge nerator is reprogrammed with the desired value s, which are in
the CCCR, and begins to relock to those values.
Clocks and Power Manager
Note:This sequence occurs even if the be fore and after frequencies are the same.
2. The internal PLL clock generator for the processor clock wai ts for st abilization. Refer to the
Intel® PXA250 and PXA210 Application Processors Electrical, Mechanical, and Thermal
Specification for details.
3. The CPU clocks restart and the CPU resumes operation at the state indicated by the TURBO
bit (either Run or Turbo Mode ). Interr upts to the CPU are no longer gated.
4. The FCS bit is not automatically cleared. To prevent an accidental return to the Frequency
Change Sequence, software must not immed iately clear the FCS bit. The bit must be clear ed
on the next requir ed write to the register.
5. V alues may be written to the CCCR, but they are ignored until the Frequency Change
Sequence is re-entered.
6. The SDRAM must transition out of self-refresh mode and into its idle state. See Section 6,
“Memory Controller” for details on configuring th e SDRAM interface.
3.4.833-MHz Idle Mode
33-MHz idle mode has the lowest power consumption of any idle mode. T he run mode frequency
selected in the Core Clock Con figurati on Register (CCCR) di rectly af fect s the processor idle mode
power consumption. Faster run mode f requencies consume more power. 33-MHz idle mode places
the processor a s pecial l ow speed run mode before en ter ing idle . This i s similar to normal i dle si nce
the CPU core c loc k can be stopped during periods of processor inactivity and co ntinue to monitor
on- and off- chip interrupt service requests. 33- MHz idle limitations are:
• Peripherals will not func tion correctly and should be di sabled before entering this mode.
• A Frequency Cha nge Sequence must be performed upon e ntry to and exit from 33-MHz idle
mode.
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Clocks and Power Manager
• SDRAM is placed in self refresh bef ore entering 33-MHz idle mode, because SDRAM cannot
be refreshed correctly in 33-MHz idle mode. Carefully consider th e pro cessor interrupt
behavior when the SDRAM in sel f refresh. To allow the interrupts to occur while SDRAM is
in self refresh, set the I and F bits in the CPSR. This allows interrupts to wake the processor
from idle mode without jumping to the interrupt handler. When the system’s SDRAM is no
longer in self refresh, the I and F bits can be cleared and the interrupt is handled.
• Because nBATT_FAULT and nVDD_F AULT can cause a data abort interrupt, the function of
these pins in 33-MHz idle mode also needs special consideration. Either the Imprecise Data
Abort Enable (IDAE) bit i n the Power Manager Control Re gister (PMCR ) must be clear,
(causing the processor to immediately enter sleep mode if either nBATT_FAULT or
nVDD_FAULT are asser te d) or take software precautions to av oid starting e xecution in or
trying to use SDRA M while it is in self refresh.
During 33-Mhz idle mode these system unit modules are functional:
• Real-time clock
• Operating system timer
• Interru p t c on t ro lle r
• General purpo se I/O
• Clocks and power manager
• Flash ROM/SRAM
Unlike norm al id le mode, in 33-MH z idl e mo de al l ot her periph era l un its c annot be us ed , inc ludin g
SDRAM, LCD and DMA controllers.
3.4.8.1Entering 33-MHz Idle Mode
During idle mode, the processor core clocks stop. Before the clocks stop, all critical applications
must be fi nish e d an d pe ri phe ral s tur ned off. If software i s exec utin g f ro m SD RAM , the l ast th ree of
the following steps must b e loaded into the cache before being performed.
1. Set the I and F bits in the CPSR register to mask all interrupts
2. Place the SDRAM into self refresh mode
3. Perform a frequenc y cha nge sequence to 33MHz mode. The CCCR value for this mode is
0x13F
4. Enter idle mode by selecting the PWRMODE[M] bit (refer to Sectio n 3. 7. 2 )
3.4.8.2B ehavior in 33-MHz Idle Mode
In 33-MHz idle mode the CPU clocks are stopped. While in 33-MHz idle mode the se features of
the processor all oper ate norm ally : the RTC timer, the OS t imers inclu ding t he wa tchd og t imer , an d
the GPIO interrupt capabilities.
When ICCR[DIM] is clear ed, any enabled int e rrupt wakes up the processor. When ICCR[DIM] is
set, onl y unmasked interrup ts cause wake -up.
Enabled interru pts are interrupts that are allowed at the unit level. Masked inte rr upts are interrupts
that are prevented from interrupting the core based on the Interrupt Controller Mask Register
(ICMR).
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3.4.8.3Exiting 33-MHz Idle Mode
The 33-MHz idle mode exit procedur e is the same as the exit procedure for normal idle mode.
However, because the I and F bits are set in th e CPSR, the proc es so r does not immedi ately jump to
the interrupt vector. Instead processing continues with the instruction foll owing the last executed
instructi on bef ore 33-M Hz idle m ode was en ter ed. I f exe c ution o cc urs fro m SD RAM, s t eps 1 and 2
must have been previously lo aded into the instruction cache. The steps below are then taken:
1. Perform a frequency change to a supported run mode frequency, greater or e qual to 100 MHz.
2. Take the SDRAM out of self refresh.
3. Clear the I and F bits in the CPS R . Execution immediately jumps to the pending interrupt
handler.
3.4.9Sleep M ode
Sleep Mode offers lower power consumption at the expense of the loss of most of the internal
processor state. In Sleep Mode, the proces s or goes through an orderly shut-down seq uence and
power is removed from the core. The Power Manager watches for a wake-up event and, after it
receives one, r e-establi shes p owe r and goe s thr ough a reset s equence. D uring Sleep Mode, the RTC
and Power Mana ger continue to function. Pin states can be controlled throughout Sleep Mode and
external SDRAM is preserved because it is in self-refr es h m ode.
Clocks and Power Manager
Because all activity on the proces s or except the RTC stops when Sleep Mode starts, peripherals
must be disabled to allo w an orderly shutdown. When Sleep Mod e exits, the processor’ s state resets
and processing resu mes in a boot-up mode.
3.4.9.1Sleep Mode External Voltage Regulator Requirements
To implement Sleep Mode in the simplest manner, the External Voltage Regulator, which supplies
power to the processor’s internal elements, must have the following characteristics:
• A power enable input pin that enables the primary supply output connected to VCC and
PLL_VCC. This pin must be connected to the pro c essor’s PWR_EN pin. To suppor t fast sleep
walk-up by maintaining power during sleep, the regulator should be software configurable to
ignore PWR_EN. When PWR_EN is not used, VCC and PLL_VCC may be powered on
before or simultaneously with VCCN and VCCQ. In this configurat ion, when PWR_EN is
deasserted, the core regulator mu s t be able to maintain regulation when the load power is as
little as 0.5 mW. Core supply current du ring sleep will vary with voltage and temperature.
• When core power is enabled during sleep, the power manage ment IC or logic tha t ge nerates
nVDD_FAULT must assert this signal when any supply including VCC and PLL_VCC falls
below the lower regulation limit during sleep. nVDD_FAULT must not be deasserted until all
supplies are in re gulation again since there is no power supply stabilization delay during the
fast sleep walk-up sequence. If nVDD_FAULT is asserted during fast sleep walk-up, then the
processor returns to Sleep Mode.
• When configured to disable the core supply to save power during sleep, the core regulator’s
output must be driven to ground when PWR_EN goes low.
• Higher-voltage outputs connected to VCCQ and VCCN are continuously driven and do not
change when the PWR_EN pin is asserted.
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Clocks and Power Manager
3.4.9.2Preparing for Sleep Mode
Before Sleep Mode starts, software must take the following steps:
1. The Memory Controller must be confi gured to ensur e SDRA M conten ts are m aintain ed d uring
Sleep Mode. See Section 6, “Memory Controller” for de t ails.
2. If a graceful shutdown is required for a peripheral, the peripheral must be disabled before
Sleep Mode asserts. This includes monitoring DMA trans fers to and from peripherals or
memories to ensure they are completed. All other peripherals need not be disabled, since they
are held in their reset states internally durin g Sleep Mode.
3. The following Power Manager registers must be set up for prope r sleep en try and exit:
— PM GPIO Sleep S tate r egist ers (PGS R0, PGSR1, PGSR2) . To avoid contention on th e b us
when the processor att empts to wake up , ensur e that t he c hip s elects are not set to 0 durin g
sleep mode. If a GPIO is used as a n input, it must not be allowed to float during sl e e p
mode. The GPIO can be pulled up or down externally or changed to an output and driven
with the unasserted value.
— PM General Configuration Register Float bits [FS/ FP] must be configured appr opriately
for the system . The General Configu ration Regis ter Flo at b its must b e clear ed on wake u p.
To avoid contention on the bus when the p rocessor attempts to wake up, ensure that the
chip selects are not set to 0 during sleep mode. The PCFR[OPDE] bit must be cleared to
leave the 3.6864 MHz enabled dur ing sleep if the fast walk-up sleep con figuration is
selected by se tting the PMFW[FWAKE] bit.
— PMFW configuration register must be se t to select betw e e n the standa rd a nd fast sleep
wakeup conf igurations. Set PMFW[FWAKE] to 1 to disable the 10 ms power supply
stabiliza tion delay during sleep wakeup if power is maintained during sleep. This
configuration redu ces the s leep wakeup time to approxi mately 650
µs.
4. Before the IDAE bi t is set, software must configure an imprecis e da ta abort exception handle r
to put the pr oce sso r i nto slee p mo de w hen a d ata ab or t o ccur s in resp ons e t o nVD D_FAULT or
nBATT_FAULT assertion. This abort exception event indicates that the processor is in p eril of
losing its main power supply.
5. The following Power Manager registers must be set up to dete c t wa ke-up sources and
oscillator activity:
— PM GPIO Sleep State registers (PGSR0, PGSR,1 and PGSR2).
— PM Wake-up Enable regis t er (PWER)
— PM GPIO Falling-edge Detect Enable and PM GPIO Rising-edg e Detect Enable registers
(PFER and PRER)
— OPDE bit in the Power Manager Configuration Register (PCFR)
— IDAE bit in PMCR
Note:The PCFR[OPDE] bit must be cleared to enable the 3.6864 MHz oscillator during sleep when fast
sleep wakeup is selected by setting the PMFW[FWAKE] bit.
3.4.9.3E ntering Sleep Mode
Software uses the PWRMODE register to enter sleep mode (See Section 3.7.2).
3-16 Intel® PXA255 Process or Developer’s Manual
Clocks and Power Manager
If the external volt age regul ator is fail ing or the main ba ttery is low or missi ng, s ome syst ems must
enter sleep mode quickly. When nBATT_F AULT or nVDD_FAULT is asserted, the system is
required to s hut down immediately.
To allow the assertion of nVDD_FAULT or nBA T T_FAULT to cause an imprecise data abort, set
the Imprecise Data Abort Enable (IDAE) bit in the PMCR. Setting the IDAE bit in the PMCR will
result in s oftware executing the data abort handler routine as part of entering sleep mode. If the
IDAE bit is cle ar , th e process or en ters sleep mode im mediat ely wit hout ex ecuting the abor t handl er
routine.
Note:Using an exception handler to invoke sleep in response to a power fault event is advantageous
because software can clear the PMFW [FWAKE] bit and configure the po wer man agem ent IC to
use PWR_EN to disable the core power supply during sleep to minimize power consumption from
a critically low battery.
PSSR[VFS] a nd P SSR [BFS ] c an not be u se d prio r t o en ter ing Sl ee p Mode to de term ine whi ch t ype
of fault oc c urred, VDD fault or battery fault, respectively. If either nVDD_FAULT or
nBATT_FAU LT signals are asserted or if both are asserted at the same time (and the IDAE bit of
the PMCR is set), the software data abort handler will be c a l led. Since there is only one co mm on
data abort handler, software must first determine if one of the two nVDD_FAULT or
nBATT_FAU LT assertion events result ed in an imprecise data abort by reading Coprocessor 7,
Register 4, Bit 5 (PSFS). If the PSFS bit is cleared, neither a nVDD_FAULT or nBATT_FAULT
assertio n oc c urred and the data abort handler was called for some oth e r reason. I f the PSFS bit is
set, this indicates either a nVDD_FAULT or nBATT_FAULT assertion occurred, but it is not
possible to determin e which of the two faults was asserted. For either case, nVDD_FAUL T or
nBATT_FAULT assertion, software should shut the system down as quickly as possible by
performing the steps outlined below to enter Sleep Mod e.
Note:All addresses (data and ins truction) used in the abort handler routines should be resident and
accessible in the memory page tables, i.e. system software developers should ensure no further
aborts occur while exec uting an abort handler. The proces sor does not support recu rsive (nes te d)
aborts. The system must not assert nBATT_FAULT or nVDD_FAULT signals more than once
before nRESET_OUT is asserted. System software can not return to normal ex ecution following a
nBATT_FAU LT or nVDD_FAULT. If a battery or VDD fault occurs while executin g in the abort
mode, the abort h andler is reenter ed. Th is con dition of a recur sive abort occur rence ca n be detected
in software by reading the Saved Program Status Register (SPSR) to see if the previous context
was executing in abort mode.
To enter Sleep Mode, software must complete the followin g se quence:
1. Software uses exte rnal memory and the Power Manager Scratc h Pad Registe r (PSPR) to
preserve critical states.
2. Software sets Sleep Mode in PWRMODE[M]. An interrupt immediately aborts Sleep Mode
and normal processing resumes.
3. The CPU waits until all instructions in the pipel ine are complete.
4. The Memory Controller completes outstanding tr ansactions in its buffers and from the CPU .
New transactions from the LCD or DMA control lers are ignored.
5. The Memory Controller places the SDRAM in self- ref resh mode.
6. The Power Manager switches the GPIO output pins to their sleep state. This sleep state is
programmed in advance by loading the Power Manag er GPI O Sleep State registers (PGSR0,
PGSR1, and PGS R2) . To avoid contenti on o n the bus wh en th e proc ess or at te mpts to w ake up,
ensure that the chip selects are not set to 0 during sleep mode.
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Clocks and Power Manager
7. The CPU clock stops and power is removed from the Core.
8. PWR_EN is deasserted.
When the Power Manger get the indication fr om the Memory Controller that it has finished its
outstanding transact ions and has p ut the SDRAM int o self- refresh , there ar e e ight co re clock cycles
before the GPIOs latch the PGSR values and four core clo ck cycles after that, nRESET_OUT
asserts low.
In some systems the Im precise Data A bo rt laten cy l asts longer than th e r esidua l cha rge in t he f aile d
power supply can sustai n ope ration. This normally only occurs when the processor is in a Power
Mode or Sequence that requires that the processor exit before Sleep Mode starts. Frequency
Change Sequence is an example of such a Po wer Sequence. In these Power Modes and Sequences,
the IDAE bit must n ot be set. This allows the processor to enters Sleep Mode immediately but any
critical states in the proces s or are lost.
If the IDAE bi t is not set and the nVDD_FAULT or nBATT_FAULT pin is asserted, the Sleep
Sequence begins at Step 4.
3.4.9.4Behavior in Sleep Mode
In Sleep Mode, all processor and periphera l clock s are disabled, except the RTC. The processor
does not recognize interrupts or external pin transitions except valid wake-up signals, Reset
signals, and the nBATT_FAULT signal.
If the nBATT_FAULT signal is asserted while in Sleep Mo de, GPIO[ 1:0] are set as the only valid
wake-up s i gnals.
The Power Manager watches for wake up eve nts programmed by the CP U be fore Sleep Mode
starts or set by the Power Manager it detects a fault condition. In or der to detect a rising-edge or
falling-e dge on a GPIO pin, the rising- or falling-edge must be he ld for more than one full
32.768 kHz clock cycle. The Power Manager takes three 32.768 kHz clock cycles to ackno wled ge
the GPIO edge a nd begin the wake up sequence.
Refer to Table 2-6, “Pin & Signal Descriptions for the PXA255 Pr oc e ssor” on pag e2-9 for the
PXA255 processor pin st a t e s during slee p mode reset and other res e ts.
3.4.9.5E xiting Sleep Mode
Sleep Mode exits when Hardware Reset is asserted. Hardware Reset’s entry and exit sequences
take precedence over Sleep Mode.
Note:If Hardware Reset is asserted during Sleep Mode, the DRAM contents are lost because all states,
including Memo ry Controller conf iguration and information about the previous Sleep Mode, are
reset.
Normally, Sleep Mode exits in the following sequence. Any time the nBATT_FAULT pin is
asserted, the processor returns to Sleep Mode. The nVDD_FAULT pin is ignored until the external
power supply stab ilization timer expires.
1. A pre-programmed wa ke up event from an enabled GPIO or RTC source occurs. If the
nBATT_FAULT pin is as serted, the w a ke up source is ig nored.
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Clocks and Power Manager
2. The PWR_EN signal is asserted and the Power Manager waits for the external power supply to
stabilize. If nVDD_FAULT is asserted after the external power supply timer expires , the
processor returns to Sleep Mode.
3. If PCFR[OPDE] and OSCC[OON] were set when Sleep Mode started, the 3.6864 MHz
oscillator is enabled and stabil izes. Otherwise, the 3.6864 MHz oscillator is already stable and
this step is bypassed.
4. The processor’s PLL clock generator is reprogrammed with the values in the CCCR and
stabilizes.
5. The Sleep Mode configuration in PWRMODE[M] is cleared.
6. The processor’ s int ern al rese t is de as serted an d th e CP U be gi ns a n or mal bo ot se que nce. When
the normal boot sequence begins, all of the processor’s unit s, except the RTC and portions of
the Clocks and Power Manager and the Memory Controller, return to thei r predefined reset
settings.
7. The nRESET_OUT pin is deasserted. This indicates that the processor is about to perform a
fetch from the Re set vector.
8. Clear PSSR[PH] before accessing GPIOs, including chip selects that are muxed with GPIOs.
9. Clear PCFR[FS] and PCFR[FP] if either was set before Sleep Mode was triggered.
10. The SDRAM must transition out of self-refresh mode an d into its idle state. See Section 6,
“Memory Controller” for details on configuring th e SDRAM interface.
11. Software must exami ne the RCSR, to determine what caused the reb oot, and the Power
Manager Sleep Status register (PSSR), to determine what tr iggered Sleep Mode.
12. If the PSPR was use d to pres erv e any cri ti ca l state s du ri n g Sle ep Mo de, soft ware can now
recover the information.
If the nVDD_FAULT or nBATT_FAULT pin is asserted during the Sleep Mode exit sequen ce, th e
system re-enters Sleep Mode in the following sequence:
1. Regardless of the state of the IDAE bit:
— All GPIO edge detects and the RTC alarm interrupt are cleared.
— The Power M anag er w ake -up sour ce regi s ter s (P WER, PR ER, a nd PF ER) a re l oad e d with
0x0000 0003, their wake-up fault state. This limits the potential wake-up sources to a
rising or falling edge on GPIO[0] or GPIO[1]. The wake-up fault stat e prevents spu rious
events from causing an unwanted wake-up while the battery is low or the power supply is
at risk. The fault state is also the default state after a Hardware Reset.
2. The PLL clock generators are disabled.
3. If the OPDE bit in the PCFR is set and the OON bit in the OSCC is set, the 3.6864MHz
oscillator is disabled. If the oscillator is disabled, Sleep Mode consumes less power. If it is
enabled, Sleep Mode exits more quickly.
4. An internal reset is generated to the core and most peripheral modules . This reset asserts the
nRESET_OUT pin.
5. The PWR_EN pin is deasserted. If PMFW[FWAKE] is cleared, the system must respond by
grounding the VCC and PLL_VCC power supplies to minimize power consumption.
Intel® PXA255 Processor Developer’s Manual3-19
Clocks and Power Manager
3.4.10Power Mode Summ ary
Table 3-4 shows the actions that occur when a Power Mode is entered. Table 3-5 shows the actions
that occur when a Power Mode is exited. In the tables, an empty cell means that the power mode
skips that step. Table 3-6 shows the expected behavior for power supplies in each power mode.
Table 3-4. Power Mode Entry Sequence Table
Step
1Software writes a bit in CP14xxxxx
2The CPU waits until all instructions to be completedxxxxx
3Wake up sources are cleared and limited to GP[1:0]x
4The PM places GPIOs in their sleep statesxx
5The Memo ry Controller finishes all outstanding transactionsxxx
6The Memory Controller places SDRAMs in self-refreshxxx
7The PLL is disabledxxx
8If O PD E and OOK bits are set, disable 3.6864 MHz oscillatorxx
9Internal Reset to most modules. nRESET_OUT assertedxx
10PWR_EN is deasserted. Power is cut offxx
11P ower to mo st I/O pins is cut off
1: Fault Sleep Mode starts if IDAE is clear and nBATT_FAULT or nVDD_FAULT is asserted.
.
Description of Action
Table 3-5. Power Mode Exit Sequence Table (Sheet 1 of 2)
Step
1Wake up source or Interrupt is receivedxxx
2Power to I/O pins restored
3PWR_EN is assertedxx
4External power rampxx
5Enable 3.6864 MHz oscillator if OPDE and OOK are setxx
Wait for 3.6864 MHz oscillator to stabilize if OPDE and OOK
6
are set
7Enable PLL with new frequencyxxx
8Wait for PLL stabilizationxxx
9Wait for internal stabilizationxx
10Clear CP14 bitxx
Description of Action
Sleep
Turbo
Turbo
Idle
Freq Change
Run (from Turbo)
Idle
Freq Change
Run (from Turbo)
1
Sleep
Fault
Sleep
1
Sleep
Fault
xx
3-20 Intel® PXA255 Process or Developer’s Manual
Table 3-5. Power Mode Exit Sequ en ce Table (Sheet 2 of 2)
Clocks and Power Manager
Step
11Deassert nRESET_OUTxx
12Restart CPU clocks, enable interruptsxxxxxx
1: Fault Sleep Mode starts if IDAE is clear and nBATT_FAULT or nVDD_FAULT is asserted.
Description of Action
Turbo
Idle
Freq Change
Run (from Turbo)
Sleep
Sleep
1
Fault
Intel® PXA255 Processor Developer’s Manual3-21
Clocks and Power Manager
Table 3-6. Power and Clock Supply Sources and States During Power Modes
Power Mode
Module
Supply Source
TurboRunIdle
PwCkPw Ck Pw Ck Pw Ck Pw Ck Pw Ck
Freq
Change
Sleep
CPU,
Caches,
Buffers
Memory
Controller
LCD
Controller
DMA
Controller
General
Periphs.
OS timer
Interrupts
Real Time
Clock
Power
Manager
GP[3:0], PM
pads, Osc
pads
General IOH
KEY:
T: Turbo clock
R: Run clock
V: Module powered off VCC.
I: Module powered off internal regulator
H: Module powered off VCCQ or VCCN
D: Module is dynamic or actively clocked
S: Module is static or clocks are gated.
VCC
VCC/
Reg
(V/R)
HV/
Batt
(H/B)
Run/
Turbo
(R/T)
Mem
PLL
3.686
MHz Osc
32.768
kHz Osc
Dynamic/
Static
(D/S)
On
OnOnOn
VOnVOnVOnVOn I On
HDHDHDHDHS
T
On
R
On
Off
On
changing
Off Off
On
3.5Power Manager Registers
This section describes the 32-bit regis te rs that control the Power Manager.
3-22 Intel® PXA255 Process or Developer’s Manual
3.5.1Power Manager Control Register (PMCR)
The PMCR is used to select the manner in which S leep Mode is entered when the nVDD_FAUL T
or the nBATT_FA ULT pin is asserted low. When the IDAE bit is set, an Imprecise Data Abort
indication is sent to the CPU. The CPU then performs an abort routin e. Software must ensure that
the abort routine sets the Sleep Mode configuration in the PWRMODE register (see Section 3.7.2,
“Power Mode Register (PWRMODE)”). The IDAE bit is cleared in any Reset and when Sleep
Mode exits. Software may also cl ear the IDAE bit when necessary. The PMCR must be protected
through Memory Managem e nt Unit (MMU) permissions.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Reserved.
Read undefined and must always be written with zeroes.
Imprecise Data Abort Enable.
0 – Allow immediate entry to sleep mode when nVDD_FAULT or nBATT_FAULT is
asserted.
1 – Force imprecise data abort signal to CPU to allow softw are to enter sleep mode
when nVDD_FAULT or nBATT_FAULT is asserted. Recommended mode.
Cleared on hardware, watchdog, and GPIO reset, or when sleep m ode exits.
IDAE
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Clocks and Power Manager
3.5.2Power Manager General Configuration Register (PCFR)
The PCFR contains bits used to configure functions in the processor. When the OPDE bit is set, it
allows the 3.6864 MHz oscillator to be disabled during Sleep Mode. The OPDE bit is cleared in
Hardware, Watchdog, and GPIO Resets. The Float PCMCIA (FP) and Float Static Memory (FS)
bits control the state of the PCMCIA contr ol pins and the static memory c ontrol pins during Sleep
Mode.
This is a read/write register. Ignore reads from res erved bits. Write zeros to reserved bits.
Reserved.
Read undefined and must always be written with zeroes.
Float Static Chip Selects during Sleep Mode.
0 = Static Chip Select pins are not floated in Sleep Mode. nCS[5:1] are driven to the
state of the appropriate PGSR register bits. nCS[1], nWE, and nOE are driven high.
1 = Static Chip Select pins are floated in Sleep Mode. The pins nCS[5:0], nWE, and
nOE are affected.
Cleared on Hardware, Watchdog, and GPIO Resets.
Float PCMCIA controls during Sleep Mode.
0 = PCMCIA pins are not floated in Sleep Mode. They are driven to the state of the
appropriate PGSR register bits.
1 = The PCMCIA signals: nPOE, nPWE, nPIOW, nPIOR, and nPCE[2:1] are floated in
Sleep Mode. nPSKTSEL and nPREG are derived from address signa ls and assume
the state of the address bus during Sleep Mode.
Cleared on Hardware, Watchdog, and GPIO Resets.
3.6864 MHz oscillator power-down enable.
If the 32.7686 kHz crystal is disabled because the OON bit in the Oscillator
Configuration Register is 0, OPDE is ignored and the 3.6864 MHz oscillator is not
disabled.
0 = Do not stop the oscillator during Sleep Mode.
1 = Stop the 3.6864 MHz oscillator during Sleep Mode.
Cleared on Hardware, Watchdog, and GPIO Resets.
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Clocks and Power Manager
3.5.3Power Manager Wake-Up Enable Register (PWER)
Table 3-9 shows the location of all wa ke up source enable bits in the Power Manager Wake-Up
Enable Register (PWER). If a GPIO is to be used as a wake up source from Sl eep, it must be
programmed as an input in the GPDR and either one or both of the corre sponding bits in the PRER
and PFER must be set. When the IDAE bit is zero and a fault condition is detected on the
nVDD_FAULT or nBA TT_FAUL T pin, PWER is set t o 0x0000 0003 and only allows GP[1:0] as
wake-up sources. When the IDA E bit is set, fault conditions on the nVDD_FAULT or
nBATT_FAULT pins do not affect wake-up sources. PWER is also set to 0x0000 0003 in
Hardwar e , Watchdog, or GPIO Re sets.
Software should enable wakeups only for those GPIO pins that are configured as inputs during
sleep. Any GPIO pins that are configured as outputs during sleep, should have their asso ciated
wake enable bits set to logic zero in all three PMU wake enable registers (PWER, PRER, and
PFER).
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
The PRER, shown in Table 3-10, determines whether the GPIO pin enabled with the PWER
register causes a wake u p f rom sleep mode on that GPIO pin’s rising edge. When PWER[ID AE] is
zero and a fault cond iti on is det ec ted on the nVDD_FAULT or nBATT_F AULT pin, PRER is se t to
0x0000_0003. This ena ble s rising edge s on GP[1:0] to act as wake up sources. When
PWER[IDA E] is set, fault conditions on the nVDD_FAULT or nBATT_FAUL T pi ns do not affe c t
wake-up sources. PRER is a lso set to 0x0000_0003 in hardware, watchd og, and GPIO resets.
Software should enable wakeups only for those GPIO pins that are configured as inputs during
sleep. Any GPIO pins th at are configured as outputs during sleep, should have their associated
wake enable bits set to logic zero in all three PMU wake enable registers (P WER, PRER, and
PFER).
This is a read/write register. Ignore reads from res erved bits. Write zeros to reserved bits.
The PFER, Table 3-11, determines if the GPIO pin enabled with the PWER causes a wake up f ro m
sleep mode on that GPIO pin’ s falling edge. When PWER[IDAE] is zero and a fault condition is
detected on the nVDD_F AULT or nBATT_FAULT pin, PFER is set to 0x0000_0003. This enabl es
falling edges on GP[ 1:0] to act as wake up sources. When PWER[IDAE] is se t, fault conditions on
the nVDD_FAULT or nBATT_FAULT pins do not affect wake-up sources. PFER is al so set to
0x0000_0003 during hardware, watchdog, and GPIO resets.
Software should enable wakeups only for those GPIO pins that are configured as inputs during
sleep. Any GPIO pins that are configured as outputs during sleep, should have their asso ciated
wake enable bits set to logic zero in all three PMU wake enable registers (PWER, PRER, and
PFER).
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Reserved.
Read undefined and must always be written with zeroes.
Sleep mode Falling-edge Wake-up Enable
0 – Wake up due to GPx falling-edge detect disabled.
1 – Wake up due to GPx falling-edge detect enabled.
Set to 0x0003 on hardware, watchdog, and GPIO resets.
FE14
FE1
FE0
Intel® PXA255 Processor Developer’s Manual3-27
Clocks and Power Manager
3.5.6Power Manager GPIO Edge Detect Status Register (PEDR)
The PEDR, Table 3-12, indicates whi c h of the GPIO pins enabled through the PWER, PRER, and
PFER register s cau sed a wa ke up from sleep m ode. The bits in PEDR can onl y be se t on a risin g or
falling edg e on a gi ven GPIO p in. If PR ER is set , th e bit s in PED R ca n only b e set on a r is ing e dge .
If PFER is set, the bits in PE DR can only be set on a falling edge. To reset a bit in PEDR to zero,
write a 1 to it. The PEDR bi ts are reset to zero in hardware, watchdog, and GPIO resets.
This is a read/write register. Ignore reads from res erved bits. Write zeros to reserved bits.
Reserved.
Read undefined and must always be written with zeroes.
Sleep mode Edge Detect Status
0 – Wake up on GPx not detected.
1 – Wake up due to edge on GPx detected.
Cleared by hardware, watchdog, and GPIO resets. Cleared by writing a 1.
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Clocks and Power Manager
3.5.7Power Manager Sleep Status Register (PSSR)
The PSSR, shown in Table 3-13, contains the following status flags:
• Software Sleep Status (SSS) flag is set when the sleep mode configuration in the PWRMODE
register is set and sleep mode starts (see Section 3.7.2).
• Battery Fault S tat us (BF S) bit is set af ter wake u p any ti me the nBATT_FAULT pin is asserted
(even when the processor is already in sleep m ode).
• VDD Fault Status (VFS) bit is set after wake up when the nVDD_FAULT pin is asserted and
causes the processor to enter sleep mode. The VFS bit is not set if software start s the s leep
mode and then the nVDD_FAULT pin is asser ted.
• Peripheral Control Hold (PH) bit is set when sleep mode start s and indicates that the GPIO
pins are retaining their sleep mode s tate values.
• Read Disable Hold (RDH) bit is set in hardware, GPIO, and watchdog resets and sleep mode.
The RDH bit indicates th at all the pro cessor’ s GPIO inpu t pat hs ar e disabl ed. To allow a GPIO
input pin to be enabled, software must reset the RDH bit by writing a one to it. Clearing RDH
also disables the 10K to 60 K GPIO pullup resistors that are present during and after
hardware, GPIO and watchdog reset. Sleep mode disables the GPIO input path, but the pullup
resisters are not re -enabled in this case.
To clear a status flag write a 1 to it. Wri ting a 0 to a status bit has no effect. Hardware, watch dog ,
and GPIO resets clear or set the PSSR bits.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Read Disable Hold.
0 – GPIO pins are configured according to their GPIO configuration
1 – Receivers of all GPIO pins that can act as inputs are disabled and following a
5RDH
4PH
3—reserved
hardware, GPIO, or watchdog reset, internal GPIO pull-ups are active. Must be
cleared by the processor after the peripheral and GPIO interfaces are configured
but before they are used.
Set by hardware, watchdog, and GPIO resets and sleep mode. Cleared by writing a 1.
Peripheral Control Hold.
0 – GPIO pins are configured according to their GPIO configuration
1 – GPIO pins are being held in their sleep mode state. Set when sleep mode starts.
Must be cleared by the processor after the peripheral interfaces have been
configured but before they are actually used by the processor.
Cleared by hardware, watchdog, and GPIO resets. Cleared by writing a 1.
VDD Fault Status.
0 – nVDD_FAULT pin has not been asserted since it was last cleared by a reset or the
CPU.
2VFS
1BFS
0SSS
1 – nVDD_FAULT pin was asserted in Run or idle mode and caused the chip to enter
sleep mode; bit is set only after wake up.
This bit is not set when nVDD_FAULT is asserted while in sleep mode.
Cleared by hardware, watchdog, and GPIO resets.
Battery Fault Status.
0 – nBATT_FAULT pin has not been asserted since it was last cleared by a reset or the
CPU.
1 – nBATT_FAULT pin has been asserted; bit is set only after wake up.
This bit can be set when nBATT_FAULT is asserted while in sleep mode.
Cleared by hardware, watchdog, and GPIO resets.
Software Sleep Status.
0 – Software has not entered sleep mode through the sleep mode bit since the SSS
was last cleared by a reset or the CPU.
1 – Chip was placed in sleep mode by setting the sleep mode bit.
Cleared by hardware, watchdog, and GPIO resets.
PH
RDH
VFS
reserved
3.5.8Power Manager Scratch Pad Register (PSPR)
BFS
SSS
The PM contains a 32-bit register that can be used to save processor configuration in formation in
any desired format. The PSPR, shown in Table 3-14, is a holding register that is powered during
sleep mode and is re set by h ard war e, wat chdo g, and GP IO res ets . Du ri ng r un and t ur bo mod es , an y
value can be written to PSPR. The value can be read after sleep mode exits. The value in PSPR can
be used to rep re sent the processor’s configu ration before sleep mode is invoked.
This is a read/write register. Ignore reads from res erved bits. Write zeros to reserved bits.
32-bit word is preserved in sleep mode.
Cleared by hardware, watchdog, and GPIO resets .
Clocks and Power Manager
3.5.9Power Manager Fast Sleep Walk-up Configuration Register
(PMFW)
The PSPR, shown in Table 3-15, provides a single bit called FWAKE which is used to select
between the standar d and fast sleep walk-up sequences. The PMFW register is reset by a hardware
reset, GP IO reset, watchdog reset, but is not cle a red by the sleep walk-up sequ e nc e . Using an
exception handler to inv oke sleep in response to a power fault event is advantageous because
software can clear the PMFW[FWAKE] bit and configure the power management IC to use
PWR_EN to disa ble the core power supply during sleep to minimize powe r consumption from a
critically low batt ery. Also, the PCFR[OPDE] bit must be cleared to ena ble the 3.6864 MHz
oscillator during sleep when fast sleep walk-up is selected by setting the PMFW[FWAKE] bit.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 3-15. PMFW Register Bitmap and Bit Definitions
Reserved
Read undefined and must always be written with zeroes.
FAST WAKEUP ENABLE
0 – Selects the standard sleep wakeup sequence with a 10 ms power supply
stabilization delay when power is disabled during sleep.
1 – Selects the fast sleep wakeup sequence without a power supply stabilization delay
when power is maintained during sleep.
Cleared by hardware reset.
Reserved
Read undefined and must always be written with zeroes.
Power Manager
3.5.10Power Manager GPIO Sleep State Registers (PGSR0,
PGSR1, PGSR2)
PGSR0, PGSR1, and PGSR2, shown in Table 3-16, Table 3-17, and Table 3-18 allow s of t wa re to
select the output state of each GPIO pin when the processor goes into sleep mode. When a
transition to sleep mode is required (through software or the nBATT_FAULT or nVDD_FAULT
pin), the contents of the PGSR register s are loaded into the GPIO out put data registers that s oftware
normally controls t hr ough the GPSR and GPCR register s. Only pins that are already configured as
outputs reflect the new state. All bits in the output registers are loaded. When the processor reenters the run mode, these GPI O pin s retain the programmed sleep st ate until software resets
PSSR[PH]. If a pi n is reconfigu red f rom an i nput to an outpu t, the register’ s las t conten ts are d riven
onto the pin.
FWAKE
Reserved
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
0 – Pin is driven to a zero during sleep mode
1 – Pin is driven to a one during sleep mode
Cleared by hardware, watchdog, and GPIO resets.
SS84
SS83
SS82
SS81
SS80
SS79
SS78
SS77
SS76
SS75
SS74
SS73
SS72
SS71
SS70
SS69
SS68
SS67
SS66
3.5.11Reset Controller Status Register (RCSR)
The CPU uses the RCSR, shown in Table 3-19, to determine a reset’s last cause or causes. The
processor can be reset in four ways:
• Hardware reset
• Watchdog reset
• Sleep mode
• GPIO reset
Refer to Table 2-4, “Effect of E ac h Type of Re set o n In terna l Regi ster S ta te ” on pa ge 2-6 for details
of the behavior of different modules during each type of reset.
SS65
SS64
Each RCSR status bit is set by a differe nt reset sour ce and can be cleared by writi ng a 1 back to the
bit. The RCSR status bits for watchdog reset, sleep mode, and GPIO resets have a hardwa re reset
state of zero.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
GPIO Reset.
0 – GPIO reset has not occurred since the last time the CPU or hardware reset cleared
3GPR
2SMR
1WDR
0HWR
this bit.
1 – GPIO reset has occurred since the last time the CPU or hardwar e reset c l ear ed this
bit.
Cleared by hardware reset and by setting to a 1.
Sleep Mode.
0 – Sleep mode has not occurred sinc e the last time the CPU or hardware reset cleared
this bit.
1 – Sleep mode has occurred since the last time the CPU or hardware reset cleared
this bit.
Cleared by hardware reset and by setting to a 1.
Watchdog Reset.
0 – Watchdog reset has not occurred since the last time the CPU or hardware reset
cleared this bit.
1 – W atchdog reset has occur red since the last time the CPU or hardware reset cleared
this bit.
Cleared by hardware reset and by setting to a 1.
Hardware Reset.
0 – Hardware reset has not occurred since the last time the CPU cleared this bit.
1 – Hardware reset has occurred since the last time the CPU cleared this bit.
Set by hardware reset. Cleared by setting to a 1.
GPR
SMR
WDR
HWR
3.6Clocks Manager Registers
The Clocks Manager contains three registers:
• Core Clock Configuration Register (CCCR)
• Clock Enable Register (CKEN )
• Oscillator Configuration Register (OSCC)
3.6.1C ore Clock Configuration Register (CCCR)
The CCCR, shown in Table 3-20, controls th e core clock frequency, from which the core, memory
controller, LCD c ontroller, and DMA controller frequencies are derived. The crysta l frequency to
memory freq ue ncy multiplier (L), me mory frequency to run mode frequency multiplier (M), a nd
run mode frequency to turbo mode frequency multiplier (N) ar e set in this register. The clock
frequencies are shown below.
3-34 Intel® PXA255 Process or Developer’s Manual
Clocks and Power Manager
Memory fr equen cy = 3.68 64 MHz c rysta l freq. * cr ystal fre quenc y to memor y freque ncy multip lier
(L)
Run mode frequency = Memory frequency * memory fr e quency to run mode frequency multiplie r
(M)
Turb o mode frequency = run mode frequency * ru n mode frequency to turbo mode frequency
multiplier (N )
The value for L is chosen based on external memory or LCD requirements and can be constant
while M and N chang e to all ow run a nd turb o m ode fre quen cy c han ges wi tho ut d isru pti ng memo ry
settings. The value for M is chosen based on bus bandwidth requirements and minimum core
performance requirements. The value f or N is chosen based on peak core performance
requirements.
Run Mode Frequency to Turbo Mode Frequency Multiplier
Turbo mode Freq. = Run mode frequency * N
000 – reserved
001 – reserved
010 – Multiplier = 1
011 – M ultiplier = 1.5
100 – Multiplier = 2
101 – reserved
110 – M ultiplier = 3
111 – reserved
Set to 010 on hardware and watchdog resets.
Memory Frequency to Run Mode Frequency Multiplier
Memory Freq. = Crystal Freq. * L
00 – reserved
01 – Multiplier = 1 (Run mode frequency is equal to memory frequency)
10 – Multiplier = 2 (Run mode frequency is 2 times the memory frequency)
11 – Multiplier = 3 (run mode frequency is 4 times the memory frequency)
Set to 01 on hardware and watchdog resets.
Crystal Frequency to Memory Frequency Multiplier
00000 – reserved
00001 – Multiplier = 27 (Memory Frequency is 99.53MHz from 3.6864MHz crystal)
00010 – reserved
00011 – M ultiplier = 36 (Memory Frequency is 132.71MHz from 3.6864 MHz crystal)
00100 – reserved
00101 – Multiplier = 45 (Memory Frequency is 165.89MHz from 3.6864 MHz crystal)
00110 to 11111 – reserved
Set to 00001 on hardware and watchdog resets.
Clocks Manager
Intel® PXA255 Processor Developer’s Manual3-35
Clocks and Power Manager
3.6.2Clock Enable Register (CKEN)
CKEN, shown in Table 3-21, enables or disables the clocks to most of the peripheral units. For
lowest power con sump tio n, the c lock to any uni t t hat is not bei ng used must be dis ab led by writ ing
a zero to the appropriate bit.
This is a read/write register. Ignore reads from res erved bits. Write zeros to reserved bits.
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
I2C Unit Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
FICP Unit Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
These bits are set by hardware reset or watchdog reset
MMC Unit Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
These bits are set by hardware reset or watchdog reset
USB Unit Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
This bit must be set to allow the 48Mhz clock output on GP7 Alternate Function 1.
NSSP Unit Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
BTUART Unit Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
These bits are set by hardware reset or watchdog reset
FFUART Unit Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
STUART Unit Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
HWUART Un it Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
SSP Unit Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
AC97 Unit Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
PWM1 Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
PWM0 Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
CKEN11
CKEN13
CKEN12
reserved
reserved
reserved
CKEN1
CKEN0
Intel® PXA255 Processor Developer’s Manual3-37
Clocks and Power Manager
3.6.3Oscillator Configuration Register (OSCC)
The OSCC, shown in Table 3-22, controls the 32.7 68kHz oscillator configur a t ion. It contains two
bits, the set-only 32.768 KHz OSCC[OON] and the read-only 32.768 kHz OSCC[OOK].
OSCC[OON] enables the ex ter nal 32.76 8 kHz oscillator and can only be s et by s oftware . W hen the
oscillator is enabl ed, it takes up to 10 seconds for to stabil ize. When the oscillato r is stabilized, the
processor sets OSCC[OOK].
When OSCC[OOK] is set, the RTC and PM are clocked from the 32.768 KHz oscillator.
Otherwise, the 3.6864 MHz oscillator is used. The OPDE bit, which allows the 3.6864 MHz
oscillator to be disabl ed in sleep mode, is ignored (treated as if it were clear) if O SCC[ OO K] is
clear. OSCC[OOK] can only be re set by a hardware reset.
This is a read/write register. Ignore reads from res erved bits. Write zeros to reserved bits.