Intel PXA255 User Manual

Intel® PXA255 Processor

Developer’s Manual

March, 2003

Order Num ber: 278693-001

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ii Intel® PXA255 Processor Developer’s Manual

Contents

1 Introduction...................................................................................................................................1-1

1.1 Intel® XScale™ Microa rc hit ec tur e Featur es...... ................................................................1-1

1.2 System Integrati on Feat ur es................................................................................ ..............1-1

1.2.1 Memory Control ler.......................................................... ......................................1-2

1.2.2 Clocks and Power Controllers...............................................................................1-2

1.2.3 Universal Serial Bus (USB) Client.........................................................................1-2

1.2.4 DMA Controller (DMAC).......................................................................................1-3

1.2.5 LCD Controller......................................................................................................1-3

1.2.6 AC97 Controlle r ....................................................................................................1-3

1.2.7 Inter-IC Sound (I2S) Controller.............................................................................1-3

1.2.8 Multimedia Card (MMC) Controller.......................................................................1-3

1.2.9 Fast Infrared (FIR) Communica tion Port ...............................................................1-3

1.2.10 Synchronous Ser ial Protocol Controller (SSPC)...................................................1-4

1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit....................................................1 -4

1.2.12 GPIO.....................................................................................................................1-4

1.2.13 UARTs..................................................................................................................1-4

1.2.14 Real-Time Clock (RTC).........................................................................................1-5

1.2.15 OS Timers.............................................................................................................1-5

1.2.16 Pulse-Width Mod ulator (PWM) .............................................................................1-5

1.2.17 Interrupt Control ....................................................................................................1 -5

1.2.18 Network Synchronous Serial Protocol Port...........................................................1-5

2 System Architecture.................................................................. ...................................................2-1

2.1 Overview............................................................................................................................2 -1

2.2 Intel® XScale™ Microa rc hit ec tur e Implemen tat i on Opti o ns............... ... ............................2-2

2.2.1 Coprocessor 7 Register 4 - PSFS Bit...................................................................2-2

2.2.2 Coprocessor 14 Registers 0-3 - Performance Monitoring.....................................2-3

2.2.3 Coprocessor 14 Register 6 and 7- Clock and Power Management......................2-3

2.2.4 Coprocessor 15 Register 0 - ID Register Definition..............................................2-3

2.2.5 Coprocessor 15 Register 1 - P-Bit........................................................................2-4

2.3 I/O Ordering.......................................................................................................................2-5

2.4 Semaphores......................................................................................................................2-5

2.5 Interrupts............................................................................................................................2-5

2.6 Reset .................................................................................................................................2-6

2.7 Internal Registe rs....... .................................................. ......................................................2 -7

2.8 Selecting Peripherals vs. General Purpose I/O.................................................................2-7

2.9 Power on Reset and Boot Operatio n..................................... ............................................2-8

2.10 Power Management...........................................................................................................2-8

2.11 Pin List...............................................................................................................................2-8

2.12 Memory Map....................................................................................................................2-18

2.13 System Architecture Register Summary ..........................................................................2-21

3 Clocks and Power Manager.........................................................................................................3-1

3.1 Clock Manager Introduction...............................................................................................3 -1

3.2 Power Manager Introduction..............................................................................................3-2

3.3 Clock Manager...................................................................................................................3-2

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Contents

3.3.1 32.768 kHz Oscillator. .......................... .................................................................3-4

3.3.2 3.6864 MHz Oscillator ..........................................................................................3-4

3.3.3 Core Phase Locked Loop.....................................................................................3-4

3.3.4 95.85 MHz Peripheral Phase Locked Loop..........................................................3-5

3.3.5 147.46 MHz Peripheral Phase Locked Loop........................................................3-5

3.3.6 Clock Gating.........................................................................................................3-6

3.4 Resets and Power Modes..................................................................................................3-6

3.4.1 Hardware Reset....................................................................................................3-6

3.4.2 Watchdog Reset...................................................................................................3-7

3.4.3 GPIO Reset................................................................. .........................................3-8

3.4.4 Run Mode........... ... .......................................................................... .....................3-9

3.4.5 Turbo Mode..........................................................................................................3-9

3.4.6 Idle Mode............ ........................... .................................................. ...................3-10

3.4.7 Frequency Change Sequence............................................................................3-11

3.4.8 33-MHz Idle Mode......................................... .....................................................3-13

3.4.9 Sleep Mode.........................................................................................................3-15

3.4.10 Power Mode Summary....................................................................................... 3-20

3.5 Power Manager Registers...............................................................................................3-22

3.5.1 Power Manager Control Register (PMCR).........................................................3-23

3.5.2 Power Manager General Configuration Register (PCFR)...................................3-24

3.5.3 Power Manager Wake-Up Enable Register (PWER)..........................................3-25

3.5.4 Power Manager Rising-Edge Detect Enable Register (PRER)..........................3-26

3.5.5 Power Manager Falling-Edge Detect Enable Register (PFER)..........................3-27

3.5.6 Power Manager GPIO Edge Detect Status Register (PEDR) .............................3-28

3.5.7 Power Manager Sleep Status Register (PSSR) .................................................3-29

3.5.8 Power Manager Scratch Pad Register (PSPR)..................................................3 -30

3.5.9 Power Manager Fast Slee p Walk-u p Co nfig u rati o n Register (PMFW)...............3-31

3.5.10 P ower Manage r GP IO Sleep State Registers (PGSR0, PGSR1, PGSR2).. .. . .. ..3-31

3.5.11 Reset Controller Status Register (RCSR)...........................................................3-33

3.6 Clocks Manager Registers...... ... ......................................................................................3-34

3.6.1 Core Clock Configuration Register (C CCR) .......................................................3-34

3.6.2 Clock Enable Register (CKEN)................ ...........................................................3-36

3.6.3 Oscillator Configura tio n Registe r (OSCC)................... .......................... .............3-38

3.7 Coprocessor 14: Clock and Power Management............................................................3-38

3.7.1 Core Clock Configuration Register (CCLKCFG).................................................3-39

3.7.2 Power Mode Register (PWRMODE)...................................................................3-40

3.8 External Hardwa r e Considerations................... .... ...........................................................3-40

3.8.1 Power-On-Reset Considerations........................................................................3 -40

3.8.2 Power Supply Connectivity.................................................................................3-40

3.8.3 Driving the Cr ystal Pins from an External Clo ck Source.....................................3-41

3.8.4 Noise Coupling Between Driven Crystal Pins and a Crystal Oscillator...............3-41

3.9 Clocks and Power Manager Register Summary..............................................................3-41

3.9.1 Clocks Manager Register Locations...................................................................3-41

3.9.2 Power Manager Register Summary....................................................................3-41

4 System Integration Unit................................................................................................................4-1

4.1 General-Purpose I/O..........................................................................................................4-1

4.1.1 GPIO Operation................................ ....................................................................4-1

4.1.2 GPIO Alternate Funct ion s.............. .................................................. .....................4-2

4.1.3 GPIO Register De fi n iti o ns.... ... ..............................................................................4-6

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Contents

4.2 Interrupt Contro l ler............... ... ......................................................................... ................4-20

4.2.1 Interrupt Controller Operation.............................................................................4-20

4.2.2 Interrupt Con tr olle r Re gis te r De fi n iti o ns.......... ... .................................................4-21

4.3 Real-Time Clock (RTC) ...................................................................................................4-28

4.3.1 Real-Time Clock Operation.................................................................................4-28

4.3.2 RTC Register Definitions ....................................................................................4-29

4.3.3 Trim Procedure...................................................................................................4-32

4.4 Operating System (OS) Timer.................... ... .................................................. ................4-34

4.4.1 Watchdog Timer Operation............... .... ..............................................................4-35

4.4.2 OS Timer Register Defin i tio ns............................................... .............................4-35

4.5 Pulse Width Modulator.....................................................................................................4-38

4.5.1 Pulse Width Modulator Operation.......................................................................4-38

4.5.2 Register Descriptions..........................................................................................4-40

4.5.3 Pulse Width Modulator Output Wave Example...................................................4-43

4.6 System Integration Unit Register Summary.....................................................................4-44

4.6.1 GPIO Register Locations....................................................................................4-44

4.6.2 Interrupt Con tr olle r Re gis te r Lo ca tio ns........... ....................................................4-45

4.6.3 Real-Time Clock Register Lo cations...................................................................4-45

4.6.4 OS Timer Register Locati o ns......... ... .................................................. ................4-45

4.6.5 Pulse Width Mo dulator Register Locations.........................................................4-46

5 DMA Controller........... ... ......................................................................... ......................................5-1

5.1 DMA Description.................. .................................................. ............................................5-1

5.1.1 DMAC Channels...................................................................................................5-2

5.1.2 Signal Descriptions......................................... ......................................................5-2

5.1.3 DMA Channel Prio rity Scheme.............................................................................5-3

5.1.4 DMA Descriptors...................................................................................................5-5

5.1.5 Channel States.....................................................................................................5-8

5.1.6 Read and Write Order...........................................................................................5-9

5.1.7 Byte Transfer Order..............................................................................................5-9

5.1.8 Trailing Bytes......................................................................................................5-10

5.2 Transferring Data .............................................................................................................5-11

5.2.1 Servicing Internal Peripherals.............................................................................5-11

5.2.2 Quick Referenc e for DMA Progr ammin g............................................................5-13

5.2.3 Servicing Companion Chips and External Peripherals.......................................5-14

5.2.4 Memory-to-Mem ory Mov es................... .......................... ....................................5-16

5.3 DMAC Registers..............................................................................................................5-17

5.3.1 DMA Interrupt Register (DINT)...........................................................................5-17

5.3.2 DMA Channel Control/Status Register ( DCSRx)................................................5-17

5.3.3 DMA Request to Channel Map Re gisters (DRCMRx)........................................5-20

5.3.4 DMA Descriptor Address Registers (DDADRx)..................................................5-20

5.3.5 DMA Source Address Registers.........................................................................5-21

5.3.6 DMA Target Address Registers (DTADRx).........................................................5-22

5.3.7 DMA Command Registers (DCMDx)..................................................................5-23

5.4 Examples.........................................................................................................................5-26

5.5 DMA Controller Re gister Summary .................................................................................5-28

6 Memory Controller........................................................................................................................6-1

6.1 Overview............................................................................................................................6-1

6.2 Functional Descr ip ti o n...................... .................................................................................6-2

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Contents

6.2.1 SDRAM Interfa ce Overview..................................................................................6-2

6.2.2 Static Memory Inter fac e / Variab le Late nc y I/O Interf ac e................... ..................6-3

6.2.3 16-Bit PC Card / Compact Flash Interface ...........................................................6-4

6.3 Memory System Example s............................................. ...................................................6-4

6.4 Memory Accesses.................................................................................... .........................6-7

6.4.1 Reads and Writes................... ......................................................................... .....6-8

6.4.2 Aborts and Nonexistent Memory ............. ... .................................................. ........6-8

6.5 Synchronous DRAM Memory Interface.............................................................................6-8

6.5.1 SDRAM MDCNFG Re gister (MDCNFG................................................................6-8

6.5.2 SDRAM Mode Register Set Configuration Register (MDMRS)..........................6-12

6.5.3 SDRAM MDREFR Register (MDREFR).............................................................6-14

6.5.4 Fixed-Delay or Return-Clock Data Latching.......................................................6-17

6.5.5 SDRAM Memory Options...................................................................................6-18

6.5.6 SDRAM Command Overview.............................................................................6-27

6.5.7 SDRAM Waveforms............................................................................................6-28

6.6 Synchronous Static Memory Interface.............................................................................6-32

6.6.1 Synchronous Static Memory Configuration Register (SXCNFG)........................6-32

6.6.2 Sy nchronous Sta tic Memory Mode R egister Set Confi guration

6.6.3 Synchronous Static Memory Timing Diagrams...................................................6-38

6.6.4 Non-SDRAM Timing SXMEM Operation............................................................6-39

6.7 Asynchronous Sta tic Memory.......................................................................................... 6 -42

6.7.1 Static Memory Inter fac e............. ........................... ..............................................6-42

6.7.2 Asynchronous Static Memory Control Registers (MSCx)...................................6 -44

6.7.3 ROM Interface ....................................................................................................6-48

6.7.4 SRAM Interface Overv i ew................ .................................................. ................6-51

6.7.5 Variable Latency I/O (VLIO) Interface Overview.................................................6-53

6.7.6 FLASH Memory Interface...................................................................................6-56

6.8 16-Bit PC Car d/Compact Flash Interface ........................................................................6-58

6.8.1 Expansion Memory Timing Configuration Register............................................6-58

6.8.2 Expansion Memory Configuration Register (MECR)..........................................6-61

6.8.3 16-Bit PC Card Overview....................................................................................6-62

6.8.4 External Logic for 16-Bit PC Card Implementation.............................................6-64

6.8.5 Expansion Card Interface Timing Diagrams and Parameters ............................6-67

6.9 Companion Chip Int erfa ce................... .................................................. ..........................6-68

6.9.1 Alternate Bus Master Mode................................................................................6-70

6.10 Options and Settings for Boot Memory............................................................................6 -72

6.10.1 Alternate Booting................................................................................................6-72

6.10.2 Boot Time Defaults................. ... .................................................. .......................6-72

6.10.3 Memory Interface Reset and Initialization...........................................................6 -76

6.11 Hardware, Watc hdog, or Sleep Reset Operation............................................................6-77

6.12 GPIO Reset Procedure....................................................................................................6 -79

6.13 Memory Controller Register Summary............................................................................6-79

7 LCD Controller..............................................................................................................................7-1

7.1 Overview............................................................................................................................7-1

7.1.1 Features................................................................................................................7-2

7.1.2 Pin Descriptions....................................................................................................7-4

7.2 LCD Controller Operation..................................................................................................7-4

7.2.1 Enabling th e Controller.........................................................................................7-4

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Contents

7.2.2 Disabling the Controller ........................................................................................7-5

7.2.3 Resetting the Controller........................................................................................7-5

7.3 Detailed Module Descriptions............................................................................................7-5

7.3.1 Input FIFOs...........................................................................................................7-5

7.3.2 Lookup Palette......................................................................................................7-6

7.3.3 Temporal Modulate d Ener gy Distr i buti o n (TMED ) Dith e rin g.. ... ............................7-6

7.3.4 Output FIFOs................ ........................... .............................................................7-8

7.3.5 LCD Controller Pin Usage ....................................................................................7-8

7.3.6 DMA......................................................................................................................7-9

7.4 LCD External Palette and Frame Buffers........................................................................7-10

7.4.1 External Palette Buffer........................................................................................7-10

7.4.2 External Frame Buffer.........................................................................................7-11

7.5 Functional Timing................... ......................................................................... ................7-14

7.6 Register Descrip ti o ns.... ... ................................................................................................7-17

7.6.1 LCD Controller Control Register 0 (LCCR0).......................................................7-18

7.6.2 LCD Controller Control Register 1 (LCCR1).......................................................7-24

7.6.3 LCD Controller Control Register 2 (LCCR2).......................................................7-26

7.6.4 LCD Controller Control Register 3 (LCCR3).......................................................7-28

7.6.5 LCD Controller DMA...........................................................................................7-32

7.6.6 LCD DMA Frame Branch Registers (FBRx).......................................................7-37

7.6.7 LCD Controller Status Re gister (LCSR)..............................................................7-38

7.6.8 LCD Controlle r In te rrup t ID Re gis ter (L IID R)......................................................7-41

7.6.9 TMED RGB Seed Register (TRGBR).................................................................7-42

7.6.10 TMED Control Register (TCR)............................................................................7-43

7.7 LCD Controller Register Summary..................................................................................7-44

8 Synchronous Seri al Port Co nt ro ll er.................... ... .......................................................................8-1

8.1 Overview............................................................................................................................8-1

8.2 Signal Description ..............................................................................................................8-1

8.2.1 External Interface to Synchronous Serial Peripherals ..........................................8-1

8.3 Functional Descr ip ti o n...................... .................................................................................8-2

8.3.1 Data Transfer........................................................................................................8-2

8.4 Data Formats.....................................................................................................................8-2

8.4.1 Serial Data Formats for Transfer to/fr om Peripherals...........................................8-2

8.4.2 Parallel Data Formats for FIFO Storage...............................................................8-6

8.5 FIFO Operation a nd Data Transfers..................................................................................8-7

8.5.1 Using Programmed I/O Data Tran sfers................................................................8-7

8.5.2 Using DMA Data Transfers................... .................................................. ..............8-7

8.6 Baud-Rate Generati on............... .... ......................................................................... ...........8-7

8.7 SSP Serial Port R egisters..................................................................................................8-8

8.7.1 SSP Control Re gister 0 (SSCR0).........................................................................8 -8

8.7.2 SSP Control Re gister 1 (SSCR1).......................................................................8-11

8.7.3 SSP Data Register (SSDR) ................................................................................8-15

8.7.4 SSP Status Register (SSSR)..............................................................................8-16

8.8 SSP Controller Register Summary..................................................................................8-19

C Bus Interface Unit...................................................................................................................9-1

9.1 Overview............................................................................................................................9-1

9.2 Signal Description ..............................................................................................................9-1

9.3 Functional Descr ip ti o n...................... .................................................................................9-1

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Contents

9.3.1 Operational Blocks................................................................................................9-3

9.3.2 I2C Bus Interface Modes.....................................................................................9-3

9.3.3 Start and Stop Bus States ....................................................................................9-4

9.4 I2C Bus Operation.............................................................................................................9-7

9.4.1 Serial Clo ck Line (SCL) Generation......................................................................9-7

9.4.2 Data and Addressing Management......................................................................9-7

9.4.3 I2C Acknowledge..................................................................................................9-8

9.4.4 Arbitration .............................................................................................................9-9

9.4.5 Master Operations..............................................................................................9 -12

9.4.6 Slave Operatio ns................. .................................................. .............................9-14

9.4.7 General Call Address..................... .....................................................................9-16

9.5 Slave Mode Programming Examples ..............................................................................9-18

9.5.1 Initialize Unit.......................................................................................................9 -18

9.5.2 Write n Byte s as a Slave.....................................................................................9-18

9.5.3 Read n Bytes as a Slave....................................................................................9-18

9.6 Master Programming Examples......................................................................................9-19

9.6.1 Initialize Unit.......................................................................................................9 -19

9.6.2 Write 1 Byte as a Master ....................................................................................9-19

9.6.3 Read 1 Byte as a Master....................................................................................9-20

9.6.4 Write 2 Bytes and Repeated Start Read 1 Byte as a Master..............................9-20

9.6.5 Read 2 Bytes as a Master - Send STOP Using the Abort..................................9-21

9.7 Glitch Suppressio n Logi c........ ......................................................................... ................9-21

9.8 Reset Conditions.............................................................................................................9-21

9.9 Register Definitions..........................................................................................................9-22

9.9.1 I2C Bus Monitor Regis te r (IB MR).......................................... .............................9-22

9.9.2 I2C Data Buffer Register (IDBR).........................................................................9-22

9.9.3 I2C Control Register (ICR)..................................................................................9-23

9.9.4 I2C Status Register (ISR) ...................................................................................9-25

9.9.5 I2C Slave Ad dress Register (ISAR)....................................................................9-27

10 UARTs........................................................................................................................................10-1

10.1 Feature List............ ... .................................................. .....................................................10-1

10.2 Overview..........................................................................................................................10-2

10.2.1 Full Function UART................ ........................... .................................................10-2

10.2.2 Bluetooth UART..................................................................................................10-2

10.2.3 Standard UART ..................................................................................................1 0-2

10.2.4 Compatibility with 16550.....................................................................................10-2

10.3 Signal Descrip ti o ns.................... ... ................................................................................... 1 0-3

10.4 UART Operational Description........................................................................................10-4

10.4.1 Reset..................................................................................................................10-5

10.4.2 Internal Register Descript i ons............................ .................................................10-5

10.4.3 FIFO Interrupt Mod e Opera ti o n................................................................. .......10-21

10.4.4 FIFO Polled Mode Operation ............................................................................10-22

10.4.5 DMA Requests. ... ..............................................................................................10-22

10.4.6 Slow Infrared Asy nc hron o us Inte rfa ce........... .... ...............................................10-23

10.5 UART Register Summary..............................................................................................10-26

10.5.1 UART Register Differences..............................................................................10-28

11 Fast Infrared Communication Port..............................................................................................11-1

11.1 Signal Descrip ti o n............ ........................... .....................................................................11-1

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11.2 FICP Operation................................................................................................................11-1

11.2.1 4PPM Modulation...............................................................................................11-2

11.2.2 Frame Format.....................................................................................................11-3

11.2.3 Address Field......................................................................................................11-3

11.2.4 Control Field................. .... ......................................................................... .........11-3

11.2.5 Data Field ...........................................................................................................11-3

11.2.6 CRC Field...........................................................................................................11-4

11.2.7 Baud Rate Generation............ .......................................................................... ..11-4

11.2.8 Receive Operatio n...................................... ........................................................11-4

11.2.9 Transmit Operation.............................................................................................11-5

11.2.10 Transmit and Receive FIFOs..............................................................................11-6

11.2.11 Trailin g or Error Bytes in the Receive FIFO........................................................11-7

11.3 FICP Register Definition s ................................................................................................11-7

11.3.1 FICP Control Regis te r 0 (ICCR0) .......................... ..............................................11-8

11.3.2 FICP Control Regis te r 1 (ICCR1) .......................... ............................................11-10

11.3.3 FICP Control Regis te r 2 (ICCR2) .......................... ............................................11-11

11.3.4 FICP Data Reg ister (ICDR)...............................................................................11-12

11.3.5 FICP Status Register 0 (ICSR0).......................................................................1 1-13

11.3.6 FICP Status Register 1 (ICSR1).......................................................................1 1-15

11.4 FICP Register Summary................................................................................................11-16

12 USB Device Control ler...... .... ......................................................................................................12-1

12.1 USB Overview ................................................................... ..............................................12-1

12.2 Device Configuration.......................................................................................................12-2

12.3 USB Protocol............. ... ......................................................................... ..........................12-2

12.3.1 Signalling Le vels.................................................................................................12-3

12.3.2 Bit Encoding........................................................................................................12-3

12.3.3 Field Formats.................... ... ......................................................................... ......12-4

12.3.4 Packet Formats...................................................................................................12-5

12.3.5 Transaction Formats ...........................................................................................12-6

12.3.6 UDC Device Requests........................................................................................12-8

12.3.7 Configuration ......................................................................................................12-9

12.4 UDC Hardware Connection...........................................................................................12-10

12.4.1 Self-Powered De vice .............. ..........................................................................12-10

12.4.2 Bus-Powered De vic es................... ........................... ........................................12-12

12.5 UDC Operation..............................................................................................................12-12

12.5.1 Case 1: EP0 Control Read .................................................... ...........................12-12

12.5.2 Case 2: EP0 Control Read with a Premature Status Stage..............................12-13

12.5.3 Case 3: EP0 C ontrol Write Wi th or Without a Pre m at ure Status

Stage ................................................................................................................12-14

12.5.4 Case 4: EP0 No Data Command......................................................................12-15

12.5.5 Case 5: EP1 Data Transmit (BULK-IN).... ... ......................................................12-15

12.5.6 Case 6: EP2 Data Receive (BULK-OUT)..........................................................1 2-16

12.5.7 Case 7: EP3 Data Transmit (ISOCHR ON OUS-IN)................ ...........................12-17

12.5.8 Case 8: EP4 Data Receive (ISOCHRONOUS-OUT)........................................12-18

12.5.9 Case 9: EP5 Data Transmit (INTERRUPT-IN) ......... ........................................12-20

12.5.10 Case 10: RESET Interrupt................................................................................12-20

12.5.11 Case 11: SUSPEND Interrupt...........................................................................12-21

12.5.12 Case 12: RESUME Interrupt.............................................................................12-21

12.6 UDC Register Definitions...............................................................................................12-21

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12.6.1 UDC Control Re gis te r (U DCC R).... ....................... ... .........................................12-22

12.6.2 UDC Contro l Function Register (UDCCFR)......................................................12-24

12.6.3 UDC Endpoint 0 Control/Status Register (UDCCS0) .......................................12-25

12.6.4 UDC Endpoint x Cont ro l/Status Register (UDCCS1/6/11)..... ...........................12-27

12.6.5 UDC Endpoint x Cont ro l/Status Register (UDCCS2/7/12)..... ...........................12-29

12.6.6 UDC Endpoint x Cont ro l/Status Register (UDCCS3/8/13)..... ...........................12-31

12.6.7 UDC Endpoint x Cont ro l/Status Register (UDCCS4/9/14)..... ...........................12-32

12.6.8 UDC Endpoint x Cont ro l/ St at us Re gis t e r (UDCCS5/10/15)..............................12-34

12.6.9 UDC Interrupt Contro l Register 0 (UICR0).......................................................12-36

12.6.10 UDC Interrupt Control Register 1 (UICR1) .......................................................12-38

12.6.11 U DC Status/Interrupt Register 0 (USIR0).........................................................12-39

12.6.12 U DC Status/Interrupt Register 1 (USIR1).........................................................12-41

12.6.13 U DC Frame Number High Registe r (UFNHR)..................................................12-42

12.6.14 U DC Frame Number Low Register (UFNLR)...................................................12-44

12.6.15 UDC Byte Count Register x (UBCR2/4/7/9/12/14)...........................................12-44

12.6.16 UDC Endpoint 0 Data Register (UDDR0).........................................................12-45

12.6.17 UDC Endpoint x Data Register (UDDR1/6/11).................................................12-46

12.6.18 UDC Endpoint x Data Register (UDDR2/7/12).................................................12-46

12.6.19 UDC Endpoint x Data Register (UDDR3/8/13).................................................12-47

12.6.20 UDC Endpoint x Data Register (UDDR4/9/14).................................................12-47

12.6.21 UDC Endpoint x Data Register (UDDR5/10/15)...............................................12-48

12.7 USB Device Controller Register Summary....................................................................12-48

13 AC’97 Controller Unit..................................................................................................................13-1

13.1 Overview..........................................................................................................................13-1

13.2 Feature List............ ... .................................................. .....................................................13-1

13.3 Signal Descrip ti o n............ ........................... .....................................................................13-2

13.3.1 Signal Configuration Steps.................................................................................13-2

13.3.2 Example AC-link .................................................................................................13-2

13.4 AC-link Digital Serial In terface Protocol...........................................................................13-3

13.4.1 AC-link Audio Output Frame (SDATA_OUT) ......................................................13-4

13.4.2 AC-link Audio Input Frame (SDATA_IN).............................................................13-8

13.5 AC-link Low Power Mode....................................................................................... .......13-12

13.5.1 Powering Down the AC-l in k..............................................................................13-12

13.5.2 Waking up th e AC-link......................................................................................13-13

13.6 ACUNIT Operation.........................................................................................................13-14

13.6.1 Initialization.......................................................................................................13-15

13.6.2 Trailing bytes.................................................................................................... 13-17

13.6.3 Operational Flow for Accessing CODEC Registers..........................................13-17

13.7 Clocks and Sampling Fre que nc i es................ ... .............................................................13-17

13.8 Functional Description...................................................................................................13-18

13.8.1 FIFOs................................................................................................................13-18

13.8.2 Interrupts...........................................................................................................13-19

13.8.3 Registers...........................................................................................................13-19

13.9 AC’97 Register Summary..............................................................................................13-35

14 Inter-Integrated-Circuit Sound (I2S) Controller...........................................................................14-1

14.1 Overview..........................................................................................................................14-1

14.2 Signal Descrip ti o ns.................... ... ................................................................................... 1 4-2

14.3 Controller Operation........................................................................................................14-3

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14.3.1 Initializatio n.........................................................................................................14-3

14.3.2 Disabling and Enabling Audio Replay.................................................................14-4

14.3.3 Disabling an d Enabling Audio Record................................................................14-4

14.3.4 Transmit FIFO Errors..........................................................................................14-5

14.3.5 Receive FIFO Errors................... ... .....................................................................14-5

14.3.6 Trailing Bytes......................................................................................................14-5

14.4 Serial Audio Clocks and Sampling Frequencies..............................................................14-5

14.5 Data Formats...................................................................................................................14-6

14.5.1 FIFO and Memory Format..................................................................................14-6

14.5.2 I2S and MSB-Justified Serial Audi o Format s......................................................14-6

14.6 Registers..........................................................................................................................14-8

14.6.1 Serial Audio Controller Global Control Register (SACR0)..................................14-8

14.6.2 Serial Audio Controller I2S/MSB-Justified Control Register

(SACR1) ...........................................................................................................1 4-10

14.6.3 Serial Audio Controller I2S/MSB-Justified Status Register

(SASR0)............................................................................................................14-11

14.6.4 Serial Audio Clock Divider Register ( SADIV)....................................................14-12

14.6.5 Serial Audio Interrupt Clear Register (SAICR)..................................................14-13

14.6.6 Serial Audio Interrupt Mask Register (SAIMR) .................................................14-14

14.6.7 Serial Audio Data Register (SADR)..................................................................14-14

14.7 Interrupts........................................................................................................................14-15

14.8 I

S Controller Register Summary ..................................................................................14-15

15 MultiMediaCard Controller.......................................................................................................... 15-1

15.1 Overview..........................................................................................................................15-1

15.2 MMC Controller Functional Description...........................................................................15-4

15.2.1 Signal Descrip ti o n................... .... ........................................................................15-6

15.2.2 MMC Controller Reset........................................................................................15-6

15.2.3 Card Initializa tion Sequence................. .......................... ....................................15-6

15.2.4 MMC and SPI Modes..........................................................................................15-6

15.2.5 Error Detection....................................................................................................15-8

15.2.6 Interrupts.............................................................................................................15-8

15.2.7 Clock Control......................................................................................................15-9

15.2.8 Data FIFOs.......................................................................................................15-10

15.3 Card Communication Protocol.......................................................................................15-12

15.3.1 Basic, No Data, Command and Re sponse Sequence......................................15-13

15.3.2 Data Transfer....................................................................................................15-13

15.3.3 Busy Sequence.................................................................................................1 5-16

15.3.4 SPI Functionality...............................................................................................15-17

15.4 MultiMediaCard Controller Operation............................................................................1 5-17

15.4.1 Start and Stop Clock................... ... .................................................. .................15-17

15.4.2 Initialize.............................................................................................................15-17

15.4.3 Enabling SPI Mode...........................................................................................15-17

15.4.4 No Data Command and Response Sequence..................................................15-18

15.4.5 Erase ................................................................................................................15-18

15.4.6 Single Data Block Wri te.............. .......................... ............................................15-18

15.4.7 Single Block Read ........................................................................... .................15-19

15.4.8 Multiple Block Write..........................................................................................15-20

15.4.9 Multiple Block Read..........................................................................................15-20

15.4.10 Stream Write.............. .................................................. .....................................15-21

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15.4.11 Stream Read.....................................................................................................15-21

15.5 MMC Controller Registers.............................................................................................15-22

15.5.1 MMC_STRPCL Regis ter.. .... .................................................. ...........................15-22

15.5.2 MMC_Status Register (MMC_STAT) ...............................................................15-23

15.5.3 MMC_CLKRT Register (MMC_CLKRT)...........................................................15-24

15.5.4 MMC_SPI Register (MMC_SPI)................................................................ .......15-25

15.5.5 MMC_CMDAT Registe r (MMC_CMD AT ).................... .....................................15-26

15.5.6 MMC_RESTO Register (MMC_RESTO)..........................................................15-27

15.5.7 MMC_RDTO Register (MMC_RDTO) ..............................................................15-28

15.5.8 MMC_BLKLEN Register (MMC_BLKLEN).......................................................15-29

15.5.9 MMC_NOB Register (MMC_NOB)...................................................................15-29

15.5.10 MMC_PRTBUF Register (MMC_PRTBUF)......................................................15-30

15.5.11 MMC_I_MASK Register (MMC_I_MASK) ........................................................ 15-30

15.5.12 MMC_I_REG Register (MMC_I_REG).............................................................15-31

15.5.13 MMC_CMD Register (MMC_CMD) ......... .................................................. .......15-33

15.5.14 MMC_ARGH Register (MMC_ARGH)..............................................................15-35

15.5.15 MMC_ARGL Register (MMC_ARGL)............ .... ...............................................15-35

15.5.16 MMC_RES FIFO........ .......................... .................................................. ...........15-36

15.5.17 MMC_RXFIFO FIFO.........................................................................................15-36

15.5.18 MMC_TXFIFO FIFO .. ... .................................................. ..................................15-37

15.6 MultiMediaCard Controller Register Summary..............................................................15-37

16 Network SSP Serial Port.............................................................. ..............................................16-1

16.1 Overview..........................................................................................................................16-1

16.2 Features...........................................................................................................................16-1

16.3 Signal Descrip ti o n............ ........................... .....................................................................16-2

16.4 Operation .........................................................................................................................16-2

16.4.1 Processor and DMA FIFO Access......................................................................16-2

16.4.2 Trailing Bytes in the Receive FIFO.....................................................................16-3

16.4.3 Data Formats......................................................................................................16-3

16.4.4 Hi-Z on SSPTXD...............................................................................................16-13

16.4.5 FIFO Operation............. .................................................. ..................................16-17

16.4.6 Baud-Rate Generation......................................................................................16-17

16.5 Register Descriptions.....................................................................................................16-18

16.5.1 SSP Control Register 0 (SSCR0).....................................................................16-18

16.5.2 SSP Control Register 1 (SSCR1).....................................................................16-20

16.5.3 SSP Programmable Serial Protocol Register (SSPSP)....................................16-22

16.5.4 SSP Time Out Register (SSTO).......................................................................16-24

16.5.5 SSP Interrupt Test Register (SSITR)................................................................16-24

16.5.6 SSP Status Register (SSSR)............................................................................16-25

16.5.7 SSP Data Register (SSDR)..............................................................................16-28

16.6 Network SSP Serial Port Registe r Summary........... ........................... .......................... .16-29

17 Hardware UART.........................................................................................................................17-1

17.1 Overview..........................................................................................................................17-1

17.2 Features...........................................................................................................................17-1

17.3 Signal Descrip ti o ns.................... ... ................................................................................... 1 7-3

17.4 Operation .........................................................................................................................17-3

17.4.1 Reset..................................................................................................................17-4

17.4.2 FIFO Operation............. .................................................. ....................................17-4

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17.4.3 Autoflow Contro l ............................................. ....................................................17-7

17.4.4 Auto-Baud-Rate Detection..................................................................................17-7

17.4.5 Slow Infrared Asynchronous Interface................................................................17-8

17.5 Register Descri p tio ns.... .................................................................................................17-10

17.5.1 Receive Buffer Register (RBR).........................................................................17-10

17.5.2 Transmit Holding Register (THR)......................................................................17-10

17.5.3 Divisor Latch Registers (DLL and DLH)............................................................17-10

17.5.4 Interrupt Enable Register (IER) ........................................................................17-11

17.5.5 Interrupt Ide nti fi ca tio n Re gis te r (II R).................. ... ............................................17-13

17.5.6 FIFO Control Regis te r (FCR)................... .........................................................17-15

17.5.7 Receive FIFO Occupa ncy Reg ister (FOR).......................................................17-16

17.5.8 Auto-Baud Control Registe r (ABR)...................................................................17-17

17.5.9 Auto-Baud Count Re gis ter (AC R)................... ... ...............................................17-17

17.5.10 Line Control Register (LCR)..............................................................................1 7-18

17.5.11 Line Status Register (LSR)...............................................................................17-19

17.5.12 Modem Contr ol Re gis te r (MC R)..................... ..................................................17-21

17.5.13 Modem Sta tus Register (MSR) .........................................................................17-23

17.5.14 Scratch pad Register (SCR)..............................................................................17-24

17.5.15 Infrared Selection Re gister (ISR)......................................................................17-24

17.6 Hardware UART Register Summary........... ... ................................................................17-25

Figures

2-1 Block Diagram ...........................................................................................................................2-2

2-2 Memory Map (Part One) — From 0x8000_0000 to 0xFFFF FFFF..........................................2-19

2-3 Memory Map (Part Two) — From 0x0000_0000 to 0x7FFF FFFF..........................................2-20

3-1 Clocks Manager Block Di agr am............... ........................... ......................................................3-3

4-1 General-Purpose I/O Block Diagram.........................................................................................4-2

4-2 Interrupt Con tr olle r Blo ck Di a gram.............. ............................................................................4-21

4-3 PWMn Block Diagram.... .................................................. ........................................................4-39

4-4 Basic Pulse Width Waveform..................................................................................................4-43

5-1 DMAC Block Diagram................................................................................................................5-1

5-2 DREQ timing requirements........................................................................................................5-3

5-3 No-Descrip to r Fetc h Mode Chann el Sta te............. ....................................................................5-6

5-4 Descriptor Fetch Mode Channel State.......................................................................................5-8

5-5 Little Endian Transfers.............................................................................................................5-10

6-1 General Memory Interface Configuration...................................................................................6-2

6-2 SDRAM Memory System Example............................................................................................6-5

6-3 Static Memory System Exam ple.............................................................. ..................................6-6

6-4 External to Internal Address Mapping Options........................................................................6-19

6-5 Basic SDRAM Timing Parameters...........................................................................................6-29

6-6 SDRAM_Read_diffbank_diffrow..............................................................................................6-29

6-7 SDRAM_read_samebank_diffrow...........................................................................................6-30

6-8 SDRAM_read_sameban k_samerow .......................................................................................6-30

6-9 SDRAM_write..........................................................................................................................6-31

6-10 SDRAM 4-Beat Read/ 4-Beat Wr ite To Dif fere nt Parti ti ons.....................................................6-31

6-11 SDRAM 4-Beat Write / 4-Write Same Bank, Same Row........... ..............................................6-32

6-12 SMROM Read Timing Diagra m Hal f- Memo ry Cl ock Fr eque n cy.............................................6-39

6-13 Burst-of-Eight Synchronous Flash Timing Diagram (non-divide-by-2 mode)..........................6-41

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6-14 Flash Memory Reset Using State Machine.............................................................................6-42

6-15 Flash Memory Reset Log ic if Watchdog Reset is Not Necessary...........................................6-42

6-16 MSC0/1/2.................................................................................................................................6-45

6-17 32-Bi t Burst-of-Eig ht ROM or Flash R ead Timing Diagram (MSC0[R DF ] = 4,

MSC0[RDN] = 1, MSC0[RRR] = 1)..........................................................................................6-49

6-18 Eigh t -Beat Burst Re ad from 16-Bit Burst-of-Fou r ROM or Flash

(MSC0[RDF] = 4, MSC0[RDN] = 1, MSC0[RRR] = 0).............................................................6-50

6-19 32-Bi t Non-burst ROM, SRAM, or F la sh Read Timin g Di agram - Four Data

Beats (MSC0[RDF] = 4, MSC0[RRR] = 1)...............................................................................6-51

6-20 32-Bi t SRAM Write Timing Diagram (4 -beat Burst (MSC0[RDN] = 2,

MSC0[RRR] = 1)......................................................................................................................6-52

6-21 32-Bit Variable Latency I/O Read Tim ing (Burst-of -F our, One Wait C yc l e Per

Beat) (MSC0[RDF] = 2, MSC0[RDN] = 2, MSC0[RRR] = 1)...................................................6-54

6-22 32-Bit Variable Latency I/O Write T i m i ng (Burst-of-Four, Variabl e Wait Cycles

Per Beat) .................................................................................................................................6-55

6-23 Asynchronous 32-Bit Flash Write Timing Diagram (2 Writes).................................................6 -57

6-24 MCMEM1.................................................................................................................................6-58

6-25 MCATT1..................................................................................................................................6-58

6-26 16-Bit PC Ca rd Memory Map ..................................................................................................6-62

6-27 Expansion Card External Logic for a One-Socket Configuration.............................................6-65

6-28 Expansion Card External Logic for a Two-Socket Configuration.............................................6-66

6-29 16-Bit PC Card Memory or I/O 16-Bit (Half-word) Access.......................................................6-67

6-30 16-Bit PC Card I/O 16-Bit Access to 8-Bit Device...................................................................6-68

6-31 Alternate Bus Master Mode.....................................................................................................6-69

6-32 Variable Latency IO.................................................................................................................6-69

6-33 Asynchronous Boot Time Configurations and Registe r Defaults.............................................6-74

6-34 SMROM Boot Time Configurations and Register Defaults......................................................6 -75

6-35 SMROM Boot Time Configurations and Register Defaults......................................................6 -76

7-1 LCD Controller Block Diagram ..................................................................................................7-3

7-2 Temporal Dithering Concept - Single Color...............................................................................7-6

7-3 Compare Range for TMED........................................................................................................7-7

7-4 TMED Block Diagram............. ......................................................................... .........................7-8

7-5 Palette Buffe r Format.............. .................................................. ..............................................7-11

7-6 1 Bit Per Pixel Data Memory Organiz ation................... .......................... .................................7-11

7-7 2 Bits Per Pixel Data Memory Organization............................................................................7-12

7-8 4 Bits Per Pixel Data Memory Organization............................................................................7-12

7-9 8 Bits Per Pixel Data Memory Organization............................................................................7-12

7-10 16 Bits Per Pixel Data Memory Organization - Passive Mode ................................................7-13

7-11 16 Bits Per Pixel Data Memory Organization - Active Mode ...................................................7-13

7-12 Passive Mode Start-of-Frame Timing......................................................................................7-15

7-13 Passive Mode End-of-Frame Timing.......................................................................................7-15

7-14 Passive Mode Pixel Clock and Data Pin Timing......................................................................7-16

7-15 Active Mode Timing.................................................................................................................7-16

7-16 Active Mode Pixel Clock and Data Pin Timing ........................................................................7-17

7-17 Frame Buffer/Palette Output to LCD Data Pins in Active Mode..............................................7-20

7-18 LCD Data-Pin Pixel Ordering...................................................................................................7-22

8-1 Texas Instru ments’ Synchronous Seri al Fra me* For mat.................. .........................................8-4

8-2 Motorola SPI* Frame Format.....................................................................................................8-5

8-3 National Micro wir e* Fra me For mat.............. ........................... .................................................. .8-6

8-4 Motorola SPI* Frame Formats for SPO and SPH Programming.............................................8-13

9-1 I

C Bus Configuration Example.................................................................................................9-2

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9-2 Start and Stop Conditio ns............ ......................................................................... .....................9-5

9-3 START and STOP Conditions...................................................................................................9-6

9-4 Data Format of First Byte in Master Transaction.......................................................................9-8

9-5 Acknowledge on the I2C Bus.....................................................................................................9-9

9-6 Clock Synchronization During the Arbitr ation Procedure.........................................................9-10

9-7 Arbitration Procedure of Two Masters.....................................................................................9-11

9-8 Master-Receive r Read from Slave-Transmitter.......................................................................9-14

9-9 Mas t er-Receiver Read from Slave-Transmit ter / Repeated Start / Master -T ransmitter

Write to Slave-Rec eiv er........ ... .......................................................................... ......................9-14

9-10 A Complete Da ta Transfer.......................................................................................................9-14

9-11 Master-Transmitter Write to Slave-Receive r ............................................................................9-16

9-12 Master-Receive r Read to Slave-Transmitter ...........................................................................9-16

9-13 Master-Receiver Read to Slave-Transmitter, Repeated START, Master-Transmitter

Write to Slave-Rec eiv er........ ... .......................................................................... ......................9-16

9-14 General Call Address...............................................................................................................9-17

10-1 Example UART Data Frame....................................................................................................10-4

10-2 Example NRZ Bit Encoding – (0b0100 1011...........................................................................10-5

10-3 IR Transmit and Receive Example........................................................................................10-25

10-4 XMODE Example...................................................................................................................10-25

11-1 4PPM Modulation Encodings...................................................................................................11-2

11-2 4PPM Modulation Example.....................................................................................................11-2

11-3 Frame Format fo r IrDA Transmission (4.0 Mbps)....................................................................11-3

12-1 NRZI Bit Encoding Example....................................................................................................12-4

12-2 Self-Powere d Devi c e.......................................... ...................................................................12-11

13-1 Data Transfer Through the AC-link..........................................................................................13-3

13-2 AC’97 Standard Bidi re ctio n al Aud io Frame.................. ........................... ................................13-4

13-3 AC-link Audio Output Frame....................................................................................................13-5

13-4 Start of Audio Output Frame ....................................................................................................13-5

13-5 AC’97 Input Frame...................................................................................................................13-9

13-6 Start of an Audio Input Frame..................................................................................................13-9

13-7 AC-link Powerd ow n Timi ng.............................. ......................................................................13-12

13-8 SDATA_IN Wake Up Signaling..............................................................................................13-13

13-9 PCM Transmit and Receive Operation..................................................................................13-27

13-10 Mic-in Receive-Only Operation..............................................................................................13-29

13-11 Modem Transmit and Receive Operation ..............................................................................13-32

14-1 I2S Data Formats (16 bits).......................................................................................................14-7

14-2 MSB-Justified Data Formats (16 bits .......................................................................................14-7

14-3 Transmit and Receive FIFO Accesses Through the SADR...................................................14-15

15-1 MMC System Interaction.........................................................................................................15-1

15-2 MMC Mode Operation Without Data Token.............................................................................15-3

15-3 MMC Mode Operation With Data Token..................................................................................15-3

15-4 SPI Mode Operation Without Data Token...............................................................................15-4

15-5 SPI Mode Read Operation.......................................................................................................15-4

15-6 SPI Mode Write Operation .......................................................................................................15-4

16-1 Texas Instruments Synchronous Serial Frame* Protocol (multiple transfers).........................16-5

16-2 Texas Instruments Synchronous Serial Frame* Protocol (single transfers)............................16-6

16-3 Motorola SPI* F rame Protocol (multiple transfers)..................................................................16-7

16-4 Motorola SPI* F rame Protocol (single transfers).....................................................................16-7

16-5 Mot orola SPI* Frame Protocols for SPO and SPH Program ming (multiple

transfers)..................................................................................................................................16-8

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16-6 Moto rola SPI* Frame P rotocols for SP O and SPH Progr am ming (single

transfers).................................................................................................................................16-9

16-7 National Semiconductor Microwire* Frame Protocol (multiple transfers)..............................16-10

16-8 National Semiconductor Microwire* Frame Protocol (single transfers).................................16-10

16-9 Programmable Serial Protocol (multiple transfers)................................................................16-11

16-10 Programmable Serial Protocol (single transfers)...................................................................16-12

16-11 TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=0.................................................................16-13

16-12 TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=1.................................................................16-14

16-13 Motorola SPI with SSCR[TTE]=1...........................................................................................16-14

16-14 National Semiconductor Microwire with SSCR1[TTE]=1.......................................................16-15

16-15 PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (slave to frame).............................16-15

16-16 PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (master to frame)..........................16-16

16-17 PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=1 (must be slave to

frame)....................................................................................................................................16-16

17-1 Example UART Data Frame....................................................................................................17-3

17-2 Example NRZ Bit Encoding – (0b0100 1011...........................................................................17-4

17-3 IR Transmit and Receiv e Example..........................................................................................17-9

17-4 XMODE Example. ...................................................................................................................17-9

Tables

2-1 CPU Core Fault Register Bit Definitions....................................................................................2-3

2-2 ID Bit Definiti o ns............ ........................... .................................................................................2-4

2-3 PXA255 Processor ID Value s......... ......................................................................... ..................2-4

2-4 Effect of Each Type of Reset on Internal Register State...........................................................2-6

2-5 Processor Pin Types .................................................................................................................2-8

2-6 Pin & Signal Descriptions for the PXA255 Processor................................................................2-9

2-7 Pin Description Notes..............................................................................................................2-17

2-8 System Archite cture Register Address Summary ...................................................................2-21

3-1 Core PLL Output Frequencies for 3.6864 MHz Crystal.............................................................3-5

3-2 95.85 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal..................................3-5

3-3 147.46 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal................................3-6

3-4 Power Mode En try Sequence Table .......................................................................................3-20

3-5 Power Mode Exit Sequence Table.........................................................................................3-20

3-6 Power and Clock Supply Sources and States During Power Modes .....................................3-22

3-7 PMCR Bit Definitions...............................................................................................................3-23

3-8 PCFR Bit Definitions................................................................................................................3-24

3-9 PWER Bit Definitions...............................................................................................................3-25

3-10 PRER Bit Definitions................................................................................................................3-26

3-11 PFER Bit Definit ion s.................................... ............................................................................3-27

3-12 PEDR Bit Definitions................................................................................................................3-28

3-13 PSSR Bit Definitions................................................................................................................3-29

3-14 PSPR Bit Definitions................................................................................................................3-30

3-15 PMFW Register Bitmap and Bit Definitions.............................................................................3-31

3-16 PGSR0 Bit Definitions.............................................................................................................3-32

3-17 PGSR1 Bit Definitions.............................................................................................................3-32

3-18 PGSR2 Bit Definitions.............................................................................................................3-33

3-19 RCSR Bit Definitions ...............................................................................................................3-34

3-20 CCCR Bit Definitions ........ .......................................................................................................3-35

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3-21 CKEN Bit Definition s............. ......................................................................... ..........................3-36

3-22 OSCC Bit Definitions...............................................................................................................3-38

3-23 Coprocessor 14 Clock and Power Management Summary.....................................................3-39

3-24 CCLKCFG Bit Definitions.........................................................................................................3-39

3-25 PWRMODE Bit Defini tio ns. .................................................. ................................................. ...3-40

3-26 Clocks Manager Re gis ter Summary......... ......................................................................... ......3-41

3-27 Power Manager Regis te r Summary... .... ......................................................................... .........3-42

4-1 GPIO Alternate Functions..........................................................................................................4-3

4-2 GPIO Register Definitions..........................................................................................................4-6

4-3 GPLR0 Bit Definitions................................................................................................................4-7

4-4 GPLR1 Bit Definitions................................................................................................................4-8

4-5 GPLR2 Bit Definitions................................................................................................................4-8

4-6 GPDR0 Bit Definiti o ns........................................ .......................................................................4-9

4-7 GPDR1 Bit Definiti o ns........................................ .......................................................................4-9

4-8 GPDR2 Bit Definiti o ns........................................ .......................................................................4-9

4-9 GPSR0 Bit Definitions................................................... .................................................. .........4-10

4-10 GPSR1 Bit Definiti ons.... .................................................. ........................................................4-10

4-11 GPSR2 Bit Definiti ons.... .................................................. ........................................................4-11

4-12 GPCR0 Bit Defini tio ns............. .... ......................................................................... ...................4-11

4-13 GPCR1 Bit Defini tio ns............. .... ......................................................................... ...................4-11

4-14 GPCR2 Bit Defini tio ns............. .... ......................................................................... ...................4-12

4-15 GRER0 Bit Definiti o ns........................................ .....................................................................4-13

4-16 GRER1 Bit Definiti o ns........................................ .....................................................................4-13

4-17 GRER2 Bit Definiti o ns........................................ .....................................................................4-13

4-18 GFER0 Bit Definitions..............................................................................................................4-14

4-19 GFER1 Bit Definitions..............................................................................................................4-14

4-20 GFER2 Bit Definitions..............................................................................................................4-14

4-21 GEDR0 Bit Defini tio ns............. .... ......................................................................... ...................4-15

4-22 GEDR1 Bit Defini tio ns............. .... ......................................................................... ...................4-15

4-23 GEDR2 Bit Defini tio ns............. .... ......................................................................... ...................4-16

4-24 GAFR0_L Bit De finitions ..........................................................................................................4-17

4-25 GAFR0_U Bit Definitions.........................................................................................................4-17

4-26 GAFR1_L Bit De finitions ..........................................................................................................4-18

4-27 GAFR1_U Bit Definitions.........................................................................................................4-18

4-28 GAFR2_L Bit De finitions ..........................................................................................................4-19

4-29 GAFR2_U Bit Definitions.........................................................................................................4-19

4-30 ICMR Bit Definition s........................ .................................................. .......................................4-22

4-31 ICLR Bit Definitions..................................................................................................................4-23

4-32 ICCR Bit Definitions.................................................................................................................4-23

4-33 ICIP Bit Definiti o ns............. ... ......................................................................... ..........................4-24

4-34 ICFP Bit Definitions..................................................................................................................4-24

4-35 ICPR Bit Definitions.................................................................................................................4-25

4-36 List of First–Level Interrupts....................................................................................................4-27

4-37 RTTR Bit Definitions................................................................................................................4-30

4-38 RTAR Bit Definitions ................................................................................................................4-30

4-39 RCNR Bit Definitions...............................................................................................................4-31

4-40 RTSR Bit Definitions ................................................................................................................4-32

4-41 OSMR[x] Bit Defini ti ons................................................................. ..........................................4-36

4-42 OIER Bit Definitions.................................................................................................................4-36

4-43 OWER Bit Definitions...............................................................................................................4-37

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4-44 OSCR Bit Definit i ons.................. .... ......................................................................... ................4-37

4-45 OSSR Bit De finitions ...............................................................................................................4-38

4-46 PWM_CTRLn Bit Definitions ...................................................................................................4-41

4-47 PWM_DUTYn Bit Defi nit i ons............................................................ .......................................4-42

4-48 PWM_PERVALn Bit Definitions...............................................................................................4-43

4-49 GPIO Registe r Addr ess es.................... .................................................. .................................4-44

4-50 Interrupt Controller Register Addresses..................................................................................4-45

4-51 RTC Registe r Addre ss es................ .........................................................................................4-45

4-52 OS Timer Register Addresses.................................................................................................4-45

4-53 Pulse Width Modulator Register Addresses............................................................................4-46

5-1 DMAC Signal List ......................................................................................................................5-2

5-2 Channel Priority (if all channels a re running concurrently)........................................................5-4

5-3 Channel Priority.........................................................................................................................5-4

5-4 Priority Sch emes Exa mple s................................ .......................................................................5-5

5-5 DMA Quick Reference for Inter n al Peri p hera ls.................. ........................... ..........................5-13

5-6 DINT Bit Definitions.................................................................................................................5 -17

5-7 DCSRx Bit Defin iti o ns.... ... .......................................................................... .............................5-18

5-8 DRCMRx Bit Definitions..........................................................................................................5-20

5-9 DDADRx Bit Definitions...........................................................................................................5-21

5-10 DSADRx Bit Definitions...........................................................................................................5-22

5-11 DTADRx Bit Defi nit i ons.................. .................................................. .......................................5-23

5-12 DCMDx Bit Definitions.................................................................. ...........................................5-24

5-13 DMA Controller Register Summary.........................................................................................5-28

6-1 Device Transactions..................................................................................................................6-7

6-2 MDCNFG Bit Defin i tio ns................. ......................................................................... ..................6-9

6-3 MDMRS Bit Definitions............................................................................................................6-12

6-4 MDMRSLP Register Bit Definitions.........................................................................................6-14

6-5 MDREFR Bit Definitions..........................................................................................................6-15

6-6 Sample SDRAM Memory Size Options...................................................................................6-18

6-7 External to Internal Address Mapping for Normal Bank Addressing.......................................6-19

6-8 External to Internal Address Mapping fo r SA-1111 Addressing..............................................6-21

6-9 Pin Mapping to SDRAM Devices with Normal Bank Addressing.............................................6-23

6-10 Pin Mapping to SDRAM Devices with SA1 111 Addressing.....................................................6 -25

6-11 SDRAM Command Encoding..................................................................................................6 -28

6-12 SDRAM Mode Register Opcode Table....................................................................................6 -28

6-13 SXCNFG Bit Definit i ons............................... ............................................................................6-33

6-14 SXCNFG..................................................................................................................................6-36

6-15 Synchronous Static Memory External to Internal Address Mapping Options..........................6-37

6-16 SXMRS Bit Defini tio ns................ ........................... ..................................................................6-38

6-17 Read Configuration Register Programming Values.................................................................6-40

6-18 Frequenc y Code Co nf igu rati o n Values Bas ed on Clo ck Sp eed..............................................6-40

6-20 16-Bit Bus Write Access..........................................................................................................6-44

6-19 32-Bit Bus Write Access..........................................................................................................6-44

6-21 MSC0/1/2 Bit Definitions..........................................................................................................6-45

6-22 Asynchronous Static Memory and Variable Latency I/O Capabilities......................................6 -48

6-23 MCMEM0/1 Bit Definitions.......................................................................................................6-58

6-24 MCATT0/1 Bit Defi n iti o ns................................... .....................................................................6-59

6-25 MCIO0/1 Bit Definition s ...........................................................................................................6-59

6-26 Card Inter fa ce Comman d Asser ti o n Code Table.....................................................................6-60

6-27 MECR Bit Definition.................................................................................................................6-61

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6-28 Common Memory Space Write Commands............................................ .......................... ......6-63

6-29 Common Memory Space Read Commands.......... .... .................................................. ............6-63

6-30 Attribute Memory Space Write Commands .............................................................................6-63

6-31 Attribute Memory Space Read Commands.............................................................................6-63

6-32 16-Bit I/O Sp ace Write Commands (nIOIS16 = 0)...................................................................6-63

6-33 16-Bit I/O Space Read Commands (nIOIS16 = 0)...................................................................6-63

6-34 8-Bit I/O Space Write Commands (nIOIS16 = 1) .....................................................................6-64

6-35 8-Bit I/O Space Read Commands (nIOIS16 = 1).....................................................................6-64

6-36 BOOT_SEL Definitions............................................................................................................6-72

6-37 BOOT_DEF Bitmap.................................................................................................................6-73

6-38 Valid Boot Configurations Based on Processor Type..............................................................6-73

6-39 Memory Controller Pin Reset Values.......................................................................................6-77

6-40 Memory Controller Register Summary ....................................................................................6-79

7-1 Pin Descriptions.........................................................................................................................7-4

7-2 LCD Controller Data Pin Utilization..........................................................................................7-21

7-3 LCCR0 Bit Definitions ..............................................................................................................7-23

7-4 LCCR1 Bit Definitions ..............................................................................................................7-26

7-5 LCCR2 Bit Definitions ..............................................................................................................7-28

7-6 LCCR3 Bit Definitions ..............................................................................................................7-31

7-7 FDADRx Bit Definitions............................................................................................................7-33

7-8 FSADRx Bit Definitions............................................................................................................7-34

7-9 FIDRx Bit Definitions................................................................................................................7-34

7-10 LDCMDx Bit Defini ti o ns.................. ......................................................................... ................7-36

7-11 FBRx Bit Definitions.................................................................................................................7-37

7-12 LCSR Bit Definitions................................................................................................................7-40

7-13 LIICR Bit Definit i ons............................................... ..................................................................7-41

7-14 TRGBR Bit Definitions.............................................................................................................7-42

7-15 TCR Bit Definitions..................................................................................................................7-44

7-16 LCD Controlle r Regis te r Summary................................................................ ..........................7-44

8-1 External Interface to Codec.......................................................................................................8-1

8-2 SSCR0 Bit Definitions................................................................................................................8 -9

8-3 SSCR1 Bit Definitions..............................................................................................................8-11

8-4 TFT and RFT Values for DMA Servicing.................................................................................8-15

8-5 SSDR Bit Definiti ons.................................... ............................................................................8-15

8-6 SSSR Bit Definitions................................................................................................................8-17

8-7 SSP Controller Register Summary..........................................................................................8-19

9-1 I2C Signal Description...............................................................................................................9-1

9-2 I2C Bus Definitions.............. .................................................. ...................................................9-2

9-3 Modes of Operation.............. ........................... .................................................. ........................9-3

9-4 START and STOP Bit Definitions..............................................................................................9-4

9-5 Master Transactions................................................................................................................9-12

9-6 Slave Transactions..................................................................................................................9-15

9-7 General Call Ad dress Second Byte Definitions .......................................................................9-17

9-8 IBMR Bit Definitions............. ... .................................................. ..............................................9-22

9-9 IDBR Bit Definitions................................................................................................................9-23

9-10 ICR Bit Definitions... ................................................................................................ ................9-23

9-11 ISR Bit Definitio ns............. ... ......................................................................... ..........................9-26

9-12 ISAR Bit Definitions...................................................................................... ..........................9-27

10-1 UART Signal Descriptions....................................................................................................... 10-3

10-2 UART Registe r Addresses as Offsets of a Base.....................................................................10-6

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10-3 RBR Bit Definitions..................................................................................................................1 0-6

10-4 THR Bit Defin iti o ns..................................................................................................................1 0-7

10-5 DLL Bit Definit ion s........................................................... ........................................................10-8

10-6 DLH Bit Definitions..................................................................................................................10-8

10-7 IER Bit Definitions....................................................................................................................10-9

10-8 Interrupt Conditions...............................................................................................................10-10

10-9 IIR Bit Definitions...................................................................................................................10-10

10-10 Interrupt Identification Register Decode................................................................................10-11

10-11 FCR Bit Defin iti o ns..................... ...........................................................................................10-12

10-12 LCR Bit Definitions ................................................................................................................10-14

10-13 LSR Bit Definitions................................................................................................................. 10-15

10-14 MCR Bit Definitions............................................................................................................... 10-18

10-15 MSR Bit Definit ion s........ ........................... .............................................................................10-20

10-16 SPR Bit Definiti ons........................................................................................... .....................10-21

10-17 ISR Bit Definitions..................................................................................................................10-24

10-18 FFUART Regis te r Summary.... ........................... ...................................................................10-26

10-19 BTUART Register Summary.................................................................................................10-26

10-20 STUART Register Summary.................................................................................................10-27

10-21 Flow Control Registers in BTUART and STUART........ ... ......................................................10-28

11-1 FICP Signal Desc rip tio n................. ... .................................................. .................................... 1 1-1

11-2 ICCR0 Bit Definitions...............................................................................................................11-8

11-3 ICCR1 Bit Definitions.............................................................................................................11-10

11-4 ICCR2 Bit Definitions.............................................................................................................11-11

11-5 ICRD Bit Definit i ons........................................ .......................................................................11-12

11-6 ICSR0 Bit Definitions.............................................................................................................11-13

11-7 ICSR1 Bit Definitions.............................................................................................................11-15

11-8 FICP Registe r Summary....... .................................................. ...............................................11-16

12-1 Endpoint Co nfig u rati o n............ ......................................................................... .......................12-2

12-2 USB States............. .................................................. ...............................................................12-3

12-3 IN, OUT, and SETUP Token Packet F orm at............ ........................... ....................................12-5

12-4 SOF Token Packet Form at................ ... .......................................................................... .........12-5

12-5 Data Packet Format.................................................................................................................1 2-6

12-6 Handshak e Packe t Forma t................................................................................... ...................12-6

12-7 Bulk Transaction Formats........................................................................................................12-7

12-8 Isochron ous Tra ns ac ti o n Formats.................................................................................. .........12-7

12-9 Control Transaction Formats...................................................................................................12-7

12-10 Interrupt Transaction Formats.................................................................................................12-8

12-11 Host Device Request Summary ..............................................................................................12-9

12-12 UDCCR Bit Definitions...........................................................................................................12-22

12-13 UDC Control Function Register.............................................................................................12-24

12-14 UDCCS0 Bit Definitions.........................................................................................................12-25

12-15 UDCCS1/6/11 Bit Definitions.................................................................................................12-27

12-16 UDCCS2/7/12 Bit Definitions.................................................................................................12-29

12-17 UDCCS3/8/13 Bit Definitions.................................................................................................12-31

12-18 UDCCS4/9/14 Bit Definitions.................................................................................................12-33

12-19 UDCCS5/10/15 Bit Definitions...............................................................................................12-34

12-20 UICR0 Bit Definitions.............................................................................................................12-37

12-21 UICR1 Bit Definitions.............................................................................................................12-38

12-22 USIR0 Bit Definitions.............................................................................................................12-39

12-23 USIR1 Bit Definitions.............................................................................................................12-41

xx Intel® PXA255 Processor Developer’s Manual

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12-24 UFNHR Bit Definitions...........................................................................................................12-43

12-25 UFNLR Bit Definitions............................................................................................................12-44

12-26 UBCR2/4/7/9/12/14 Bit Definitions.........................................................................................12-45

12-27 UDDR0 Bit Definitions ...........................................................................................................12-46

12-28 UDDR1/6/11 Bit Definitions ...................................................................................................12-46

12-29 UDDR2/7/12 Bit Definitions ...................................................................................................12-47

12-30 UDDR3/8/13 Bit Definitions ...................................................................................................12-47

12-31 UDDR4/9/14 Bit Definitions ...................................................................................................12-48

12-32 UDDR5/10/15 Bit Definitions.................................................................................................12-48

12-33 USB Device Controller Register Summary............................................................................1 2-48

13-1 External Interface to CODECs.................................................................................................13-2

13-2 Supported Data Stream Formats.............................................................................................13-3

13-3 Slot 1 Bit Definition s. .................................................. ..............................................................13-7

13-4 Slot 2 Bit Definition s. .................................................. ..............................................................13-7

13-5 Input Slot 1 Bit Definitions......................................................................................................13-10

13-6 Input Slot 2 Bit Definitions......................................................................................................13-11

13-7 GCR Bit Definitions................................................................................................................13-20

13-8 GSR Bit Definiti o ns........ ........................... .............................................................................13-22

13-9 POCR Bit Definitions.............................................................................................................13-23

13-10 PICR Bit Definitions...............................................................................................................13-24

13-11 POSR Bit Definitions..............................................................................................................13-25

13-12 PISR Bit Definit ion s........... ... ......................................................................... ........................13-25

13-13 CAR Bit Definition s................................................................. ...............................................13-26

13-14 PCDR Bit Definitions..............................................................................................................13-26

13-15 MCCR Bit Defini tio ns...................... .......................................................................................13-27

13-16 MCSR Bit Definitions.............................................................................................................13-28

13-17 MCDR Bit Defini tio ns...................... .......................................................................................13-28

13-18 MOCR Bit Definitions.............................................................................................................13-29

13-19 MICR Bit Definit ion s. ................................................................................................ ..............13-30

13-20 MOSR Bit Definiti o ns......... ......................................................................... ...........................13-30

13-21 MISR Bit Definitions...............................................................................................................1 3-31

13-22 MODR Bit Definitions.............................................................................................................13-31

13-23 Address Mapping for CODEC Registers...............................................................................13-33

13-24 Register Mapping Summary..................................................................................................13-35

14-1 External Interface to CODEC...................................................................................................14-2

14-2 Supported Sampling Frequencies ...........................................................................................14-6

14-3 SACR0 Bit Definitions..............................................................................................................14-9

14-4 FIFO Write/Read table...........................................................................................................14-10

14-5 TFTH and RFTH Values for DMA Servicing..........................................................................14-10

14-6 SACR1 Bit Definitions............................................................................................................14-11

14-7 SASR0 Bit Definitions............................................................................................................14-12

14-8 SADIV Bit Definiti ons..................................................................... ........................................14-13

14-9 SAICR Bit Definitions.............................................................................................................14-13

14-10 SAIMR Bit Descriptions.........................................................................................................14-14

14-11 SADR Bit Descript i ons............. ..............................................................................................14-14

14-12 Register Memory Map ...........................................................................................................14-16

15-1 Command Token Format.........................................................................................................15-2

15-2 MMC Data Token Format........................................................................................................15-2

15-3 SPI Data Token Format...........................................................................................................15-2

15-4 MMC Signal Description..........................................................................................................15-6

Intel® PXA255 Processor Developer’s Manual xxi

15-5 MMC_STRPCL Bit Defi nit i ons.................. ......................................................................... ....15-23

15-6 MMC_STAT Bit Definitions....................................................................................................15-23

15-7 MMC_CLK Bit Definitions......................................................................................................15-25

15-8 MMC_SPI Bit De finitions .......................................................................................................15-25

15-9 MMC_CMDAT Bit Defi n itions......................................................................................... .......15-26

15-10 MMC_RESTO Bit Definitions.................................................................................................15-27

15-11 MMC_RDTO Register ...........................................................................................................15-28

15-12 MMC_BLKLEN Bit Definition s ...............................................................................................15-29

15-13 MMC_NOB Bit Definitions.....................................................................................................15-29

15-14 MMC_PRTBUF Bit Definitions...............................................................................................15-30

15-15 MMC_I_MASK Bit Definitions................................................................................................15-30

15-16 MMC_I_REG Bit Definitions.................................................................................................. 15-32

15-17 MMC_CMD Registe r.................. .................................................. .........................................15-33

15-18 Command Index Values.................... .................................................. ..................................15-33

15-19 MMC_ARGH Bit Def init i ons.............................................................................. .....................15-35

15-20 MMC_ARGL Bit Defi n iti o ns.......................................................... .........................................15-35

15-21 MMC_RES, FIFO Entry.........................................................................................................15-36

15-22 MMC_RXFIFO, FIF O Entry...................... .................................................. ...........................15-36

15-23 MMC_TXFIFO, FIFO Entry....................................................................................................15-37

15-24 MMC Controller Registers.....................................................................................................15-37

16-1 SSP Serial Port I/O Signals............ .......................... .................................................. .............1 6-2

16-2 Programmable Serial Protocol (PSP) Parameters ................................................................16-12

16-3 SSCR0 Bit Defini ti ons.......................................................................... ..................................16-19

16-4 SSCR1 Bit Defini ti ons.......................................................................... ..................................16-21

16-5 SSPSP Bit Definition s.... ........................... .............................................................................16-23

16-6 SSTO Bit Definitions..............................................................................................................16-24

16-7 SSITR Bit Definitions.............................................................................................................16-25

16-8 SSSR Bit Definitions..............................................................................................................16-26

16-9 SSDR Bit Definitions..............................................................................................................16-29

16-10 NSSP Register Address Map ................................................................................................16-29

17-1 UART Signal Descriptions.......................................................................................................17-3

17-2 RBR Bit Definitions................................................................................................................17-10

17-3 THR Bit Defin iti o ns................................................................................................................17-10

17-4 DLL Bit Definit ion s........................................................... ......................................................17-11

17-5 Divisor Latch Register High (DLH) Bit Definitions .................................................................17-11

17-6 IER Bit Definitions..................................................................................................................17-12

17-7 Interrupt Conditions...............................................................................................................17-13

17-8 IIR Bit Definitions...................................................................................................................17-13

17-9 Interrupt Identification Register Decode................................................................................17-14

17-10 FCR Bit Defin iti o ns..................... ...........................................................................................17-15

17-11 FOR Bit Definitions................................................................................................................17-16

17-12 ABR Bit Definiti ons........................................................................................... .....................17-17

17-13 ACR Bit Definitions................................................................................................................17-18

17-14 LCR Bit Definitions ................................................................................................................17-18

17-15 LSR Bit Definitions................................................................................................................. 17-20

17-16 MCR Bit Definitions............................................................................................................... 17-22

17-17 MSR Bit Definit ion s........ ........................... .............................................................................17-23

17-18 SCR Bit Definitions................................................................................................................17-24

17-19 ISR Bit Definitions..................................................................................................................17-25

17-20 HWUART Registe r Loca ti o ns............ .................................................. ..................................17-25

Contents

Intel® PXA255 Processor Developer’s Manual xxiii

Contents

Revision History

Date Revision Description

March 2003 -001 Initial release

xxiv Intel® PXA255 Processor Developer’s Manual

Introduction 1

This document applies to the Intel® PXA255 Processor (PXA255 pro ces sor). It is an application specific standard product (ASSP) that provides i ndustry-leading MIPS/mW performance for handheld computing appli cations. The processor is a highly integrated system on a chip and includes a high-performance low-power Intel® XS cale™ microarchitecture with a variety of different system peripherals.

The PXA255 proc esso r is a 17x17mm 256-pin PBG A package config uration fo r high per forma nce. The 17x17m m package has a 32-bit memory da ta bus and the full assortment of peripherals.

1.1 Intel® XScale™ Microarchitecture Features

The Intel® XScale™ microarchitecture provides these f eatures:

• ARM* Architecture Version 5TE ISA compliant.

— ARM* Thumb Instruction S upport — ARM* DSP Enhance d Instructions

• Low power cons umption and high performance

• Intel® Media Processing Technology

— Enhanced 16-bit Multiply — 40-bit Accumulator

• 32-KByte Instruction Cache

• 32-KByte Data Cache

• 2-KByte Mini Data Cache

• 2-KByte Mini Instruction Cache

• Instruction and Data Memor y Ma nagement Units

• Branch T arget Buffer

• Debug Capability via JTAG Port

Refer to the Int e l® XScale™ Micr oarchitecture for the Intel® PXA255 Processor User’s Manual for more detai l s.

1.2 System Integration Features

The processor integrat es the In tel® XScale™ microarchitectur e with this peripheral set:

• Memory Controller

• Clock and Power Controllers

• Universal Serial Bus Client

Intel® PXA255 Processor Developer’s Manual 1-1

Introduction

• DMA Controller

• LCD Controller

• AC97

• I

• MultiMediaCard

• FIR Communication

• Synchronous Serial Pro t oc ol Port

• I

• General Purp ose I/O pins

• UARTs

• Real-Time Clock

• OS Timers

• Pulse Width Modulation

• Interru p t C on t ro l

1.2.1 Memory Controller

The Memory Con troller provides glueless control s i gnals with programmable tim ing for a wide assortment of mem ory-chip types and organizations. It supports up to four S DRAM partitions; six static chip s elects for SRA M, S SRAM, F lash , ROM , SROM, and compa nion chip s; su pport for two PCMCIA o r Compa ct Flas h slots

1.2.2 Clocks and Power Controllers

The processor functional blocks are dr iven by clocks that are deri ve d from a 3.6864-MHz crystal and an optional 32.768-kHz crystal.

The 3.6864-MHz crystal drives a core Phase Lock ed Loo p ( PLL) and a Per iph eral PLL. The PLLs produce selec t ed clock frequencies to run particular functional blocks.

The 32.768-kHz crystal provides an optional clock source that must be selected after a hard reset. This clock drive s the Real Time Clock (RTC), Power Management Controller, and Interrupt Controller. The 32.768-kHz crystal is on a separate power island to provide an active clock while the processor is in s leep mode.

Power management controls the transition between the turbo/run, idle, and sleep operating m ode s.

1.2.3 Unive rsal Serial Bus (USB) Client

The USB Client Module is bas ed on the Universal Serial Bus Specification, Revisio n 1.1. It supports up to s ixteen endpoints and it provides an interna lly generated 48-MHz clock. The USB Device Controller provides FIFOs with DMA access to or from memory.

1-2 Intel® PXA255 Process or Developer’s Manual

1.2.4 DMA Controller (DMAC)

The DMAC provide s sixteen prioritized channels to service transfer requests from internal peripherals and up to two dat a transfer requests from external companion chips. The DMAC is descriptor-based to allow comma nd c haining and looping constructs.

The DMAC op e ra t e s in Fl ow-Throu gh Mo de wh e n pe rf orming peri p he r a l- to -memory, memory- to peripheral, and memory- to- memory transfers. The DMAC is compatibl e with peripherals that use word, half-word, or byte data sizes.

1.2.5 LCD Controller

The LCD Controller supports both passi ve (DSTN) and active (TFT) flat-panel displays with a maximum supported resolution of 640 x480x16-bit/pixel. An internal 256 entry palette expa nds 1, 2, 4, or 8-bit encoded pixels. Non-encoded 16-bit pixels bypass the palette.

Two dedicated DMA channels a l low the LCD Controller to support single- and dual-panel displays . P a ssive monochrome mode supp orts up to 256 gra y-scale levels and passive color mode supports up to 64K colors. Active color mode supports up to 64K colors.

1.2.6 AC97 Controller

Introduction

The AC97 Controller supports AC97 Revision 2.0 CODECs. These CODECs can operate at sample rates up to 48 KHz. The controller provid es independent 16-bit channels for Stereo PCM In, Stereo PCM Out, Modem In , Mod em Out, and mono Microphone In. Each channel includes a FIFO that supports DMA access to memory.

1.2.7 Inter-IC Sound (I2S) Controller

The I2S Controller provides a serial link to standard I2S CODECs for digital stereo sound. It supports both the Normal-I connectio n to a n I The controller includes FIFOs that support DMA access to memory.

S CODEC. I2S Controller signals are multiplexed with AC97 Controller pins.

S and MSB-Justif ied I2S formats, and provides four signals for

1.2.8 Multimedia Card (MMC) Controller

The MMC Controller provide s a serial i nterface to sta ndard me mory cards . The controller suppor ts up to two cards in e ither MMC or SPI modes with serial da ta transfers up to 20 Mbps. Th e MMC controller has FIFOs that support DMA access to and from memory.

1.2.9 Fast Infrared (FIR) Communication Port

The FIR Com munication Port is based on the 4-Mbps Infrared Data Association (IrDA) Specification. It operates at half-duplex and has FIFOs with DMA access to memory. The FIR Communication Port uses the STUART’s transmit and receive pins to directly connect to external IrDA LED transceivers.

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Introduction

1.2.10 Synchronous Serial Protocol Controller (SSPC)

The SSP Port provides a full-duplex synchronous serial interface th at operates at bit rates from

7.2 kHz to 1.84 MHz. It supports National Semico nductor’s Microwire*, Texas Instruments’ Synchronous Serial Protocol*, and Motorola’s Serial Peripheral Interface*. The SSPC has FI FO s with DMA access to memory.

1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit

The I2C Bus Interface Unit provides a general purpose 2-pin serial communication port.The interface uses one pin for data and address and a second pin for clocking.

1.2.12 GPIO

Each GPIO pin can be individually programmed as an output or an input. Inputs can cau se interrupts on rising or falling edge s. Primary GPIO pins are not shared with peripherals while secondary GPIO pins have alternate functions which can be mapped to the peripherals.

1.2.13 UARTs

The processor provides three Univers al Asynchronous Receiver/Transmitters. Each UART can be used as a slow infrared (SIR) transmitter/receiver based on the Infrared Data Associatio n Serial Infrar ed (SIR) Physical Layer Link Specification.

1.2.13.1 Full Function UART (FFUART)

The FFUART baud rate is pr og ramm abl e up to 2 30 Kbps. The FFUART provides a c omp lete se t of modem control pins: nCTS, nRTS, nDSR, nDTR, nRI, and nDCD. It has FIFOs with DMA access to or from memory.

1.2.13.2 Bluetooth UART (BTUART)

The BTUART baud rate is programma ble up to 921 Kbps. The BTUART provide s a partial set of modem control pins: nCTS and nRTS. Other modem control pi ns can be implemented via GPIOs. The BTUART has FIFOs wi th DMA access to or from memory .

1.2.13.3 Standard UART (STUART)

The STUART baud rate is pr og rammab le up to 230 Kbps. The S TUART does not prov ide any modem control pins. The mode m control pins can be impleme nted via GPIOs. The STUART has FIFOs wit h DM A a c ces s to or from memory.

The STUART’s transmit and receive pins are multipl exed with the Fast Infrared Communication Port.

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1.2.13.4 Hardware UART (HWUART)

The PXA255 processor has a UART with hardware flow control. The HWUART provides a partial set of modem contr ol pins: nCTS and nRTS. These modem control pi ns pr ovi de full hardwar e f low control. Other modem control pins can be implemented via GPIOs. The HWUART baud rate is programmable up to 921.6 Kbps.

The HWUART’ s pins are multiplexed with the PCMCIA contr ol pins. Because of this, these HWUART pins operate at the same voltage as the memory bus. Also, since the PCMCIA pin nPWE is used for variable-latency input/output (VLIO), while using these pins for the HWUAR T, VLIO is unavailabl e. The HWUART pins are also available over the BTUART pins. When operating over the BTUART pins, the HWUART pins operate at the I/O voltage.

1.2.14 Real-Time Clock (RTC)

The Real-Time Clock can be clocked from either crys tal. A system with a 32.768-KHz cry st al consumes le ss p owe r d ur ing Sl eep v ers u s a s ystem usi ng o nly th e 3.68 64- MHz crys tal. Th is cr ysta l can be remov e d to save syst e m cost. The RTC provides a consta nt frequenc y output with a programmable alarm regis ter. This alarm register can be used t o wake up the processor from Sleep mode.

Introduction

1.2.15 OS Timers

The OS Timers can be used to prov ide a 3.68-MHz reference counter with four match registers. These registers can be config ured to cause interrupts when equal to th e ref erence counter. One match register can be used to cause a watch dog reset.

1.2.16 Pulse-Width Modulator (PWM)

The PWM has two independent outputs that can be progra mmed to drive two GPIOs. The frequency and duty cycle are ind ependently programmable. For example, one GPIO can control LCD contrast and the other LCD brigh t ne ss.

1.2.17 Interrupt Control

The Interrupt Controller directs the processor interrupts into the core’s IRQ and FIQ inputs . The Mask Register enables or dis a bles individual interrupt sources.

1.2.18 Network Synchronous Serial Protocol Port

The PXA2 5 5 pr oc e s so r ha s a n SSP port optim iz e d f or con n e c ti o n to ot he r ne t work ASICs . T hi s NSSP adds a Hi-Z function to TXD, the ability to control when Hi-Z occur s, and swapping the TXD/RXD pins.

This port is not multiplexed with other interfaces.

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Introduction

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