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Added note to Table 3-1 about supported frequencies
Explained RDY_sync signal
Correct GPIO numbers in Table 4-35
Changed behavior of GPIO pins out of reset
Added Polling directions for I2C
Intel® PXA255 Processor Developer’s Manualxxiii
Contents
xxivIntel® PXA255 Processor Developer’s Manual
Introduction1
This document applies to the Intel® PXA255 Processor (PXA255 processor). It is an application
specific standard product (ASSP) that provides industry-leading MIPS/mW performance for
handheld computing applications. The processor is a highly integrated system on a chip and
includes a high-performance low-power Intel XScale® microarchitecture with a variety of
different system peripherals.
The PXA255 processor is a 17x17mm 256-pin PBGA package configuration for high performance.
The 17x17mm package has a 32-bit memory data bus and the full assortment of peripherals.
1.1Intel XScale® Microarchitecture Features
The Intel XScale® microarchitecture provides these features:
• ARM* Architecture Version 5TE ISA compliant.
— ARM* Thumb Instruction Support
— ARM* DSP Enhanced Instructions
• Low power consumption and high performance
• Intel® Media Processing Technology
— Enhanced 16-bit Multiply
— 40-bit Accumulator
• 32-KByte Instruction Cache
• 32-KByte Data Cache
• 2-KByte Mini Data Cache
• 2-KByte Mini Instruction Cache
• Instruction and Data Memory Management Units
• Branch Target Buffer
• Debug Capability via JTAG Port
Refer to the Intel XScale® Microarchitecture for the Intel® PXA255 Processor User’s Manual for
more details.
1.2System Integration Features
The processor integrates the Intel XScale® microarchitecture with this peripheral set:
• Memory Controller
• Clock and Power Controllers
• Universal Serial Bus Client
Intel® PXA255 Processor Developer’s Manual1-1
Introduction
• DMA Controller
• LCD Controller
• AC97
2
• I
S
• MultiMediaCard
• FIR Communication
• Synchronous Serial Protocol Port
2
• I
C
• General Purpose I/O pins
• UARTs
• Real-Time Clock
• OS Timers
• Pulse Width Modulation
• Interrupt Control
1.2.1Memory Controller
The Memory Controller provides glueless control signals with programmable timing for a wide
assortment of memory-chip types and organizations. It supports up to four SDRAM partitions; six
static chip selects for SRAM, SSRAM, Flash, ROM, SROM, and companion chips; support for two
PCMCIA or Compact Flash slots
1.2.2Clocks and Power Controllers
The processor functional blocks are driven by clocks that are derived from a 3.6864-MHz crystal
and an optional 32.768-kHz crystal.
The 3.6864-MHz crystal drives a core Phase Locked Loop (PLL) and a Peripheral PLL. The PLLs
produce selected clock frequencies to run particular functional blocks.
The 32.768-kHz crystal provides an optional clock source that must be selected after a hard reset.
This clock drives the Real Time Clock (RTC), Power Management Controller, and Interrupt
Controller. The 32.768-kHz crystal is on a separate power island to provide an active clock while
the processor is in sleep mode.
Power management controls the transition between the turbo/run, idle, and sleep operating modes.
1.2.3Universal Serial Bus (USB) Client
The USB Client Module is based on the Universal Serial Bus Specification, Revision 1.1. It
supports up to sixteen endpoints and it provides an internally generated 48-MHz clock. The USB
Device Controller provides FIFOs with DMA access to or from memory.
1-2 Intel® PXA255 Processor Developer’s Manual
1.2.4DMA Controller (DMAC)
The DMAC provides sixteen prioritized channels to service transfer requests from internal
peripherals and up to two data transfer requests from external companion chips. The DMAC is
descriptor-based to allow command chaining and looping constructs.
The DMAC operates in Flow-Through Mode when performing peripheral-to-memory, memory-toperipheral, and memory-to-memory transfers. The DMAC is compatible with peripherals that use
word, half-word, or byte data sizes.
1.2.5LCD Controller
The LCD Controller supports both passive (DSTN) and active (TFT) flat-panel displays with a
maximum supported resolution of 640x480x16-bit/pixel. An internal 256 entry palette expands 1,
2, 4, or 8-bit encoded pixels. Non-encoded 16-bit pixels bypass the palette.
Two dedicated DMA channels allow the LCD Controller to support single- and dual-panel
displays. Passive monochrome mode supports up to 256 gray-scale levels and passive color mode
supports up to 64K colors. Active color mode supports up to 64K colors.
Introduction
1.2.6AC97 Controller
The AC97 Controller supports AC97 Revision 2.0 CODECs. These CODECs can operate at
sample rates up to 48 KHz. The controller provides independent 16-bit channels for Stereo PCM
In, Stereo PCM Out, Modem In, Modem Out, and mono Microphone In. Each channel includes a
FIFO that supports DMA access to memory.
1.2.7Inter-IC Sound (I2S) Controller
The I2S Controller provides a serial link to standard I2S CODECs for digital stereo sound. It
supports both the Normal-I
connection to an I
The controller includes FIFOs that support DMA access to memory.
2
S CODEC. I2S Controller signals are multiplexed with AC97 Controller pins.
2
S and MSB-Justified I2S formats, and provides four signals for
1.2.8Multimedia Card (MMC) Controller
The MMC Controller provides a serial interface to standard memory cards. The controller supports
up to two cards in either MMC or SPI modes with serial data transfers up to 20 Mbps. The MMC
controller has FIFOs that support DMA access to and from memory.
1.2.9Fast Infrared (FIR) Communication Port
The FIR Communication Port is based on the 4-Mbps Infrared Data Association (IrDA)
Specification. It operates at half-duplex and has FIFOs with DMA access to memory. The FIR
Communication Port uses the STUART’s transmit and receive pins to directly connect to external
IrDA LED transceivers.
Intel® PXA255 Processor Developer’s Manual1-3
Introduction
1.2.10Synchronous Serial Protocol Controller (SSPC)
The SSP Port provides a full-duplex synchronous serial interface that operates at bit rates from
7.2 kHz to 1.84 MHz. It supports National Semiconductor’s Microwire*, Texas Instruments’
Synchronous Serial Protocol*, and Motorola’s Serial Peripheral Interface*. The SSPC has FIFOs
with DMA access to memory.
1.2.11Inter-Integrated Circuit (I2C) Bus Interface Unit
The I2C Bus Interface Unit provides a general purpose 2-pin serial communication port.The
interface uses one pin for data and address and a second pin for clocking.
1.2.12GPIO
Each GPIO pin can be individually programmed as an output or an input. Inputs can cause
interrupts on rising or falling edges. Primary GPIO pins are not shared with peripherals while
secondary GPIO pins have alternate functions which can be mapped to the peripherals.
1.2.13UARTs
The processor provides three Universal Asynchronous Receiver/Transmitters. Each UART can be
used as a slow infrared (SIR) transmitter/receiver based on the Infrared Data Association Serial
Infrared (SIR) Physical Layer Link Specification.
1.2.13.1Full Function UART (FFUART)
The FFUART baud rate is programmable up to 230 Kbps. The FFUART provides a complete set of
modem control pins: nCTS, nRTS, nDSR, nDTR, nRI, and nDCD. It has FIFOs with DMA access
to or from memory.
1.2.13.2Bluetooth UART (BTUART)
The BTUART baud rate is programmable up to 921 Kbps. The BTUART provides a partial set of
modem control pins: nCTS and nRTS. Other modem control pins can be implemented via GPIOs.
The BTUART has FIFOs with DMA access to or from memory.
1.2.13.3Standard UART (STUART)
The STUART baud rate is programmable up to 230 Kbps. The STUART does not provide any
modem control pins. The modem control pins can be implemented via GPIOs. The STUART has
FIFOs with DMA access to or from memory.
The STUART’s transmit and receive pins are multiplexed with the Fast Infrared Communication
Port.
1-4 Intel® PXA255 Processor Developer’s Manual
1.2.13.4Hardware UART (HWUART)
The PXA255 processor has a UART with hardware flow control. The HWUART provides a partial
set of modem control pins: nCTS and nRTS. These modem control pins provide full hardware flow
control. Other modem control pins can be implemented via GPIOs. The HWUART baud rate is
programmable up to 921.6 Kbps.
The HWUART’s pins are multiplexed with the PCMCIA control pins. Because of this, these
HWUART pins operate at the same voltage as the memory bus. Also, since the PCMCIA pin
nPWE is used for variable-latency input/output (VLIO), while using these pins for the HWUART,
VLIO is unavailable. The HWUART pins are also available over the BTUART pins. When
operating over the BTUART pins, the HWUART pins operate at the I/O voltage.
1.2.14Real-Time Clock (RTC)
The Real-Time Clock can be clocked from either crystal. A system with a 32.768-KHz crystal
consumes less power during Sleep versus a system using only the 3.6864-MHz crystal. This crystal
can be removed to save system cost. The RTC provides a constant frequency output with a
programmable alarm register. This alarm register can be used to wake up the processor from Sleep
mode.
Introduction
1.2.15OS Timers
The OS Timers can be used to provide a 3.68-MHz reference counter with four match registers.
These registers can be configured to cause interrupts when equal to the reference counter. One
match register can be used to cause a watchdog reset.
1.2.16Pulse-Width Modulator (PWM)
The PWM has two independent outputs that can be programmed to drive two GPIOs. The
frequency and duty cycle are independently programmable. For example, one GPIO can control
LCD contrast and the other LCD brightness.
1.2.17Interrupt Control
The Interrupt Controller directs the processor interrupts into the core’s IRQ and FIQ inputs. The
Mask Register enables or disables individual interrupt sources.
1.2.18Network Synchronous Serial Protocol Port
The PXA255 processor has an SSP port optimized for connection to other network ASICs. This
NSSP adds a Hi-Z function to TXD, the ability to control when Hi-Z occurs, and swapping the
TXD/RXD pins.
This port is not multiplexed with other interfaces.
Intel® PXA255 Processor Developer’s Manual1-5
Introduction
1-6 Intel® PXA255 Processor Developer’s Manual
System Architecture2
2.1Overview
The PXA255 processor is an integrated system-on-a-chip microprocessor for high performance,
low power portable handheld and handset devices. It incorporates the Intel XScale®
microarchitecture with on-the-fly frequency scaling and sophisticated power management to
provide industry leading MIPs/mW performance. The PXA255 processor is ARM* Architecture
Version 5TE instruction set compliant (excluding floating point instructions) and follows the
ARM* programmer’s model.
The processor’s memory interface supports a variety of memory types to allow design flexibility.
Support for the connection of two companion chips permits a glueless interface to external devices.
An integrated LCD display controller provides support for displays up to 640x480 pixels, and
permits 1-, 2-, 4-, and 8-bit grayscale and 8- or 16-bit color pixels. A 256 entry/512 byte palette
RAM provides flexibility in color mapping.
A set of serial devices and general system resources provide computational and connectivity
capability for a variety of applications. Refer to Figure 2-1 for an overview of the microprocessor
system architecture.
The processor incorporates the Intel XScale® microarchitecture which is described in a separate
document. This core contains implementation options which an Application Specific Standard
Product (ASSP) may elect to implement or omit. This section describes those options.
Most of these options are specified within the coprocessor register space. The processor does not
implement any coprocessor registers beyond those defined in the Intel XScale® microarchitecture.
The coprocessor registers which are ASSP specific, as stated in the Intel XScale® Microarchitecture for the Intel® PXA255 Processor User’s Manual, order number 278793, are
defined in the following sections.
2.2.1Coprocessor 7 Register 4 - PSFS Bit
Bit 5 of this register is defined as the Power Source Fault Status bit or PSFS bit. This bit is set when
either nVDD_FAULT or nBATT_FAULT pins are asserted and the Imprecise Data Abort Enable
(IDAE) bit in the Power Manager Control Register (PMCR) is set.
This is a read-only register. Ignore reads from reserved bits.
2-2 Intel® PXA255 Processor Developer’s Manual
Table 2-1. CPU Core Fault Register Bit Definitions
The processor does not define any performance monitoring features beyond those called out in the
Intel XScale® Microarchitecture for the Intel® PXA255 Processor User’s Manual, order number
278793. The interrupt generated by performance monitoring events is defined in Chapter 4,
“System Integration Unit”. The ASSP defined performance monitoring events (events 0x10 -
0x17), defined through the PMNC register are reserved for the processor.
2.2.3Coprocessor 14 Register 6 and 7- Clock and Power
Management
These registers allow software to use the clocking and power management modes. The valid
operations are described in Table 3-23, “Coprocessor 14 Clock and Power Management Summary”
on page 3-39.
2.2.4Coprocessor 15 Register 0 - ID Register Definition
This register may be read by software to determine the device type and revision. The contents of
this register for the Intel® PXA255 Processor is defined in the table below. Combined, this register
must read as 0x6905 2X0R where R = 0b0000 for the first stepping and then increments for
subsequent steppings, and X is the revision of the Intel XScale® microarchitecture present. Please
see the Intel Developer Homepage at http://developer.intel.com for updates.
This field is updated when new sets of features are added to the core. This
allows software that is dependant on core features to target a specific core.
Core generation:
– Intel XScale® core
0b001
This field is updated each time a core is revised. Differences may include
errata, software workarounds, etc.
Core revision:
0b000
– First version of the core.
0b010
– Third version of the core.
0b011
– Fourth version of the core.
Product Number
0b010000 – PXA255 processor
This field tracks the different steppings for each ASSP.
Product Revision
– A0 Stepping
0b0110
Core
generation
Core
Revision
Product
Number
Product
Revision
Table 2-3. PXA255 Processor ID Values
Stepping ARM IDJTAG ID
A00x6905_2D060x6926_4013
2.2.5Coprocessor 15 Register 1 - P-Bit
Bit 1 of this register is defined as the Page Table Memory Attribute bit or P-bit. It is not
implemented in the processor and must be written as zero. Similarly, the P-bit in the page table
descriptor in the MMU is not implemented and must be written to zero.
2-4 Intel® PXA255 Processor Developer’s Manual
2.3I/O Ordering
The processor uses queues that accept memory requests from the three internal masters: core,
DMA Controller, and LCD Controller. Operations issued by a master are completed in the order
they were received. Operations from one master may be interrupted by operations from another
master. The processor does not provide a method to regulate the order of operations from different
masters.
Loads and stores to internal addresses are generally completed more quickly than those issued to
external addresses. The difference in completion time allows one operation to be received before
another operation, but completed after the second operation.
In the following sequence, the store to the address in r4 is completed before the store to the address
in r2 because the first store waits for memory in the queue while the second is not delayed.
str r1, [r2]; store to external memory address [r2].
str r3, [r4]; store to internal (on-chip) memory address [r4].
If the two stores are control operations that must be completed in order, the recommended sequence
is to insert a load to an unbuffered, uncached memory page followed by an operation that depends
on data from the load:
System Architecture
str r1, [r2]; first store issued
ldr r5, [r6]; load from external unbuffered, uncached address ([r2] if possible)
mov r5, r5; nop stalls until r5 is loaded
str r3, [r4]; second store completes in program order
2.4Semaphores
The Swap (SWP) and Swap Byte (SWPB) instructions, as described in the ARM* Architecture
reference, may be used for semaphore manipulation. No on-chip master or process can access a
memory location between the load and store portion of a SWP or SWPB to the same location.
Note:Semaphore coherency may be interrupted because an external companion chip that uses the
MBREQ/MBGNT handshake can take ownership of the bus during a locked sequence. To allow
semaphore manipulation by external companion chips, the software must manage coherency.
2.5Interrupts
The interrupt controller is described in detail in Section 4.2, “Interrupt Controller”. All on-chip
interrupts are enabled, masked, and routed to the core FIQ or IRQ. Each interrupt is enabled or
disabled at the source through an interrupt mask bit. Generally, all interrupt bits in a unit are ORed
together and present a single value to the interrupt controller.
Intel® PXA255 Processor Developer’s Manual2-5
System Architecture
Each interrupt goes through the Interrupt Controller Mask Register and then the Interrupt
Controller Level Register directs the interrupt into either the IRQ or FIQ. If an interrupt is taken,
the software may read the Interrupt Controller Pending Register to identify the source. After it
identifies the interrupt source, software is responsible for servicing the interrupt and clearing it in
the source unit before exiting the service routine.
Note:Clearing interrupts may take a delay. To allow the status bit to clear before returning from an
interrupt service routine (ISR), clear the interrupt early in the routine.
2.6Reset
The processor can be reset in any of three ways: Hardware, Watchdog, and GPIO resets. Each is
described in more detail in Section 3.4, “Resets and Power Modes” on page 3-6.
• Hardware reset results from asserting the nRESET pin and forces all units into reset state.
• Watchdog reset results from a time-out in the OS Timer and may be used to recover from
runaway code. Watchdog reset is disabled by default and must be enabled by software.
• GPIO reset is a “soft reset” that is less destructive than Hardware and Watchdog resets.
Each type of reset affects the state of the processor pins. Table 2-4 shows each pin’s state after each
type of reset.
Leaving Sleep Mode causes a Sleep Mode reset. Unlike other resets, Sleep Mode resets do not
change the state of the pins.
The Reset Controller Status Register (RCSR) contains information on the type of reset, including
Sleep Mode resets.
Table 2-4. Effect of Each Type of Reset on Internal Register State (Sheet 1 of 2)
UnitSleep ModeGPIO ResetWatchdog ResetHard Reset
Coreresetresetresetreset
Memory Controllerresetpreservedresetreset
LCD Controllerresetresetresetreset
DMA Controllerresetresetresetreset
Full Function UARTresetresetresetreset
Bluetooth UARTresetresetresetreset
Standard UARTresetresetresetreset
Hardware UARTresetresetresetreset
2
I
Cresetresetresetreset
2
I
Sresetresetresetreset
AC97resetresetresetreset
USBresetresetresetreset
ICPresetresetresetreset
RTCpreservedpreservedreset (except RTTR)reset
OS Timerresetresetresetreset
2-6 Intel® PXA255 Processor Developer’s Manual
System Architecture
Table 2-4. Effect of Each Type of Reset on Internal Register State (Sheet 2 of 2)
All internal registers are mapped in physical memory space on 32-bit address boundaries. Use
word access loads and stores to access internal registers. Internal register space must be mapped as
non-cacheable.
Byte and halfword accesses to internal registers are not permitted and yield unpredictable results.
Register space where a register is not specifically mapped is defined as reserved space. Reading or
writing reserved space causes unpredictable results.
The processor does not use all register bit locations. The unused bit locations are marked reserved
and are allocated for future use. Write reserved bit locations as zeros. Ignore the values of these bits
during reads because they are unpredictable.
2.8Selecting Peripherals vs. General Purpose I/O
Most peripherals connect to the external pins through GPIOs. To use a peripheral connected
through a GPIO, the software must first configure the GPIO so that the desired peripheral is
connected to its pins. The default state of the pins is GPIO inputs.
To allocate a peripheral to a pin, disable the GPIO function for that pin, then map the peripheral
function onto the pin by selecting the proper alternate function for the pin. Some GPIOs have
multiple alternate functions. After a function is selected for a pin, all other functions are excluded.
For this reason some peripherals are mapped to multiple GPIOs, as shown in Section 4.1.2, “GPIO
Alternate Functions” on page 4-2. Multiple mapping does not mean multiple instances of a
peripheral - only that the peripheral is connected to the pins in several ways.
Intel® PXA255 Processor Developer’s Manual2-7
System Architecture
2.9Power on Reset and Boot Operation
Before the device that uses the processor is powered on, the system must assert nRESET and
nTRST. To allow the internal clocks to stabilize, all power supplies must be stable for a specified
period before nRESET or nTRST are deasserted. When nRESET is asserted, nRESET_OUT is
driven active and can be used to reset other devices in the system. For additional information, see
the Intel® PXA255 Processor Design Guide.
When the system deasserts nRESET and nTRST, the processor deasserts nRESET_OUT a
specified time later and the device attempts to boot from physical address location 0x0000_0000.
The BOOT_SEL[2:0] pins are sampled when reset is deasserted and let the user specify the type
and width of memory device from which the processor attempts to boot. The software can read the
pins as described in Section 6.10.2, “Boot Time Defaults” on page 6-74.
2.10Power Management
The processor offers a number of modes to manage power in the system. These range widely in
level of power savings and level of functionality. The following modes are supported:
• Turbo Mode: low latency (nanoseconds) switch between two preprogrammed frequencies.
• Run Mode: normal full function mode.
• Idle Mode: core clocks are stopped - resume through an interrupt.
• Sleep Mode: low power mode that does not save state but keeps I/Os powered. The RTC,
Power Manager, and Clock modules are saved, except for Coprocessor 14.
Note:In low power modes, ensure that input pins are not floating and output pins are not driven by an
external device that opposes how the processor is driving that pin. In either case, the system will
draw excess current. Current draw that varies in sleep mode or varies greatly between parts is
typically a sign of floating pins.
Section 3.4, “Resets and Power Modes” describes the modes in detail.
2.11Pin List
Some of the processor pins can be connected to multiple signals. The signal connected to the pin is
determined by the GPIO Alternate Function Select Registers (GAFRn m). Some signals can go to
multiple pins. The signal must be routed to only one pin by using the GAFRn m registers. Because
this is true, some pins are listed twice, once in each unit that can use the pin.
Table 2-5. Processor Pin Types
TypeFunction
ICCMOS input
OCCMOS output
OCZCMOS output, Hi-Z
ICOCZCMOS bidirectional, Hi-Z
2-8 Intel® PXA255 Processor Developer’s Manual
System Architecture
Table 2-5. Processor Pin Types
TypeFunction
IAAnalog Input
OAAnalog output
IAOAAnalog bidirectional
SUPSupply pin (either VCC or VSS)
Table 2-6 describes the PXA255 processor pins.
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 1 of 9)
Pin NameTypeSignal DescriptionsReset StateSleep State
Memory Controller Pins
MA[25:0]OCZ
MD[15:0]ICOCZ
MD[31:16]ICOCZ
nOEOCZ
nWEOCZ
nSDCS[3:0]OCZ
DQM[3:0]OCZ
nSDRASOCZ
nSDCASOCZ
SDCKE[0]OC
SDCKE[1]OC
SDCLK[0]OC
Memory address bus. (output) Signals the address
requested for memory accesses.
Memory data bus. (input/output) Lower 16 bits of the
data bus.
Memory data bus. (input/output) Used for 32-bit
memories.
Memory output enable. (output) Connect to the output
enables of memory devices to control data bus drivers.
Memory write enable. (output) Connect to the write
enables of memory devices.
SDRAM CS for banks 3 through 0. (output) Connect to
the chip select (CS) pins for SDRAM. For the PXA255
processor nSDCS0 can be Hi-Z, nSDCS1-3 cannot.
SDRAM DQM for data bytes 3 through 0. (output)
Connect to the data output mask enables (DQM) for
SDRAM.
SDRAM RAS. (output) Connect to the row address
strobe (RAS) pins for all banks of SDRAM.
SDRAM CAS. (output) Connect to the column address
strobe (CAS) pins for all banks of SDRAM.
Synchronous Static Memory clock enable. (output)
Connect to the CKE pins of SMROM. The memory
controller provides control register bits for deassertion.
SDRAM and/or Synchronous Static Memory clock
enable. (output) Connect to the clock enable pins of
SDRAM. It is deasserted during sleep. SDCKE[1] is
always deasserted upon reset. The memory controller
provides control register bits for deassertion.
Synchronous Static Memory clock. (output) Connect to
the clock (CLK) pins of SMROM. It is driven by either the
internal memory controller clock, or the internal memory
controller clock divided by 2. At reset, all clock pins are
free running at the divide by 2 clock speed and may be
turned off via free running control register bits in the
memory controller. The memory controller also provides
control register bits for clock division and deassertion of
each SDCLK pin. SDCLK[0] control register assertion bit
defaults to on if the boot-time static memory bank 0 is
configured for SMROM.
Driven LowDriven Low
Hi-Z Driven Low
Hi-ZDriven Low
Driven HighNote [4]
Driven HighNote [4]
Driven HighNote [5]
Driven LowDriven Low
Driven HighDriven High
Driven HighDriven High
Driven LowDriven Low
Driven LowDriven Low
Intel® PXA255 Processor Developer’s Manual2-9
System Architecture
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 2 of 9)
Pin NameTypeSignal DescriptionsReset StateSleep State
SDCLK[1]OCZSDRAM Clocks (output) Connect SDCLK[1] and
SDCLK[2]OCDriven LowDriven Low
nCS[5]/
GPIO[33]
nCS[4]/
GPIO[80]
nCS[3]/
GPIO[79]
nCS[2]/
GPIO[78]
nCS[1]/
GPIO[15]
nCS[0]ICOCZ
RD/nWROCZ
RDY/
GPIO[18]
L_DD[8]/
GPIO[66]
L_DD[15]/
GPIO[73]
MBGNT/
GP[13]
MBREQ/
GP[14]
PCMCIA/CF Control Pins
nPOE/
GPIO[48]
nPWE/
GPIO[49]
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
SDCLK[2] to the clock pins of SDRAM in bank pairs 0/1
and 2/3, respectively. They are driven by either the
internal memory controller clock, or the internal memory
controller clock divided by 2. At reset, all clock pins are
free running at the divide by 2 clock speed and may be
turned off via free running control register bits in the
memory controller. The memory controller also provides
control register bits for clock division and deassertion of
each SDCLK pin. SDCLK[2:1] control register assertion
bits are always deasserted upon reset.
Static chip selects. (output) Chip selects to static
memory devices such as ROM and Flash. Individually
programmable in the memory configuration registers.
nCS[5:0] can be used with variable latency I/O devices.
Static chip select 0. (output) Chip select for the boot
memory. nCS[0] is a dedicated pin.
Read/Write for static interface. (output) Signals that the
current transaction is a read or write.
Variable Latency I/O Ready pin. (input) Notifies the
memory controller when an external bus device is ready
to transfer data.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
Memory Controller alternate bus master request.
(input) Allows an external device to request the system
bus from the Memory Controller.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
Memory Controller grant. (output) Notifies an external
device that it has been granted the system bus.
Memory Controller grant. (output) Notifies an external
device that it has been granted the system bus.
Memory Controller alternate bus master request.
(input) Allows an external device to request the system
bus from the Memory Controller.
PCMCIA output enable. (output) Reads from PCMCIA
memory and to PCMCIA attribute space.
PCMCIA write enable. (output) Performs writes to
PCMCIA memory and to PCMCIA attribute space. Also
used as the write enable signal for Variable Latency I/O.
Driven LowDriven Low
Pulled High Note[1]
Driven HighNote [4]
Driven LowHolds last state
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Note [4]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [5]
Note [5]
2-10 Intel® PXA255 Processor Developer’s Manual
System Architecture
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 3 of 9)
Pin NameTypeSignal DescriptionsReset StateSleep State
PCMCIA card enable 2. (output) Selects a PCMCIA
card. nPCE[2] enables the high byte lane and nPCE[1]
enables the low byte lane.
MMC clock. (output) Clock signal for the MMC
Controller.
PCMCIA card enable 1. (outputs) Selects a PCMCIA
card. nPCE[2] enables the high byte lane and nPCE[1]
enables the low byte lane.
IO Select 16. (input) Acknowledge from the PCMCIA
card that the current address is a valid 16 bit wide I/O
address.
PCMCIA wait. (input) Driven low by the PCMCIA card to
extend the length of the transfers to/from the PXA255
processor.
PCMCIA socket select. (output) Used by external
steering logic to route control, address, and data signals
to one of the two PCMCIA sockets. When PSKTSEL is
low, socket zero is selected. When PSKTSEL is high,
socket one is selected. Has the same timing as the
address bus.
PCMCIA Register select. (output) Indicates that the
target address on a memory transaction is attribute
space. Has the same timing as the address bus.
LCD display data. (outputs) Transfers pixel information
from the LCD Controller to the external LCD panel.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
Memory Controller alternate bus master request.
(input) Allows an external device to request the system
bus from the Memory Controller.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
MMC chip select 0. (output) Chip select 0 for the MMC
Controller.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
MMC chip select 1. (output) Chip select 1 for the MMC
Controller.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
MMC clock. (output) Clock for the MMC Controller.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
RTC clock. (output) Real time clock 1 Hz tick.
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Note [5]
Note [5]
Note [5]
Note [5]
Note [5]
Note [5]
Note [5]
Note [5]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Intel® PXA255 Processor Developer’s Manual2-11
System Architecture
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 4 of 9)
Pin NameTypeSignal DescriptionsReset StateSleep State
L_DD[13]/
GPIO[71]
L_DD[14]/
GPIO[72]
L_DD[15]/
GPIO[73]
L FCLK/
GPIO[74]
L LCLK/
GPIO[75]
L PCLK/
GPIO[76]
L BIAS/
GPIO[77]
Full Function UART Pins
FFRXD/
GPIO[34]
FFTXD/
GPIO[39]
FFCTS/
GPIO[35]
FFDCD/
GPIO[36]
FFDSR/
GPIO[37]
FFRI/
GPIO[38]
FFDTR/
GPIO[40]
FFRTS/
GPIO[41]
Bluetooth UART Pins
BTRXD/
GPIO[42]
BTTXD/
GPIO[43]
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZFull Function UART Clear-to-Send. (input)
ICOCZFull Function UART Data-Carrier-Detect. (input)
ICOCZFull Function UART Data-Set-Ready. (input)
ICOCZFull Function UART Ring Indicator. (input)
ICOCZFull Function UART Data-Terminal-Ready. (output)
ICOCZFull Function UART Request-to-Send. (output)
ICOCZBluetooth UART Receive. (input)
ICOCZBluetooth UART Transmit. (output)
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
3.6864 MHz clock. (output) Output from 3.6864 MHz
oscillator.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
32 kHz clock. (output) Output from the 32 kHz oscillator.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
Memory Controller grant. (output) Notifies an external
device it has been granted the system bus.
LCD frame clock. (output) Indicates the start of a new
frame. Also referred to as Vsync.
LCD line clock. (output) Indicates the start of a new line.
Also referred to as Hsync.
LCD pixel clock. (output) Clocks valid pixel data into the
LCD’s line shift buffer.
AC bias drive. (output) Notifies the panel to change the
polarity for some passive LCD panel. For TFT panels,
this signal indicates valid pixel data.
Full Function UART Receive. (input)
MMC chip select 0. (output) Chip select 0 for the MMC
Controller.
Full Function UART Transmit. (output)
MMC chip select 1. (output) Chip select 1 for the MMC
Controller.
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
2-12 Intel® PXA255 Processor Developer’s Manual
System Architecture
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 5 of 9)
Pin NameTypeSignal DescriptionsReset StateSleep State
32kHz/GP[12]ICOCZ 32 kHz clo ck. (output) Output from the 32 kHz oscillator.
Miscellaneous Pins
BOOT_SEL
[2:0]
PWR_ENOC
nBATT_FAULT IC
nVDD_FAULTIC
nRESETIC
nRESET_OUTOC
JTAG and Test Pins
nTRSTIC
TDIIC
ICOCZ
ICBoot select pins. (input) Indicates type of boot device.InputInput
from the PLL.
NOTE: This clock is only generated when the USB unit
clock enable is set.
Real time clock. (output) 1 Hz output derived from the
32kHz or 3.6864MHz output.
3.6864 MHz clock. (output) Output from 3.6864 MHz
oscillator.
Power Enable for the power supply. (output) When
negated, it signals the power supply to remove power to
the core because the system is entering sleep mode.
Main Battery Fault. (input) Signals that main battery is
low or removed. Assertion causes PXA255 processor to
enter sleep mode or force an Imprecise Data Exception,
which cannot be masked. PXA255 processor will not
recognize a walk-up event while this signal is asserted.
Minimum assertion time for nBATT_FAULT is 1 ms.
VDD Fault. (input) Signals that the main power source is
going out of regulation. nVDD_FAULT causes the
PXA255 processor to enter sleep mode or force an
Imprecise Data Exception, which cannot be masked.
nVDD_FAULT is ignored after a walk-up event until the
power supply timer completes (approximately 10 ms).
Minimum assertion time for nVDD_FAULT is 1 ms.
Hard reset. (input) Level sensitive input used to start the
processor from a known address. Assertion causes the
current instruction to terminate abnormally and causes a
reset. When nRESET is driven high, the processor starts
execution from address 0. nRESET must remain low until
the power supply is stable and the internal 3.6864 MHz
oscillator has stabilized.
Reset Out. (output) Asserted when nRESET is asserted
and deasserts after nRESET is deasserted but before the
first instruction fetch. nRESET_OUT is also asserted for
“soft” reset events: sleep, watchdog reset, or GPIO reset.
JTAG Test Interface Reset. Resets the JTAG/Debug
port. If JTAG/Debug is used, drive nTRST from low to
high either before or at the same time as nRESET. If
JTAG is not used, nTRST must be either tied to nRESET
or tied low.
JTAG test data input. (input) Data from the JTAG
controller is sent to the PXA255 processor using this pin.
This pin has an internal pull-up resistor.
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Pulled High Note[1]
Driven High
InputInput
InputInput
Input
Driven low during
any reset sequence
- driven high prior to
first fetch.
InputInput
InputInput
Note [3]
Note [3]
Note [3]
Note [3]
Driven low while
entering sleep
mode. Driven high
when sleep exit
sequence begins.
Input. Driving low
during sleep will
cause normal
reset sequence
and exit from sleep
mode.
Driven Low
2-16 Intel® PXA255 Processor Developer’s Manual
System Architecture
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 9 of 9)
Pin NameTypeSignal DescriptionsReset StateSleep State
TDOOCZ
TMSIC
TCKIC
TESTICTest Mode. (input) Reserved. Must be grounded. InputInput
TESTCLKICTest Clock. (input) Reserved. Must be grounded.InputInput
Power and Ground Pins
VCCSUP
VSSSUP
PLL_VCCSUP
PLL_VSSSUP
VCCQSUP
VSSQSUP
VCCNSUP
VSSNSUP
JTAG test data output. (output) Data from the PXA255
processor is returned to the JTAG controller using this
pin.
JTAG test mode select. (input) Selects the test mode
required from the JTAG controller. This pin has an
internal pull-up resistor.
JTAG test clock. (input) Clock for all transfers on the
JTAG test interface.
Positive supply for internal logic. Must be connected
to the low voltage supply on the PCB.
Ground supply for internal logic. Must be connected to
the common ground plane on the PCB.
Positive supply for PLLs and oscillators. Must be
connected to the common low voltage supply.
Ground supply for the PLL. Must be connected to
common ground plane on the PCB.
Positive supply for all CMOS I/O except memory bus
and PCMCIA pins. Must be connected to the common
3.3v supply on the PCB.
Ground supply for all CMOS I/O except memory bus
and PCMCIA pins. Must be connected to the common
ground plane on the PCB.
Positive supply for memory bus and PCMCIA pins.
Must be connected to the common 3.3v or 2.5v supply on
the PCB.
Ground supply for memory bus and PCMCIA pins.
Must be connected to the common ground plane on the
PCB.
Hi-ZHi-Z
InputInput
InputInput
PoweredNote [6]
GroundedGrounded
PoweredNote [6]
GroundedGrounded
PoweredNote [7]
GroundedGrounded
PoweredNote [7]
GroundedGrounded
Table 2-7. Pin Description Notes (Sheet 1 of 2)
NoteDescription
GPIO Reset Operation: Configured as GPIO inputs by default after any reset. The input buffers for these pins
are disabled to prevent current drain and the pins are pulled high with 10K to 60K internal resistors. The input
paths must be enabled and the pullups turned off by clearing the Read Disable Hold (RDH) bit described in
[1]
Section 3.5.7, “Power Manager Sleep Status Register (PSSR)” on page 3-29. Even though sleep mode sets the
RDH bit, the pull-up resistors are not re-enabled by sleep mode.
Crystal oscillator pins: These pins are used to connect the external crystals to the on-chip oscillators. Refer to
[2]
Section 3.3.1, “32.768 kHz Oscillator” on page 3-4 and Section 3.3.2, “3.6864 MHz Oscillator” on page 3-4 for
details on Sleep Mode operation.
GPIO Sleep operation: During the transition into sleep mode, the state of these pins is determined by the
corresponding PGSRn. See Section 3.5.10, “Power Manager GPIO Sleep State Registers (PGSR0, PGSR1,
PGSR2)” and Section 4.1.3.2, “GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)” on page 4-8. If
[3]
selected as an input, this pin does not drive during sleep. If selected as an output, the value contained in the
Sleep State Register is driven out onto the pin and held there while the PXA255 processor is in Sleep Mode.
GPIOs configured as inputs after exiting sleep mode cannot be used until PSSR[RDH] is cleared.
Intel® PXA255 Processor Developer’s Manual2-17
System Architecture
Table 2-7. Pin Description Notes (Sheet 2 of 2)
NoteDescription
Static Memory Control Pins: During Sleep Mode, these pins can be programmed to either drive the value in the
Sleep State Register or to be placed in Hi-Z. To select the Hi-Z state, software must set the FS bit in the Power
[4]
Manager General Configuration Register. If PCFR[FS] is not set, then during the transition to sleep these pins
function as described in [3], above. For nWE, nOE, and nCS[0], if PCFR[FS] is not set, they are driven high by
the Memory Controller before entering sleep. If PCFR[FS] is set, these pins are placed in Hi-Z.
PCMCIA Control Pins: During Sleep Mode: Can be programmed either to drive the value in the Sleep State
[5]
Register or to be placed in Hi-Z. To select the Hi-Z state, software must set PCFR[FP]. If it is not set, then during
the transition to sleep these pins function as described in [3], above.
[6]During sleep, this supply may be driven low. This supply must never be high impedance.
[7]Remains powered in sleep mode.
2.12Memory Map
Figure 2-2 and Figure 2-3 show the full processor memory map.
Any unused register space from 0x4000_0000 to 0x4BFF_FFFF is reserved.
Note:Accessing reserved portions of the memory map will give unpredictable results.
The PCMCIA interface is divided into Socket 0 and Socket 1 space. These two sockets are each
subdivided into I/O, memory and attribute space. Each socket is allocated 256 MB of memory
space.
2-18 Intel® PXA255 Processor Developer’s Manual
Figure 2-2. Memory Map (Part One) — From 0x8000_0000 to 0xFFFF FFFF
System Architecture
0xFFFF_FFFF
0xFC00_0000
0xF800_0000
0xF400_0000
0xF000_0000
0xEC00_0000
0xE800_0000
0xE400_0000
0xE000_0000
0xDC00_0000
0xD800_0000
0xD400_0000
0xD000_0000
0xCC00_0000
0xC800_0000
0xC400_0000
0xC000_0000
0xBC00_0000
0xB800_0000
0xB400_0000
0xB000_0000
0xAC00_0000
0xA800_0000
0xA400_0000
0xA000_0000
0x9C00_0000
0x9800_0000
0x9400_0000
0x9000_0000
0x8C00_0000
0x8800_0000
0x8400_0000
0x8000_0000
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
SDRAM Bank 3 (64 MB)
SDRAM Bank 2 (64 MB)
SDRAM Bank 1 (64 MB)
SDRAM Bank 0 (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Intel® PXA255 Processor Developer’s Manual2-19
System Architecture
Figure 2-3. Memory Map (Part Two) — From 0x0000_0000 to 0x7FFF FFFF
0x7FFF FFFF
0x7C00_0000
0x7800_0000
0x7400_0000
0x7000_0000
0x6C00_0000
0x6800_0000
0x6400_0000
0x6000_0000
0x5C00_0000
0x5800_0000
0x5400_0000
0x5000_0000
0x4C00_0000
0x4800_0000
0x4400_0000
0x4000_0000
0x3C00_0000
0x3800_0000
0x3400_0000
0x3000_0000
0x2C00_0000
0x2800_0000
0x2400_0000
Memory Mapped registers (Memory Ctl)
Memory Mapped registers (Peripherals)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Reserved (64 MB)
Memory Mapped registers (LCD)
PCMCIA/CF- Slot 1 (256 MB)
PCMCIA/CF - Slot 0 (256MB)
0x2000_0000
0x1C00_0000
0x1800_0000
0x1400_0000
0x1000_0000
0x0C00_0000
0x0800_0000
0x0400_0000
0x0000_0000
Reserved (64 MB)
Reserved (64 MB)
Static Chip Select 5 (64 MB)
Static Chip Select 4 (64 MB)
Static Chip Select 3 (64 MB)
Static Chip Select 2 (64 MB)
Static Chip Select 1 (64 MB)
Static Chip Select 0 (64 MB)
2-20 Intel® PXA255 Processor Developer’s Manual
2.13System Architecture Register Summary
Table 2-8. System Architecture Register Address Summary (Sheet 1 of 12)
UnitAddressRegister SymbolRegister Description
DMA
Controller
0x4000_0000
0x4000_0000DCSR0DMA Control / Status Register for Channel 0
0x4000_0004DCSR1DMA Control / Status Register for Channel 1
0x4000_0008DCSR2DMA Control / Status Register for Channel 2
0x4000_000CDCSR3DMA Control / Status Register for Channel 3
0x4000_0010DCSR4DMA Control / Status Register for Channel 4
0x4000_0014DCSR5DMA Control / Status Register for Channel 5
0x4000_0018DCSR6DMA Control / Status Register for Channel 6
0x4000_001CDCSR7DMA Control / Status Register for Channel 7
0x4000_0020DCSR8DMA Control / Status Register for Channel 8
0x4000_0024DCSR9DMA Control / Status Register for Channel 9
0x4000_0028DCSR10DMA Control / Status Register for Channel 10
0x4000_002CDCSR11DMA Control / Status Register for Channel 11
0x4000_0030DCSR12DMA Control / Status Register for Channel 12
0x4000_0034DCSR13DMA Control / Status Register for Channel 13
0x4000_0038DCSR14DMA Control / Status Register for Channel 14
0x4000_003CDCSR15DMA Control / Status Register for Channel 15
0x4000_00f0DINTDMA Interrupt Register
0x4000_0100DRCMR0Request to Channel Map Register for DREQ 0
0x4000_0104DRCMR1Request to Channel Map Register for DREQ 1
0x4000_0108DRCMR2Request to Channel Map Register for I2S receive Request
0x4000_010CDRCMR3Request to Channel Map Register for I2S transmit Request
0x4000_0110DRCMR4Request to Channel Map Register for BTUART receive Request
0x4000_0114DRCMR5Request to Channel Map Register for BTUART transmit Request.
0x4000_0118DRCMR6Request to Channel Map Register for FFUART receive Request
0x4000_011CDRCMR7Request to Channel Map Register for FFUART transmit Request
0x4000_0120DRCMR8Request to Channel Map Register for AC97 microphone Request
0x4000_0124DRCMR9Request to Channel Map Register for AC97 modem receive Request
0x4000_0128DRCMR10Request to Channel Map Register for AC97 modem transmit Request
0x4000_012CDRCMR11Request to Channel Map Register for AC97 audio receive Request
0x4000_0130DRCMR12Request to Channel Map Register for AC97 audio transmit Request
0x4000_0134DRCMR13Request to Channel Map Register for SSP receive Request
0x4000_0138DRCMR14Request to Channel Map Register for SSP transmit Request
0x4000_013CDRCMR15Request to Channel Map Register for NSSP receive Request
0x4000_0140DRCMR16Request to Channel Map Register for NSSP transmit Request
0x4000_0144DRCMR17Request to Channel Map Register for ICP receive Request
0x4000_0148DRCMR18Request to Channel Map Register for ICP transmit Request
System Architecture
Intel® PXA255 Processor Developer’s Manual2-21
System Architecture
Table 2-8. System Architecture Register Address Summary (Sheet 2 of 12)
UnitAddressRegister SymbolRegister Description
0x4000_014CDRCMR19Request to Channel Map Register for STUART receive Request
0x4000_0150DRCMR20Request to Channel Map Register for STUART transmit Request
0x4000_0154DRCMR21Request to Channel Map Register for MMC receive Request
0x4000_0158DRCMR22Request to Channel Map Register for MMC transmit Request
0x4000_015CDRCMR23Reserved
0x4000_0160DRCMR24Reserved
0x4000_0164DRCMR25Request to Channel Map Register for USB endpoint 1 Request
0x4000_0168DRCMR26Request to Channel Map Register for USB endpoint 2 Request
0x4000_016CDRCMR27Request to Channel Map Register for USB endpoint 3 Request
0x4000_0170DRCMR28Request to Channel Map Register for USB endpoint 4 Request
0x4000_0174DRCMR29Request to Channel Map Register for HWUART receive Request
0x4000_0178DRCMR30Request to Channel Map Register for USB endpoint 6 Request
0x4000_017CDRCMR31Request to Channel Map Register for USB endpoint 7 Request
0x4000_0180DRCMR32Request to Channel Map Register for USB endpoint 8 Request
0x4000_0184DRCMR33Request to Channel Map Register for USB endpoint 9 Request
0x4000_0188DRCMR34Request to Channel Map Register for HWUART transmit Request
0x4000_018CDRCMR35Request to Channel Map Register for USB endpoint 11 Request
0x4000_0190DRCMR36Request to Channel Map Register for USB endpoint 12 Request
0x4000_0194DRCMR37Request to Channel Map Register for USB endpoint 13 Request
0x4000_0198DRCMR38Request to Channel Map Register for USB endpoint 14 Request
0x4400_003CLIIDRLCD Controller Interrupt ID Register
0x4400_0040TRGBRTMED RGB Seed Register
0x4400_0044TCRTMED Control Register
0x4800_0000
System Architecture
Intel® PXA255 Processor Developer’s Manual2-31
System Architecture
Table 2-8. System Architecture Register Address Summary (Sheet 12 of 12)
UnitAddressRegister SymbolRegister Description
0x4800_0000MDCNFGSDRAM Configuration Register 0
0x4800_0004MDREFRSDRAM Refresh Control Register
0x4800_0008MSC0Static Memory Control Register 0
0x4800_000CMSC1Static Memory Control Register 1
0x4800_0010MSC2Static Memory Control Register 2
0x4800_0014MECR
0x4800_001CSXCNFGSynchronous Static Memory Control Register
0x4800_0024SXMRSMRS value to be written to SMROM
0x4800_0028MCMEM0Card interface Common Memory Space Socket 0 Timing Configuration
0x4800_002CMCMEM1Card interface Common Memory Space Socket 1 Timing Configuration
0x4800_0030MCATT0Card interface Attribute Space Socket 0 Timing Configuration
0x4800_0034MCATT1Card interface Attribute Space Socket 1 Timing Configuration
0x4800_0038MCIO0Card interface I/O Space Socket 0 Timing Configuration
0x4800_003CMCIO1Card interface I/O Space Socket 1 Timing Configuration
0x4800_0040MDMRSMRS value to be written to SDRAM
0x4800_0044BOOT_DEF
0x4800_0058MDMRSLPLow Power SDRAM Mode Register Set Configuration Register
0x 4 800 _00 64S A 1111CRS A1111 C omp ati bility Register
Expansion Memory (PCMCIA/Compact Flash) Bus Configuration
Register
Read-only Boot-Time Register. Contains BOOT_SEL and PKG SEL
values.
2-32 Intel® PXA255 Processor Developer’s Manual
Clocks and Power Manager3
The Clocks and Power Manager for the PXA255 processor controls the clock frequency to each
module and manages transitions between the different power manager (PM) operating modes to
optimize both computing performance and power consumption.
3.1Clock Manager Introduction
The Clocks and Power Manager provides fixed clocks for each peripheral unit. Many of the
devices’ peripheral clocks can be disabled using the Clock Enable Register (CKEN), or through
bits in the peripheral’s control registers. To minimize power consumption, turn off the clock to any
unit that is not being used. The Clocks and Power Manager also provides the programmablefrequency clocks for the LCD Controller, Memory Controller, and CPU. These clocks are related to
each other because they come from the same internal Phase Locked Loop (PLL) clock source. To
program the PLL’s frequency, follow these steps (for information on the factors L, M, and N, see
Section 3.6.1, “Core Clock Configuration Register (CCCR)” on page 3-34):
1. Determine the fastest synchronous memory requirement (SDRAM frequency).
2. If the SDRAM frequency is less than 99.5 MHz, the Memory Frequency must be twice the
SDRAM Frequency and the SDRAM clock ratio in the Memory Controller must be set to two.
If the SDRAM frequency is 99.5 MHz, the Memory Frequency is equal to the SDRAM
frequency.
3. Round the Memory Frequency down to the nearest value of 99.5 MHz (L = 0x1B), 118.0 MHz
(L = 0x20), 132.7 MHz (L = 0x24), 147.5 MHz (L = 0x28), or 165.9 MHz (L = 0x2D), and
program the value of L in the Core Clock Configuration register. This frequency (or half, if the
SDRAM clock ratio is 2) is the External Synchronous Memory Frequency.
4. Determine the required Core Frequency for normal (Run Mode) operation. This mode is used
during normal processing, when the application must make occasional fetches to external
memory. The possible values are one, two, or four times the Memory Frequency. Program this
value (M) in the Core Clock Configuration register.
5. Determine the required Core Frequency for Turbo Mode operation. This mode is generally
used when the application runs entirely from the caches, because any fetches to external
memory slow the Core’s performance. This value is a multiple (1.0, 1.5, 2.0, or 3.0) of the Run
Mode Frequency. Program the value (N) in the Core Clock Configuration register.
6. Configure the LCD Controller and Memory Controller for the new Memory Frequency and
enter the Frequency Change Sequence (described in Section 3.4.7, “Frequency Change
Sequence” on page 3-11).
Note: Not all frequency combinations are valid. See Section 3.3.3, “Core Phase Locked Loop” for valid
combinations.
Intel® PXA255 Processor Developer’s Manual3-1
Clocks and Power Manager
3.2Power Manager Introduction
The Clocks and Power Manager can place the processor in one of three resets.
• Hardware Reset (nRESET asserted) is a nonmaskable total reset. It is used at power up or
when no system information requires preservation.
• Watchdog Reset is asserted through the Watchdog Timer and resets the system except the
Clocks and Power Manager. This reset is used as a code monitor. If code fails to complete a
specified sequence, the processor assumes a fatal system error has occurred and causes a
Watchdog Reset.
• GPIO Reset is enabled through the GPIO alternate function registers. It is used as an
alternative to Hardware Reset that preserves the Memory Controller registers and a few critical
states in the Clocks and Power Manager and the Real Time Clock (RTC).
The Clocks and Power Manager also controls the entry into and exit from any of the low power or
special clocking modes on processor. These modes are:
• Turbo Mode: the Core runs at its peak frequency. In this mode, make very few external
memory accesses because the Core must wait on the external memory.
• Run Mode: the Core runs at its normal frequency. In this mode, the Core is assumed to be
doing frequent external memory accesses, so running slower is optimum for the best power/
performance trade-off.
• Idle Mode: the Core is not being clocked, but the rest of the system is fully operational. This
mode is used during brief lulls in activity, when the external system must continue operation
but the Core is idle.
• Sleep Mode: places the processor in its lowest power state but maintains I/O state, RTC, and
the Clocks and Power Manager. Wake-up from Sleep Mode requires re-booting the system,
since most internal state was lost. The core power must be grounded in sleep to prevent current
leakage.
The Clocks and Power Manager also controls the processor’s actions during the Frequency Change
Sequence. The Frequency Change Sequence is a sequence that changes the Core Frequency (Run
and Turbo) and Memory Frequency from the previously stored values to the new values in the Core
Clock Configuration register. This sequence takes time to complete due to PLL relock time, but it
allows dynamic frequency changes without compromising external memory integrity. Any
peripherals that rely on the Core or Memory Controller must be configured to withstand a data flow
interruption.
3.3Clock Manager
The processor’s clocking system incorporates five major clock sources:
• 32.768 kHz Oscillator
• 3.6864 MHz Oscillator
• Programmable Frequency Core PLL
• 95.85 MHz Fixed Frequency Peripheral PLL
• 147.46 MHz Fixed Frequency PLL
3-2 Intel® PXA255 Processor Developer’s Manual
The clocks manager also contains clock gating for power reduction.
Figure 3-1 shows a functional representation of the clocking network. “L” is in the core PLL.
The PXbus is the internal bus between the Core, the DMA/Bridge, the LCD Controller, and the
Memory Controller as shown in Figure 3-1. This bus is clocked at 1/2 the run mode frequency. For
optimal performance, the PXbus should be clocked as fast as possible. For example, if a target core
frequency of 200 MHz is desired use 200 MHz run mode instead of 200 MHz turbo mode with run
at 100 MHz. Increasing the PXbus frequency may help reduce the latency involved in accessing
non-cacheable memory.
Figure 3-1. Clocks Manager Block Diagram
Clocks and Power Manager
32.768 k
RTC
32.768
32.768 k
PWR_MGR
/1/112
kHz
OSC
3.6864
MHz
OSC
RETAINS POWER IN SLEEP
USB
FICP
I2C
3.6864
PWM
100-400
MHz
PLL*
147.46
MHz
PLL
95.846
MHz
PLL
MMC
3.6864
SSP
3.6864
GPIO
UARTs
/N
/4
DMA
Bridge
/
3.6864
OST
/2
AC97
CPU
CORE
MEM
Controller
/M
LCD
Controller
PXbus
I2S
47.923
Intel® PXA255 Processor Developer’s Manual3-3
47.923
31.949
19.169
14.746
12.288
5.672
Clocks and Power Manager
3.3.132.768 kHz Oscillator
The 32.768 kHz oscillator is a low power, low frequency oscillator that clocks the RTC and Power
Manager. This oscillator is disabled out of Hardware Reset and the RTC and Power Manager
blocks use the 3.6864 MHz oscillator instead. Software writes the Oscillator On bit in the
Oscillator Configuration Register to enable the 32.768 kHz.This configures the RTC and Power
Manager to use the 32.768 kHz oscillator after it stabilizes.
32.768 kHz oscillator use is optional and provides the lowest power consumption during Sleep
Mode. In less power-sensitive applications, disable the 32.768 kHz oscillator in the Oscillator
Configuration Register (OSCC) and leave the external pins floating (no external crystal required)
for cost savings. If the 32.768 kHz oscillator is not in the system, the frequency of the RTC and
Power Manager will be 3.6864 MHz divided by 112 (32.914 kHz). In Sleep, the 3.6864 MHz
oscillator consumes hundreds of microamps of extra power when it stays enabled. See
Section 3.5.2, “Power Manager General Configuration Register (PCFR)” on page 3-24 for
information on The Oscillator Power Down Enable (OPDE) bit, which determines if the
3.6864 MHz oscillator is enabled in Sleep Mode. No external capacitors are required.
3.3.23.6864 MHz Oscillator
The 3.6864 MHz oscillator provides the primary clock source for the processor. The on-chip PLL
frequency multipliers, Synchronous Serial Port (SSP), Pulse Width Modulator (PWM), and the
Operating System Timer (OST) use the 3.6864 MHz oscillator as a reference. Out of Hardware
Reset, the 3.6864 MHz oscillator also drives the RTC and Power Manager (PM). The user may
then enable the 32.768 kHz oscillator, which will drive the RTC and PM after it is stabilized. The
3.6864 MHz oscillator can be disabled during Sleep Mode by setting the OPDE (see Section 3.5.2)
bit but only if the 32.768 kHz oscillator is enabled and stabilized (both the OON and OOK bits in
the OSCC set). See Section 3.6.3 for more information. No external capacitors are required.
3.3.3Core Phase Locked Loop
The Core PLL is the clock source of the CPU Core, the Memory Controller, the LCD Controller,
and DMA Controller. The Core PLL uses the 3.6864 MHz oscillator as a reference and multiplies
its frequency by the following variables:
• L: Crystal Frequency to Memory Frequency Multiplier, set to 27, 36 or 45.
• M: Memory Frequency to Run Mode Frequency Multiplier, set to 1, 2 or 4.
• N: Run Mode Frequency to Turbo Mode Frequency Multiplier, set to 1.0, 1.5, 2.0, or 3.0.
The output frequency selections are shown in Table 3-1, “Core PLL Output Frequencies for
3.6864 MHz Crystal”. See Section 3.6.1 for programming information on the L, M, and N factors.
See Section 3.6.1, “Core Clock Configuration Register (CCCR)” for the hexadecimal settings.
Do not choose a combination that generates a frequency that is not supported in the voltage range
and package in which the processor is operating.
SDCLK must not be greater than 100 MHz. If MEMCLK is greater than 100 MHz, the SDCLK to
MEMCLK ratio must be set to 1:2 in the Memory Controller.
3-4 Intel® PXA255 Processor Developer’s Manual
Table 3-1. Core PLL Output Frequencies for 3.6864 MHz Crystal
Clocks and Power Manager
LM
271
361
272
362
452
274
Turbo Mode Frequency (MHz) for Values
Configuration Register (CCCR[15:0])
1.00
(Run)
99.5
@1.0 V
132.7
@1.0 V
199.1
@1.0 V
265.4
@1.1 V
331.8
@1.3 V
398.1
@1.3 V
“N” and Core Clock
programming for Values of “N”
1.502.003.00
—
———66132.766
298.6
@1.1 V
———132.7132.766
———165.9165.983
———19699.599.5
199.1
@1.0 V
398.1
@1.3 V
298.6
@1.1 V
PXbus
Frequency
(MHz)
5099.599.5
—99.599.599.5
Note: These are the only supported frequency settings.
3.3.495.85 MHz Peripheral Phase Locked Loop
The 95.85 MHz PLL is the clock source for many of the peripheral blocks’ external interfaces.
These interfaces require ~48 MHz (UDC/USB, FICP), ~33 MHz (I
generated frequency is not exactly the required frequency due to the chosen crystal and the lack of
a perfect Least Common Multiple between the units. The chosen frequencies keep each unit’s clock
frequency within the unit’s clock tolerance. If a crystal other than 3.6864 MHz is used, the clock
frequencies to the peripheral blocks’ interfaces may not yield the desired baud rates (or protocol’s
rate).
The 147.46 MHz PLL is the clock source for many of the peripheral blocks’ external interfaces.
These interfaces require ~14.75 MHz (UARTs), 12.288 MHz (AC97), and variable frequencies
2
(I
S). The generated frequency may not exactly match the required frequency due to the choice of
crystal and the lack of a perfect Least Common Multiple between the units. The chosen frequencies
Intel® PXA255 Processor Developer’s Manual3-5
Clocks and Power Manager
keep each unit’s clock frequency within the unit’s clock tolerance. If a crystal other than
3.6864 MHz is used, the clock frequencies to the peripheral blocks’ interfaces may not yield the
desired baud rates (or other protocol’s rate)
The Clocks Manager contains the CKEN register. This register contains configuration bits that can
disable the clocks to individual units. The configuration bits are used when a module is not being
used. After Hardware Reset, any module that is not being used must have its clock disabled. If a
module is temporarily quiescent but does not have clock gating functionality, the CKEN register
can be used to disable the unit’s clock.
When a module’s clock is disabled, the registers in that module are still readable and writable. The
AC97 is an exception and is completely inaccessible if the clock is disabled.
3.4Resets and Power Modes
The Clocks and Power Manager Unit determines the processor’s Resets, Power Sequences and
Power Modes. Each behaves differently during operation and has specific entry and exit sequences.
The resets and power modes are:
• Hardware Reset
• Watchdog Reset
• GPIO Reset
• Run Mode
• Turbo Mode
• Idle Mode
• Frequency Change Sequence
• Sleep Mode
3.4.1Hardware Reset
To invoke the Hardware Reset and reset all units in the processor to a known state, assert the
nRESET pin. Hardware Reset is only intended to be used for power up and complete resets.
3-6 Intel® PXA255 Processor Developer’s Manual
3.4.1.1Invoking Hardware Reset
Hardware Reset is invoked when the nRESET pin is pulled low by an external source. The
processor does not provide a method of masking or disabling the propagation of the external pin
value. When the nRESET pin is asserted, Hardware Reset is invoked, regardless of the mode of
operation. The nRESET_OUT pin is asserted when the nRESET pin is asserted. To enter Hardware
Reset, nRESET must be held low for t
state to propagate. Refer to the Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification for details.
DHW_NRESET
3.4.1.2Behavior During Hardware Reset
During Hardware Reset, all internal registers and units are held at their defined reset conditions.
While the nRESET pin is asserted, nothing inside the processor is active except the 3.6864 MHz
oscillator. The internal clocks are stopped and the chip is static. All pins return to their reset
conditions and the nBATT_FAULT and nVDD_FAULT pins are ignored. Because the memory
controller receives a full reset, all dynamic RAM contents are lost during Hardware Reset.
3.4.1.3Completing Hardware Reset
To complete Hardware Reset, deassert the nRESET pin. All power supplies must be stable for
t
D_NRESET
Mechanical, and Thermal Specification for details. After the nRESET pin is deasserted, the
following sequence occurs:
before nRESET is deasserted. Refer to the Intel® PXA255 Processor Electrical,
Clocks and Power Manager
to allow the system to stabilize and the reset
1. The 3.6864 MHz oscillator and internal PLL clock generators wait for stabilization.
2. The nRESET_OUT pin is deasserted.
3. The normal boot-up sequence begins. All processor units return to their predefined reset
conditions. Software must examine the Reset Controller Status register (RCSR) to determine
the cause for the boot.
3.4.2Watchdog Reset
Watchdog Reset is invoked when software fails to properly prevent the Watchdog Time-out Event
from occurring. It is assumed that Watchdog Resets are only generated when software is not
executing properly and has potentially destroyed data. In Watchdog Reset all units in the are reset
except the Clocks and Power Manager.
3.4.2.1Invoking Watchdog Reset
Watchdog Reset is invoked when the Watchdog Enable bit (WE) in the OWER is set and the
OSMR[3] matches the OS timer counter. When these conditions are met, they invoke Watchdog
Reset, regardless of the previous mode of operation. Watchdog Reset asserts nRESET_OUT.
3.4.2.2Behavior During Watchdog Reset
During Watchdog Reset, all units except the Real Time Clock and parts of the Clocks and Power
Manager maintain their defined reset conditions. All pins except the oscillator pins assume their
reset conditions and the nBATT_FAULT and nVDD_FAULT pins are ignored. All dynamic RAM
contents are lost during Watchdog Reset because the memory controller receives a full reset.
Intel® PXA255 Processor Developer’s Manual3-7
Clocks and Power Manager
Refer to Table 2-6, “Pin & Signal Descriptions for the PXA255 Processor” for the pin states during
Watchdog and other Resets.
3.4.2.3Completing a Watchdog Reset
Watchdog resets immediately revert to hardware resets when the nRESET pin is asserted.
Otherwise, the completion sequence for watchdog reset is:
1. The 3.6864 MHz oscillator and internal PLL clock generators wait for stabilization. The
32.768 kHz oscillator’s configuration and status are not affected by watchdog reset.
2. The nRESET_OUT pin is deasserted after t
Electrical, Mechanical, and Thermal Specification.
3. The normal boot-up sequence begins. All processor units except the RTTR in the RTC and
parts of the Clocks and Power Manager return to their predefined reset conditions. Software
must examine the RCSR to determine the cause for the reboot.
3.4.3GPIO Reset
A GPIO Reset is invoked when GP[1] is properly configured as a reset source and is asserted low
for greater than four 3.6864-MHz clock cycles. In GPIO Reset all processor units except the RTC,
parts of the Clocks and Power Manager, and the Memory Controller return to their predefined,
known states.
3.4.3.1Invoking GPIO Reset
To use the GPIO Reset function, set it up through the GPIO Controller. The GP[1] pin must be
configured as an input and set to its alternate GPIO Reset function in the GPIO Controller. The
GPIO Reset alternate function is level-sensitive and not edge-triggered. To ensure no spurious
resets are generated when the alternate GPIO Reset function is set, follow these steps:
1. GP[1] must be set up as an output with its data register set to a 1.
2. Externally drive the GP[1] pin to a high state.
3. Configure GP[1] as an input.
4. Configure GP[1] for its Alternate (Reset) Function.
DHW_OUT
. Refer to the Intel® PXA255 Processor
The previous mode of operation does not affect a GPIO Reset. When performing a GPIO Reset,
nRESET_OUT is asserted. If GP[1] is asserted for less than four 3.6864-MHz clock cycles, the
processor may remain in its previous mode or enter into a GPIO reset.
GPIO Reset does not function in Sleep Mode because all GPIO pins’ Alternate Function Inputs are
disabled. External wake-up sources must be routed through one of the enabled GPIO wake-up
sources (see Section 3.5.3 for details) during Sleep Mode. GP[1] may be enabled as a wake-up
source.
3.4.3.2Behavior During GPIO Reset
During GPIO Reset, most, but not all, internal registers and processes are held at their defined reset
conditions. The exceptions are the RTC, the Clocks and Power Manager (unless otherwise noted),
and the Memory Controller. During GPIO Reset, the clocks unit continues to operate with its
3-8 Intel® PXA255 Processor Developer’s Manual
previously programmed values, so the processor enters and exits GPIO Reset with the same clock
configurations. All pins except the oscillator and Memory Controller pins return to their reset
conditions and the nBATT_FAULT and nVDD_FAULT pins are ignored.
GPIO Reset does not reset the Memory Controller Configuration registers. This creates the
possibility that the contents of external memories may be preserved if the external memories are
properly configured before GPIO Reset is entered. To preserve SDRAM contents during a GPIO
Reset, software must correctly configure the Memory Control and the time spent in GPIO Reset
must be shorter than the SDRAM refresh interval. The amount of time spent in GPIO Reset
depends on the CPU’s mode before GPIO Reset. See Section 6, “Memory Controller” for details.
Refer to Table 2-6, “Pin & Signal Descriptions for the PXA255 Processor” for the states of all the
PXA255 processor pins during GPIO reset and other resets.
3.4.3.3Completing GPIO Reset
GPIO Reset immediately reverts to Hardware Reset when the nRESET pin is asserted. Otherwise,
the completion sequence for GPIO Reset is:
1. The GPIO Reset Source is deasserted because the internal reset has propagated to the GPIO
Controller and its registers, which are set back to their reset states.
Clocks and Power Manager
2. The nRESET_OUT pin is deasserted.
3. The normal boot-up sequence begins. All processor units except the Real Time Clock, parts of
the Clocks and Power Manager, and the Memory Controller return to their predefined reset
conditions. Software must examine the RCSR to determine the cause for the reset.
3.4.4Run Mode
Run Mode is the processor’s normal operating mode. All power supplies are enabled and all
functionally enabled clocks are running. Run Mode is entered after any power mode, power
sequence, or reset completes its sequence. Run Mode is exited when any other power mode, power
sequence, or reset begins.
3.4.5Turbo Mode
Turbo Mode allows the user to clock the processor core at a higher frequency during peak
processing requirements. It allows a synchronous switch in frequencies without disrupting the
Memory Controller, LCD Controller, or any peripheral.
3.4.5.1Entering Turbo Mode
Turbo Mode is invoked when software sets the TURBO bit in the Clock Config (CCLKCFG)
Register (See Section 3.7.1). After software sets the TURBO bit, the CPU waits for all instructions
currently in the pipeline to complete. When the instructions are completed, the CPU resumes
operation at the higher Turbo Mode Frequency.
Software can set or clear other bits in the CCLKCFG in the same write that sets the TURBO bit.
The other bits in the register take precedence over Turbo Mode, so, if another bit is set, that mode’s
sequence is followed before the CPU enters Turbo Mode. When the CPU exits the other mode, it
enters either Run or Turbo Mode, based on the state of the CCLKCFG [TURBO] bit.
Intel® PXA255 Processor Developer’s Manual3-9
Clocks and Power Manager
Do not confuse the CCLKCFG Register, which is in Coprocessor 14, with the CCCR (See
Section 3.6.1), which is in the processor’s Clocks and Power Manager.
3.4.5.2Behavior in Turbo Mode
The processor’s behavior in Turbo Mode is identical to its behavior in Run Mode, except that the
processor’s clock frequency relative to the memory and peripherals is increased by N, the value in
the CCCR (see Section 3.6.1). Turbo mode is intended for use during peak processing, when there
are very few accesses to external memory. The higher Core to external memory clock ratio
increases the relative delay for each external memory access. This increased delay lowers the
processor’s power efficiency. For optimum performance, software must load applications in the
caches in Run Mode and execute them in Turbo Mode.
3.4.5.3Exiting Turbo Mode
To exit Turbo Mode, software clears the TURBO bit in the CCLKCFG Register. After software
clears the TURBO bit, the CPU waits for all instructions in the pipeline to complete. When the
instructions are completed, the CPU enters Run Mode.
Other bits in the CCLKCFG may be set or cleared in the write that clears CCLKCFG [TURBO].
All other bits in the register take precedence over Turbo Mode, so the new mode’s proper sequence
is followed.
Idle, Sleep, Frequency Change Sequence, and Reset have precedence over Turbo Mode and cause
the processor to exit Turbo Mode. When the CPU exits of one of these modes, it enters either Run
or Turbo Mode, based on the state of CCLKCFG [TURBO].
3.4.6Idle Mode
Idle Mode allows the user to stop the CPU core clock during periods of processor inactivity and
continue to monitor on- and off-chip interrupt service requests. Idle mode does not change clock
generation, so when an interrupt occurs the CPU is quickly reactivated in the state that preceded
Idle Mode.
During Idle mode these resources are active:
• System unit modules (real-time clock, operating system timer, interrupt controller, general-
purpose I/O, and clocks and power manager)
• Peripheral unit modules (DMA controller, LCD controller, and all other peripheral units)
• Memory Controller resources
3.4.6.1Entering Idle Mode
During Idle Mode, the clocks to the CPU core stop. All critical applications must be finished and
peripherals must be set up to generate interrupts when they require CPU attention. To enter the Idle
Mode, software selects Idle Mode in PWRMODE[M] (See Section 3.7.2). An interrupt
immediately aborts Idle Mode and normal processing resumes. After software selects Idle Mode,
the CPU waits until all instructions in the pipeline are completed. When the instructions are
completed, the CPU clock stops and Idle Mode begins. In Idle Mode, interrupts are recognized as
wake-up sources.
3-10 Intel® PXA255 Processor Developer’s Manual
3.4.6.2Behavior in Idle Mode
In Idle Mode the CPU clocks are stopped, but the remainder of the processor operates normally.
For example, the LCD controller can continue refreshing the screen with the same frame buffer
data in memory.
When ICCR[DIM] is cleared, any enabled interrupt wakes up the processor. When ICCR[DIM] is
set, only unmasked interrupts cause wake-up.
Enabled interrupts are interrupts that are allowed at the unit level. Masked interrupts are interrupts
that are prevented from interrupting the core based on the Interrupt Controller Mask Register.
3.4.6.3Exiting Idle Mode
Idle Mode exits when any Reset is asserted. Reset entry and exit sequences take precedence over
Idle Mode. When the Reset exit sequence is completed, the CPU is not in Idle Mode. If the
Watchdog Timer is enabled, software must set the Watchdog Match Registers before it sets Idle
Mode to ensure that another interrupt will bring the processor out of Idle Mode before the
Watchdog Reset is asserted. Use an RTC alarm or another OS timer channel for this purpose.
Any enabled interrupt causes Idle Mode to exit. When ICCR[DIM] is cleared, the Interrupt
Controller Mask register (ICMR) is ignored during Idle Mode. This means that an interrupt does
not have to be unmasked to cause Idle Mode to exit. Idle Mode exits in the following sequence:
Clocks and Power Manager
1. A valid, enabled Interrupt asserts.
2. The CPU clocks restart and the CPU resumes operation at the state indicated by CCLKCFG
[TURBO].
Idle Mode also exits when the nBATT_FAULT or nVDD_FAULT pin is asserted. When either pin
is asserted, Idle Mode exits in the following sequence:
1. The nBATT_FAULT or nVDD_FAULT pin is asserted.
2. If the Imprecise Data Abort Enable (IDAE) bit in the Power Manager Control Register
(PMCR) is clear (not recommended), the processor enters Sleep Mode immediately.
3. If the IDAE bit is set, the nBATT_FAULT or nVDD_FAULT assertion is treated as a valid
interrupt to the clocks module and Idle Mode exits using its normal, interrupt-driven sequence.
Software must then shut down the system and enter Sleep Mode. See Section 3.4.9.3,
“Entering Sleep Mode” for more details.
3.4.7Frequency Change Sequence
The Frequency Change Sequence is used to change the processor clock frequency. During the
Frequency Change Sequence, the CPU, Memory Controller, LCD Controller, and DMA clocks
stop. The other peripheral units continue to function during the Frequency Change Sequence. This
mode is intended to be used to change the frequency from the default condition at initial boot-up. It
may also be used as a power-saving feature used to allow the processor to run at the minimum
required frequency when the software requires major changes in frequency.
3.4.7.1Preparing for a Frequency Change Sequence
Software must complete the following steps before it initiates the Frequency Change Sequence:
Intel® PXA255 Processor Developer’s Manual3-11
Clocks and Power Manager
1. Configure the Memory Controller to ensure SDRAM contents are maintained during the
Frequency Change Sequence. The Memory Controller’s refresh timer must be programmed to
match the maximum refresh time associated with the slower of two frequencies (current and
desired). The SDRAM divide by two must be set to a value that prevents the SDRAM
frequency from exceeding the specified frequency. For example, to change from 100/100 to
133/66, the SDRAM bus must be set to divide by two before the frequency change. To change
from 133/66 to 100/100, the SDRAM must be set to one-to-one after the frequency change
sequence is completed. See Section 6, “Memory Controller” for more details.
2. Disable the LCD Controller or configure it to avoid the effects of an interruption in the LCD
clocks and data from the processor.
3. Configure peripheral units to handle a lack of DMA service for up to 500 µs. If a peripheral
unit can not function for 500 µs without DMA service, it must be disabled.
4. Disable peripheral units that can not accommodate a 500 µs interrupt latency. The interrupts
generated during the Frequency Change Sequence are serviced when the sequence exits.
5. Program the CCCR (Section 3.6.1, “Core Clock Configuration Register (CCCR)”) to reflect
the desired frequency.
3.4.7.2Invoking the Frequency Change Sequence
To invoke the Frequency Change Sequence, software must set FCS in the CCLKCFG (See
Section 3.7.1). When software sets FCS, it may also set or clear other bits in CCLKCFG. If
software sets the TURBO bit in the same write, the CPU enters Turbo Mode when the Frequency
Change Sequence exits.
After software sets the FCS:
1. The CPU clock stops and interrupts to the CPU are gated.
2. The Memory Controller completes all outstanding transactions in its buffers and from the
CPU. New transactions from the LCD or DMA controllers are ignored.
3. The Memory Controller places the SDRAM in self-refresh mode.
Note:Program the Memory Controller to ensure the correct self-refresh time for SDRAM, given the
slower of the current and desired clock frequencies.
3.4.7.3Behavior During the Frequency Change Sequence
In the frequency change sequence, the processor’s PLL clock generator is in the process of locking
to the correct frequency and cannot be used. This means that interrupts cannot be processed.
Interrupts that occur during the frequency change sequence are serviced after the processor’s PLL
has locked. The 95.85 MHz and 147.46 MHz PLL clock generators are active and peripherals,
except the memory, LCD, and DMA controllers, may continue to operate normally, provided they
can accommodate the inability to process DMA or interrupt requests. DMA or interrupt requests
are not recognized until the frequency change sequence is complete.
The Imprecise Data Abort is also not recognized and if nVDD_FAULT or nBATT_FAULT is
asserted, the assertion is ignored until the Frequency Change Sequence exits. This means that the
processor does not enter Sleep Mode until the Frequency Change Sequence is complete.
3-12 Intel® PXA255 Processor Developer’s Manual
3.4.7.4Completing the Frequency Change Sequence
The Frequency Change Sequence exits when any Reset is asserted. In Hardware and Watchdog
Resets, the Reset entry and exit sequences take precedence over the Frequency Change Sequence
and the PLL resumes in its Reset condition. In GPIO Reset, the Reset exit sequence is delayed
while the PLL relocks and the frequency is set to the desired frequency of the Frequency Change
Sequence.
If the Watchdog Timer is enabled during the Frequency Change Sequence, set the Watchdog Match
Register to ensure that the Frequency Change Sequence completes before the Watchdog Reset is
asserted.
If Hardware or Watchdog Reset is asserted during the Frequency Change Sequence, the DRAM
contents are lost because all states, including Memory Controller configuration and information
about the previous Frequency Change Sequence, are reset. If GPIO Reset is asserted during the
Frequency Change Sequence, the SDRAM contents will be lost during the GPIO Reset exit
sequence if the SDRAM is not in self-refresh mode and the exit sequence exceeds the refresh
interval.
Normally, the Frequency Change Sequence exits in the following sequence:
1. The processor’s PLL clock generator is reprogrammed with the desired values, which are in
the CCCR, and begins to relock to those values.
Clocks and Power Manager
Note: This sequence occurs even if the before and after frequencies are the same.
2. The internal PLL clock generator for the processor clock waits for stabilization. Refer to the
Intel® PXA250 and PXA210 Application Processors Electrical, Mechanical, and Thermal
Specification for details.
3. The CPU clocks restart and the CPU resumes operation at the state indicated by the TURBO
bit (either Run or Turbo Mode). Interrupts to the CPU are no longer gated.
4. The FCS bit is not automatically cleared. To prevent an accidental return to the Frequency
Change Sequence, software must not immediately clear the FCS bit. The bit must be cleared
on the next required write to the register.
5. Values may be written to the CCCR, but they are ignored until the Frequency Change
Sequence is re-entered.
6. The SDRAM must transition out of self-refresh mode and into its idle state. See Section 6,
“Memory Controller” for details on configuring the SDRAM interface.
3.4.833-MHz Idle Mode
33-MHz idle mode has the lowest power consumption of any idle mode. The run mode frequency
selected in the Core Clock Configuration Register (CCCR) directly affects the processor idle mode
power consumption. Faster run mode frequencies consume more power. 33-MHz idle mode places
the processor a special low speed run mode before entering idle. This is similar to normal idle since
the CPU core clock can be stopped during periods of processor inactivity and continue to monitor
on- and off-chip interrupt service requests. 33-MHz idle limitations are:
• Peripherals will not function correctly and should be disabled before entering this mode.
• A Frequency Change Sequence must be performed upon entry to and exit from 33-MHz idle
mode.
Intel® PXA255 Processor Developer’s Manual3-13
Clocks and Power Manager
• SDRAM is placed in self refresh before entering 33-MHz idle mode, because SDRAM cannot
be refreshed correctly in 33-MHz idle mode. Carefully consider the processor interrupt
behavior when the SDRAM in self refresh. To allow the interrupts to occur while SDRAM is
in self refresh, set the I and F bits in the CPSR. This allows interrupts to wake the processor
from idle mode without jumping to the interrupt handler. When the system’s SDRAM is no
longer in self refresh, the I and F bits can be cleared and the interrupt is handled.
• Because nBATT_FAULT and nVDD_FAULT can cause a data abort interrupt, the function of
these pins in 33-MHz idle mode also needs special consideration. Either the Imprecise Data
Abort Enable (IDAE) bit in the Power Manager Control Register (PMCR) must be clear,
(causing the processor to immediately enter sleep mode if either nBATT_FAULT or
nVDD_FAULT are asserted) or take software precautions to avoid starting execution in or
trying to use SDRAM while it is in self refresh.
During 33-Mhz idle mode these system unit modules are functional:
• Real-time clock
• Operating system timer
• Interrupt controller
• General purpose I/O
• Clocks and power manager
• Flash ROM/SRAM
Unlike normal idle mode, in 33-MHz idle mode all other peripheral units cannot be used, including
SDRAM, LCD and DMA controllers.
3.4.8.1Entering 33-MHz Idle Mode
During idle mode, the processor core clocks stop. Before the clocks stop, all critical applications
must be finished and peripherals turned off. If software is executing from SDRAM, the last three of
the following steps must be loaded into the cache before being performed.
1. Set the I and F bits in the CPSR register to mask all interrupts
2. Place the SDRAM into self refresh mode
3. Perform a frequency change sequence to 33MHz mode. The CCCR value for this mode is
0x13F
4. Enter idle mode by selecting the PWRMODE[M] bit (refer to Section 3.7.2)
3.4.8.2Behavior in 33-MHz Idle Mode
In 33-MHz idle mode the CPU clocks are stopped. While in 33-MHz idle mode these features of
the processor all operate normally: the RTC timer, the OS timers including the watchdog timer, and
the GPIO interrupt capabilities.
When ICCR[DIM] is cleared, any enabled interrupt wakes up the processor. When ICCR[DIM] is
set, only unmasked interrupts cause wake-up.
Enabled interrupts are interrupts that are allowed at the unit level. Masked interrupts are interrupts
that are prevented from interrupting the core based on the Interrupt Controller Mask Register
(ICMR).
3-14 Intel® PXA255 Processor Developer’s Manual
3.4.8.3Exiting 33-MHz Idle Mode
The 33-MHz idle mode exit procedure is the same as the exit procedure for normal idle mode.
However, because the I and F bits are set in the CPSR, the processor does not immediately jump to
the interrupt vector. Instead processing continues with the instruction following the last executed
instruction before 33-MHz idle mode was entered. If execution occurs from SDRAM, steps 1 and 2
must have been previously loaded into the instruction cache. The steps below are then taken:
1. Perform a frequency change to a supported run mode frequency, greater or equal to 100 MHz.
2. Take the SDRAM out of self refresh.
3. Clear the I and F bits in the CPSR. Execution immediately jumps to the pending interrupt
handler.
3.4.9Sleep Mode
Sleep Mode offers lower power consumption at the expense of the loss of most of the internal
processor state. In Sleep Mode, the processor goes through an orderly shut-down sequence and
power is removed from the core. The Power Manager watches for a wake-up event and, after it
receives one, re-establishes power and goes through a reset sequence. During Sleep Mode, the RTC
and Power Manager continue to function. Pin states can be controlled throughout Sleep Mode and
external SDRAM is preserved because it is in self-refresh mode.
Clocks and Power Manager
Because all activity on the processor except the RTC stops when Sleep Mode starts, peripherals
must be disabled to allow an orderly shutdown. When Sleep Mode exits, the processor’s state resets
and processing resumes in a boot-up mode.
3.4.9.1Sleep Mode External Voltage Regulator Requirements
To implement Sleep Mode in the simplest manner, the External Voltage Regulator, which supplies
power to the processor’s internal elements, must have the following characteristics:
• A power enable input pin that enables the primary supply output connected to VCC and
PLL_VCC. This pin must be connected to the processor’s PWR_EN pin. To support fast sleep
walk-up by maintaining power during sleep, the regulator should be software configurable to
ignore PWR_EN. When PWR_EN is not used, VCC and PLL_VCC may be powered on
before or simultaneously with VCCN and VCCQ. In this configuration, when PWR_EN is
deasserted, the core regulator must be able to maintain regulation when the load power is as
little as 0.5 mW. Core supply current during sleep will vary with voltage and temperature.
• When core power is enabled during sleep, the power management IC or logic that generates
nVDD_FAULT must assert this signal when any supply including VCC and PLL_VCC falls
below the lower regulation limit during sleep. nVDD_FAULT must not be deasserted until all
supplies are in regulation again since there is no power supply stabilization delay during the
fast sleep walk-up sequence. If nVDD_FAULT is asserted during fast sleep walk-up, then the
processor returns to Sleep Mode.
• When configured to disable the core supply to save power during sleep, the core regulator’s
output must be driven to ground when PWR_EN goes low.
• Higher-voltage outputs connected to VCCQ and VCCN are continuously driven and do not
change when the PWR_EN pin is asserted.
Intel® PXA255 Processor Developer’s Manual3-15
Clocks and Power Manager
3.4.9.2Preparing for Sleep Mode
Before Sleep Mode starts, software must take the following steps:
1. The Memory Controller must be configured to ensure SDRAM contents are maintained during
Sleep Mode. See Section 6, “Memory Controller” for details.
2. If a graceful shutdown is required for a peripheral, the peripheral must be disabled before
Sleep Mode asserts. This includes monitoring DMA transfers to and from peripherals or
memories to ensure they are completed. All other peripherals need not be disabled, since they
are held in their reset states internally during Sleep Mode.
3. The following Power Manager registers must be set up for proper sleep entry and exit:
— PM GPIO Sleep State registers (PGSR0, PGSR1, PGSR2). To avoid contention on the bus
when the processor attempts to wake up, ensure that the chip selects are not set to 0 during
sleep mode. If a GPIO is used as an input, it must not be allowed to float during sleep
mode. The GPIO can be pulled up or down externally or changed to an output and driven
with the unasserted value.
— PM General Configuration Register Float bits [FS/FP] must be configured appropriately
for the system. The General Configuration Register Float bits must be cleared on wake up.
To avoid contention on the bus when the processor attempts to wake up, ensure that the
chip selects are not set to 0 during sleep mode. The PCFR[OPDE] bit must be cleared to
leave the 3.6864 MHz enabled during sleep if the fast walk-up sleep configuration is
selected by setting the PMFW[FWAKE] bit.
— PMFW configuration register must be set to select between the standard and fast sleep
wakeup configurations. Set PMFW[FWAKE] to 1 to disable the 10 ms power supply
stabilization delay during sleep wakeup if power is maintained during sleep. This
configuration reduces the sleep wakeup time to approximately 650 µs.
4. Before the IDAE bit is set, software must configure an imprecise data abort exception handler
to put the processor into sleep mode when a data abort occurs in response to nVDD_FAULT or
nBATT_FAULT assertion. This abort exception event indicates that the processor is in peril of
losing its main power supply.
5. The following Power Manager registers must be set up to detect wake-up sources and
oscillator activity:
— PM GPIO Sleep State registers (PGSR0, PGSR,1 and PGSR2).
— OPDE bit in the Power Manager Configuration Register (PCFR)
— IDAE bit in PMCR
Note:The PCFR[OPDE] bit must be cleared to enable the 3.6864 MHz oscillator during sleep when fast
sleep wakeup is selected by setting the PMFW[FWAKE] bit.
3.4.9.3Entering Sleep Mode
Software uses the PWRMODE register to enter sleep mode (See Section 3.7.2).
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Clocks and Power Manager
If the external voltage regulator is failing or the main battery is low or missing, some systems must
enter sleep mode quickly. When nBATT_FAULT or nVDD_FAULT is asserted, the system is
required to shut down immediately.
To allow the assertion of nVDD_FAULT or nBATT_FAULT to cause an imprecise data abort, set
the Imprecise Data Abort Enable (IDAE) bit in the PMCR. Setting the IDAE bit in the PMCR will
result in software executing the data abort handler routine as part of entering sleep mode. If the
IDAE bit is clear, the processor enters sleep mode immediately without executing the abort handler
routine.
Note: Using an exception handler to invoke sleep in response to a power fault event is advantageous
because software can clear the PMFW[FWAKE] bit and configure the power management IC to
use PWR_EN to disable the core power supply during sleep to minimize power consumption from
a critically low battery.
PSSR[VFS] and PSSR[BFS] can not be used prior to entering Sleep Mode to determine which type
of fault occurred, VDD fault or battery fault, respectively. If either nVDD_FAULT or
nBATT_FAULT signals are asserted or if both are asserted at the same time (and the IDAE bit of
the PMCR is set), the software data abort handler will be called. Since there is only one common
data abort handler, software must first determine if one of the two nVDD_FAULT or
nBATT_FAULT assertion events resulted in an imprecise data abort by reading Coprocessor 7,
Register 4, Bit 5 (PSFS). If the PSFS bit is cleared, neither a nVDD_FAULT or nBATT_FAULT
assertion occurred and the data abort handler was called for some other reason. If the PSFS bit is
set, this indicates either a nVDD_FAULT or nBATT_FAULT assertion occurred, but it is not
possible to determine which of the two faults was asserted. For either case, nVDD_FAULT or
nBATT_FAULT assertion, software should shut the system down as quickly as possible by
performing the steps outlined below to enter Sleep Mode.
Note: All addresses (data and instruction) used in the abort handler routines should be resident and
accessible in the memory page tables, i.e. system software developers should ensure no further
aborts occur while executing an abort handler. The processor does not support recursive (nested)
aborts. The system must not assert nBATT_FAULT or nVDD_FAULT signals more than once
before nRESET_OUT is asserted. System software can not return to normal execution following a
nBATT_FAULT or nVDD_FAULT. If a battery or VDD fault occurs while executing in the abort
mode, the abort handler is reentered. This condition of a recursive abort occurrence can be detected
in software by reading the Saved Program Status Register (SPSR) to see if the previous context
was executing in abort mode.
To enter Sleep Mode, software must complete the following sequence:
1. Software uses external memory and the Power Manager Scratch Pad Register (PSPR) to
preserve critical states.
2. Software sets Sleep Mode in PWRMODE[M]. An interrupt immediately aborts Sleep Mode
and normal processing resumes.
3. The CPU waits until all instructions in the pipeline are complete.
4. The Memory Controller completes outstanding transactions in its buffers and from the CPU.
New transactions from the LCD or DMA controllers are ignored.
5. The Memory Controller places the SDRAM in self-refresh mode.
6. The Power Manager switches the GPIO output pins to their sleep state. This sleep state is
programmed in advance by loading the Power Manager GPIO Sleep State registers (PGSR0,
PGSR1, and PGSR2). To avoid contention on the bus when the processor attempts to wake up,
ensure that the chip selects are not set to 0 during sleep mode.
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Clocks and Power Manager
7. The CPU clock stops and power is removed from the Core.
8. PWR_EN is deasserted.
When the Power Manger get the indication from the Memory Controller that it has finished its
outstanding transactions and has put the SDRAM into self-refresh, there are eight core clock cycles
before the GPIOs latch the PGSR values and four core clock cycles after that, nRESET_OUT
asserts low.
In some systems the Imprecise Data Abort latency lasts longer than the residual charge in the failed
power supply can sustain operation. This normally only occurs when the processor is in a Power
Mode or Sequence that requires that the processor exit before Sleep Mode starts. Frequency
Change Sequence is an example of such a Power Sequence. In these Power Modes and Sequences,
the IDAE bit must not be set. This allows the processor to enters Sleep Mode immediately but any
critical states in the processor are lost.
If the IDAE bit is not set and the nVDD_FAULT or nBATT_FAULT pin is asserted, the Sleep
Sequence begins at Step 4.
3.4.9.4Behavior in Sleep Mode
In Sleep Mode, all processor and peripheral clocks are disabled, except the RTC. The processor
does not recognize interrupts or external pin transitions except valid wake-up signals, Reset
signals, and the nBATT_FAULT signal.
If the nBATT_FAULT signal is asserted while in Sleep Mode, GPIO[1:0] are set as the only valid
wake-up signals.
The Power Manager watches for wake up events programmed by the CPU before Sleep Mode
starts or set by the Power Manager it detects a fault condition. In order to detect a rising-edge or
falling-edge on a GPIO pin, the rising- or falling-edge must be held for more than one full
32.768 kHz clock cycle. The Power Manager takes three 32.768 kHz clock cycles to acknowledge
the GPIO edge and begin the wake up sequence.
Refer to Table 2-6, “Pin & Signal Descriptions for the PXA255 Processor” on page 2-9 for the
PXA255 processor pin states during sleep mode reset and other resets.
3.4.9.5Exiting Sleep Mode
Sleep Mode exits when Hardware Reset is asserted. Hardware Reset’s entry and exit sequences
take precedence over Sleep Mode.
Note:If Hardware Reset is asserted during Sleep Mode, the DRAM contents are lost because all states,
including Memory Controller configuration and information about the previous Sleep Mode, are
reset.
Normally, Sleep Mode exits in the following sequence. Any time the nBATT_FAULT pin is
asserted, the processor returns to Sleep Mode. The nVDD_FAULT pin is ignored until the external
power supply stabilization timer expires.
1. A pre-programmed wake up event from an enabled GPIO or RTC source occurs. If the
nBATT_FAULT pin is asserted, the wake up source is ignored.
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Clocks and Power Manager
2. The PWR_EN signal is asserted and the Power Manager waits for the external power supply to
stabilize. If nVDD_FAULT is asserted after the external power supply timer expires, the
processor returns to Sleep Mode.
3. If PCFR[OPDE] and OSCC[OON] were set when Sleep Mode started, the 3.6864 MHz
oscillator is enabled and stabilizes. Otherwise, the 3.6864 MHz oscillator is already stable and
this step is bypassed.
4. The processor’s PLL clock generator is reprogrammed with the values in the CCCR and
stabilizes.
5. The Sleep Mode configuration in PWRMODE[M] is cleared.
6. The processor’s internal reset is deasserted and the CPU begins a normal boot sequence. When
the normal boot sequence begins, all of the processor’s units, except the RTC and portions of
the Clocks and Power Manager and the Memory Controller, return to their predefined reset
settings.
7. The nRESET_OUT pin is deasserted. This indicates that the processor is about to perform a
fetch from the Reset vector.
8. Clear PSSR[PH] before accessing GPIOs, including chip selects that are muxed with GPIOs.
9. Clear PCFR[FS] and PCFR[FP] if either was set before Sleep Mode was triggered.
10. The SDRAM must transition out of self-refresh mode and into its idle state. See Section 6,
“Memory Controller” for details on configuring the SDRAM interface.
11. Software must examine the RCSR, to determine what caused the reboot, and the Power
Manager Sleep Status register (PSSR), to determine what triggered Sleep Mode.
12. If the PSPR was used to preserve any critical states during Sleep Mode, software can now
recover the information.
If the nVDD_FAULT or nBATT_FAULT pin is asserted during the Sleep Mode exit sequence, the
system re-enters Sleep Mode in the following sequence:
1. Regardless of the state of the IDAE bit:
— All GPIO edge detects and the RTC alarm interrupt are cleared.
— The Power Manager wake-up source registers (PWER, PRER, and PFER) are loaded with
0x0000 0003, their wake-up fault state. This limits the potential wake-up sources to a
rising or falling edge on GPIO[0] or GPIO[1]. The wake-up fault state prevents spurious
events from causing an unwanted wake-up while the battery is low or the power supply is
at risk. The fault state is also the default state after a Hardware Reset.
2. The PLL clock generators are disabled.
3. If the OPDE bit in the PCFR is set and the OON bit in the OSCC is set, the 3.6864 MHz
oscillator is disabled. If the oscillator is disabled, Sleep Mode consumes less power. If it is
enabled, Sleep Mode exits more quickly.
4. An internal reset is generated to the core and most peripheral modules. This reset asserts the
nRESET_OUT pin.
5. The PWR_EN pin is deasserted. If PMFW[FWAKE] is cleared, the system must respond by
grounding the VCC and PLL_VCC power supplies to minimize power consumption.
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Clocks and Power Manager
3.4.10Power Mode Summary
Tab le 3 -4 shows the actions that occur when a Power Mode is entered. Table 3-5 shows the actions
that occur when a Power Mode is exited. In the tables, an empty cell means that the power mode
skips that step. Tabl e 3-6 shows the expected behavior for power supplies in each power mode.
Table 3-4. Power Mode Entry Sequence Table
Step
1Software writes a bit in CP14xxxxx
2The CPU waits until all instructions to be completedxxxxx
3Wake up sources are cleared and limited to GP[1:0]x
4The PM places GPIOs in their sleep statesxx
5The Memory Controller finishes all outstanding transactionsxxx
6The Memory Controller places SDRAMs in self-refreshxxx
7The PLL is disabledxxx
8If OPDE and OOK bits are set, disable 3.6864 MHz oscillatorxx
9Internal Reset to most modules. nRESET_OUT assertedxx
10PWR_EN is deasserted. Power is cut offxx
11Power to most I/O pins is cut off
1: Fault Sleep Mode starts if IDAE is clear and nBATT_FAULT or nVDD_FAULT is asserted.
.
Description of Action
Table 3-5. Power Mode Exit Sequence Table (Sheet 1 of 2)
Step
1Wake up source or Interrupt is receivedxxx
2Power to I/O pins restored
3PWR_EN is assertedxx
4External power rampxx
5Enable 3.6864 MHz oscillator if OPDE and OOK are setxx
Wait for 3.6864 MHz oscillator to stabilize if OPDE and OOK
6
are set
7Enable PLL with new frequencyxxx
8Wait for PLL stabilizationxxx
9Wait for internal stabilizationxx
10Clear CP14 bitxx
Description of Action
Sleep
Tur bo
Turbo
Idle
Freq Change
Run (from Turbo)
Idle
Freq Change
Run (from Turbo)
1
Sleep
Fault
Sleep
1
Sleep
Fault
xx
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Table 3-5. Power Mode Exit Sequence Table (Sheet 2 of 2)
Clocks and Power Manager
Step
11Deassert nRESET_OUTxx
12Restart CPU clocks, enable interruptsxxxxxx
1: Fault Sleep Mode starts if IDAE is clear and nBATT_FAULT or nVDD_FAULT is asserted.
Description of Action
Tur bo
Idle
Run (from Turbo)
Sleep
Freq Change
Sleep
1
Fault
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Clocks and Power Manager
Table 3-6. Power and Clock Supply Sources and States During Power Modes
Power Mode
Module
Supply Source
TurboRunIdle
PwCkPw Ck Pw Ck Pw Ck Pw Ck Pw Ck
Freq
Change
Sleep
CPU,
Caches,
Buffers
Memory
Controller
LCD
Controller
DMA
Controller
General
Periphs.
OS timer
Interrupts
Real Time
Clock
Power
Manager
GP[3:0], PM
pads, Osc
pads
General IOH
KEY:
T: Tu r b o c l ock
R: Run clock
V: Module powered off VCC.
I: Module powered off internal regulator
H: Module powered off VCCQ or VCCN
D: Module is dynamic or actively clocked
S: Module is static or clocks are gated.
VCC
VCC/
Reg
(V/R)
HV/
Batt
(H/B)
Run/
Turbo
(R/T)
Mem
PLL
3.686
MHz Osc
32.768
kHz Osc
Dynamic/
Static
(D/S)
T
On
OnOnOn
VOnVOnVOnVOn I On
HDHDHDHDHS
On
R
On
Off
On
changing
Off Off
On
3.5Power Manager Registers
This section describes the 32-bit registers that control the Power Manager.
3-22 Intel® PXA255 Processor Developer’s Manual
3.5.1Power Manager Control Register (PMCR)
The PMCR is used to select the manner in which Sleep Mode is entered when the nVDD_FAULT
or the nBATT_FAULT pin is asserted low. When the IDAE bit is set, an Imprecise Data Abort
indication is sent to the CPU. The CPU then performs an abort routine. Software must ensure that
the abort routine sets the Sleep Mode configuration in the PWRMODE register (see Section 3.7.2,
“Power Mode Register (PWRMODE)”). The IDAE bit is cleared in any Reset and when Sleep
Mode exits. Software may also clear the IDAE bit when necessary. The PMCR must be protected
through Memory Management Unit (MMU) permissions.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Read undefined and must always be written with zeroes.
Imprecise Data Abort Enable.
0 – Allow immediate entry to sleep mode when nVDD_FAULT or nBATT_FAULT is
asserted.
1 – Force imprecise data abort signal to CPU to allow software to enter sleep mode
when nVDD_FAULT or nBATT_FAULT is asserted. Recommended mode.
Cleared on hardware, watchdog, and GPIO reset, or when sleep mode exits.
IDAE
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3.5.2Power Manager General Configuration Register (PCFR)
The PCFR contains bits used to configure functions in the processor. When the OPDE bit is set, it
allows the 3.6864 MHz oscillator to be disabled during Sleep Mode. The OPDE bit is cleared in
Hardware, Watchdog, and GPIO Resets. The Float PCMCIA (FP) and Float Static Memory (FS)
bits control the state of the PCMCIA control pins and the static memory control pins during Sleep
Mode.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Read undefined and must always be written with zeroes.
Float Static Chip Selects during Sleep Mode.
0 = Static Chip Select pins are not floated in Sleep Mode. nCS[5:1] are driven to the
state of the appropriate PGSR register bits. nCS[1], nWE, and nOE are driven high.
1 = Static Chip Select pins are floated in Sleep Mode. The pins nCS[5:0], nWE, and
nOE are affected.
Cleared on Hardware, Watchdog, and GPIO Resets.
Float PCMCIA controls during Sleep Mode.
0 = PCMCIA pins are not floated in Sleep Mode. They are driven to the state of the
appropriate PGSR register bits.
1 = The PCMCIA signals: nPOE, nPWE, nPIOW, nPIOR, and nPCE[2:1] are floated in
Sleep Mode. nPSKTSEL and nPREG are derived from address signals and assume
the state of the address bus during Sleep Mode.
Cleared on Hardware, Watchdog, and GPIO Resets.
3.6864 MHz oscillator power-down enable.
If the 32.7686 kHz crystal is disabled because the OON bit in the Oscillator
Configuration Register is 0, OPDE is ignored and the 3.6864 MHz oscillator is not
disabled.
0 = Do not stop the oscillator during Sleep Mode.
1 = Stop the 3.6864 MHz oscillator during Sleep Mode.
Cleared on Hardware, Watchdog, and GPIO Resets.
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Clocks and Power Manager
3.5.3Power Manager Wake-Up Enable Register (PWER)
Table 3-9 shows the location of all wake up source enable bits in the Power Manager Wake-Up
Enable Register (PWER). If a GPIO is to be used as a wake up source from Sleep, it must be
programmed as an input in the GPDR and either one or both of the corresponding bits in the PRER
and PFER must be set. When the IDAE bit is zero and a fault condition is detected on the
nVDD_FAULT or nBATT_FAULT pin, PWER is set to 0x0000 0003 and only allows GP[1:0] as
wake-up sources. When the IDAE bit is set, fault conditions on the nVDD_FAULT or
nBATT_FAULT pins do not affect wake-up sources. PWER is also set to 0x0000 0003 in
Hardware, Watchdog, or GPIO Resets.
Software should enable wakeups only for those GPIO pins that are configured as inputs during
sleep. Any GPIO pins that are configured as outputs during sleep, should have their associated
wake enable bits set to logic zero in all three PMU wake enable registers (PWER, PRER, and
PFER).
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
The PRER, shown in Table 3-10, determines whether the GPIO pin enabled with the PWER
register causes a wake up from sleep mode on that GPIO pin’s rising edge. When PWER[IDAE] is
zero and a fault condition is detected on the nVDD_FAULT or nBATT_FAULT pin, PRER is set to
0x0000_0003. This enables rising edges on GP[1:0] to act as wake up sources. When
PWER[IDAE] is set, fault conditions on the nVDD_FAULT or nBATT_FAULT pins do not affect
wake-up sources. PRER is also set to 0x0000_0003 in hardware, watchdog, and GPIO resets.
Software should enable wakeups only for those GPIO pins that are configured as inputs during
sleep. Any GPIO pins that are configured as outputs during sleep, should have their associated
wake enable bits set to logic zero in all three PMU wake enable registers (PWER, PRER, and
PFER).
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
The PFER, Table 3- 11, determines if the GPIO pin enabled with the PWER causes a wake up from
sleep mode on that GPIO pin’s falling edge. When PWER[IDAE] is zero and a fault condition is
detected on the nVDD_FAULT or nBATT_FAULT pin, PFER is set to 0x0000_0003. This enables
falling edges on GP[1:0] to act as wake up sources. When PWER[IDAE] is set, fault conditions on
the nVDD_FAULT or nBATT_FAULT pins do not affect wake-up sources. PFER is also set to
0x0000_0003 during hardware, watchdog, and GPIO resets.
Software should enable wakeups only for those GPIO pins that are configured as inputs during
sleep. Any GPIO pins that are configured as outputs during sleep, should have their associated
wake enable bits set to logic zero in all three PMU wake enable registers (PWER, PRER, and
PFER).
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Read undefined and must always be written with zeroes.
Sleep mode Falling-edge Wake-up Enable
0 – Wake up due to GPx falling-edge detect disabled.
1 – Wake up due to GPx falling-edge detect enabled.
Set to 0x0003 on hardware, watchdog, and GPIO resets.
FE14
FE1
FE0
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3.5.6Power Manager GPIO Edge Detect Status Register (PEDR)
The PEDR, Table 3-12, indicates which of the GPIO pins enabled through the PWER, PRER, and
PFER registers caused a wake up from sleep mode. The bits in PEDR can only be set on a rising or
falling edge on a given GPIO pin. If PRER is set, the bits in PEDR can only be set on a rising edge.
If PFER is set, the bits in PEDR can only be set on a falling edge. To reset a bit in PEDR to zero,
write a 1 to it. The PEDR bits are reset to zero in hardware, watchdog, and GPIO resets.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Read undefined and must always be written with zeroes.
Sleep mode Edge Detect Status
0 – Wake up on GPx not detected.
1 – Wake up due to edge on GPx detected.
Cleared by hardware, watchdog, and GPIO resets. Cleared by writing a 1.
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Clocks and Power Manager
3.5.7Power Manager Sleep Status Register (PSSR)
The PSSR, shown in Table 3-13, contains the following status flags:
• Software Sleep Status (SSS) flag is set when the sleep mode configuration in the PWRMODE
register is set and sleep mode starts (see Section 3.7.2).
• Battery Fault Status (BFS) bit is set after wake up any time the nBATT_FAULT pin is asserted
(even when the processor is already in sleep mode).
• VDD Fault Status (VFS) bit is set after wake up when the nVDD_FAULT pin is asserted and
causes the processor to enter sleep mode. The VFS bit is not set if software starts the sleep
mode and then the nVDD_FAULT pin is asserted.
• Peripheral Control Hold (PH) bit is set when sleep mode starts and indicates that the GPIO
pins are retaining their sleep mode state values.
• Read Disable Hold (RDH) bit is set in hardware, GPIO, and watchdog resets and sleep mode.
The RDH bit indicates that all the processor’s GPIO input paths are disabled. To allow a GPIO
input pin to be enabled, software must reset the RDH bit by writing a one to it. Clearing RDH
also disables the 10 K to 60 K GPIO pull-up resistors that are present during and after
hardware, GPIO and watchdog reset. Sleep mode disables the GPIO input path, but the pull-up
resisters are not re-enabled in this case.
To clear a status flag write a 1 to it. Writing a 0 to a status bit has no effect. Hardware, watchdog,
and GPIO resets clear or set the PSSR bits.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
0 – GPIO pins are configured according to their GPIO configuration
1 – Receivers of all GPIO pins that can act as inputs are disabled and following a
5RDH
4PH
3—reserved
hardware, GPIO, or watchdog reset, internal GPIO pull-ups are active. Must be
cleared by the processor after the peripheral and GPIO interfaces are configured
but before they are used.
Set by hardware, watchdog, and GPIO resets and sleep mode. Cleared by writing a 1.
Peripheral Control Hold.
0 – GPIO pins are configured according to their GPIO configuration
1 – GPIO pins are being held in their sleep mode state. Set when sleep mode starts.
Must be cleared by the processor after the peripheral interfaces have been
configured but before they are actually used by the processor.
Cleared by hardware, watchdog, and GPIO resets. Cleared by writing a 1.
0 – nVDD_FAULT pin has not been asserted since it was last cleared by a reset or the
CPU.
2VFS
1BFS
0SSS
1 – nVDD_FAULT pin was asserted in Run or idle mode and caused the chip to enter
sleep mode; bit is set only after wake up.
This bit is not set when nVDD_FAULT is asserted while in sleep mode.
Cleared by hardware, watchdog, and GPIO resets.
Battery Fault Status.
0 – nBATT_FAULT pin has not been asserted since it was last cleared by a reset or the
CPU.
1 – nBATT_FAULT pin has been asserted; bit is set only after wake up.
This bit can be set when nBATT_FAULT is asserted while in sleep mode.
Cleared by hardware, watchdog, and GPIO resets.
Software Sleep Status.
0 – Software has not entered sleep mode through the sleep mode bit since the SSS
was last cleared by a reset or the CPU.
1 – Chip was placed in sleep mode by setting the sleep mode bit.
Cleared by hardware, watchdog, and GPIO resets.
PH
RDH
VFS
reserved
3.5.8Power Manager Scratch Pad Register (PSPR)
BFS
SSS
The PM contains a 32-bit register that can be used to save processor configuration information in
any desired format. The PSPR, shown in Table 3-14, is a holding register that is powered during
sleep mode and is reset by hardware, watchdog, and GPIO resets. During run and turbo modes, any
value can be written to PSPR. The value can be read after sleep mode exits. The value in PSPR can
be used to represent the processor’s configuration before sleep mode is invoked.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
3.5.9Power Manager Fast Sleep Walk-up Configuration Register
(PMFW)
The PSPR, shown in Table 3-15, provides a single bit called FWAKE which is used to select
between the standard and fast sleep walk-up sequences. The PMFW register is reset by a hardware
reset, GPIO reset, watchdog reset, but is not cleared by the sleep walk-up sequence. Using an
exception handler to invoke sleep in response to a power fault event is advantageous because
software can clear the PMFW[FWAKE] bit and configure the power management IC to use
PWR_EN to disable the core power supply during sleep to minimize power consumption from a
critically low battery. Also, the PCFR[OPDE] bit must be cleared to enable the 3.6864 MHz
oscillator during sleep when fast sleep walk-up is selected by setting the PMFW[FWAKE] bit.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 3-15. PMFW Register Bitmap and Bit Definitions
Read undefined and must always be written with zeroes.
FAST WAKEUP ENABLE
0 – Selects the standard sleep wakeup sequence with a 10 ms power supply
stabilization delay when power is disabled during sleep.
1 – Selects the fast sleep wakeup sequence without a power supply stabilization delay
when power is maintained during sleep.
Cleared by hardware reset.
Reserved
Read undefined and must always be written with zeroes.
Power Manager
3.5.10Power Manager GPIO Sleep State Registers (PGSR0,
PGSR1, PGSR2)
PGSR0, PGSR1, and PGSR2, shown in Table 3-16, Table 3-17, and Table 3-18 allow software to
select the output state of each GPIO pin when the processor goes into sleep mode. When a
transition to sleep mode is required (through software or the nBATT_FAULT or nVDD_FAULT
pin), the contents of the PGSR registers are loaded into the GPIO output data registers that software
normally controls through the GPSR and GPCR registers. Only pins that are already configured as
outputs reflect the new state. All bits in the output registers are loaded. When the processor reenters the run mode, these GPIO pins retain the programmed sleep state until software resets
PSSR[PH]. If a pin is reconfigured from an input to an output, the register’s last contents are driven
onto the pin.
FWAKE
Reserved
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
0 – Pin is driven to a zero during sleep mode
1 – Pin is driven to a one during sleep mode
Cleared by hardware, watchdog, and GPIO resets.
SS84
SS83
SS82
SS81
SS80
SS79
SS78
SS77
SS76
SS75
SS74
SS73
SS72
SS71
SS70
SS69
SS68
SS67
SS66
3.5.11Reset Controller Status Register (RCSR)
The CPU uses the RCSR, shown in Table 3-19, to determine a reset’s last cause or causes. The
processor can be reset in four ways:
• Hardware reset
• Watchdog reset
• Sleep mode
• GPIO reset
Refer to Table 2-4, “Effect of Each Type of Reset on Internal Register State” on page 2-6 for details
of the behavior of different modules during each type of reset.
SS65
SS64
Each RCSR status bit is set by a different reset source and can be cleared by writing a 1 back to the
bit. The RCSR status bits for watchdog reset, sleep mode, and GPIO resets have a hardware reset
state of zero.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
0 – GPIO reset has not occurred since the last time the CPU or hardware reset cleared
3GPR
2SMR
1WDR
0HWR
this bit.
1 – GPIO reset has occurred since the last time the CPU or hardware reset cleared this
bit.
Cleared by hardware reset and by setting to a 1.
Sleep Mode.
0 – Sleep mode has not occurred since the last time the CPU or hardware reset cleared
this bit.
1 – Sleep mode has occurred since the last time the CPU or hardware reset cleared
this bit.
Cleared by hardware reset and by setting to a 1.
Watchdog Reset.
0 – Watchdog reset has not occurred since the last time the CPU or hardware reset
cleared this bit.
1 – Watchdog reset has occurred since the last time the CPU or hardware reset cleared
this bit.
Cleared by hardware reset and by setting to a 1.
Hardware Reset.
0 – Hardware reset has not occurred since the last time the CPU cleared this bit.
1 – Hardware reset has occurred since the last time the CPU cleared this bit.
Set by hardware reset. Cleared by setting to a 1.
GPR
SMR
WDR
HWR
3.6Clocks Manager Registers
The Clocks Manager contains three registers:
• Core Clock Configuration Register (CCCR)
• Clock Enable Register (CKEN)
• Oscillator Configuration Register (OSCC)
3.6.1Core Clock Configuration Register (CCCR)
The CCCR, shown in Table 3-20, controls the core clock frequency, from which the core, memory
controller, LCD controller, and DMA controller frequencies are derived. The crystal frequency to
memory frequency multiplier (L), memory frequency to run mode frequency multiplier (M), and
run mode frequency to turbo mode frequency multiplier (N) are set in this register. The clock
frequencies are shown below.
3-34 Intel® PXA255 Processor Developer’s Manual
Memory frequency = 3.6864 MHz crystal freq. * crystal frequency to memory frequency multiplier
(L)
Run mode frequency = Memory frequency * memory frequency to run mode frequency multiplier
(M)
Turbo mode frequency = run mode frequency * run mode frequency to turbo mode frequency
multiplier (N)
The value for L is chosen based on external memory or LCD requirements and can be constant
while M and N change to allow run and turbo mode frequency changes without disrupting memory
settings. The value for M is chosen based on bus bandwidth requirements and minimum core
performance requirements. The value for N is chosen based on peak core performance
requirements.
Run Mode Frequency to Turbo Mode Frequency Multiplier
Turbo mode Freq. = Run mode frequency * N
000 – reserved
001 – reserved
010 – Multiplier = 1
011 – Multiplier = 1.5
100 – Multiplier = 2
101 – reserved
110 – Multiplier = 3
111 – res erv e d
Set to 010 on hardware and watchdog resets.
Memory Frequency to Run Mode Frequency Multiplier
Memory Freq. = Crystal Freq. * L
00 – reserved
01 – Multiplier = 1 (Run mode frequency is equal to memory frequency)
10 – Multiplier = 2 (Run mode frequency is 2 times the memory frequency)
11 – Multiplier = 3 (Run mode frequency is 4 times the memory frequency)
Set to 01 on hardware and watchdog resets.
Crystal Frequency to Memory Frequency Multiplier
00000 – reserved
00001 – Multiplier = 27 (Memory Frequency is 99.53MHz from 3.6864 MHz crystal)
00010 – reserved
00011 – Multiplier = 36 (Memory Frequency is 132.71MHz from 3.6864 MHz crystal)
00100 – reserved
00101 – Multiplier = 45 (Memory Frequency is 165.89MHz from 3.6864 MHz crystal)
00 110 t o 11111 – res e rved
Set to 00001 on hardware and watchdog resets.
Clocks Manager
Intel® PXA255 Processor Developer’s Manual3-35
Clocks and Power Manager
3.6.2Clock Enable Register (CKEN)
CKEN, shown in Table 3-21, enables or disables the clocks to most of the peripheral units. For
lowest power consumption, the clock to any unit that is not being used must be disabled by writing
a zero to the appropriate bit.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
BTUART Unit Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
These bits are set by hardware reset or watchdog reset
FFUART Unit Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
STUART Unit Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
HWUART Unit Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
SSP Unit Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
AC97 Unit Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
PWM1 Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
PWM0 Clock Enable
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
CKEN11
CKEN13
CKEN12
reserved
reserved
reserved
CKEN2
CKEN1
CKEN0
Intel® PXA255 Processor Developer’s Manual3-37
Clocks and Power Manager
3.6.3Oscillator Configuration Register (OSCC)
The OSCC, shown in Table 3-22, controls the 32.768 kHz oscillator configuration. It contains two
bits, the set-only 32.768 KHz OSCC[OON] and the read-only 32.768 kHz OSCC[OOK].
OSCC[OON] enables the external 32.768 kHz oscillator and can only be set by software. When the
oscillator is enabled, it takes up to 10 seconds for to stabilize. When the oscillator is stabilized, the
processor sets OSCC[OOK].
When OSCC[OOK] is set, the RTC and PM are clocked from the 32.768 KHz oscillator.
Otherwise, the 3.6864 MHz oscillator is used. The OPDE bit, which allows the 3.6864 MHz
oscillator to be disabled in sleep mode, is ignored (treated as if it were clear) if OSCC[OOK] is
clear. OSCC[OOK] can only be reset by a hardware reset.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.