Intel PXA255 User Manual 2

Intel® PXA255 Processor

Developer’s Manual

January, 2004

Order Number: 278693-002

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ii Intel® PXA255 Processor Developer’s Manual

Contents

1 Introduction...................................................................................................................................1-1

1.1 Intel XScale® Microarchitecture Features.........................................................................1-1

1.2 System Integration Features..............................................................................................1-1

1.2.1 Memory Controller ................................................................................................1-2

1.2.2 Clocks and Power Controllers...............................................................................1-2

1.2.3 Universal Serial Bus (USB) Client.........................................................................1-2

1.2.4 DMA Controller (DMAC) .......................................................................................1-3

1.2.5 LCD Controller ......................................................................................................1-3

1.2.6 AC97 Controller ....................................................................................................1-3

1.2.7 Inter-IC Sound (I2S) Controller .............................................................................1-3

1.2.8 Multimedia Card (MMC) Controller .......................................................................1-3

1.2.9 Fast Infrared (FIR) Communication Port...............................................................1-3

1.2.10 Synchronous Serial Protocol Controller (SSPC)...................................................1-4

1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit....................................................1-4

1.2.12 GPIO.....................................................................................................................1-4

1.2.13 UARTs ..................................................................................................................1-4

1.2.14 Real-Time Clock (RTC).........................................................................................1-5

1.2.15 OS Timers.............................................................................................................1-5

1.2.16 Pulse-Width Modulator (PWM) .............................................................................1-5

1.2.17 Interrupt Control....................................................................................................1-5

1.2.18 Network Synchronous Serial Protocol Port...........................................................1-5

2 System Architecture .....................................................................................................................2-1

2.1 Overview............................................................................................................................2-1

2.2 Intel XScale® Microarchitecture Implementation Options.................................................2-2

2.2.1 Coprocessor 7 Register 4 - PSFS Bit ...................................................................2-2

2.2.2 Coprocessor 14 Registers 0-3 - Performance Monitoring.....................................2-3

2.2.3 Coprocessor 14 Register 6 and 7- Clock and Power Management......................2-3

2.2.4 Coprocessor 15 Register 0 - ID Register Definition..............................................2-3

2.2.5 Coprocessor 15 Register 1 - P-Bit ........................................................................2-4

2.3 I/O Ordering.......................................................................................................................2-5

2.4 Semaphores ......................................................................................................................2-5

2.5 Interrupts............................................................................................................................2-5

2.6 Reset .................................................................................................................................2-6

2.7 Internal Registers...............................................................................................................2-7

2.8 Selecting Peripherals vs. General Purpose I/O .................................................................2-7

2.9 Power on Reset and Boot Operation .................................................................................2-8

2.10 Power Management...........................................................................................................2-8

2.11 Pin List...............................................................................................................................2-8

2.12 Memory Map....................................................................................................................2-18

2.13 System Architecture Register Summary..........................................................................2-21

3 Clocks and Power Manager .........................................................................................................3-1

3.1 Clock Manager Introduction...............................................................................................3-1

3.2 Power Manager Introduction..............................................................................................3-2

3.3 Clock Manager...................................................................................................................3-2

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Contents

3.3.1 32.768 kHz Oscillator............................................................................................3-4

3.3.2 3.6864 MHz Oscillator ..........................................................................................3-4

3.3.3 Core Phase Locked Loop .....................................................................................3-4

3.3.4 95.85 MHz Peripheral Phase Locked Loop ..........................................................3-5

3.3.5 147.46 MHz Peripheral Phase Locked Loop ........................................................3-5

3.3.6 Clock Gating .........................................................................................................3-6

3.4 Resets and Power Modes..................................................................................................3-6

3.4.1 Hardware Reset....................................................................................................3-6

3.4.2 Watchdog Reset ...................................................................................................3-7

3.4.3 GPIO Reset ..........................................................................................................3-8

3.4.4 Run Mode .............................................................................................................3-9

3.4.5 Turbo Mode ..........................................................................................................3-9

3.4.6 Idle Mode............................................................................................................3-10

3.4.7 Frequency Change Sequence............................................................................3-11

3.4.8 33-MHz Idle Mode ..............................................................................................3-13

3.4.9 Sleep Mode.........................................................................................................3-15

3.4.10 Power Mode Summary .......................................................................................3-20

3.5 Power Manager Registers ...............................................................................................3-22

3.5.1 Power Manager Control Register (PMCR) .........................................................3-23

3.5.2 Power Manager General Configuration Register (PCFR)...................................3-24

3.5.3 Power Manager Wake-Up Enable Register (PWER)..........................................3-25

3.5.4 Power Manager Rising-Edge Detect Enable Register (PRER) ..........................3-26

3.5.5 Power Manager Falling-Edge Detect Enable Register (PFER) ..........................3-27

3.5.6 Power Manager GPIO Edge Detect Status Register (PEDR).............................3-28

3.5.7 Power Manager Sleep Status Register (PSSR) .................................................3-29

3.5.8 Power Manager Scratch Pad Register (PSPR) ..................................................3-30

3.5.9 Power Manager Fast Sleep Walk-up Configuration Register (PMFW)...............3-31

3.5.10 Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2).........3-31

3.5.11 Reset Controller Status Register (RCSR)...........................................................3-33

3.6 Clocks Manager Registers...............................................................................................3-34

3.6.1 Core Clock Configuration Register (CCCR) .......................................................3-34

3.6.2 Clock Enable Register (CKEN)...........................................................................3-36

3.6.3 Oscillator Configuration Register (OSCC) ..........................................................3-38

3.7 Coprocessor 14: Clock and Power Management ............................................................3-38

3.7.1 Core Clock Configuration Register (CCLKCFG).................................................3-39

3.7.2 Power Mode Register (PWRMODE)...................................................................3-40

3.8 External Hardware Considerations ..................................................................................3-40

3.8.1 Power-On-Reset Considerations........................................................................3-40

3.8.2 Power Supply Connectivity.................................................................................3-40

3.8.3 Driving the Crystal Pins from an External Clock Source.....................................3-41

3.8.4 Noise Coupling Between Driven Crystal Pins and a Crystal Oscillator...............3-41

3.9 Clocks and Power Manager Register Summary..............................................................3-41

3.9.1 Clocks Manager Register Locations...................................................................3-41

3.9.2 Power Manager Register Summary....................................................................3-41

4 System Integration Unit ................................................................................................................4-1

4.1 General-Purpose I/O..........................................................................................................4-1

4.1.1 GPIO Operation....................................................................................................4-1

4.1.2 GPIO Alternate Functions.....................................................................................4-2

4.1.3 GPIO Register Definitions.....................................................................................4-6

iv Intel® PXA255 Processor Developer’s Manual

4.2 Interrupt Controller...........................................................................................................4-20

4.2.1 Interrupt Controller Operation .............................................................................4-20

4.2.2 Interrupt Controller Register Definitions..............................................................4-21

4.3 Real-Time Clock (RTC) ...................................................................................................4-28

4.3.1 Real-Time Clock Operation.................................................................................4-28

4.3.2 RTC Register Definitions ....................................................................................4-29

4.3.3 Trim Procedure ...................................................................................................4-32

4.4 Operating System (OS) Timer .........................................................................................4-34

4.4.1 Watchdog Timer Operation.................................................................................4-35

4.4.2 OS Timer Register Definitions ............................................................................4-35

4.5 Pulse Width Modulator.....................................................................................................4-38

4.5.1 Pulse Width Modulator Operation.......................................................................4-38

4.5.2 Register Descriptions..........................................................................................4-40

4.5.3 Pulse Width Modulator Output Wave Example...................................................4-43

4.6 System Integration Unit Register Summary.....................................................................4-44

4.6.1 GPIO Register Locations....................................................................................4-44

4.6.2 Interrupt Controller Register Locations ...............................................................4-45

4.6.3 Real-Time Clock Register Locations...................................................................4-45

4.6.4 OS Timer Register Locations..............................................................................4-45

4.6.5 Pulse Width Modulator Register Locations.........................................................4-46

Contents

5 DMA Controller.............................................................................................................................5-1

5.1 DMA Description................................................................................................................5-1

5.1.1 DMAC Channels...................................................................................................5-2

5.1.2 Signal Descriptions ...............................................................................................5-2

5.1.3 DMA Channel Priority Scheme .............................................................................5-3

5.1.4 DMA Descriptors...................................................................................................5-5

5.1.5 Channel States .....................................................................................................5-8

5.1.6 Read and Write Order...........................................................................................5-9

5.1.7 Byte Transfer Order ..............................................................................................5-9

5.1.8 Trailing Bytes ......................................................................................................5-10

5.2 Transferring Data.............................................................................................................5-11

5.2.1 Servicing Internal Peripherals.............................................................................5-11

5.2.2 Quick Reference for DMA Programming ............................................................5-13

5.2.3 Servicing Companion Chips and External Peripherals .......................................5-14

5.2.4 Memory-to-Memory Moves.................................................................................5-16

5.3 DMAC Registers ..............................................................................................................5-17

5.3.1 DMA Interrupt Register (DINT) ...........................................................................5-17

5.3.2 DMA Channel Control/Status Register (DCSRx)................................................5-17

5.3.3 DMA Request to Channel Map Registers (DRCMRx) ........................................5-20

5.3.4 DMA Descriptor Address Registers (DDADRx) ..................................................5-20

5.3.5 DMA Source Address Registers .........................................................................5-21

5.3.6 DMA Target Address Registers (DTADRx).........................................................5-22

5.3.7 DMA Command Registers (DCMDx)..................................................................5-23

5.4 Examples.........................................................................................................................5-26

5.5 DMA Controller Register Summary .................................................................................5-28

6 Memory Controller........................................................................................................................6-1

6.1 Overview............................................................................................................................6-1

6.2 Functional Description .......................................................................................................6-2

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Contents

6.2.1 SDRAM Interface Overview..................................................................................6-2

6.2.2 Static Memory Interface / Variable Latency I/O Interface .....................................6-3

6.2.3 16-Bit PC Card / Compact Flash Interface ...........................................................6-4

6.3 Memory System Examples ................................................................................................6-4

6.4 Memory Accesses .............................................................................................................6-7

6.4.1 Reads and Writes .................................................................................................6-8

6.4.2 Aborts and Nonexistent Memory ..........................................................................6-8

6.5 Synchronous DRAM Memory Interface .............................................................................6-8

6.5.1 SDRAM MDCNFG Register (MDCNFG................................................................6-8

6.5.2 SDRAM Mode Register Set Configuration Register (MDMRS) ..........................6-12

6.5.3 SDRAM MDREFR Register (MDREFR) .............................................................6-14

6.5.4 Fixed-Delay or Return-Clock Data Latching.......................................................6-17

6.5.5 SDRAM Memory Options ...................................................................................6-18

6.5.6 SDRAM Command Overview.............................................................................6-27

6.5.7 SDRAM Waveforms............................................................................................6-28

6.6 Synchronous Static Memory Interface.............................................................................6-32

6.6.1 Synchronous Static Memory Configuration Register (SXCNFG)........................6-32

6.6.2 Synchronous Static Memory Mode Register Set Configuration

6.6.3 Synchronous Static Memory Timing Diagrams...................................................6-38

6.6.4 Non-SDRAM Timing SXMEM Operation ............................................................6-39

6.7 Asynchronous Static Memory..........................................................................................6-42

6.7.1 Static Memory Interface......................................................................................6-42

6.7.2 Static Memory SA-1111 Compatibility Configuration Register (SA1111CR)......6-44

6.7.3 Asynchronous Static Memory Control Registers (MSCx)...................................6-46

6.7.4 ROM Interface ....................................................................................................6-50

6.7.5 SRAM Interface Overview ..................................................................................6-53

6.7.6 Variable Latency I/O (VLIO) Interface Overview.................................................6-55

6.7.7 FLASH Memory Interface...................................................................................6-58

6.8 16-Bit PC Card/Compact Flash Interface ........................................................................6-60

6.8.1 Expansion Memory Timing Configuration Register ............................................6-60

6.8.2 Expansion Memory Configuration Register (MECR) ..........................................6-63

6.8.3 16-Bit PC Card Overview....................................................................................6-64

6.8.4 External Logic for 16-Bit PC Card Implementation.............................................6-66

6.8.5 Expansion Card Interface Timing Diagrams and Parameters ............................6-69

6.9 Companion Chip Interface...............................................................................................6-70

6.9.1 Alternate Bus Master Mode ................................................................................6-72

6.10 Options and Settings for Boot Memory............................................................................6-74

6.10.1 Alternate Booting ................................................................................................6-74

6.10.2 Boot Time Defaults .............................................................................................6-74

6.10.3 Memory Interface Reset and Initialization...........................................................6-78

6.11 Hardware, Watchdog, or Sleep Reset Operation ............................................................6-79

6.12 GPIO Reset Procedure....................................................................................................6-81

6.13 Memory Controller Register Summary ............................................................................6-81

7 LCD Controller..............................................................................................................................7-1

7.1 Overview............................................................................................................................7-1

7.1.1 Features................................................................................................................7-2

7.1.2 Pin Descriptions....................................................................................................7-4

7.2 LCD Controller Operation ..................................................................................................7-4

vi Intel® PXA255 Processor Developer’s Manual

7.2.1 Enabling the Controller .........................................................................................7-4

7.2.2 Disabling the Controller ........................................................................................7-5

7.2.3 Resetting the Controller........................................................................................7-5

7.3 Detailed Module Descriptions ............................................................................................7-5

7.3.1 Input FIFOs...........................................................................................................7-5

7.3.2 Lookup Palette......................................................................................................7-6

7.3.3 Temporal Modulated Energy Distribution (TMED) Dithering.................................7-6

7.3.4 Output FIFOs ........................................................................................................7-8

7.3.5 LCD Controller Pin Usage ....................................................................................7-8

7.3.6 DMA......................................................................................................................7-9

7.4 LCD External Palette and Frame Buffers ........................................................................7-10

7.4.1 External Palette Buffer........................................................................................7-10

7.4.2 External Frame Buffer.........................................................................................7-11

7.5 Functional Timing ............................................................................................................7-14

7.6 Register Descriptions.......................................................................................................7-17

7.6.1 LCD Controller Control Register 0 (LCCR0).......................................................7-18

7.6.2 LCD Controller Control Register 1 (LCCR1).......................................................7-24

7.6.3 LCD Controller Control Register 2 (LCCR2).......................................................7-26

7.6.4 LCD Controller Control Register 3 (LCCR3).......................................................7-28

7.6.5 LCD Controller DMA ...........................................................................................7-32

7.6.6 LCD DMA Frame Branch Registers (FBRx) .......................................................7-37

7.6.7 LCD Controller Status Register (LCSR)..............................................................7-38

7.6.8 LCD Controller Interrupt ID Register (LIIDR) ......................................................7-41

7.6.9 TMED RGB Seed Register (TRGBR) .................................................................7-42

7.6.10 TMED Control Register (TCR)............................................................................7-43

7.7 LCD Controller Register Summary ..................................................................................7-44

Contents

8 Synchronous Serial Port Controller ..............................................................................................8-1

8.1 Overview............................................................................................................................8-1

8.2 Signal Description..............................................................................................................8-1

8.2.1 External Interface to Synchronous Serial Peripherals ..........................................8-1

8.3 Functional Description .......................................................................................................8-2

8.3.1 Data Transfer........................................................................................................8-2

8.4 Data Formats.....................................................................................................................8-2

8.4.1 Serial Data Formats for Transfer to/from Peripherals...........................................8-2

8.4.2 Parallel Data Formats for FIFO Storage...............................................................8-6

8.5 FIFO Operation and Data Transfers..................................................................................8-7

8.5.1 Using Programmed I/O Data Transfers ................................................................8-7

8.5.2 Using DMA Data Transfers...................................................................................8-7

8.6 Baud-Rate Generation.......................................................................................................8-7

8.7 SSP Serial Port Registers..................................................................................................8-8

8.7.1 SSP Control Register 0 (SSCR0) .........................................................................8-8

8.7.2 SSP Control Register 1 (SSCR1) .......................................................................8-11

8.7.3 SSP Data Register (SSDR) ................................................................................8-15

8.7.4 SSP Status Register (SSSR)..............................................................................8-16

8.8 SSP Controller Register Summary ..................................................................................8-19

9I2C Bus Interface Unit...................................................................................................................9-1

9.1 Overview............................................................................................................................9-1

9.2 Signal Description..............................................................................................................9-1

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Contents

9.3 Functional Description .......................................................................................................9-1

9.3.1 Operational Blocks................................................................................................9-3

9.3.2 I2C Bus Interface Modes .....................................................................................9-3

9.3.3 Start and Stop Bus States ....................................................................................9-4

9.4 I2C Bus Operation .............................................................................................................9-7

9.4.1 Serial Clock Line (SCL) Generation......................................................................9-7

9.4.2 Data and Addressing Management ......................................................................9-7

9.4.3 I2C Acknowledge..................................................................................................9-8

9.4.4 Polling...................................................................................................................9-9

9.4.5 Arbitration .............................................................................................................9-9

9.4.6 Master Operations..............................................................................................9-12

9.4.7 Slave Operations ................................................................................................9-14

9.4.8 General Call Address.......................................................................................... 9-16

9.5 Slave Mode Programming Examples ..............................................................................9-18

9.5.1 Initialize Unit .......................................................................................................9-18

9.5.2 Write n Bytes as a Slave.....................................................................................9-18

9.5.3 Read n Bytes as a Slave ....................................................................................9-18

9.6 Master Programming Examples ......................................................................................9-19

9.6.1 Initialize Unit .......................................................................................................9-19

9.6.2 Write 1 Byte as a Master ....................................................................................9-19

9.6.3 Read 1 Byte as a Master ....................................................................................9-20

9.6.4 Write 2 Bytes and Repeated Start Read 1 Byte as a Master..............................9-20

9.6.5 Read 2 Bytes as a Master - Send STOP Using the Abort ..................................9-21

9.7 Glitch Suppression Logic.................................................................................................9-21

9.8 Reset Conditions .............................................................................................................9-21

9.9 Register Definitions..........................................................................................................9-22

9.9.1 I2C Bus Monitor Register (IBMR).......................................................................9-22

9.9.2 I2C Data Buffer Register (IDBR).........................................................................9-22

9.9.3 I2C Control Register (ICR)..................................................................................9-23

9.9.4 I2C Status Register (ISR) ...................................................................................9-25

9.9.5 I2C Slave Address Register (ISAR)....................................................................9-27

10 UARTs........................................................................................................................................10-1

10.1 Feature List......................................................................................................................10-1

10.2 Overview..........................................................................................................................10-2

10.2.1 Full Function UART ............................................................................................10-2

10.2.2 Bluetooth UART..................................................................................................10-2

10.2.3 Standard UART ..................................................................................................10-2

10.2.4 Compatibility with 16550.....................................................................................10-2

10.3 Signal Descriptions..........................................................................................................10-3

10.4 UART Operational Description ........................................................................................10-4

10.4.1 Reset ..................................................................................................................10-5

10.4.2 Internal Register Descriptions.............................................................................10-5

10.4.3 FIFO Interrupt Mode Operation ........................................................................10-21

10.4.4 FIFO Polled Mode Operation............................................................................10-22

10.4.5 DMA Requests..................................................................................................10-22

10.4.6 Slow Infrared Asynchronous Interface..............................................................10-23

10.5 UART Register Summary ..............................................................................................10-26

10.5.1 UART Register Differences ..............................................................................10-28

viii Intel® PXA255 Processor Developer’s Manual

Contents

11 Fast Infrared Communication Port..............................................................................................11-1

11.1 Signal Description............................................................................................................11-1

11.2 FICP Operation................................................................................................................11-1

11.2.1 4PPM Modulation ...............................................................................................11-2

11.2.2 Frame Format.....................................................................................................11-3

11.2.3 Address Field......................................................................................................11-3

11.2.4 Control Field .......................................................................................................11-3

11.2.5 Data Field ...........................................................................................................11-3

11.2.6 CRC Field ...........................................................................................................11-4

11.2.7 Baud Rate Generation........................................................................................11-4

11.2.8 Receive Operation ..............................................................................................11-4

11.2.9 Transmit Operation .............................................................................................11-5

11.2.10 Transmit and Receive FIFOs..............................................................................11-6

11.2.11 Trailing or Error Bytes in the Receive FIFO........................................................11-7

11.3 FICP Register Definitions ................................................................................................11-7

11.3.1 FICP Control Register 0 (ICCR0)........................................................................11-8

11.3.2 FICP Control Register 1 (ICCR1)......................................................................11-10

11.3.3 FICP Control Register 2 (ICCR2)......................................................................11-11

11.3.4 FICP Data Register (ICDR)...............................................................................11-12

11.3.5 FICP Status Register 0 (ICSR0) .......................................................................11-13

11.3.6 FICP Status Register 1 (ICSR1) .......................................................................11-15

11.4 FICP Register Summary................................................................................................11-16

12 USB Device Controller................................................................................................................12-1

12.1 USB Overview .................................................................................................................12-1

12.2 Device Configuration .......................................................................................................12-2

12.3 USB Protocol ...................................................................................................................12-2

12.3.1 Signalling Levels.................................................................................................12-3

12.3.2 Bit Encoding........................................................................................................12-3

12.3.3 Field Formats......................................................................................................12-4

12.3.4 Packet Formats...................................................................................................12-5

12.3.5 Transaction Formats...........................................................................................12-6

12.3.6 UDC Device Requests........................................................................................12-8

12.3.7 Configuration ......................................................................................................12-9

12.4 UDC Hardware Connection ...........................................................................................12-10

12.4.1 Self-Powered Device ........................................................................................12-10

12.4.2 Bus-Powered Devices ......................................................................................12-12

12.5 UDC Operation ..............................................................................................................12-12

12.5.1 Case 1: EP0 Control Read ...............................................................................12-12

12.5.2 Case 2: EP0 Control Read with a Premature Status Stage..............................12-13

12.5.3 Case 3: EP0 Control Write With or Without a Premature Status Stage............12-14

12.5.4 Case 4: EP0 No Data Command......................................................................12-15

12.5.5 Case 5: EP1 Data Transmit (BULK-IN).............................................................12-15

12.5.6 Case 6: EP2 Data Receive (BULK-OUT)..........................................................12-16

12.5.7 Case 7: EP3 Data Transmit (ISOCHRONOUS-IN)...........................................12-17

12.5.8 Case 8: EP4 Data Receive (ISOCHRONOUS-OUT)........................................12-18

12.5.9 Case 9: EP5 Data Transmit (INTERRUPT-IN) .................................................12-20

12.5.10 Case 10: RESET Interrupt ................................................................................12-20

12.5.11 Case 11: SUSPEND Interrupt...........................................................................12-21

12.5.12 Case 12: RESUME Interrupt.............................................................................12-21

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Contents

12.6 UDC Register Definitions...............................................................................................12-21

12.6.1 UDC Control Register (UDCCR).......................................................................12-22

12.6.2 UDC Control Function Register (UDCCFR)......................................................12-24

12.6.3 UDC Endpoint 0 Control/Status Register (UDCCS0) .......................................12-25

12.6.4 UDC Endpoint x Control/Status Register (UDCCS1/6/11)................................12-27

12.6.5 UDC Endpoint x Control/Status Register (UDCCS2/7/12)................................12-29

12.6.6 UDC Endpoint x Control/Status Register (UDCCS3/8/13)................................12-31

12.6.7 UDC Endpoint x Control/Status Register (UDCCS4/9/14)................................12-32

12.6.8 UDC Endpoint x Control/Status Register (UDCCS5/10/15)..............................12-34

12.6.9 UDC Interrupt Control Register 0 (UICR0) .......................................................12-36

12.6.10 UDC Interrupt Control Register 1 (UICR1) .......................................................12-38

12.6.11 UDC Status/Interrupt Register 0 (USIR0).........................................................12-39

12.6.12 UDC Status/Interrupt Register 1 (USIR1).........................................................12-41

12.6.13 UDC Frame Number High Register (UFNHR) ..................................................12-42

12.6.14 UDC Frame Number Low Register (UFNLR) ...................................................12-44

12.6.15 UDC Byte Count Register x (UBCR2/4/7/9/12/14) ...........................................12-44

12.6.16 UDC Endpoint 0 Data Register (UDDR0).........................................................12-45

12.6.17 UDC Endpoint x Data Register (UDDR1/6/11) .................................................12-46

12.6.18 UDC Endpoint x Data Register (UDDR2/7/12) .................................................12-46

12.6.19 UDC Endpoint x Data Register (UDDR3/8/13) .................................................12-47

12.6.20 UDC Endpoint x Data Register (UDDR4/9/14) .................................................12-47

12.6.21 UDC Endpoint x Data Register (UDDR5/10/15) ...............................................12-48

12.7 USB Device Controller Register Summary....................................................................12-48

13 AC’97 Controller Unit..................................................................................................................13-1

13.1 Overview..........................................................................................................................13-1

13.2 Feature List......................................................................................................................13-1

13.3 Signal Description............................................................................................................13-2

13.3.1 Signal Configuration Steps .................................................................................13-2

13.3.2 Example AC-link .................................................................................................13-2

13.4 AC-link Digital Serial Interface Protocol...........................................................................13-3

13.4.1 AC-link Audio Output Frame (SDATA_OUT)......................................................13-4

13.4.2 AC-link Audio Input Frame (SDATA_IN).............................................................13-8

13.5 AC-link Low Power Mode ..............................................................................................13-12

13.5.1 Powering Down the AC-link..............................................................................13-12

13.5.2 Waking up the AC-link ......................................................................................13-13

13.6 ACUNIT Operation.........................................................................................................13-14

13.6.1 Initialization.......................................................................................................13-15

13.6.2 Trailing bytes ....................................................................................................13-17

13.6.3 Operational Flow for Accessing CODEC Registers..........................................13-17

13.7 Clocks and Sampling Frequencies ................................................................................13-17

13.8 Functional Description ...................................................................................................13-18

13.8.1 FIFOs................................................................................................................13-18

13.8.2 Interrupts...........................................................................................................13-19

13.8.3 Registers...........................................................................................................13-19

13.9 AC’97 Register Summary ..............................................................................................13-35

14 Inter-Integrated-Circuit Sound (I2S) Controller...........................................................................14-1

14.1 Overview..........................................................................................................................14-1

14.2 Signal Descriptions..........................................................................................................14-2

x Intel® PXA255 Processor Developer’s Manual

14.3 Controller Operation ........................................................................................................14-3

14.3.1 Initialization .........................................................................................................14-3

14.3.2 Disabling and Enabling Audio Replay.................................................................14-4

14.3.3 Disabling and Enabling Audio Record ................................................................14-4

14.3.4 Transmit FIFO Errors..........................................................................................14-5

14.3.5 Receive FIFO Errors...........................................................................................14-5

14.3.6 Trailing Bytes ......................................................................................................14-5

14.4 Serial Audio Clocks and Sampling Frequencies..............................................................14-5

14.5 Data Formats...................................................................................................................14-6

14.5.1 FIFO and Memory Format ..................................................................................14-6

14.5.2 I2S and MSB-Justified Serial Audio Formats......................................................14-6

14.6 Registers..........................................................................................................................14-8

14.6.1 Serial Audio Controller Global Control Register (SACR0) ..................................14-8

14.6.2 Serial Audio Controller I2S/MSB-Justified Control Register (SACR1)..............14-10

14.6.3 Serial Audio Controller I2S/MSB-Justified Status Register (SASR0)................14-11

14.6.4 Serial Audio Clock Divider Register (SADIV)....................................................14-12

14.6.5 Serial Audio Interrupt Clear Register (SAICR)..................................................14-13

14.6.6 Serial Audio Interrupt Mask Register (SAIMR) .................................................14-14

14.6.7 Serial Audio Data Register (SADR) ..................................................................14-14

14.7 Interrupts........................................................................................................................14-15

14.8 I

S Controller Register Summary ..................................................................................14-15

Contents

15 MultiMediaCard Controller..........................................................................................................15-1

15.1 Overview..........................................................................................................................15-1

15.2 MMC Controller Functional Description...........................................................................15-4

15.2.1 Signal Description...............................................................................................15-6

15.2.2 MMC Controller Reset ........................................................................................15-6

15.2.3 Card Initialization Sequence ...............................................................................15-6

15.2.4 MMC and SPI Modes..........................................................................................15-6

15.2.5 Error Detection....................................................................................................15-8

15.2.6 Interrupts.............................................................................................................15-8

15.2.7 Clock Control ......................................................................................................15-9

15.2.8 Data FIFOs .......................................................................................................15-10

15.3 Card Communication Protocol.......................................................................................15-12

15.3.1 Basic, No Data, Command and Response Sequence......................................15-13

15.3.2 Data Transfer....................................................................................................15-13

15.3.3 Busy Sequence.................................................................................................15-16

15.3.4 SPI Functionality...............................................................................................15-17

15.4 MultiMediaCard Controller Operation ............................................................................15-17

15.4.1 Start and Stop Clock.........................................................................................15-17

15.4.2 Initialize.............................................................................................................15-17

15.4.3 Enabling SPI Mode ...........................................................................................15-17

15.4.4 No Data Command and Response Sequence..................................................15-18

15.4.5 Erase ................................................................................................................15-18

15.4.6 Single Data Block Write....................................................................................15-18

15.4.7 Single Block Read ............................................................................................15-19

15.4.8 Multiple Block Write ..........................................................................................15-20

15.4.9 Multiple Block Read ..........................................................................................15-20

15.4.10 Stream Write.....................................................................................................15-21

15.4.11 Stream Read.....................................................................................................15-21

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Contents

15.5 MMC Controller Registers ............................................................................................. 15-22

15.5.1 MMC_STRPCL Register...................................................................................15-22

15.5.2 MMC_Status Register (MMC_STAT) ...............................................................15-23

15.5.3 MMC_CLKRT Register (MMC_CLKRT) ...........................................................15-24

15.5.4 MMC_SPI Register (MMC_SPI) .......................................................................15-25

15.5.5 MMC_CMDAT Register (MMC_CMDAT) .........................................................15-26

15.5.6 MMC_RESTO Register (MMC_RESTO)..........................................................15-27

15.5.7 MMC_RDTO Register (MMC_RDTO) ..............................................................15-28

15.5.8 MMC_BLKLEN Register (MMC_BLKLEN) .......................................................15-29

15.5.9 MMC_NOB Register (MMC_NOB) ...................................................................15-29

15.5.10 MMC_PRTBUF Register (MMC_PRTBUF)......................................................15-30

15.5.11 MMC_I_MASK Register (MMC_I_MASK) ........................................................15-30

15.5.12 MMC_I_REG Register (MMC_I_REG) .............................................................15-31

15.5.13 MMC_CMD Register (MMC_CMD) ..................................................................15-33

15.5.14 MMC_ARGH Register (MMC_ARGH)..............................................................15-35

15.5.15 MMC_ARGL Register (MMC_ARGL) ...............................................................15-35

15.5.16 MMC_RES FIFO...............................................................................................15-36

15.5.17 MMC_RXFIFO FIFO.........................................................................................15-36

15.5.18 MMC_TXFIFO FIFO.........................................................................................15-37

15.6 MultiMediaCard Controller Register Summary ..............................................................15-37

16 Network SSP Serial Port ............................................................................................................16-1

16.1 Overview..........................................................................................................................16-1

16.2 Features...........................................................................................................................16-1

16.3 Signal Description............................................................................................................16-2

16.4 Operation.........................................................................................................................16-2

16.4.1 Processor and DMA FIFO Access......................................................................16-2

16.4.2 Trailing Bytes in the Receive FIFO.....................................................................16-3

16.4.3 Data Formats......................................................................................................16-3

16.4.4 Hi-Z on SSPTXD...............................................................................................16-13

16.4.5 FIFO Operation.................................................................................................16-17

16.4.6 Baud-Rate Generation......................................................................................16-17

16.5 Register Descriptions.....................................................................................................16-18

16.5.1 SSP Control Register 0 (SSCR0) ..................................................................... 16-18

16.5.2 SSP Control Register 1 (SSCR1) ..................................................................... 16-20

16.5.3 SSP Programmable Serial Protocol Register (SSPSP)....................................16-22

16.5.4 SSP Time Out Register (SSTO) .......................................................................16-24

16.5.5 SSP Interrupt Test Register (SSITR)................................................................16-24

16.5.6 SSP Status Register (SSSR)............................................................................16-25

16.5.7 SSP Data Register (SSDR) ..............................................................................16-28

16.6 Network SSP Serial Port Register Summary.................................................................16-29

17 Hardware UART.........................................................................................................................17-1

17.1 Overview..........................................................................................................................17-1

17.2 Features...........................................................................................................................17-1

17.3 Signal Descriptions..........................................................................................................17-3

17.4 Operation.........................................................................................................................17-3

17.4.1 Reset ..................................................................................................................17-4

17.4.2 FIFO Operation...................................................................................................17-4

17.4.3 Autoflow Control .................................................................................................17-7

xii Intel® PXA255 Processor Developer’s Manual

17.4.4 Auto-Baud-Rate Detection..................................................................................17-7

17.4.5 Slow Infrared Asynchronous Interface................................................................17-8

17.5 Register Descriptions.....................................................................................................17-10

17.5.1 Receive Buffer Register (RBR).........................................................................17-10

17.5.2 Transmit Holding Register (THR)......................................................................17-10

17.5.3 Divisor Latch Registers (DLL and DLH)............................................................17-10

17.5.4 Interrupt Enable Register (IER) ........................................................................17-11

17.5.5 Interrupt Identification Register (IIR).................................................................17-13

17.5.6 FIFO Control Register (FCR)............................................................................17-15

17.5.7 Receive FIFO Occupancy Register (FOR) .......................................................17-16

17.5.8 Auto-Baud Control Register (ABR) ...................................................................17-17

17.5.9 Auto-Baud Count Register (ACR).....................................................................17-17

17.5.10 Line Control Register (LCR)..............................................................................17-18

17.5.11 Line Status Register (LSR) ...............................................................................17-19

17.5.12 Modem Control Register (MCR) .......................................................................17-21

17.5.13 Modem Status Register (MSR) .........................................................................17-23

17.5.14 Scratchpad Register (SCR) ..............................................................................17-24

17.5.15 Infrared Selection Register (ISR)......................................................................17-24

17.6 Hardware UART Register Summary..............................................................................17-25

Contents

Figures

2-1 Block Diagram ...........................................................................................................................2-2

2-2 Memory Map (Part One) — From 0x8000_0000 to 0xFFFF FFFF ..........................................2-19

2-3 Memory Map (Part Two) — From 0x0000_0000 to 0x7FFF FFFF ..........................................2-20

3-1 Clocks Manager Block Diagram ................................................................................................3-3

4-1 General-Purpose I/O Block Diagram .........................................................................................4-2

4-2 Interrupt Controller Block Diagram ..........................................................................................4-21

4-3 PWMn Block Diagram..............................................................................................................4-39

4-4 Basic Pulse Width Waveform ..................................................................................................4-43

5-1 DMAC Block Diagram................................................................................................................5-1

5-2 DREQ timing requirements........................................................................................................5-3

5-3 No-Descriptor Fetch Mode Channel State.................................................................................5-6

5-4 Descriptor Fetch Mode Channel State.......................................................................................5-8

5-5 Little Endian Transfers.............................................................................................................5-10

6-1 General Memory Interface Configuration...................................................................................6-2

6-2 SDRAM Memory System Example............................................................................................6-5

6-3 Static Memory System Example................................................................................................6-6

6-4 External to Internal Address Mapping Options ........................................................................6-19

6-5 Basic SDRAM Timing Parameters...........................................................................................6-29

6-6 SDRAM_Read_diffbank_diffrow..............................................................................................6-29

6-7 SDRAM_read_samebank_diffrow ...........................................................................................6-30

6-8 SDRAM_read_samebank_samerow .......................................................................................6-30

6-9 SDRAM_write ..........................................................................................................................6-31

6-10 SDRAM 4-Beat Read/ 4-Beat Write To Different Partitions.....................................................6-31

6-11 SDRAM 4-Beat Write / 4-Write Same Bank, Same Row .........................................................6-32

6-12 SMROM Read Timing Diagram Half-Memory Clock Frequency .............................................6-39

6-13 Burst-of-Eight Synchronous Flash Timing Diagram (non-divide-by-2 mode) ..........................6-41

6-14 Flash Memory Reset Using State Machine .............................................................................6-42

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6-15 Flash Memory Reset Logic if Watchdog Reset is Not Necessary ...........................................6-42

6-16 MSC0/1/2.................................................................................................................................6-46

6-17 32-Bit Burst-of-Eight ROM or Flash Read Timing Diagram (MSC0[RDF] = 4,

MSC0[RDN] = 1, MSC0[RRR] = 1)..........................................................................................6-51

6-18 Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash

(MSC0[RDF] = 4, MSC0[RDN] = 1, MSC0[RRR] = 0).............................................................6-52

6-19 32-Bit Non-burst ROM, SRAM, or Flash Read Timing Diagram - Four Data

Beats (MSC0[RDF] = 4, MSC0[RRR] = 1)...............................................................................6-53

6-20 32-Bit SRAM Write Timing Diagram (4-beat Burst (MSC0[RDN] = 2,

MSC0[RRR] = 1)......................................................................................................................6-54

6-21 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per

Beat) (MSC0[RDF] = 2, MSC0[RDN] = 2, MSC0[RRR] = 1) ...................................................6-56

6-22 32-Bit Variable Latency I/O Write Timing (Burst-of-Four, Variable Wait Cycles

Per Beat) .................................................................................................................................6-57

6-23 Asynchronous 32-Bit Flash Write Timing Diagram (2 Writes) .................................................6-59

6-24 MCMEM1.................................................................................................................................6-60

6-25 MCATT1 ..................................................................................................................................6-60

6-26 16-Bit PC Card Memory Map ..................................................................................................6-64

6-27 Expansion Card External Logic for a One-Socket Configuration.............................................6-67

6-28 Expansion Card External Logic for a Two-Socket Configuration.............................................6-68

6-29 16-Bit PC Card Memory or I/O 16-Bit (Half-word) Access.......................................................6-69

6-30 16-Bit PC Card I/O 16-Bit Access to 8-Bit Device ...................................................................6-70

6-31 Alternate Bus Master Mode.....................................................................................................6-71

6-32 Variable Latency IO.................................................................................................................6-71

6-33 Asynchronous Boot Time Configurations and Register Defaults.............................................6-76

6-34 SMROM Boot Time Configurations and Register Defaults......................................................6-77

6-35 SMROM Boot Time Configurations and Register Defaults......................................................6-78

7-1 LCD Controller Block Diagram ..................................................................................................7-3

7-2 Temporal Dithering Concept - Single Color...............................................................................7-6

7-3 Compare Range for TMED........................................................................................................7-7

7-4 TMED Block Diagram ...............................................................................................................7-8

7-5 Palette Buffer Format ..............................................................................................................7-11

7-6 1 Bit Per Pixel Data Memory Organization.............................................................................. 7-11

7-7 2 Bits Per Pixel Data Memory Organization ............................................................................7-12

7-8 4 Bits Per Pixel Data Memory Organization ............................................................................7-12

7-9 8 Bits Per Pixel Data Memory Organization ............................................................................7-12

7-10 16 Bits Per Pixel Data Memory Organization - Passive Mode ................................................7-13

7-11 16 Bits Per Pixel Data Memory Organization - Active Mode ...................................................7-13

7-12 Passive Mode Start-of-Frame Timing......................................................................................7-15

7-13 Passive Mode End-of-Frame Timing.......................................................................................7-15

7-14 Passive Mode Pixel Clock and Data Pin Timing......................................................................7-16

7-15 Active Mode Timing .................................................................................................................7-16

7-16 Active Mode Pixel Clock and Data Pin Timing ........................................................................7-17

7-17 Frame Buffer/Palette Output to LCD Data Pins in Active Mode ..............................................7-20

7-18 LCD Data-Pin Pixel Ordering...................................................................................................7-22

8-1 Texas Instruments’ Synchronous Serial Frame* Format...........................................................8-4

8-2 Motorola SPI* Frame Format.....................................................................................................8-5

8-3 National Microwire* Frame Format............................................................................................8-6

8-4 Motorola SPI* Frame Formats for SPO and SPH Programming.............................................8-13

9-1 I

C Bus Configuration Example................................................................................................9-2

9-2 Start and Stop Conditions..........................................................................................................9-5

xiv Intel® PXA255 Processor Developer’s Manual

Contents

9-3 START and STOP Conditions ...................................................................................................9-6

9-4 Data Format of First Byte in Master Transaction.......................................................................9-8

9-5 Acknowledge on the I2C Bus.....................................................................................................9-9

9-6 Clock Synchronization During the Arbitration Procedure.........................................................9-10

9-7 Arbitration Procedure of Two Masters .....................................................................................9-11

9-8 Master-Receiver Read from Slave-Transmitter .......................................................................9-14

9-9 Master-Receiver Read from Slave-Transmitter / Repeated Start / Master-

Transmitter Write to Slave-Receiver........................................................................................9-14

9-10 A Complete Data Transfer .......................................................................................................9-14

9-11 Master-Transmitter Write to Slave-Receiver............................................................................9-16

9-12 Master-Receiver Read to Slave-Transmitter ...........................................................................9-16

9-13 Master-Receiver Read to Slave-Transmitter, Repeated START, Master-

Transmitter Write to Slave-Receiver........................................................................................9-16

9-14 General Call Address...............................................................................................................9-17

10-1 Example UART Data Frame ....................................................................................................10-4

10-2 Example NRZ Bit Encoding – (0b0100 1011 ...........................................................................10-5

10-3 IR Transmit and Receive Example ........................................................................................10-25

10-4 XMODE Example...................................................................................................................10-25

11-1 4PPM Modulation Encodings...................................................................................................11-2

11-2 4PPM Modulation Example .....................................................................................................11-2

11-3 Frame Format for IrDA Transmission (4.0 Mbps)....................................................................11-3

12-1 NRZI Bit Encoding Example ....................................................................................................12-4

12-2 Self-Powered Device .............................................................................................................12-11

13-1 Data Transfer Through the AC-link..........................................................................................13-3

13-2 AC’97 Standard Bidirectional Audio Frame .............................................................................13-4

13-3 AC-link Audio Output Frame....................................................................................................13-5

13-4 Start of Audio Output Frame....................................................................................................13-5

13-5 AC’97 Input Frame...................................................................................................................13-9

13-6 Start of an Audio Input Frame..................................................................................................13-9

13-7 AC-link Powerdown Timing....................................................................................................13-12

13-8 SDATA_IN Wake Up Signaling..............................................................................................13-13

13-9 PCM Transmit and Receive Operation ..................................................................................13-27

13-10 Mic-in Receive-Only Operation..............................................................................................13-29

13-11 Modem Transmit and Receive Operation ..............................................................................13-32

14-1 I2S Data Formats (16 bits).......................................................................................................14-7

14-2 MSB-Justified Data Formats (16 bits .......................................................................................14-7

14-3 Transmit and Receive FIFO Accesses Through the SADR...................................................14-15

15-1 MMC System Interaction .........................................................................................................15-1

15-2 MMC Mode Operation Without Data Token.............................................................................15-3

15-3 MMC Mode Operation With Data Token..................................................................................15-3

15-4 SPI Mode Operation Without Data Token ...............................................................................15-4

15-5 SPI Mode Read Operation.......................................................................................................15-4

15-6 SPI Mode Write Operation.......................................................................................................15-4

16-1 Texas Instruments Synchronous Serial Frame* Protocol (multiple transfers) .........................16-5

16-2 Texas Instruments Synchronous Serial Frame* Protocol (single transfers) ............................16-6

16-3 Motorola SPI* Frame Protocol (multiple transfers) ..................................................................16-7

16-4 Motorola SPI* Frame Protocol (single transfers) .....................................................................16-7

16-5 Motorola SPI* Frame Protocols for SPO and SPH Programming (multiple transfers).............16-8

16-6 Motorola SPI* Frame Protocols for SPO and SPH Programming (single transfers)................16-9

16-7 National Semiconductor Microwire* Frame Protocol (multiple transfers) ..............................16-10

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Contents

16-8 National Semiconductor Microwire* Frame Protocol (single transfers) .................................16-10

16-9 Programmable Serial Protocol (multiple transfers)................................................................16-11

16-10 Programmable Serial Protocol (single transfers)...................................................................16-12

16-11 TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=0.................................................................16-13

16-12 TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=1.................................................................16-14

16-13 Motorola SPI with SSCR[TTE]=1...........................................................................................16-14

16-14 National Semiconductor Microwire with SSCR1[TTE]=1.......................................................16-15

16-15 PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (slave to frame).............................16-15

16-16 PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (master to frame) ..........................16-16

16-17 PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=1 (must be slave to frame)...............16-16

17-1 Example UART Data Frame....................................................................................................17-3

17-2 Example NRZ Bit Encoding – (0b0100 1011...........................................................................17-4

17-3 IR Transmit and Receive Example..........................................................................................17-9

17-4 XMODE Example. ...................................................................................................................17-9

Tables

2-1CPU Core Fault Register Bit Definitions...............................................................................2-3

2-2 ID Bit Definitions........................................................................................................................2-4

2-3 PXA255 Processor ID Values....................................................................................................2-4

2-4 Effect of Each Type of Reset on Internal Register State...........................................................2-6

2-5 Processor Pin Types .................................................................................................................2-8

2-6 Pin & Signal Descriptions for the PXA255 Processor................................................................2-9

2-7 Pin Description Notes..............................................................................................................2-17

2-8 System Architecture Register Address Summary ...................................................................2-21

3-1 Core PLL Output Frequencies for 3.6864 MHz Crystal.............................................................3-5

3-2 95.85 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal ..................................3-5

3-3 147.46 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal................................3-6

3-4 Power Mode Entry Sequence Table.......................................................................................3-20

3-5 Power Mode Exit Sequence Table .........................................................................................3-20

3-6 Power and Clock Supply Sources and States During Power Modes .....................................3-22

3-7 PMCR Bit Definitions ...............................................................................................................3-23

3-8 PCFR Bit Definitions................................................................................................................3-24

3-9 PWER Bit Definitions...............................................................................................................3-25

3-10 PRER Bit Definitions................................................................................................................3-26

3-11 PFER Bit Definitions................................................................................................................3-27

3-12 PEDR Bit Definitions................................................................................................................3-28

3-13 PSSR Bit Definitions................................................................................................................3-29

3-14 PSPR Bit Definitions................................................................................................................3-30

3-15 PMFW Register Bitmap and Bit Definitions.............................................................................3-31

3-16 PGSR0 Bit Definitions .............................................................................................................3-32

3-17 PGSR1 Bit Definitions .............................................................................................................3-32

3-18 PGSR2 Bit Definitions .............................................................................................................3-33

3-19 RCSR Bit Definitions ...............................................................................................................3-34

3-20 CCCR Bit Definitions ...............................................................................................................3-35

3-21 CKEN Bit Definitions................................................................................................................3-36

3-22 OSCC Bit Definitions ...............................................................................................................3-38

3-23 Coprocessor 14 Clock and Power Management Summary.....................................................3-39

3-24 CCLKCFG Bit Definitions ........................................................................................................3-39

3-25 PWRMODE Bit Definitions ......................................................................................................3-40

xvi Intel® PXA255 Processor Developer’s Manual

Contents

3-26 Clocks Manager Register Summary........................................................................................3-41

3-27 Power Manager Register Summary.........................................................................................3-42

4-1 GPIO Alternate Functions.......................................................................................................... 4-3

4-2 GPIO Register Definitions..........................................................................................................4-6

4-3 GPLR0 Bit Definitions................................................................................................................4-7

4-4 GPLR1 Bit Definitions................................................................................................................4-8

4-5 GPLR2 Bit Definitions................................................................................................................4-8

4-6 GPDR0 Bit Definitions ...............................................................................................................4-9

4-7 GPDR1 Bit Definitions ...............................................................................................................4-9

4-8 GPDR2 Bit Definitions ...............................................................................................................4-9

4-9 GPSR0 Bit Definitions..............................................................................................................4-10

4-10 GPSR1 Bit Definitions..............................................................................................................4-10

4-11 GPSR2 Bit Definitions..............................................................................................................4-11

4-12 GPCR0 Bit Definitions .............................................................................................................4-11

4-13 GPCR1 Bit Definitions .............................................................................................................4-11

4-14 GPCR2 Bit Definitions .............................................................................................................4-12

4-15 GRER0 Bit Definitions .............................................................................................................4-13

4-16 GRER1 Bit Definitions .............................................................................................................4-13

4-17 GRER2 Bit Definitions .............................................................................................................4-13

4-18 GFER0 Bit Definitions..............................................................................................................4-14

4-19 GFER1 Bit Definitions..............................................................................................................4-14

4-20 GFER2 Bit Definitions..............................................................................................................4-14

4-21 GEDR0 Bit Definitions .............................................................................................................4-15

4-22 GEDR1 Bit Definitions .............................................................................................................4-15

4-23 GEDR2 Bit Definitions .............................................................................................................4-16

4-24 GAFR0_L Bit Definitions..........................................................................................................4-17

4-25 GAFR0_U Bit Definitions .........................................................................................................4-17

4-26 GAFR1_L Bit Definitions..........................................................................................................4-18

4-27 GAFR1_U Bit Definitions .........................................................................................................4-18

4-28 GAFR2_L Bit Definitions..........................................................................................................4-19

4-29 GAFR2_U Bit Definitions .........................................................................................................4-19

4-30 ICMR Bit Definitions.................................................................................................................4-22

4-31 ICLR Bit Definitions..................................................................................................................4-23

4-32 ICCR Bit Definitions .................................................................................................................4-23

4-33 ICIP Bit Definitions...................................................................................................................4-24

4-34 ICFP Bit Definitions..................................................................................................................4-24

4-35 ICPR Bit Definitions .................................................................................................................4-25

4-36 List of First–Level Interrupts ....................................................................................................4-27

4-37 RTTR Bit Definitions ................................................................................................................4-30

4-38 RTAR Bit Definitions ................................................................................................................4-30

4-39 RCNR Bit Definitions ...............................................................................................................4-31

4-40 RTSR Bit Definitions ................................................................................................................4-32

4-41 OSMR[x] Bit Definitions ...........................................................................................................4-36

4-42 OIER Bit Definitions.................................................................................................................4-36

4-43 OWER Bit Definitions...............................................................................................................4-37

4-44 OSCR Bit Definitions ...............................................................................................................4-37

4-45 OSSR Bit Definitions................................................................................................................4-38

4-46 PWM_CTRLn Bit Definitions....................................................................................................4-41

4-47 PWM_DUTYn Bit Definitions ...................................................................................................4-42

4-48 PWM_PERVALn Bit Definitions...............................................................................................4-43

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Contents

4-49 GPIO Register Addresses .......................................................................................................4-44

4-50 Interrupt Controller Register Addresses ..................................................................................4-45

4-51 RTC Register Addresses.........................................................................................................4-45

4-52 OS Timer Register Addresses.................................................................................................4-45

4-53 Pulse Width Modulator Register Addresses............................................................................4-46

5-1 DMAC Signal List ......................................................................................................................5-2

5-2 Channel Priority (if all channels are running concurrently)........................................................5-4

5-3 Channel Priority.........................................................................................................................5-4

5-4 Priority Schemes Examples.......................................................................................................5-5

5-5 DMA Quick Reference for Internal Peripherals .......................................................................5-13

5-6 DINT Bit Definitions .................................................................................................................5-17

5-7 DCSRx Bit Definitions..............................................................................................................5-18

5-8 DRCMRx Bit Definitions ..........................................................................................................5-20

5-9 DDADRx Bit Definitions...........................................................................................................5-21

5-10 DSADRx Bit Definitions ...........................................................................................................5-22

5-11 DTADRx Bit Definitions ...........................................................................................................5-23

5-12 DCMDx Bit Definitions .............................................................................................................5-24

5-13 DMA Controller Register Summary .........................................................................................5-28

6-1 Device Transactions ..................................................................................................................6-7

6-2 MDCNFG Bit Definitions............................................................................................................6-9

6-3 MDMRS Bit Definitions............................................................................................................6-12

6-4 MDMRSLP Register Bit Definitions .........................................................................................6-14

6-5 MDREFR Bit Definitions ..........................................................................................................6-15

6-6 Sample SDRAM Memory Size Options...................................................................................6-18

6-7 External to Internal Address Mapping for Normal Bank Addressing .......................................6-19

6-8 External to Internal Address Mapping for SA-1111 Addressing ..............................................6-21

6-9 Pin Mapping to SDRAM Devices with Normal Bank Addressing.............................................6-23

6-10 Pin Mapping to SDRAM Devices with SA1111 Addressing.....................................................6-25

6-11 SDRAM Command Encoding..................................................................................................6-28

6-12 SDRAM Mode Register Opcode Table....................................................................................6-28

6-13 SXCNFG Bit Definitions...........................................................................................................6-33

6-14 SXCNFG..................................................................................................................................6-36

6-15 Synchronous Static Memory External to Internal Address Mapping Options..........................6-37

6-16 SXMRS Bit Definitions.............................................................................................................6-38

6-17 Read Configuration Register Programming Values.................................................................6-40

6-18 Frequency Code Configuration Values Based on Clock Speed..............................................6-40

6-20 16-Bit Bus Write Access..........................................................................................................6-44

6-19 32-Bit Bus Write Access..........................................................................................................6-44

6-21 32-Bit Byte Address Bits MA[1:0] for Reads Based on DQM[3:0] ...........................................6-45

6-22 16-Bit Byte Address Bit MA[0] for Reads Based on DQM[1:0]................................................6-45

6-23 SA-1111 Register Bit Definitions .............................................................................................6-45

6-24 MSC0/1/2 Bit Definitions..........................................................................................................6-47

6-25 Asynchronous Static Memory and Variable Latency I/O Capabilities......................................6-50

6-26 MCMEM0/1 Bit Definitions.......................................................................................................6-60

6-27 MCATT0/1 Bit Definitions ........................................................................................................6-61

6-28 MCIO0/1 Bit Definitions ...........................................................................................................6-61

6-29 Card Interface Command Assertion Code Table.....................................................................6-62

6-30 MECR Bit Definition.................................................................................................................6-63

6-31 Common Memory Space Write Commands............................................................................6-65

6-32 Common Memory Space Read Commands............................................................................6-65

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6-33 Attribute Memory Space Write Commands .............................................................................6-65

6-34 Attribute Memory Space Read Commands .............................................................................6-65

6-35 16-Bit I/O Space Write Commands (nIOIS16 = 0)...................................................................6-65

6-36 16-Bit I/O Space Read Commands (nIOIS16 = 0)...................................................................6-65

6-37 8-Bit I/O Space Write Commands (nIOIS16 = 1).....................................................................6-66

6-38 8-Bit I/O Space Read Commands (nIOIS16 = 1).....................................................................6-66

6-39 BOOT_SEL Definitions............................................................................................................6-74

6-40 BOOT_DEF Bitmap .................................................................................................................6-75

6-41 Valid Boot Configurations Based on Processor Type..............................................................6-75

6-42 Memory Controller Pin Reset Values.......................................................................................6-79

6-43 Memory Controller Register Summary ....................................................................................6-81

7-1 Pin Descriptions.........................................................................................................................7-4

7-2 LCD Controller Data Pin Utilization..........................................................................................7-21

7-3 LCCR0 Bit Definitions..............................................................................................................7-23

7-4 LCCR1 Bit Definitions..............................................................................................................7-26

7-5 LCCR2 Bit Definitions..............................................................................................................7-28

7-6 LCCR3 Bit Definitions..............................................................................................................7-31

7-7 FDADRx Bit Definitions............................................................................................................7-33

7-8 FSADRx Bit Definitions............................................................................................................7-34

7-9 FIDRx Bit Definitions................................................................................................................7-34

7-10 LDCMDx Bit Definitions ...........................................................................................................7-36

7-11 FBRx Bit Definitions.................................................................................................................7-37

7-12 LCSR Bit Definitions ................................................................................................................7-40

7-13 LIICR Bit Definitions.................................................................................................................7-41

7-14 TRGBR Bit Definitions .............................................................................................................7-42

7-15 TCR Bit Definitions ..................................................................................................................7-44

7-16 LCD Controller Register Summary ..........................................................................................7-44

8-1 External Interface to Codec .......................................................................................................8-1

8-2 SSCR0 Bit Definitions................................................................................................................8-9

8-3 SSCR1 Bit Definitions..............................................................................................................8-11

8-4 TFT and RFT Values for DMA Servicing .................................................................................8-15

8-5 SSDR Bit Definitions................................................................................................................8-15

8-6 SSSR Bit Definitions................................................................................................................8-17

8-7 SSP Controller Register Summary ..........................................................................................8-19

9-1 I2C Signal Description ...............................................................................................................9-1

9-2 I2C Bus Definitions ...................................................................................................................9-2

9-3 Modes of Operation ...................................................................................................................9-3

9-4 START and STOP Bit Definitions ..............................................................................................9-4

9-5 Master Transactions ................................................................................................................9-12

9-6 Slave Transactions ..................................................................................................................9-15

9-7 General Call Address Second Byte Definitions .......................................................................9-17

9-8 IBMR Bit Definitions................................................................................................................9-22

9-9 IDBR Bit Definitions ................................................................................................................9-23

9-10 ICR Bit Definitions...................................................................................................................9-23

9-11 ISR Bit Definitions...................................................................................................................9-26

9-12 ISAR Bit Definitions ................................................................................................................9-27

10-1 UART Signal Descriptions .......................................................................................................10-3

10-2 UART Register Addresses as Offsets of a Base .....................................................................10-6

10-3 RBR Bit Definitions ..................................................................................................................10-6

10-4 THR Bit Definitions ..................................................................................................................10-7

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Contents

10-5 DLL Bit Definitions...................................................................................................................10-8

10-6 DLH Bit Definitions ..................................................................................................................10-8

10-7 IER Bit Definitions....................................................................................................................10-9

10-8 Interrupt Conditions ...............................................................................................................10-10

10-9 IIR Bit Definitions...................................................................................................................10-10

10-10 Interrupt Identification Register Decode ................................................................................10-11

10-11 FCR Bit Definitions ................................................................................................................10-12

10-12 LCR Bit Definitions ................................................................................................................10-14

10-13 LSR Bit Definitions.................................................................................................................10-15

10-14 MCR Bit Definitions ...............................................................................................................10-18

10-15 MSR Bit Definitions................................................................................................................10-20

10-16 SPR Bit Definitions ................................................................................................................10-21

10-17 ISR Bit Definitions..................................................................................................................10-24

10-18 FFUART Register Summary..................................................................................................10-26

10-19 BTUART Register Summary .................................................................................................10-26

10-20 STUART Register Summary .................................................................................................10-27

10-21 Flow Control Registers in BTUART and STUART.................................................................10-28

11-1 FICP Signal Description ..........................................................................................................11-1

11-2 ICCR0 Bit Definitions...............................................................................................................11-8

11-3 ICCR1 Bit Definitions.............................................................................................................11-10

11-4 ICCR2 Bit Definitions.............................................................................................................11-11

11-5 ICRD Bit Definitions...............................................................................................................11-12

11-6 ICSR0 Bit Definitions.............................................................................................................11-13

11-7 ICSR1 Bit Definitions.............................................................................................................11-15

11-8 FICP Register Summary........................................................................................................11-16

12-1 Endpoint Configuration............................................................................................................12-2

12-2 USB States..............................................................................................................................12-3

12-3 IN, OUT, and SETUP Token Packet Format ...........................................................................12-5

12-4 SOF Token Packet Format......................................................................................................12-5

12-5 Data Packet Format.................................................................................................................12-6

12-6 Handshake Packet Format ......................................................................................................12-6

12-7 Bulk Transaction Formats........................................................................................................12-7

12-8 Isochronous Transaction Formats...........................................................................................12-7

12-9 Control Transaction Formats ................................................................................................... 12-7

12-10 Interrupt Transaction Formats .................................................................................................12-8

12-11 Host Device Request Summary ..............................................................................................12-9

12-12 UDCCR Bit Definitions...........................................................................................................12-22

12-13 UDC Control Function Register.............................................................................................12-24

12-14 UDCCS0 Bit Definitions.........................................................................................................12-25

12-15 UDCCS1/6/11 Bit Definitions.................................................................................................12-27

12-16 UDCCS2/7/12 Bit Definitions.................................................................................................12-29

12-17 UDCCS3/8/13 Bit Definitions.................................................................................................12-31

12-18 UDCCS4/9/14 Bit Definitions.................................................................................................12-33

12-19 UDCCS5/10/15 Bit Definitions...............................................................................................12-34

12-20 UICR0 Bit Definitions.............................................................................................................12-37

12-21 UICR1 Bit Definitions.............................................................................................................12-38

12-22 USIR0 Bit Definitions.............................................................................................................12-39

12-23 USIR1 Bit Definitions.............................................................................................................12-41

12-24 UFNHR Bit Definitions...........................................................................................................12-43

12-25 UFNLR Bit Definitions............................................................................................................12-44

xx Intel® PXA255 Processor Developer’s Manual

Contents

12-26 UBCR2/4/7/9/12/14 Bit Definitions.........................................................................................12-45

12-27 UDDR0 Bit Definitions ...........................................................................................................12-46

12-28 UDDR1/6/11 Bit Definitions ...................................................................................................12-46

12-29 UDDR2/7/12 Bit Definitions ...................................................................................................12-47

12-30 UDDR3/8/13 Bit Definitions ...................................................................................................12-47

12-31 UDDR4/9/14 Bit Definitions ...................................................................................................12-48

12-32 UDDR5/10/15 Bit Definitions .................................................................................................12-48

12-33 USB Device Controller Register Summary............................................................................12-48

13-1 External Interface to CODECs.................................................................................................13-2

13-2 Supported Data Stream Formats.............................................................................................13-3

13-3 Slot 1 Bit Definitions.................................................................................................................13-7

13-4 Slot 2 Bit Definitions.................................................................................................................13-7

13-5 Input Slot 1 Bit Definitions......................................................................................................13-10

13-6 Input Slot 2 Bit Definitions......................................................................................................13-11

13-7 GCR Bit Definitions................................................................................................................13-20

13-8 GSR Bit Definitions................................................................................................................13-22

13-9 POCR Bit Definitions .............................................................................................................13-23

13-10 PICR Bit Definitions ...............................................................................................................13-24

13-11 POSR Bit Definitions..............................................................................................................13-25

13-12 PISR Bit Definitions ...............................................................................................................13-25

13-13 CAR Bit Definitions ................................................................................................................13-26

13-14 PCDR Bit Definitions..............................................................................................................13-26

13-15 MCCR Bit Definitions.............................................................................................................13-27

13-16 MCSR Bit Definitions .............................................................................................................13-28

13-17 MCDR Bit Definitions.............................................................................................................13-28

13-18 MOCR Bit Definitions.............................................................................................................13-29

13-19 MICR Bit Definitions...............................................................................................................13-30

13-20 MOSR Bit Definitions.............................................................................................................13-30

13-21 MISR Bit Definitions...............................................................................................................13-31

13-22 MODR Bit Definitions.............................................................................................................13-31

13-23 Address Mapping for CODEC Registers ...............................................................................13-33

13-24 Register Mapping Summary ..................................................................................................13-35

14-1 External Interface to CODEC...................................................................................................14-2

14-2 Supported Sampling Frequencies ...........................................................................................14-6

14-3 SACR0 Bit Definitions..............................................................................................................14-9

14-4 FIFO Write/Read table...........................................................................................................14-10

14-5 TFTH and RFTH Values for DMA Servicing ..........................................................................14-10

14-6 SACR1 Bit Definitions............................................................................................................14-11

14-7 SASR0 Bit Definitions ............................................................................................................14-12

14-8 SADIV Bit Definitions.............................................................................................................14-13

14-9 SAICR Bit Definitions.............................................................................................................14-13

14-10 SAIMR Bit Descriptions .........................................................................................................14-14

14-11 SADR Bit Descriptions...........................................................................................................14-14

14-12 Register Memory Map ...........................................................................................................14-16

15-1 Command Token Format.........................................................................................................15-2

15-2 MMC Data Token Format ........................................................................................................15-2

15-3 SPI Data Token Format...........................................................................................................15-2

15-4 MMC Signal Description ..........................................................................................................15-6

15-5 MMC_STRPCL Bit Definitions...............................................................................................15-23

15-6 MMC_STAT Bit Definitions....................................................................................................15-23

Intel® PXA255 Processor Developer’s Manual xxi

15-7 MMC_CLK Bit Definitions......................................................................................................15-25

15-8 MMC_SPI Bit Definitions .......................................................................................................15-25

15-9 MMC_CMDAT Bit Definitions ................................................................................................15-26

15-10 MMC_RESTO Bit Definitions.................................................................................................15-27

15-11 MMC_RDTO Register ...........................................................................................................15-28

15-12 MMC_BLKLEN Bit Definitions ...............................................................................................15-29

15-13 MMC_NOB Bit Definitions ..................................................................................................... 15-29

15-14 MMC_PRTBUF Bit Definitions...............................................................................................15-30

15-15 MMC_I_MASK Bit Definitions................................................................................................15-30

15-16 MMC_I_REG Bit Definitions ..................................................................................................15-32

15-17 MMC_CMD Register ............................................................................................................. 15-33

15-18 Command Index Values ........................................................................................................15-33

15-19 MMC_ARGH Bit Definitions...................................................................................................15-35

15-20 MMC_ARGL Bit Definitions ................................................................................................... 15-35

15-21 MMC_RES, FIFO Entry .........................................................................................................15-36

15-22 MMC_RXFIFO, FIFO Entry ...................................................................................................15-36

15-23 MMC_TXFIFO, FIFO Entry....................................................................................................15-37

15-24 MMC Controller Registers .....................................................................................................15-37

16-1 SSP Serial Port I/O Signals.....................................................................................................16-2

16-2 Programmable Serial Protocol (PSP) Parameters ................................................................16-12

16-3 SSCR0 Bit Definitions............................................................................................................16-19

16-4 SSCR1 Bit Definitions............................................................................................................16-21

16-5 SSPSP Bit Definitions............................................................................................................16-23

16-6 SSTO Bit Definitions..............................................................................................................16-24

16-7 SSITR Bit Definitions.............................................................................................................16-25

16-8 SSSR Bit Definitions..............................................................................................................16-26

16-9 SSDR Bit Definitions..............................................................................................................16-29

16-10 NSSP Register Address Map ................................................................................................16-29

17-1 UART Signal Descriptions.......................................................................................................17-3

17-2 RBR Bit Definitions................................................................................................................17-10

17-3 THR Bit Definitions ................................................................................................................17-10

17-4 DLL Bit Definitions.................................................................................................................17-11

17-5 Divisor Latch Register High (DLH) Bit Definitions ................................................................. 17-11

17-6 IER Bit Definitions..................................................................................................................17-12

17-7 Interrupt Conditions ...............................................................................................................17-13

17-8 IIR Bit Definitions...................................................................................................................17-13

17-9 Interrupt Identification Register Decode ................................................................................17-14

17-10 FCR Bit Definitions ................................................................................................................17-15

17-11 FOR Bit Definitions................................................................................................................17-16

17-12 ABR Bit Definitions ................................................................................................................17-17

17-13 ACR Bit Definitions................................................................................................................17-18

17-14 LCR Bit Definitions ................................................................................................................17-18

17-15 LSR Bit Definitions.................................................................................................................17-20

17-16 MCR Bit Definitions ...............................................................................................................17-22

17-17 MSR Bit Definitions................................................................................................................17-23

17-18 SCR Bit Definitions................................................................................................................17-24

17-19 ISR Bit Definitions..................................................................................................................17-25

17-20 HWUART Register Locations................................................................................................17-25

Revision History

Date Revision Description

March 2003 -001 Initial release

January 2004 -002

Contents

Replaced Table 12-13

Modified SSPFRM behavior

Added note to Table 3-1 about supported frequencies

Explained RDY_sync signal

Correct GPIO numbers in Table 4-35

Changed behavior of GPIO pins out of reset

Added Polling directions for I2C

Intel® PXA255 Processor Developer’s Manual xxiii

Contents

xxiv Intel® PXA255 Processor Developer’s Manual

Introduction 1

This document applies to the Intel® PXA255 Processor (PXA255 processor). It is an application specific standard product (ASSP) that provides industry-leading MIPS/mW performance for handheld computing applications. The processor is a highly integrated system on a chip and includes a high-performance low-power Intel XScale® microarchitecture with a variety of different system peripherals.

The PXA255 processor is a 17x17mm 256-pin PBGA package configuration for high performance. The 17x17mm package has a 32-bit memory data bus and the full assortment of peripherals.

1.1 Intel XScale® Microarchitecture Features

The Intel XScale® microarchitecture provides these features:

• ARM* Architecture Version 5TE ISA compliant.

— ARM* Thumb Instruction Support

— ARM* DSP Enhanced Instructions

• Low power consumption and high performance

• Intel® Media Processing Technology

— Enhanced 16-bit Multiply

— 40-bit Accumulator

• 32-KByte Instruction Cache

• 32-KByte Data Cache

• 2-KByte Mini Data Cache

• 2-KByte Mini Instruction Cache

• Instruction and Data Memory Management Units

• Branch Target Buffer

• Debug Capability via JTAG Port

Refer to the Intel XScale® Microarchitecture for the Intel® PXA255 Processor User’s Manual for more details.

1.2 System Integration Features

The processor integrates the Intel XScale® microarchitecture with this peripheral set:

• Memory Controller

• Clock and Power Controllers

• Universal Serial Bus Client

Intel® PXA255 Processor Developer’s Manual 1-1

Introduction

• DMA Controller

• LCD Controller

• AC97

• I

• MultiMediaCard

• FIR Communication

• Synchronous Serial Protocol Port

• I

• General Purpose I/O pins

• UARTs

• Real-Time Clock

• OS Timers

• Pulse Width Modulation

• Interrupt Control

1.2.1 Memory Controller

The Memory Controller provides glueless control signals with programmable timing for a wide assortment of memory-chip types and organizations. It supports up to four SDRAM partitions; six static chip selects for SRAM, SSRAM, Flash, ROM, SROM, and companion chips; support for two PCMCIA or Compact Flash slots

1.2.2 Clocks and Power Controllers

The processor functional blocks are driven by clocks that are derived from a 3.6864-MHz crystal and an optional 32.768-kHz crystal.

The 3.6864-MHz crystal drives a core Phase Locked Loop (PLL) and a Peripheral PLL. The PLLs produce selected clock frequencies to run particular functional blocks.

The 32.768-kHz crystal provides an optional clock source that must be selected after a hard reset. This clock drives the Real Time Clock (RTC), Power Management Controller, and Interrupt Controller. The 32.768-kHz crystal is on a separate power island to provide an active clock while the processor is in sleep mode.

Power management controls the transition between the turbo/run, idle, and sleep operating modes.

1.2.3 Universal Serial Bus (USB) Client

The USB Client Module is based on the Universal Serial Bus Specification, Revision 1.1. It supports up to sixteen endpoints and it provides an internally generated 48-MHz clock. The USB Device Controller provides FIFOs with DMA access to or from memory.

1-2 Intel® PXA255 Processor Developer’s Manual

1.2.4 DMA Controller (DMAC)

The DMAC provides sixteen prioritized channels to service transfer requests from internal peripherals and up to two data transfer requests from external companion chips. The DMAC is descriptor-based to allow command chaining and looping constructs.

The DMAC operates in Flow-Through Mode when performing peripheral-to-memory, memory-toperipheral, and memory-to-memory transfers. The DMAC is compatible with peripherals that use word, half-word, or byte data sizes.

1.2.5 LCD Controller

The LCD Controller supports both passive (DSTN) and active (TFT) flat-panel displays with a maximum supported resolution of 640x480x16-bit/pixel. An internal 256 entry palette expands 1, 2, 4, or 8-bit encoded pixels. Non-encoded 16-bit pixels bypass the palette.

Two dedicated DMA channels allow the LCD Controller to support single- and dual-panel displays. Passive monochrome mode supports up to 256 gray-scale levels and passive color mode supports up to 64K colors. Active color mode supports up to 64K colors.

Introduction

1.2.6 AC97 Controller

The AC97 Controller supports AC97 Revision 2.0 CODECs. These CODECs can operate at sample rates up to 48 KHz. The controller provides independent 16-bit channels for Stereo PCM In, Stereo PCM Out, Modem In, Modem Out, and mono Microphone In. Each channel includes a FIFO that supports DMA access to memory.

1.2.7 Inter-IC Sound (I2S) Controller

The I2S Controller provides a serial link to standard I2S CODECs for digital stereo sound. It supports both the Normal-I connection to an I The controller includes FIFOs that support DMA access to memory.

S CODEC. I2S Controller signals are multiplexed with AC97 Controller pins.

S and MSB-Justified I2S formats, and provides four signals for

1.2.8 Multimedia Card (MMC) Controller

The MMC Controller provides a serial interface to standard memory cards. The controller supports up to two cards in either MMC or SPI modes with serial data transfers up to 20 Mbps. The MMC controller has FIFOs that support DMA access to and from memory.

1.2.9 Fast Infrared (FIR) Communication Port

The FIR Communication Port is based on the 4-Mbps Infrared Data Association (IrDA) Specification. It operates at half-duplex and has FIFOs with DMA access to memory. The FIR Communication Port uses the STUART’s transmit and receive pins to directly connect to external IrDA LED transceivers.

Intel® PXA255 Processor Developer’s Manual 1-3

Introduction

1.2.10 Synchronous Serial Protocol Controller (SSPC)

The SSP Port provides a full-duplex synchronous serial interface that operates at bit rates from

7.2 kHz to 1.84 MHz. It supports National Semiconductor’s Microwire*, Texas Instruments’ Synchronous Serial Protocol*, and Motorola’s Serial Peripheral Interface*. The SSPC has FIFOs with DMA access to memory.

1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit

The I2C Bus Interface Unit provides a general purpose 2-pin serial communication port.The interface uses one pin for data and address and a second pin for clocking.

1.2.12 GPIO

Each GPIO pin can be individually programmed as an output or an input. Inputs can cause interrupts on rising or falling edges. Primary GPIO pins are not shared with peripherals while secondary GPIO pins have alternate functions which can be mapped to the peripherals.

1.2.13 UARTs

The processor provides three Universal Asynchronous Receiver/Transmitters. Each UART can be used as a slow infrared (SIR) transmitter/receiver based on the Infrared Data Association Serial Infrared (SIR) Physical Layer Link Specification.

1.2.13.1 Full Function UART (FFUART)

The FFUART baud rate is programmable up to 230 Kbps. The FFUART provides a complete set of modem control pins: nCTS, nRTS, nDSR, nDTR, nRI, and nDCD. It has FIFOs with DMA access to or from memory.

1.2.13.2 Bluetooth UART (BTUART)

The BTUART baud rate is programmable up to 921 Kbps. The BTUART provides a partial set of modem control pins: nCTS and nRTS. Other modem control pins can be implemented via GPIOs. The BTUART has FIFOs with DMA access to or from memory.

1.2.13.3 Standard UART (STUART)

The STUART baud rate is programmable up to 230 Kbps. The STUART does not provide any modem control pins. The modem control pins can be implemented via GPIOs. The STUART has FIFOs with DMA access to or from memory.

The STUART’s transmit and receive pins are multiplexed with the Fast Infrared Communication Port.

1-4 Intel® PXA255 Processor Developer’s Manual

1.2.13.4 Hardware UART (HWUART)

The PXA255 processor has a UART with hardware flow control. The HWUART provides a partial set of modem control pins: nCTS and nRTS. These modem control pins provide full hardware flow control. Other modem control pins can be implemented via GPIOs. The HWUART baud rate is programmable up to 921.6 Kbps.

The HWUART’s pins are multiplexed with the PCMCIA control pins. Because of this, these HWUART pins operate at the same voltage as the memory bus. Also, since the PCMCIA pin nPWE is used for variable-latency input/output (VLIO), while using these pins for the HWUART, VLIO is unavailable. The HWUART pins are also available over the BTUART pins. When operating over the BTUART pins, the HWUART pins operate at the I/O voltage.

1.2.14 Real-Time Clock (RTC)

The Real-Time Clock can be clocked from either crystal. A system with a 32.768-KHz crystal consumes less power during Sleep versus a system using only the 3.6864-MHz crystal. This crystal can be removed to save system cost. The RTC provides a constant frequency output with a programmable alarm register. This alarm register can be used to wake up the processor from Sleep mode.

Introduction

1.2.15 OS Timers

The OS Timers can be used to provide a 3.68-MHz reference counter with four match registers. These registers can be configured to cause interrupts when equal to the reference counter. One match register can be used to cause a watchdog reset.

1.2.16 Pulse-Width Modulator (PWM)

The PWM has two independent outputs that can be programmed to drive two GPIOs. The frequency and duty cycle are independently programmable. For example, one GPIO can control LCD contrast and the other LCD brightness.

1.2.17 Interrupt Control

The Interrupt Controller directs the processor interrupts into the core’s IRQ and FIQ inputs. The Mask Register enables or disables individual interrupt sources.

1.2.18 Network Synchronous Serial Protocol Port

The PXA255 processor has an SSP port optimized for connection to other network ASICs. This NSSP adds a Hi-Z function to TXD, the ability to control when Hi-Z occurs, and swapping the TXD/RXD pins.

This port is not multiplexed with other interfaces.

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Introduction

1-6 Intel® PXA255 Processor Developer’s Manual

System Architecture 2

2.1 Overview

The PXA255 processor is an integrated system-on-a-chip microprocessor for high performance, low power portable handheld and handset devices. It incorporates the Intel XScale® microarchitecture with on-the-fly frequency scaling and sophisticated power management to provide industry leading MIPs/mW performance. The PXA255 processor is ARM* Architecture Version 5TE instruction set compliant (excluding floating point instructions) and follows the ARM* programmer’s model.

The processor’s memory interface supports a variety of memory types to allow design flexibility. Support for the connection of two companion chips permits a glueless interface to external devices. An integrated LCD display controller provides support for displays up to 640x480 pixels, and permits 1-, 2-, 4-, and 8-bit grayscale and 8- or 16-bit color pixels. A 256 entry/512 byte palette RAM provides flexibility in color mapping.

A set of serial devices and general system resources provide computational and connectivity capability for a variety of applications. Refer to Figure 2-1 for an overview of the microprocessor system architecture.

Intel® PXA255 Processor Developer’s Manual 2-1

0 1

System Architecture

Figure 2-1. Block Diagram

RTC

OS Timer

PWM(2)

Int.

Controller

Clocks &

Power Man.

I2S

I2C

AC97

UARTs

General Purpose I/O

NSSP

Slow IrDA

Fast IrDA

SSP USB

Client

MMC

and Bridge

Peripheral Bus

DMA Controller

Color or

Grayscale

LCD

Controller

System Bus

Intelﬁ XScale

Microarchitecture

3.6864 MHz

Osc

32.768 KHz Osc

Memory

Controller

Variable

Latency I/O

Control

PCMCIA

& CF

Control

Dynamic

Memory

Control

Static

Memory

Control

ASIC

XCVR

SDRAM/ SMROM

4 banks

ROM/ Flash/ SRAM

4 banks

Socket Socket

2.2 Intel XScale® Microarchitecture Implementation Options

The processor incorporates the Intel XScale® microarchitecture which is described in a separate document. This core contains implementation options which an Application Specific Standard Product (ASSP) may elect to implement or omit. This section describes those options.

Most of these options are specified within the coprocessor register space. The processor does not implement any coprocessor registers beyond those defined in the Intel XScale® microarchitecture. The coprocessor registers which are ASSP specific, as stated in the Intel XScale® Microarchitecture for the Intel® PXA255 Processor User’s Manual, order number 278793, are defined in the following sections.

2.2.1 Coprocessor 7 Register 4 - PSFS Bit

Bit 5 of this register is defined as the Power Source Fault Status bit or PSFS bit. This bit is set when either nVDD_FAULT or nBATT_FAULT pins are asserted and the Imprecise Data Abort Enable (IDAE) bit in the Power Manager Control Register (PMCR) is set.

This is a read-only register. Ignore reads from reserved bits.

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Table 2-1. CPU Core Fault Register Bit Definitions

System Architecture

Coprocessor 7

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31:6] —

5 PSFS

[4:0] —

CPU Core Fault System Architecture

Reserved

Reserved.

Read undefined.

Power Source Fault Status

0 = nVDD_FAULT or nBATT_FAULT pin has not been asserted since it was

last cleared by a reset or the CPU.

1 = nVDD_FAULT or nBATT_FAULT pin was asserted and PMCR[IDAE] =

Read only, write ignored.

Cleared by Hardware, Watchdog, and GPIO Resets.

Reserved.

Read undefined.

PSFS

Reserved

2.2.2 Coprocessor 14 Registers 0-3 - Performance Monitoring

The processor does not define any performance monitoring features beyond those called out in the Intel XScale® Microarchitecture for the Intel® PXA255 Processor User’s Manual, order number

278793. The interrupt generated by performance monitoring events is defined in Chapter 4,

“System Integration Unit”. The ASSP defined performance monitoring events (events 0x10 -

0x17), defined through the PMNC register are reserved for the processor.

2.2.3 Coprocessor 14 Register 6 and 7- Clock and Power Management

These registers allow software to use the clocking and power management modes. The valid operations are described in Table 3-23, “Coprocessor 14 Clock and Power Management Summary”

on page 3-39.

2.2.4 Coprocessor 15 Register 0 - ID Register Definition

This register may be read by software to determine the device type and revision. The contents of this register for the Intel® PXA255 Processor is defined in the table below. Combined, this register must read as 0x6905 2X0R where R = 0b0000 for the first stepping and then increments for subsequent steppings, and X is the revision of the Intel XScale® microarchitecture present. Please see the Intel Developer Homepage at http://developer.intel.com for updates.

This is a read-only register.

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System Architecture

Table 2-2. ID Bit Definitions

CP15 Register 0 ID CP15

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Trademark

Implementation

Reset 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0

[31:24]

[23:16]

[15:13] Core Generation

[12:10] Core Revision

[9:4] Product Number

[3:0] Product Revision

Implementation

Trademark

Architecture

Versi on

Architecture

Implementation trademark.

– Intel® Corporation.

0x69

ARM* Architecture version of the core.

– ARM* Architecture version 5TE

0x05

This field is updated when new sets of features are added to the core. This allows software that is dependant on core features to target a specific core.

Core generation:

– Intel XScale® core

0b001

This field is updated each time a core is revised. Differences may include errata, software workarounds, etc.

Core revision:

0b000

– First version of the core.

0b010

– Third version of the core.

0b011

– Fourth version of the core.

Product Number

0b010000 – PXA255 processor

This field tracks the different steppings for each ASSP.

Product Revision

– A0 Stepping

0b0110

Core

generation

Core

Revision

Product

Number

Product

Revision

Table 2-3. PXA255 Processor ID Values

Stepping ARM ID JTAG ID

A0 0x6905_2D06 0x6926_4013

2.2.5 Coprocessor 15 Register 1 - P-Bit

Bit 1 of this register is defined as the Page Table Memory Attribute bit or P-bit. It is not implemented in the processor and must be written as zero. Similarly, the P-bit in the page table descriptor in the MMU is not implemented and must be written to zero.

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2.3 I/O Ordering

The processor uses queues that accept memory requests from the three internal masters: core, DMA Controller, and LCD Controller. Operations issued by a master are completed in the order they were received. Operations from one master may be interrupted by operations from another master. The processor does not provide a method to regulate the order of operations from different masters.

Loads and stores to internal addresses are generally completed more quickly than those issued to external addresses. The difference in completion time allows one operation to be received before another operation, but completed after the second operation.

In the following sequence, the store to the address in r4 is completed before the store to the address in r2 because the first store waits for memory in the queue while the second is not delayed.

str r1, [r2] ; store to external memory address [r2].

str r3, [r4] ; store to internal (on-chip) memory address [r4].

If the two stores are control operations that must be completed in order, the recommended sequence is to insert a load to an unbuffered, uncached memory page followed by an operation that depends on data from the load:

System Architecture

str r1, [r2] ; first store issued

ldr r5, [r6] ; load from external unbuffered, uncached address ([r2] if possible)

mov r5, r5 ; nop stalls until r5 is loaded

str r3, [r4] ; second store completes in program order

2.4 Semaphores

The Swap (SWP) and Swap Byte (SWPB) instructions, as described in the ARM* Architecture reference, may be used for semaphore manipulation. No on-chip master or process can access a memory location between the load and store portion of a SWP or SWPB to the same location.

Note: Semaphore coherency may be interrupted because an external companion chip that uses the

MBREQ/MBGNT handshake can take ownership of the bus during a locked sequence. To allow semaphore manipulation by external companion chips, the software must manage coherency.

2.5 Interrupts

The interrupt controller is described in detail in Section 4.2, “Interrupt Controller”. All on-chip interrupts are enabled, masked, and routed to the core FIQ or IRQ. Each interrupt is enabled or disabled at the source through an interrupt mask bit. Generally, all interrupt bits in a unit are ORed together and present a single value to the interrupt controller.

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System Architecture

Each interrupt goes through the Interrupt Controller Mask Register and then the Interrupt Controller Level Register directs the interrupt into either the IRQ or FIQ. If an interrupt is taken, the software may read the Interrupt Controller Pending Register to identify the source. After it identifies the interrupt source, software is responsible for servicing the interrupt and clearing it in the source unit before exiting the service routine.

Note: Clearing interrupts may take a delay. To allow the status bit to clear before returning from an

interrupt service routine (ISR), clear the interrupt early in the routine.

2.6 Reset

The processor can be reset in any of three ways: Hardware, Watchdog, and GPIO resets. Each is described in more detail in Section 3.4, “Resets and Power Modes” on page 3-6.

• Hardware reset results from asserting the nRESET pin and forces all units into reset state.

• Watchdog reset results from a time-out in the OS Timer and may be used to recover from

runaway code. Watchdog reset is disabled by default and must be enabled by software.

• GPIO reset is a “soft reset” that is less destructive than Hardware and Watchdog resets.

Each type of reset affects the state of the processor pins. Table 2-4 shows each pin’s state after each type of reset.

Leaving Sleep Mode causes a Sleep Mode reset. Unlike other resets, Sleep Mode resets do not change the state of the pins.

The Reset Controller Status Register (RCSR) contains information on the type of reset, including Sleep Mode resets.

Table 2-4. Effect of Each Type of Reset on Internal Register State (Sheet 1 of 2)

Unit Sleep Mode GPIO Reset Watchdog Reset Hard Reset

Core reset reset reset reset

Memory Controller reset preserved reset reset

LCD Controller reset reset reset reset

DMA Controller reset reset reset reset

Full Function UART reset reset reset reset

Bluetooth UART reset reset reset reset

Standard UART reset reset reset reset

Hardware UART reset reset reset reset

C reset reset reset reset

S reset reset reset reset

AC97 reset reset reset reset

USB reset reset reset reset

ICP reset reset reset reset

RTC preserved preserved reset (except RTTR) reset

OS Timer reset reset reset reset

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System Architecture

Table 2-4. Effect of Each Type of Reset on Internal Register State (Sheet 2 of 2)

Unit Sleep Mode GPIO Reset Watchdog Reset Hard Reset

PWM reset reset reset reset

Interrupt Controller reset reset reset reset

GPIO reset reset reset reset

Power Manager preserved reset reset reset

SSP reset reset reset reset

NSSP reset reset reset reset

MMC reset reset reset reset

Clocks preserved (except CP14) preserved (except CP14) reset (except OSCC) reset

2.7 Internal Registers

All internal registers are mapped in physical memory space on 32-bit address boundaries. Use word access loads and stores to access internal registers. Internal register space must be mapped as non-cacheable.

Byte and halfword accesses to internal registers are not permitted and yield unpredictable results.

Register space where a register is not specifically mapped is defined as reserved space. Reading or writing reserved space causes unpredictable results.

The processor does not use all register bit locations. The unused bit locations are marked reserved and are allocated for future use. Write reserved bit locations as zeros. Ignore the values of these bits during reads because they are unpredictable.

2.8 Selecting Peripherals vs. General Purpose I/O

Most peripherals connect to the external pins through GPIOs. To use a peripheral connected through a GPIO, the software must first configure the GPIO so that the desired peripheral is connected to its pins. The default state of the pins is GPIO inputs.

To allocate a peripheral to a pin, disable the GPIO function for that pin, then map the peripheral function onto the pin by selecting the proper alternate function for the pin. Some GPIOs have multiple alternate functions. After a function is selected for a pin, all other functions are excluded. For this reason some peripherals are mapped to multiple GPIOs, as shown in Section 4.1.2, “GPIO

Alternate Functions” on page 4-2. Multiple mapping does not mean multiple instances of a

peripheral - only that the peripheral is connected to the pins in several ways.

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2.9 Power on Reset and Boot Operation

Before the device that uses the processor is powered on, the system must assert nRESET and nTRST. To allow the internal clocks to stabilize, all power supplies must be stable for a specified period before nRESET or nTRST are deasserted. When nRESET is asserted, nRESET_OUT is driven active and can be used to reset other devices in the system. For additional information, see the Intel® PXA255 Processor Design Guide.

When the system deasserts nRESET and nTRST, the processor deasserts nRESET_OUT a specified time later and the device attempts to boot from physical address location 0x0000_0000.

The BOOT_SEL[2:0] pins are sampled when reset is deasserted and let the user specify the type and width of memory device from which the processor attempts to boot. The software can read the pins as described in Section 6.10.2, “Boot Time Defaults” on page 6-74.

2.10 Power Management

The processor offers a number of modes to manage power in the system. These range widely in level of power savings and level of functionality. The following modes are supported:

• Turbo Mode: low latency (nanoseconds) switch between two preprogrammed frequencies.

• Run Mode: normal full function mode.

• Idle Mode: core clocks are stopped - resume through an interrupt.

• Sleep Mode: low power mode that does not save state but keeps I/Os powered. The RTC,

Power Manager, and Clock modules are saved, except for Coprocessor 14.

Note: In low power modes, ensure that input pins are not floating and output pins are not driven by an

external device that opposes how the processor is driving that pin. In either case, the system will draw excess current. Current draw that varies in sleep mode or varies greatly between parts is typically a sign of floating pins.

Section 3.4, “Resets and Power Modes” describes the modes in detail.

2.11 Pin List

Some of the processor pins can be connected to multiple signals. The signal connected to the pin is determined by the GPIO Alternate Function Select Registers (GAFRn m). Some signals can go to multiple pins. The signal must be routed to only one pin by using the GAFRn m registers. Because this is true, some pins are listed twice, once in each unit that can use the pin.

Table 2-5. Processor Pin Types

Type Function

IC CMOS input

OC CMOS output

OCZ CMOS output, Hi-Z

ICOCZ CMOS bidirectional, Hi-Z

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System Architecture

Table 2-5. Processor Pin Types

Type Function

IA Analog Input

OA Analog output

IAOA Analog bidirectional

SUP Supply pin (either VCC or VSS)

Table 2-6 describes the PXA255 processor pins.

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 1 of 9)

Pin Name Type Signal Descriptions Reset State Sleep State

Memory Controller Pins

MA[25:0] OCZ

MD[15:0] ICOCZ

MD[31:16] ICOCZ

nOE OCZ

nWE OCZ

nSDCS[3:0] OCZ

DQM[3:0] OCZ

nSDRAS OCZ

nSDCAS OCZ

SDCKE[0] OC

SDCKE[1] OC

SDCLK[0] OC

Memory address bus. (output) Signals the address requested for memory accesses.

Memory data bus. (input/output) Lower 16 bits of the data bus.

Memory data bus. (input/output) Used for 32-bit memories.

Memory output enable. (output) Connect to the output enables of memory devices to control data bus drivers.

Memory write enable. (output) Connect to the write enables of memory devices.

SDRAM CS for banks 3 through 0. (output) Connect to the chip select (CS) pins for SDRAM. For the PXA255 processor nSDCS0 can be Hi-Z, nSDCS1-3 cannot.

SDRAM DQM for data bytes 3 through 0. (output) Connect to the data output mask enables (DQM) for SDRAM.

SDRAM RAS. (output) Connect to the row address strobe (RAS) pins for all banks of SDRAM.

SDRAM CAS. (output) Connect to the column address strobe (CAS) pins for all banks of SDRAM.

Synchronous Static Memory clock enable. (output) Connect to the CKE pins of SMROM. The memory controller provides control register bits for deassertion.

SDRAM and/or Synchronous Static Memory clock enable. (output) Connect to the clock enable pins of

SDRAM. It is deasserted during sleep. SDCKE[1] is always deasserted upon reset. The memory controller provides control register bits for deassertion.

Synchronous Static Memory clock. (output) Connect to the clock (CLK) pins of SMROM. It is driven by either the internal memory controller clock, or the internal memory controller clock divided by 2. At reset, all clock pins are free running at the divide by 2 clock speed and may be turned off via free running control register bits in the memory controller. The memory controller also provides control register bits for clock division and deassertion of each SDCLK pin. SDCLK[0] control register assertion bit defaults to on if the boot-time static memory bank 0 is configured for SMROM.

Driven Low Driven Low

Hi-Z Driven Low

Driven High Note [4]

Driven High Note [5]

Driven Low Driven Low

Driven High Driven High

Driven Low Driven Low

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System Architecture

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 2 of 9)

Pin Name Type Signal Descriptions Reset State Sleep State

SDCLK[1] OCZ SDRAM Clocks (output) Connect SDCLK[1] and

SDCLK[2] OC Driven Low Driven Low

nCS[5]/

GPIO[33]

nCS[4]/

GPIO[80]

nCS[3]/

GPIO[79]

nCS[2]/

GPIO[78]

nCS[1]/

GPIO[15]

nCS[0] ICOCZ

RD/nWR OCZ

RDY/

GPIO[18]

L_DD[8]/

GPIO[66]

L_DD[15]/

GPIO[73]

MBGNT/ GP[13]

MBREQ/ GP[14]

PCMCIA/CF Control Pins

nPOE/

GPIO[48]

nPWE/

GPIO[49]

ICOCZ

SDCLK[2] to the clock pins of SDRAM in bank pairs 0/1 and 2/3, respectively. They are driven by either the internal memory controller clock, or the internal memory controller clock divided by 2. At reset, all clock pins are free running at the divide by 2 clock speed and may be turned off via free running control register bits in the memory controller. The memory controller also provides control register bits for clock division and deassertion of each SDCLK pin. SDCLK[2:1] control register assertion bits are always deasserted upon reset.

Static chip selects. (output) Chip selects to static memory devices such as ROM and Flash. Individually programmable in the memory configuration registers. nCS[5:0] can be used with variable latency I/O devices.

Static chip select 0. (output) Chip select for the boot memory. nCS[0] is a dedicated pin.

Read/Write for static interface. (output) Signals that the current transaction is a read or write.

Variable Latency I/O Ready pin. (input) Notifies the memory controller when an external bus device is ready to transfer data.

LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel.

Memory Controller alternate bus master request.

(input) Allows an external device to request the system bus from the Memory Controller.

LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel.

Memory Controller grant. (output) Notifies an external device that it has been granted the system bus.

Memory Controller alternate bus master request.

(input) Allows an external device to request the system bus from the Memory Controller.

PCMCIA output enable. (output) Reads from PCMCIA memory and to PCMCIA attribute space.

PCMCIA write enable. (output) Performs writes to PCMCIA memory and to PCMCIA attribute space. Also used as the write enable signal for Variable Latency I/O.

Driven Low Driven Low

Pulled High Note[1]

Driven High Note [4]

Driven Low Holds last state

Pulled High Note[1]

Note [4]

Note [3]

Note [5]

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System Architecture

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 3 of 9)

Pin Name Type Signal Descriptions Reset State Sleep State

nPIOW/

GPIO[51]

nPIOR/

GPIO[50]

nPCE[2]/

GPIO[53]

nPCE[1]/

GPIO[52]

nIOIS16/

GPIO[57]

nPWAIT/

GPIO[56]

PSKTSEL/

GPIO[54]

nPREG/

GPIO[55]

LCD Controller Pins

L_DD(7:0)/

GPIO[65:58]

L_DD[8]/

GPIO[66]

L_DD[9]/

GPIO[67]

L_DD[10]/

GPIO[68]

L_DD[11]/

GPIO[69]

L_DD[12]/

GPIO[70]

ICOCZ

PCMCIA I/O write. (output) Performs write transactions to PCMCIA I/O space.

PCMCIA I/O read. (output) Performs read transactions from PCMCIA I/O space.

PCMCIA card enable 2. (output) Selects a PCMCIA card. nPCE[2] enables the high byte lane and nPCE[1] enables the low byte lane.

MMC clock. (output) Clock signal for the MMC Controller.

PCMCIA card enable 1. (outputs) Selects a PCMCIA card. nPCE[2] enables the high byte lane and nPCE[1] enables the low byte lane.

IO Select 16. (input) Acknowledge from the PCMCIA card that the current address is a valid 16 bit wide I/O address.

PCMCIA wait. (input) Driven low by the PCMCIA card to extend the length of the transfers to/from the PXA255 processor.

PCMCIA socket select. (output) Used by external steering logic to route control, address, and data signals to one of the two PCMCIA sockets. When PSKTSEL is low, socket zero is selected. When PSKTSEL is high, socket one is selected. Has the same timing as the address bus.

PCMCIA Register select. (output) Indicates that the target address on a memory transaction is attribute space. Has the same timing as the address bus.

LCD display data. (outputs) Transfers pixel information from the LCD Controller to the external LCD panel.

LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel.

Memory Controller alternate bus master request.

(input) Allows an external device to request the system bus from the Memory Controller.

LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel.

MMC chip select 0. (output) Chip select 0 for the MMC Controller.

LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel.

MMC chip select 1. (output) Chip select 1 for the MMC Controller.

LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel.

MMC clock. (output) Clock for the MMC Controller.

LCD display data. (output) Transfers pixel information

from the LCD Controller to the external LCD panel.

RTC clock. (output) Real time clock 1 Hz tick.

Pulled High Note[1]

Note [5]

Note [3]

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System Architecture

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 4 of 9)

Pin Name Type Signal Descriptions Reset State Sleep State

L_DD[13]/

GPIO[71]

L_DD[14]/

GPIO[72]

L_DD[15]/

GPIO[73]

L FCLK/

GPIO[74]

L LCLK/

GPIO[75]

L PCLK/

GPIO[76]

L BIAS/

GPIO[77]

Full Function UART Pins

FFRXD/

GPIO[34]

FFTXD/

GPIO[39]

FFCTS/

GPIO[35]

FFDCD/

GPIO[36]

FFDSR/

GPIO[37]

FFRI/

GPIO[38]

FFDTR/

GPIO[40]

FFRTS/

GPIO[41]

Bluetooth UART Pins

BTRXD/

GPIO[42]

BTTXD/

GPIO[43]

ICOCZ

ICOCZ Full Function UART Clear-to-Send. (input)

ICOCZ Full Function UART Data-Carrier-Detect. (input)

ICOCZ Full Function UART Data-Set-Ready. (input)

ICOCZ Full Function UART Ring Indicator. (input)

ICOCZ Full Function UART Data-Terminal-Ready. (output)

ICOCZ Full Function UART Request-to-Send. (output)

ICOCZ Bluetooth UART Receive. (input)

ICOCZ Bluetooth UART Transmit. (output)

LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel.

3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator.

LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel.

32 kHz clock. (output) Output from the 32 kHz oscillator.

LCD display data. (output) Transfers pixel information

from the LCD Controller to the external LCD panel.

Memory Controller grant. (output) Notifies an external device it has been granted the system bus.

LCD frame clock. (output) Indicates the start of a new frame. Also referred to as Vsync.

LCD line clock. (output) Indicates the start of a new line. Also referred to as Hsync.

LCD pixel clock. (output) Clocks valid pixel data into the LCD’s line shift buffer.

AC bias drive. (output) Notifies the panel to change the polarity for some passive LCD panel. For TFT panels, this signal indicates valid pixel data.

Full Function UART Receive. (input)

MMC chip select 0. (output) Chip select 0 for the MMC

Controller.

Full Function UART Transmit. (output)

MMC chip select 1. (output) Chip select 1 for the MMC

Controller.

Pulled High Note[1]

Note [3]

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Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 5 of 9)

Pin Name Type Signal Descriptions Reset State Sleep State

BTCTS/

GPIO[44]

BTRTS/

GPIO[45]

Standard UART and ICP Pins

IRRXD/

GPIO[46]

IRTXD/

GPIO[47]

HWUART Pins

HWTXD/ GPIO[48]

HWRXD/ GPIO[49]

HWCTS/ GPIO[50]

HWRTS/ GPIO[51]

MMC Controller Pins

MMCMD ICOCZ Multimedia Card Command. (bidirectional) Hi-Z Hi-Z

MMDAT ICOCZ Multimedia Card Data. (bidirectional) Hi-Z Hi-Z

nPCE[2]/

GPIO[53]

L_DD[9]/

GPIO[67]

L_DD[10]/

GPIO[68]

L_DD[11]/

GPIO[69]

FFRXD/

GPIO[34]

FFTXD/

GPIO[39]

ICOCZ Bluetooth UART Clear-to-Send. (input)

ICOCZ Bluetooth UART Data-Terminal-Ready. (output)

IrDA receive signal. (input) Receive pin for the FIR

ICOCZ

ICOCZ Hardware UART Transmit Data.

ICOCZ Hardware UART Receive Data.

ICOCZ Hardware UART Clear-To-Send.

ICOCZ Hardware UART Request-to-Send.

ICOCZ

function.

Standard UART receive. (input)

IrDA transmit signal. (output) Transmit pin for the

Standard UART, SIR and FIR functions.

Standard UART transmit. (output)

PCMCIA card enable 2. (outputs) Selects a PCMCIA

card. Bit one enables the high byte lane and bit zero enables the low byte lane.

MMC clock. (output) Clock signal for the MMC Controller.

LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel.

MMC chip select 0. (output) Chip select 0 for the MMC Controller.

LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel.

MMC chip select 1. (output) Chip select 1 for the MMC Controller.

LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel.

MMC clock. (output) Clock for the MMC Controller.

Full Function UART Receive. (input)

MMC chip select 0. (output) Chip select 0 for the MMC

Controller.

Full Function UART Transmit. (output)

MMC chip select 1. (output) Chip select 1 for the MMC

Controller.

Pulled High Note[1]

Pulled High

Note [1]

Pulled High

Note [1]

Pulled High

Note [1]

Pulled High

Note [1]

Pulled High Note[1]

Note [3]

Note [5]

Note [3]

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Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 6 of 9)

Pin Name Type Signal Descriptions Reset State Sleep State

MMCCLK/ GP[6]

MMCCS0/ GP[8]

MMCCS1/ GP[9]

SSP Pins

SSPSCLK/

GPIO[23]

SSPSFRM/

GPIO[24]

SSPTXD/

GPIO[25]

SSPRXD/

GPIO[26]

SSPEXTCLK/

GPIO[27]

Network SSP pins

NSSPSCLK/ GPIO[81]

NSSPSFRM/ GPIO[82]

NSSPTXD/ GPIO[83]

NSSPRXD/ GPIO[84]

USB Client Pins

USB P IAOAZ USB Client Positive. (bidirectional) Hi-Z Hi-Z

USB N IAOAZ USB Client Negative pin. (bidirectional) Hi-Z Hi-Z

AC97 Controller and I2S Controller Pins

BITCLK/

GPIO[28]

SDATA_IN0/

GPIO[29]

SDATA_IN1/

GPIO[32]

ICOCZ

ICOCZ Synchronous Serial Port Clock. (output)

ICOCZ Synchronous Serial Port Frame. (output)

ICOCZ Synchronous Serial Port Transmit. (output)

ICOCZ Synchronous Serial Port Receive. (input)

ICOCZ Synchronous Serial Port External Clock. (input)

ICOCZ Network Synchronous Serial Port Clock.

ICOCZ Network Synchronous Serial Port Frame Signal.

ICOCZ Network Synchronous Serial Port Transmit.

ICOCZ Network Synchronous Serial Port Receive.

ICOCZ

MMC clock. (output) Clock signal for the MMC Controller.

MMC chip select 0. (output) Chip select 0 for the MMC Controller.

MMC chip select 1. (output) Chip select 1 for the MMC Controller.

AC97 Audio Port bit clock. (input) AC97 clock is generated by Codec 0 and fed into the PXA255 processor and Codec 1.

AC97 Audio Port bit clock. (output) AC97 clock is generated by the PXA255 processor.

S bit clock. (input) I2S clock is generated externally

and fed into PXA255 processor.

S bit clock. (output) I2S clock is generated by the

PXA255 processor.

AC97 Audio Port data in. (input) Input line for Codec 0.

S data in. (input) Input line for the I2S Controller.

AC97 Audio Port data in. (input) Input line for Codec 1.

S system clock. (output) System clock from I2S

Controller.

Pulled High Note[1]

Pulled High

Note [1]

Pulled High

Note [1]

Pulled High

Note [1]

Pulled High

Note [1]

Pulled High Note[1]

Note [3]

2-14 Intel® PXA255 Processor Developer’s Manual

System Architecture

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 7 of 9)

Pin Name Type Signal Descriptions Reset State Sleep State

SDATA_OUT/

GPIO[30]

SYNC/

GPIO[31]

nACRESET OC AC97 Audio Port reset signal. (output) Driven Low Driven Low

I2C Controller Pins

SCL ICOCZ I

SDA ICOCZ I

PWM Pins

PWM[1:0]/

GPIO[17:16]

DMA Pins

DREQ[1:0]/

GPIO[19:20]

GPIO Pins

GPIO[1:0] ICOCZ

GPIO[14:2] ICOCZ

GPIO[22:21] ICOCZ

Crystal and Clock Pins

PXTAL IA 3.6864 Mhz crystal input. No external caps are required. Note [2] Note [2]

PEXTAL OA

TXTAL IA 32 Khz crystal input. No external caps are required. Note [2] Note [2]

TEXTAL OA 32 Khz crystal output. No external caps are required. Note [2] Note [2]

L_DD[12]/

GPIO[70]

L_DD[13]/

GPIO[71]

L_DD[14]/

GPIO[72]

ICOCZ

ICOCZ Pulse Width Modulation channels 0 and 1. (outputs)

ICOCZ

AC97 Audio Port data out. (output) Output from the PXA255 processor to Codecs 0 and 1.

S data out. (output) Output line for the I2S Controller.

AC97 Audio Port sync signal. (output) Frame sync

signal for the AC97 Controller.

S sync. (output) Frame sync signal for the I2S

Controller.

C clock. (bidirectional) Hi-Z Hi-Z

C data. (bidirectional). Hi-Z Hi-Z

DMA Request. (input) Notifies the DMA Controller that

an external device requires a DMA transaction. DREQ[1] is GPIO[19]. DREQ[0] is GPIO[20].

General Purpose I/O. Wakeup sources on both rising and falling edges on nRESET.

General Purpose I/O. More wakeup sources for sleep mode.

General Purpose I/O. Additional General Purpose I/O pins.

3.6864 Mhz crystal output. No external caps are required.

LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel.

RTC clock. (output) Real time clock 1 Hz tick.

LCD display data. (output) Transfers the pixel

information from the LCD Controller to the external LCD panel.

3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator.

LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel.

32 kHz clock. (output) Output from the 32 kHz oscillator.

Pulled High Note[1]

Pulled High

Note [1]

Pulled High

Note [1]

Pulled High

Note [1]

Note [2] Note [2]

Pulled High

Note [1]

Pulled High Note[1]

Note [3]

Intel® PXA255 Processor Developer’s Manual 2-15

System Architecture

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 8 of 9)

Pin Name Type Signal Descriptions Reset State Sleep State

48 MHz clock. (output) Peripheral clock output derived

48MHz/GP[7] ICOCZ

RTCCLK/ GP[10]

3.6MHz/GP[11] ICOCZ

32kHz/GP[12] ICOCZ 32 kHz clo ck. (output) Output from the 32 kHz oscillator.

Miscellaneous Pins

BOOT_SEL

[2:0]

PWR_EN OC

nBATT_FAULT IC

nVDD_FAULT IC

nRESET IC

nRESET_OUT OC

JTAG and Test Pins

nTRST IC

TDI IC

ICOCZ

IC Boot select pins. (input) Indicates type of boot device. Input Input

from the PLL. NOTE: This clock is only generated when the USB unit

clock enable is set.

Real time clock. (output) 1 Hz output derived from the 32kHz or 3.6864MHz output.

3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator.

Power Enable for the power supply. (output) When negated, it signals the power supply to remove power to the core because the system is entering sleep mode.

Main Battery Fault. (input) Signals that main battery is low or removed. Assertion causes PXA255 processor to enter sleep mode or force an Imprecise Data Exception, which cannot be masked. PXA255 processor will not recognize a walk-up event while this signal is asserted. Minimum assertion time for nBATT_FAULT is 1 ms.

VDD Fault. (input) Signals that the main power source is going out of regulation. nVDD_FAULT causes the PXA255 processor to enter sleep mode or force an Imprecise Data Exception, which cannot be masked. nVDD_FAULT is ignored after a walk-up event until the power supply timer completes (approximately 10 ms). Minimum assertion time for nVDD_FAULT is 1 ms.

Hard reset. (input) Level sensitive input used to start the processor from a known address. Assertion causes the current instruction to terminate abnormally and causes a reset. When nRESET is driven high, the processor starts execution from address 0. nRESET must remain low until the power supply is stable and the internal 3.6864 MHz oscillator has stabilized.

Reset Out. (output) Asserted when nRESET is asserted and deasserts after nRESET is deasserted but before the first instruction fetch. nRESET_OUT is also asserted for “soft” reset events: sleep, watchdog reset, or GPIO reset.

JTAG Test Interface Reset. Resets the JTAG/Debug port. If JTAG/Debug is used, drive nTRST from low to high either before or at the same time as nRESET. If JTAG is not used, nTRST must be either tied to nRESET or tied low.

JTAG test data input. (input) Data from the JTAG controller is sent to the PXA255 processor using this pin. This pin has an internal pull-up resistor.

Pulled High Note[1]

Driven High

Input Input

Input

Driven low during any reset sequence

- driven high prior to first fetch.

Input Input

Note [3]

Driven low while entering sleep mode. Driven high when sleep exit sequence begins.

Input. Driving low during sleep will cause normal reset sequence and exit from sleep mode.

Driven Low

2-16 Intel® PXA255 Processor Developer’s Manual

System Architecture

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 9 of 9)

Pin Name Type Signal Descriptions Reset State Sleep State

TDO OCZ

TMS IC

TCK IC

TEST IC Test Mode. (input) Reserved. Must be grounded. Input Input

TESTCLK IC Test Clock. (input) Reserved. Must be grounded. Input Input

Power and Ground Pins

VCC SUP

VSS SUP

PLL_VCC SUP

PLL_VSS SUP

VCCQ SUP

VSSQ SUP

VCCN SUP

VSSN SUP

JTAG test data output. (output) Data from the PXA255 processor is returned to the JTAG controller using this pin.

JTAG test mode select. (input) Selects the test mode required from the JTAG controller. This pin has an internal pull-up resistor.

JTAG test clock. (input) Clock for all transfers on the JTAG test interface.

Positive supply for internal logic. Must be connected to the low voltage supply on the PCB.

Ground supply for internal logic. Must be connected to the common ground plane on the PCB.

Positive supply for PLLs and oscillators. Must be connected to the common low voltage supply.

Ground supply for the PLL. Must be connected to common ground plane on the PCB.

Positive supply for all CMOS I/O except memory bus and PCMCIA pins. Must be connected to the common

3.3v supply on the PCB.

Ground supply for all CMOS I/O except memory bus and PCMCIA pins. Must be connected to the common

ground plane on the PCB.

Positive supply for memory bus and PCMCIA pins. Must be connected to the common 3.3v or 2.5v supply on the PCB.

Ground supply for memory bus and PCMCIA pins. Must be connected to the common ground plane on the PCB.

Hi-Z Hi-Z

Input Input

Powered Note [6]

Grounded Grounded

Powered Note [6]

Grounded Grounded

Powered Note [7]

Grounded Grounded

Powered Note [7]

Grounded Grounded

Table 2-7. Pin Description Notes (Sheet 1 of 2)

Note Description

GPIO Reset Operation: Configured as GPIO inputs by default after any reset. The input buffers for these pins are disabled to prevent current drain and the pins are pulled high with 10K to 60K internal resistors. The input paths must be enabled and the pullups turned off by clearing the Read Disable Hold (RDH) bit described in

[1]

Section 3.5.7, “Power Manager Sleep Status Register (PSSR)” on page 3-29. Even though sleep mode sets the

RDH bit, the pull-up resistors are not re-enabled by sleep mode.

Crystal oscillator pins: These pins are used to connect the external crystals to the on-chip oscillators. Refer to

[2]

Section 3.3.1, “32.768 kHz Oscillator” on page 3-4 and Section 3.3.2, “3.6864 MHz Oscillator” on page 3-4 for

details on Sleep Mode operation.

GPIO Sleep operation: During the transition into sleep mode, the state of these pins is determined by the corresponding PGSRn. See Section 3.5.10, “Power Manager GPIO Sleep State Registers (PGSR0, PGSR1,

PGSR2)” and Section 4.1.3.2, “GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)” on page 4-8. If

[3]

selected as an input, this pin does not drive during sleep. If selected as an output, the value contained in the Sleep State Register is driven out onto the pin and held there while the PXA255 processor is in Sleep Mode.

GPIOs configured as inputs after exiting sleep mode cannot be used until PSSR[RDH] is cleared.

Intel® PXA255 Processor Developer’s Manual 2-17

System Architecture

Table 2-7. Pin Description Notes (Sheet 2 of 2)

Note Description

Static Memory Control Pins: During Sleep Mode, these pins can be programmed to either drive the value in the Sleep State Register or to be placed in Hi-Z. To select the Hi-Z state, software must set the FS bit in the Power

[4]

Manager General Configuration Register. If PCFR[FS] is not set, then during the transition to sleep these pins function as described in [3], above. For nWE, nOE, and nCS[0], if PCFR[FS] is not set, they are driven high by the Memory Controller before entering sleep. If PCFR[FS] is set, these pins are placed in Hi-Z.

PCMCIA Control Pins: During Sleep Mode: Can be programmed either to drive the value in the Sleep State

[5]

Register or to be placed in Hi-Z. To select the Hi-Z state, software must set PCFR[FP]. If it is not set, then during the transition to sleep these pins function as described in [3], above.

[6] During sleep, this supply may be driven low. This supply must never be high impedance.

[7] Remains powered in sleep mode.

2.12 Memory Map

Figure 2-2 and Figure 2-3 show the full processor memory map.

Any unused register space from 0x4000_0000 to 0x4BFF_FFFF is reserved.

Note: Accessing reserved portions of the memory map will give unpredictable results.

The PCMCIA interface is divided into Socket 0 and Socket 1 space. These two sockets are each subdivided into I/O, memory and attribute space. Each socket is allocated 256 MB of memory space.

2-18 Intel® PXA255 Processor Developer’s Manual

Figure 2-2. Memory Map (Part One) — From 0x8000_0000 to 0xFFFF FFFF

System Architecture

0xFFFF_FFFF

0xFC00_0000

0xF800_0000

0xF400_0000

0xF000_0000

0xEC00_0000

0xE800_0000

0xE400_0000

0xE000_0000

0xDC00_0000

0xD800_0000

0xD400_0000

0xD000_0000

0xCC00_0000

0xC800_0000

0xC400_0000

0xC000_0000

0xBC00_0000

0xB800_0000

0xB400_0000

0xB000_0000

0xAC00_0000

0xA800_0000

0xA400_0000

0xA000_0000

0x9C00_0000

0x9800_0000

0x9400_0000

0x9000_0000

0x8C00_0000

0x8800_0000

0x8400_0000

0x8000_0000

Reserved (64 MB)

SDRAM Bank 3 (64 MB)

SDRAM Bank 2 (64 MB)

SDRAM Bank 1 (64 MB)

SDRAM Bank 0 (64 MB)

Reserved (64 MB)

Intel® PXA255 Processor Developer’s Manual 2-19

System Architecture

Figure 2-3. Memory Map (Part Two) — From 0x0000_0000 to 0x7FFF FFFF

0x7FFF FFFF

0x7C00_0000

0x7800_0000

0x7400_0000

0x7000_0000

0x6C00_0000

0x6800_0000

0x6400_0000

0x6000_0000

0x5C00_0000

0x5800_0000

0x5400_0000

0x5000_0000

0x4C00_0000

0x4800_0000

0x4400_0000

0x4000_0000

0x3C00_0000

0x3800_0000

0x3400_0000

0x3000_0000

0x2C00_0000

0x2800_0000

0x2400_0000

Memory Mapped registers (Memory Ctl)

Memory Mapped registers (Peripherals)

Reserved (64 MB)

Memory Mapped registers (LCD)

PCMCIA/CF- Slot 1 (256 MB)

PCMCIA/CF - Slot 0 (256MB)

0x2000_0000

0x1C00_0000

0x1800_0000

0x1400_0000

0x1000_0000

0x0C00_0000

0x0800_0000

0x0400_0000

0x0000_0000

Reserved (64 MB)

Static Chip Select 5 (64 MB)

Static Chip Select 4 (64 MB)

Static Chip Select 3 (64 MB)

Static Chip Select 2 (64 MB)

Static Chip Select 1 (64 MB)

Static Chip Select 0 (64 MB)

2-20 Intel® PXA255 Processor Developer’s Manual

2.13 System Architecture Register Summary

Table 2-8. System Architecture Register Address Summary (Sheet 1 of 12)

Unit Address Register Symbol Register Description

DMA Controller

0x4000_0000

0x4000_0000 DCSR0 DMA Control / Status Register for Channel 0

0x4000_0004 DCSR1 DMA Control / Status Register for Channel 1

0x4000_0008 DCSR2 DMA Control / Status Register for Channel 2

0x4000_000C DCSR3 DMA Control / Status Register for Channel 3

0x4000_0010 DCSR4 DMA Control / Status Register for Channel 4

0x4000_0014 DCSR5 DMA Control / Status Register for Channel 5

0x4000_0018 DCSR6 DMA Control / Status Register for Channel 6

0x4000_001C DCSR7 DMA Control / Status Register for Channel 7

0x4000_0020 DCSR8 DMA Control / Status Register for Channel 8

0x4000_0024 DCSR9 DMA Control / Status Register for Channel 9

0x4000_0028 DCSR10 DMA Control / Status Register for Channel 10

0x4000_002C DCSR11 DMA Control / Status Register for Channel 11

0x4000_0030 DCSR12 DMA Control / Status Register for Channel 12

0x4000_0034 DCSR13 DMA Control / Status Register for Channel 13

0x4000_0038 DCSR14 DMA Control / Status Register for Channel 14

0x4000_003C DCSR15 DMA Control / Status Register for Channel 15

0x4000_00f0 DINT DMA Interrupt Register

0x4000_0100 DRCMR0 Request to Channel Map Register for DREQ 0

0x4000_0104 DRCMR1 Request to Channel Map Register for DREQ 1

0x4000_0108 DRCMR2 Request to Channel Map Register for I2S receive Request

0x4000_010C DRCMR3 Request to Channel Map Register for I2S transmit Request

0x4000_0110 DRCMR4 Request to Channel Map Register for BTUART receive Request

0x4000_0114 DRCMR5 Request to Channel Map Register for BTUART transmit Request.

0x4000_0118 DRCMR6 Request to Channel Map Register for FFUART receive Request

0x4000_011C DRCMR7 Request to Channel Map Register for FFUART transmit Request

0x4000_0120 DRCMR8 Request to Channel Map Register for AC97 microphone Request

0x4000_0124 DRCMR9 Request to Channel Map Register for AC97 modem receive Request

0x4000_0128 DRCMR10 Request to Channel Map Register for AC97 modem transmit Request

0x4000_012C DRCMR11 Request to Channel Map Register for AC97 audio receive Request

0x4000_0130 DRCMR12 Request to Channel Map Register for AC97 audio transmit Request

0x4000_0134 DRCMR13 Request to Channel Map Register for SSP receive Request

0x4000_0138 DRCMR14 Request to Channel Map Register for SSP transmit Request

0x4000_013C DRCMR15 Request to Channel Map Register for NSSP receive Request

0x4000_0140 DRCMR16 Request to Channel Map Register for NSSP transmit Request

0x4000_0144 DRCMR17 Request to Channel Map Register for ICP receive Request

0x4000_0148 DRCMR18 Request to Channel Map Register for ICP transmit Request

System Architecture

Intel® PXA255 Processor Developer’s Manual 2-21

System Architecture

Table 2-8. System Architecture Register Address Summary (Sheet 2 of 12)

Unit Address Register Symbol Register Description

0x4000_014C DRCMR19 Request to Channel Map Register for STUART receive Request

0x4000_0150 DRCMR20 Request to Channel Map Register for STUART transmit Request

0x4000_0154 DRCMR21 Request to Channel Map Register for MMC receive Request

0x4000_0158 DRCMR22 Request to Channel Map Register for MMC transmit Request

0x4000_015C DRCMR23 Reserved

0x4000_0160 DRCMR24 Reserved

0x4000_0164 DRCMR25 Request to Channel Map Register for USB endpoint 1 Request

0x4000_0168 DRCMR26 Request to Channel Map Register for USB endpoint 2 Request

0x4000_016C DRCMR27 Request to Channel Map Register for USB endpoint 3 Request

0x4000_0170 DRCMR28 Request to Channel Map Register for USB endpoint 4 Request

0x4000_0174 DRCMR29 Request to Channel Map Register for HWUART receive Request

0x4000_0178 DRCMR30 Request to Channel Map Register for USB endpoint 6 Request

0x4000_017C DRCMR31 Request to Channel Map Register for USB endpoint 7 Request

0x4000_0180 DRCMR32 Request to Channel Map Register for USB endpoint 8 Request

0x4000_0184 DRCMR33 Request to Channel Map Register for USB endpoint 9 Request

0x4000_0188 DRCMR34 Request to Channel Map Register for HWUART transmit Request

0x4000_018C DRCMR35 Request to Channel Map Register for USB endpoint 11 Request

0x4000_0190 DRCMR36 Request to Channel Map Register for USB endpoint 12 Request

0x4000_0194 DRCMR37 Request to Channel Map Register for USB endpoint 13 Request

0x4000_0198 DRCMR38 Request to Channel Map Register for USB endpoint 14 Request

0x4000_019C DRCMR39 Reserved

0x4000_0200 DDADR0 DMA Descriptor Address Register Channel 0

0x4000_0204 DSADR0 DMA Source Address Register Channel 0

0x4000_0208 DTADR0 DMA Target Address Register Channel 0

0x4000_020C DCMD0 DMA Command Address Register Channel 0

0x4000_0210 DDADR1 DMA Descriptor Address Register Channel 1

0x4000_0214 DSADR1 DMA Source Address Register Channel 1

0x4000_0218 DTADR1 DMA Target Address Register Channel 1

0x4000_021C DCMD1 DMA Command Address Register Channel 1

0x4000_0220 DDADR2 DMA Descriptor Address Register Channel 2

0x4000_0224 DSADR2 DMA Source Address Register Channel 2

0x4000_0228 DTADR2 DMA Target Address Register Channel 2

0x4000_022C DCMD2 DMA Command Address Register Channel 2

0x4000_0230 DDADR3 DMA Descriptor Address Register Channel 3

0x4000_0234 DSADR3 DMA Source Address Register Channel 3

0x4000_0238 DTADR3 DMA Target Address Register Channel 3

0x4000_023C DCMD3 DMA Command Address Register Channel 3

0x4000_0240 DDADR4 DMA Descriptor Address Register Channel 4

0x4000_0244 DSADR4 DMA Source Address Register Channel 4

0x4000_0248 DTADR4 DMA Target Address Register Channel 4

2-22 Intel® PXA255 Processor Developer’s Manual

Table 2-8. System Architecture Register Address Summary (Sheet 3 of 12)

Unit Address Register Symbol Register Description

0x4000_024C DCMD4 DMA Command Address Register Channel 4

0x4000_0250 DDADR5 DMA Descriptor Address Register Channel 5

0x4000_0254 DSADR5 DMA Source Address Register Channel 5

0x4000_0258 DTADR5 DMA Target Address Register Channel 5

0x4000_025C DCMD5 DMA Command Address Register Channel 5

0x4000_0260 DDADR6 DMA Descriptor Address Register Channel 6

0x4000_0264 DSADR6 DMA Source Address Register Channel 6

0x4000_0268 DTADR6 DMA Target Address Register Channel 6

0x4000_026C DCMD6 DMA Command Address Register Channel 6

0x4000_0270 DDADR7 DMA Descriptor Address Register Channel 7

0x4000_0274 DSADR7 DMA Source Address Register Channel 7

0x4000_0278 DTADR7 DMA Target Address Register Channel 7

0x4000_027C DCMD7 DMA Command Address Register Channel 7

0x4000_0280 DDADR8 DMA Descriptor Address Register Channel 8

0x4000_0284 DSADR8 DMA Source Address Register Channel 8

0x4000_0288 DTADR8 DMA Target Address Register Channel 8

0x4000_028C DCMD8 DMA Command Address Register Channel 8

0x4000_0290 DDADR9 DMA Descriptor Address Register Channel 9

0x4000_0294 DSADR9 DMA Source Address Register Channel 9

0x4000_0298 DTADR9 DMA Target Address Register Channel 9

0x4000_029C DCMD9 DMA Command Address Register Channel 9

0x4000_02A0 DDADR10 DMA Descriptor Address Register Channel 10

0x4000_02A4 DSADR10 DMA Source Address Register Channel 10

0x4000_02A8 DTADR10 DMA Target Address Register Channel 10

0x4000_02AC DCMD10 DMA Command Address Register Channel 10

0x4000_02B0 DDADR11 DMA Descriptor Address Register Channel 11

0x4000_02B4 DSADR11 DMA Source Address Register Channel 11

0x4000_02B8 DTADR11 DMA Target Address Register Channel 11

0x4000_02BC DCMD11 DMA Command Address Register Channel 11

0x4000_02C0 DDADR12 DMA Descriptor Address Register Channel 12

0x4000_02C4 DSADR12 DMA Source Address Register Channel 12

0x4000_02C8 DTADR12 DMA Target Address Register Channel 12

0x4000_02CC DCMD12 DMA Command Address Register Channel 12

0x4000_02D0 DDADR13 DMA Descriptor Address Register Channel 13

0x4000_02D4 DSADR13 DMA Source Address Register Channel 13

0x4000_02D8 DTADR13 DMA Target Address Register Channel 13

0x4000_02DC DCMD13 DMA Command Address Register Channel 13

0x4000_02E0 DDADR14 DMA Descriptor Address Register Channel 14

0x4000_02E4 DSADR14 DMA Source Address Register Channel 14

0x4000_02E8 DTADR14 DMA Target Address Register Channel 14

System Architecture

Intel® PXA255 Processor Developer’s Manual 2-23

System Architecture

Table 2-8. System Architecture Register Address Summary (Sheet 4 of 12)

Unit Address Register Symbol Register Description

0x4000_02EC DCMD14 DMA Command Address Register Channel 14

0x4000_02F0 DDADR15 DMA Descriptor Address Register Channel 15

0x4000_02F4 DSADR15 DMA Source Address Register Channel 15

0x4000_02F8 DTADR15 DMA Target Address Register Channel 15

0x4000_02FC DCMD15 DMA Command Address Register Channel 15

Full Function UART

Bluetooth UART

I2C 0x4030_0000

0x4010_0000

0x4010_0000 FFRBR Receive Buffer Register (read only)

0x4010_0000 FFTHR Transmit Holding Register (write only)

0x4010_0004 FFIER Interrupt Enable Register (read/write)

0x4010_0008 FFIIR Interrupt ID Register (read only)

0x4010_0008 FFFCR FIFO Control Register (write only)

0x4010_000C FFLCR Line Control Register (read/write)

0x4010_0010 FFMCR Modem Control Register (read/write)

0x4010_0014 FFLSR Line Status Register (read only)

0x4010_0018 FFMSR Modem Status Register (read only)

0x4010_001C FFSPR Scratch Pad Register (read/write)

0x4010_0020 FFISR Infrared Selection Register (read/write)

0x4010_0000 FFDLL Divisor Latch Low Register (DLAB = 1) (read/write)

0x4010_0004 FFDLH Divisor Latch High Register (DLAB = 1) (read/write)

0x4020_0000

0x4020_0000 BTRBR Receive Buffer Register (read only)

0x4020_0000 BTTHR Transmit Holding Register (write only)

0x4020_0004 BTIER Interrupt Enable Register (read/write)

0x4020_0008 BTIIR Interrupt ID Register (read only)

0x4020_0008 BTFCR FIFO Control Register (write only)

0x4020_000C BTLCR Line Control Register (read/write)

0x4020_0010 BTMCR Modem Control Register (read/write)

0x4020_0014 BTLSR Line Status Register (read only)

0x4020_0018 BTMSR Modem Status Register (read only)

0x4020_001C BTSPR Scratch Pad Register (read/write)

0x4020_0020 BTISR Infrared Selection Register (read/write)

0x4020_0000 BTDLL Divisor Latch Low Register (DLAB = 1) (read/write)

0x4020_0004 BTDLH Divisor Latch High Register (DLAB = 1) (read/write)

0x4030 1680 IBMR I2C Bus Monitor Register - IBMR

0x4030 1688 IDBR I2C Data Buffer Register - IDBR

0x4030 1690 ICR I2C Control Register - ICR

0x4030 1698 ISR I2C Status Register - ISR

0x4030 16A0 ISAR I2C Slave Address Register - ISAR

2-24 Intel® PXA255 Processor Developer’s Manual

Table 2-8. System Architecture Register Address Summary (Sheet 5 of 12)

Unit Address Register Symbol Register Description

I2S 0x4040_0000

0x4040_0000 SACR0 Global Control Register

0x4040_0004 SACR1 Serial Audio I

0x4040_0008 — Reserved

0x4040_000C SASR0 Serial Audio I

0x4040_0010 — Reserved

0x4040_0014 SAIMR Serial Audio Interrupt Mask Register

0x4040_0018 SAICR Serial Audio Interrupt Clear Register

0x4040_001C

through

0x4040_005C

0x4040_0060 SADIV Audio Clock Divider Register.

0x4040_0064

through

0x4040_007C

0x4040_0080 SADR Serial Audio Data Register (TX and RX FIFO access Register).

AC97 0x4050_0000

0x4050_0000 POCR PCM Out Control Register

0x4050_0004 PICR PCM In Control Register

0x4050_0008 MCCR Mic In Control Register

0x4050_000C GCR Global Control Register

0x4050_0010 POSR PCM Out Status Register

0x4050_0014 PISR PCM In Status Register

0x4050_0018 MCSR Mic In Status Register

0x4050_001C GSR Global Status Register

0x4050_0020 CAR CODEC Access Register

0x4050_0024

through

0x4050_003C

0x4050_0040 PCDR PCM FIFO Data Register

0x4050_0044

through

0x4050_005C

0x4050_0060 MCDR Mic-in FIFO Data Register

0x4050_0064

through

0x4050_00FC

0x4050_0100 MOCR Modem Out Control Register

0x4050_0104 — Reserved

0x4050_0108 MICR Modem In Control Register

0x4050_010C — Reserved

0x4050_0110 MOSR Modem Out Status Register

— Reserved

S/MSB-Justified Control Register

S/MSB-Justified Interface and FIFO Status Register

System Architecture

Intel® PXA255 Processor Developer’s Manual 2-25

System Architecture

Table 2-8. System Architecture Register Address Summary (Sheet 6 of 12)

Unit Address Register Symbol Register Description

0x4050_0114 — Reserved

0x4050_0118 MISR Modem In Status Register

0x4050_011C

through

0x4050_013C

0x4050_0140 MODR Modem FIFO Data Register

0x4050_0144

through

0x4050_01FC

0x4050_0200

through

0x4050_02FC

0x4050_0300

through

0x4050_03FC

0x4050_0400

through

0x4050_04FC

0x4050_0500

through

0x4050_05FC

UDC 0x4060_0000

0x4060_0000 UDCCR UDC Control Register

0x4060_0008 UDCCFR UDC Control Function Register

0x4060_0010 UDCCS0 UDC Endpoint 0 Control/Status Register

0x4060_0014 UDCCS1 UDC Endpoint 1 (IN) Control/Status Register

0x4060_0018 UDCCS2 UDC Endpoint 2 (OUT) Control/Status Register

0x4060_001C UDCCS3 UDC Endpoint 3 (IN) Control/Status Register

0x4060_0020 UDCCS4 UDC Endpoint 4 (OUT) Control/Status Register

0x4060_0024 UDCCS5 UDC Endpoint 5 (Interrupt) Control/Status Register

0x4060_0028 UDCCS6 UDC Endpoint 6 (IN) Control/Status Register

0x4060_002C UDCCS7 UDC Endpoint 7 (OUT) Control/Status Register

0x4060_0030 UDCCS8 UDC Endpoint 8 (IN) Control/Status Register

0x4060_0034 UDCCS9 UDC Endpoint 9 (OUT) Control/Status Register

0x4060_0038 UDCCS10 UDC Endpoint 10 (Interrupt) Control/Status Register

0x4060_003C UDCCS11 UDC Endpoint 11 (IN) Control/Status Register

0x4060_0040 UDCCS12 UDC Endpoint 12 (OUT) Control/Status Register

0x4060_0044 UDCCS13 UDC Endpoint 13 (IN) Control/Status Register

0x4060_0048 UDCCS14 UDC Endpoint 14 (OUT) Control/Status Register

0x4060_004C UDCCS15 UDC Endpoint 15 (Interrupt) Control/Status Register

0x4060_0060 UFNRH UDC Frame Number Register High

0x4060_0064 UFNRL UDC Frame Number Register Low

— Reserved

— Primary Audio CODEC registers

— Secondary Audio CODEC registers

— Primary Modem CODEC registers

— Secondary Modem CODEC registers

2-26 Intel® PXA255 Processor Developer’s Manual

Table 2-8. System Architecture Register Address Summary (Sheet 7 of 12)

Unit Address Register Symbol Register Description

0x4060_0068 UBCR2 UDC Byte Count Register 2

0x4060_006C UBCR4 UDC Byte Count Register 4

0x4060_0070 UBCR7 UDC Byte Count Register 7

0x4060_0074 UBCR9 UDC Byte Count Register 9

0x4060_0078 UBCR12 UDC Byte Count Register 12

0x4060_007C UBCR14 UDC Byte Count Register 14

0x4060_0080 UDDR0 UDC Endpoint 0 Data Register

0x4060_0100 UDDR1 UDC Endpoint 1 Data Register

0x4060_0180 UDDR2 UDC Endpoint 2 Data Register

0x4060_0200 UDDR3 UDC Endpoint 3 Data Register

0x4060_0400 UDDR4 UDC Endpoint 4 Data Register

0x4060_00A0 UDDR5 UDC Endpoint 5 Data Register

0x4060_0600 UDDR6 UDC Endpoint 6 Data Register

0x4060_0680 UDDR7 UDC Endpoint 7 Data Register

0x4060_0700 UDDR8 UDC Endpoint 8 Data Register

0x4060_0900 UDDR9 UDC Endpoint 9 Data Register

0x4060_00C0 UDDR10 UDC Endpoint 10 Data Register

0x4060_0B00 UDDR11 UDC Endpoint 11 Data Register

0x4060_0B80 UDDR12 UDC Endpoint 12 Data Register

0x4060_0C00 UDDR13 UDC Endpoint 13 Data Register

0x4060_0E00 UDDR14 UDC Endpoint 14 Data Register

0x4060_00E0 UDDR15 UDC Endpoint 15 Data Register

0x4060_0050 UICR0 UDC Interrupt Control Register 0

0x4060_0054 UICR1 UDC Interrupt Control Register 1

0x4060_0058 USIR0 UDC Status Interrupt Register 0

0x4060_005C USIR1 UDC Status Interrupt Register 1

Standard UART

0x4070_0000

0x4070_0000 STRBR Receive Buffer Register (read only)

0x4070_0000 STTHR Transmit Holding Register (write only)

0x4070_0004 STIER Interrupt Enable Register (read/write)

0x4070_0008 STIIR Interrupt ID Register (read only)

0x4070_0008 STFCR FIFO Control Register (write only)

0x4070_000C STLCR Line Control Register (read/write)

0x4070_0010 STMCR Modem Control Register (read/write)

0x4070_0014 STLSR Line Status Register (read only)

0x4070_0018 STMSR Reserved

0x4070_001C STSPR Scratch Pad Register (read/write)

0x4070_0020 STISR Infrared Selection Register (read/write)

0x4070_0000 STDLL Divisor Latch Low Register (DLAB = 1) (read/write)

0x4070_0004 STDLH Divisor Latch High Register (DLAB = 1) (read/write)

System Architecture

Intel® PXA255 Processor Developer’s Manual 2-27

System Architecture

Table 2-8. System Architecture Register Address Summary (Sheet 8 of 12)

Unit Address Register Symbol Register Description

ICP 0x4080_0000

0x4080_0000 ICCR0 ICP Control Register 0

0x4080_0004 ICCR1 ICP Control Register 1

0x4080_0008 ICCR2 ICP Control Register 2

0x4080_000C ICDR ICP Data Register

0x4080_0010 — Reserved

0x4080_0014 ICSR0 ICP Status Register 0

0x4080_0018 ICSR1 ICP Status Register 1

RTC 0x4090_0000

0x4090_0000 RCNR RTC Count Register

0x4090_0004 RTAR RTC Alarm Register

0x4090_0008 RTSR RTC Status Register

0x4090_000C RTTR RTC Timer Trim Register

OS Timer 0x40A0_0000

0x40A0_0000 OSMR<0>

0x40A0_0004 OSMR<1>

0x40A0_0008 OSMR<2>

0x40A0_000C OSMR<3>

0x40A0_0010 OSCR OS Timer Counter Register

0x40A0_0014 OSSR OS Timer Status Register

0x40A0_0018 OWER OS Timer Watchdog Enable Register

0x40A0_001C OIER OS Timer Interrupt Enable Register

PWM 0 0x40B0_0000

0x40B0_0000 PWM_CTRL0 PWM 0 Control Register

0x40B0_0004 PWM_PWDUTY0 PWM 0 Duty Cycle Register

0x40B0_0008 PWM_PERVAL0 PWM 0 Period Control Register

PWM 1 0x40C0_0000

0x40C0_0000 PWM_CTRL1 PWM 1Control Register

0x40C0_0004 PWM_PWDUTY1 PWM 1 Duty Cycle Register

0x40C0_0008 PWM_PERVAL1 PWM 1 Period Control Register

Interrupt Control

GPIO 0x40E0_0000

0x40D0_0000

0x40D0_0000 ICIP Interrupt Controller IRQ Pending Register

0x40D0_0004 ICMR Interrupt Controller Mask Register

0x40D0_0008 ICLR Interrupt Controller Level Register

0x40D0_000C ICFP Interrupt Controller FIQ Pending Register

0x40D0_0010 ICPR Interrupt Controller Pending Register

0x40D0_0014 ICCR Interrupt Controller Control Register

0x40E0_0000 GPLR0 GPIO Pin-Level Register GPIO<31:0>

0x40E0_0004 GPLR1 GPIO Pin-Level Register GPIO<63:32>

OS Timer Match registers<3:0>

2-28 Intel® PXA255 Processor Developer’s Manual

Table 2-8. System Architecture Register Address Summary (Sheet 9 of 12)

Unit Address Register Symbol Register Description

0x40E0_0008 GPLR2 GPIO Pin-Level Register GPIO<80:64>

0x40E0_000C GPDR0 GPIO Pin Direction Register GPIO<31:0>

0x40E0_0010 GPDR1 GPIO Pin Direction Register GPIO<63:32>

0x40E0_0014 GPDR2 GPIO Pin Direction Register GPIO<80:64>

0x40E0_0018 GPSR0 GPIO Pin Direction Register GPIO<31:0>

0x40E0_001C GPSR1 GPIO Pin Output Set Register GPIO<63:32>

0x40E0_0020 GPSR2 GPIO Pin Output Set Register GPIO<80:64>

0x40E0_0024 GPCR0 GPIO Pin Output Clear Register GPIO<31:0>

0x40E0_0028 GPCR1 GPIO Pin Output Clear Register GPIO <63:32>

0x40E0_002C GPCR2 GPIO Pin Output Clear Register GPIO <80:64>

0x40E0_0030 GRER0 GPIO Rising-Edge Detect Register GPIO<31:0>

0x40E0_0034 GRER1 GPIO Rising-Edge Detect Register GPIO<63:32>

0x40E0_0038 GRER2 GPIO Rising-Edge Detect Register GPIO<80:64>

0x40E0_003C GFER0 GPIO Falling-Edge Detect Register GPIO<31:0>

0x40E0_0040 GFER1 GPIO Falling-Edge Detect Register GPIO<63:32>

0x40E0_0044 GFER2 GPIO Falling-Edge Detect Register GPIO<80:64>

0x40E0_0048 GEDR0 GPIO Edge Detect Status Register GPIO<31:0>

0x40E0_004C GEDR1 GPIO Edge Detect Status Register GPIO<63:32>

0x40E0_0050 GEDR2 GPIO Edge Detect Status Register GPIO<80:64>

0x40E0_0054 GAFR0_L GPIO Alternate Function Select Register GPIO<15:0>

0x40E0_0058 GAFR0_U GPIO Alternate Function Select Register GPIO<31:16>

0x40E0_005C GAFR1_L GPIO Alternate Function Select Register GPIO<47:32>

0x40E0_0060 GAFR1_U GPIO Alternate Function Select Register GPIO<63:48>

0x40E0_0064 GAFR2_L GPIO Alternate Function Select Register GPIO<79:64>

0x40E0_0068 GAFR2_U GPIO Alternate Function Select Register GPIO 80

Power Manager and Reset Control

0x40F0_0000

0x40F0_0000 PMCR Power Manager Control Register

0x40F0_0004 PSSR Power Manager Sleep Status Register

0x40F0_0008 PSPR Power Manager Scratch Pad Register

0x40F0_000C PWER Power Manager Wake-up Enable Register

0x40F0_0010 PRER Power Manager GPIO Rising-Edge Detect Enable Register

0x40F0_0014 PFER Power Manager GPIO Falling-Edge Detect Enable Register

0x40F0_0018 PEDR Power Manager GPIO Edge Detect Status Register

0x40F0_001C PCFR Power Manager General Configuration Register

0x40F0_0020 PGSR0 Power Manager GPIO Sleep State Register for GP[31-0]

0x40F0_0024 PGSR1 Power Manager GPIO Sleep State Register for GP[63-32]

0x40F0_0028 PGSR2 Power Manager GPIO Sleep State Register for GP[84-64]

0x40F0_002C — Reserved

System Architecture

Intel® PXA255 Processor Developer’s Manual 2-29

System Architecture

Table 2-8. System Architecture Register Address Summary (Sheet 10 of 12)

Unit Address Register Symbol Register Description

0x40F0_002C — Reserved

0x40F0_0030 RCSR Reset Controller Status Register

SSP 0x4100_0000

0x4100_0000 SSCR0 SSP Control Register 0

0x4100_0004 SSCR1 SSP Control Register 1

0x4100_0008 SSSR SSP Status Register

0x4100_000C SSITR SSP Interrupt Test Register

0x4100_0010 SSDR (Write / Read) SSP Data Write Register/SSP Data Read Register

MMC Controller

Clocks Manager

Network SSP 0x4140_0000

0x4110_0000

0x4110_0000 MMC_STRPCL Control to start and stop MMC clock

0x4110_0004 MMC_STAT MMC Status Register (read only)

0x4110_0008 MMC_CLKRT MMC clock rate

0x4110_000C MMC_SPI SPI mode control bits

0x4110_0010 MMC_CMDAT Command/response/data sequence control

0x4110_0014 MMC_RESTO Expected response time out

0x4110_0018 MMC_RDTO Expected data read time out

0x4110_001C MMC_BLKLEN Block length of data transaction

0x4110_0020 MMC_NOB Number of blocks, for block mode

0x4110_0024 MMC_PRTBUF Partial MMC TXFIFO FIFO written

0x4110_0028 MMC_I_MASK Interrupt Mask

0x4110_002C MMC_I_REG Interrupt Register (read only)

0x4110_0030 MMC_CMD Index of current command

0x4110_0034 MMC_ARGH MSW part of the current command argument

0x4110_0038 MMC_ARGL LSW part of the current command argument

0x4110_003C MMC_RES Response FIFO (read only)

0x4110_0040 MMC_RXFIFO Receive FIFO (read only)

0x4110_0044 MMC_TXFIFO Transmit FIFO (write only)

0x4130_0000

0x4130_0000 CCCR Core Clock Configuration Register

0x4130_0004 CKEN Clock Enable Register

0x4130_0008 OSCC Oscillator Configuration Register

0x4140_0000 NSSCR0 NSSP Control Register 0

0x4140_0004 NSSCR1 NSSP Control Register 1

0x4140_0008 NSSSR NSSP Status Register

0x4140_000C NSSITR NSSP Interrupt Test Register

0x4140_0010 NSSDR NSSP Data Read/Write Register

0x4140_0028 NSSTO NSSP Time Out Register

2-30 Intel® PXA255 Processor Developer’s Manual

Table 2-8. System Architecture Register Address Summary (Sheet 11 of 12)

Unit Address Register Symbol Register Description

0x4140_002C NSSPSP NSSP Programmable Serial Protocol

Hardware UART

LCD Controller

Memory Controller

0x4160_0000

0x4160_0000 HWRBR Receive Buffer Register (read only)

0x4160_0000 HWTHR Transmit Holding Register (write only)

0x4160_0004 HWIER Interrupt Enable Register (read/write)

0x4160_0008 HWIIR Interrupt ID Register (read only)

0x4160_0008 HWFCR FIFO Control Register (write only)

0x4160_000C HWLCR Line Control Register (read/write)

0x4160_0010 HWMCR Modem Control Register (read/write)

0x4160_0014 HWLSR Line Status Register (read only)

0x4160_0018 HWMSR Modem Status Register (read only)

0x4160_001C HWSPR Scratch Pad Register (read/write)

0x4160_0020 HWISR Infrared Selection Register (read/write)

0x4160_0024 HWFOR FIFO Occupancy Register (read only)

0x4160_0028 HWABR Auto-Baud Control Register (read/write)

0x4160_002C HWACR Auto-Baud Count Register

0x4160_0000 HWDLL Divisor Latch Low Register (DLAB = 1) (read/write)

0x4160_0000 HWDLH Divisor Latch High Register (DLAB = 1) (read/write)

0x4400_0000

0x4400_0000 LCCR0 LCD Controller Control Register 0

0x4400_0004 LCCR1 LCD Controller Control Register 1

0x4400_0008 LCCR2 LCD Controller Control Register 2

0x4400_000C LCCR3 LCD Controller Control Register 3

0x4400_0200 FDADR0 DMA Channel 0 Frame Descriptor Address Register

0x4400_0204 FSADR0 DMA Channel 0 Frame Source Address Register

0x4400_0208 FIDR0 DMA Channel 0 Frame ID Register

0x4400_020C LDCMD0 DMA Channel 0 Command Register

0x4400_0210 FDADR1 DMA Channel 1 Frame Descriptor Address Register

0x4400_0214 FSADR1 DMA Channel 1 Frame Source Address Register

0x4400_0218 FIDR1 DMA Channel 1 Frame ID Register

0x4400_021C LDCMD1 DMA Channel 1 Command Register

0x4400_0020 FBR0 DMA Channel 0 Frame Branch Register

0x4400_0024 FBR1 DMA Channel 1 Frame Branch Register

0x4400_0038 LCSR LCD Controller Status Register

0x4400_003C LIIDR LCD Controller Interrupt ID Register

0x4400_0040 TRGBR TMED RGB Seed Register

0x4400_0044 TCR TMED Control Register

0x4800_0000

System Architecture

Intel® PXA255 Processor Developer’s Manual 2-31

System Architecture

Table 2-8. System Architecture Register Address Summary (Sheet 12 of 12)

Unit Address Register Symbol Register Description

0x4800_0000 MDCNFG SDRAM Configuration Register 0

0x4800_0004 MDREFR SDRAM Refresh Control Register

0x4800_0008 MSC0 Static Memory Control Register 0

0x4800_000C MSC1 Static Memory Control Register 1

0x4800_0010 MSC2 Static Memory Control Register 2

0x4800_0014 MECR

0x4800_001C SXCNFG Synchronous Static Memory Control Register

0x4800_0024 SXMRS MRS value to be written to SMROM

0x4800_0028 MCMEM0 Card interface Common Memory Space Socket 0 Timing Configuration

0x4800_002C MCMEM1 Card interface Common Memory Space Socket 1 Timing Configuration

0x4800_0030 MCATT0 Card interface Attribute Space Socket 0 Timing Configuration

0x4800_0034 MCATT1 Card interface Attribute Space Socket 1 Timing Configuration

0x4800_0038 MCIO0 Card interface I/O Space Socket 0 Timing Configuration

0x4800_003C MCIO1 Card interface I/O Space Socket 1 Timing Configuration

0x4800_0040 MDMRS MRS value to be written to SDRAM

0x4800_0044 BOOT_DEF

0x4800_0058 MDMRSLP Low Power SDRAM Mode Register Set Configuration Register

0x 4 800 _00 64 S A 1111CR S A1111 C omp ati bility Register

Expansion Memory (PCMCIA/Compact Flash) Bus Configuration Register

Read-only Boot-Time Register. Contains BOOT_SEL and PKG SEL values.

2-32 Intel® PXA255 Processor Developer’s Manual

Clocks and Power Manager 3

The Clocks and Power Manager for the PXA255 processor controls the clock frequency to each module and manages transitions between the different power manager (PM) operating modes to optimize both computing performance and power consumption.

3.1 Clock Manager Introduction

The Clocks and Power Manager provides fixed clocks for each peripheral unit. Many of the devices’ peripheral clocks can be disabled using the Clock Enable Register (CKEN), or through bits in the peripheral’s control registers. To minimize power consumption, turn off the clock to any unit that is not being used. The Clocks and Power Manager also provides the programmablefrequency clocks for the LCD Controller, Memory Controller, and CPU. These clocks are related to each other because they come from the same internal Phase Locked Loop (PLL) clock source. To program the PLL’s frequency, follow these steps (for information on the factors L, M, and N, see

Section 3.6.1, “Core Clock Configuration Register (CCCR)” on page 3-34):

1. Determine the fastest synchronous memory requirement (SDRAM frequency).

2. If the SDRAM frequency is less than 99.5 MHz, the Memory Frequency must be twice the SDRAM Frequency and the SDRAM clock ratio in the Memory Controller must be set to two. If the SDRAM frequency is 99.5 MHz, the Memory Frequency is equal to the SDRAM frequency.

3. Round the Memory Frequency down to the nearest value of 99.5 MHz (L = 0x1B), 118.0 MHz (L = 0x20), 132.7 MHz (L = 0x24), 147.5 MHz (L = 0x28), or 165.9 MHz (L = 0x2D), and program the value of L in the Core Clock Configuration register. This frequency (or half, if the SDRAM clock ratio is 2) is the External Synchronous Memory Frequency.

4. Determine the required Core Frequency for normal (Run Mode) operation. This mode is used during normal processing, when the application must make occasional fetches to external memory. The possible values are one, two, or four times the Memory Frequency. Program this value (M) in the Core Clock Configuration register.

5. Determine the required Core Frequency for Turbo Mode operation. This mode is generally used when the application runs entirely from the caches, because any fetches to external memory slow the Core’s performance. This value is a multiple (1.0, 1.5, 2.0, or 3.0) of the Run Mode Frequency. Program the value (N) in the Core Clock Configuration register.

6. Configure the LCD Controller and Memory Controller for the new Memory Frequency and enter the Frequency Change Sequence (described in Section 3.4.7, “Frequency Change

Sequence” on page 3-11).

Note: Not all frequency combinations are valid. See Section 3.3.3, “Core Phase Locked Loop” for valid

combinations.

Intel® PXA255 Processor Developer’s Manual 3-1

Clocks and Power Manager

3.2 Power Manager Introduction

The Clocks and Power Manager can place the processor in one of three resets.

• Hardware Reset (nRESET asserted) is a nonmaskable total reset. It is used at power up or

when no system information requires preservation.

• Watchdog Reset is asserted through the Watchdog Timer and resets the system except the

Clocks and Power Manager. This reset is used as a code monitor. If code fails to complete a specified sequence, the processor assumes a fatal system error has occurred and causes a Watchdog Reset.

• GPIO Reset is enabled through the GPIO alternate function registers. It is used as an

alternative to Hardware Reset that preserves the Memory Controller registers and a few critical states in the Clocks and Power Manager and the Real Time Clock (RTC).

The Clocks and Power Manager also controls the entry into and exit from any of the low power or special clocking modes on processor. These modes are:

• Turbo Mode: the Core runs at its peak frequency. In this mode, make very few external

memory accesses because the Core must wait on the external memory.

• Run Mode: the Core runs at its normal frequency. In this mode, the Core is assumed to be

doing frequent external memory accesses, so running slower is optimum for the best power/ performance trade-off.

• Idle Mode: the Core is not being clocked, but the rest of the system is fully operational. This

mode is used during brief lulls in activity, when the external system must continue operation but the Core is idle.

• Sleep Mode: places the processor in its lowest power state but maintains I/O state, RTC, and

the Clocks and Power Manager. Wake-up from Sleep Mode requires re-booting the system, since most internal state was lost. The core power must be grounded in sleep to prevent current leakage.

The Clocks and Power Manager also controls the processor’s actions during the Frequency Change Sequence. The Frequency Change Sequence is a sequence that changes the Core Frequency (Run and Turbo) and Memory Frequency from the previously stored values to the new values in the Core Clock Configuration register. This sequence takes time to complete due to PLL relock time, but it allows dynamic frequency changes without compromising external memory integrity. Any peripherals that rely on the Core or Memory Controller must be configured to withstand a data flow interruption.

3.3 Clock Manager

The processor’s clocking system incorporates five major clock sources:

• 32.768 kHz Oscillator

• 3.6864 MHz Oscillator

• Programmable Frequency Core PLL

• 95.85 MHz Fixed Frequency Peripheral PLL

• 147.46 MHz Fixed Frequency PLL

3-2 Intel® PXA255 Processor Developer’s Manual

The clocks manager also contains clock gating for power reduction.

Figure 3-1 shows a functional representation of the clocking network. “L” is in the core PLL.

The PXbus is the internal bus between the Core, the DMA/Bridge, the LCD Controller, and the Memory Controller as shown in Figure 3-1. This bus is clocked at 1/2 the run mode frequency. For optimal performance, the PXbus should be clocked as fast as possible. For example, if a target core frequency of 200 MHz is desired use 200 MHz run mode instead of 200 MHz turbo mode with run at 100 MHz. Increasing the PXbus frequency may help reduce the latency involved in accessing non-cacheable memory.

Figure 3-1. Clocks Manager Block Diagram

Clocks and Power Manager

32.768 k

RTC

32.768

32.768 k

PWR_MGR

/1 /112

kHz

OSC

3.6864 MHz OSC

RETAINS POWER IN SLEEP

USB

FICP

I2C

3.6864

PWM

100-400

MHz PLL*

147.46 MHz

PLL

95.846 MHz

PLL

MMC

3.6864

SSP

3.6864

GPIO

UARTs

DMA

Bridge

3.6864

OST

AC97

CPU

CORE

MEM

Controller

LCD

Controller

PXbus

I2S

47.923

Intel® PXA255 Processor Developer’s Manual 3-3

47.923

31.949

19.169

14.746

12.288

5.672

Clocks and Power Manager

3.3.1 32.768 kHz Oscillator

The 32.768 kHz oscillator is a low power, low frequency oscillator that clocks the RTC and Power Manager. This oscillator is disabled out of Hardware Reset and the RTC and Power Manager blocks use the 3.6864 MHz oscillator instead. Software writes the Oscillator On bit in the Oscillator Configuration Register to enable the 32.768 kHz.This configures the RTC and Power Manager to use the 32.768 kHz oscillator after it stabilizes.

32.768 kHz oscillator use is optional and provides the lowest power consumption during Sleep Mode. In less power-sensitive applications, disable the 32.768 kHz oscillator in the Oscillator Configuration Register (OSCC) and leave the external pins floating (no external crystal required) for cost savings. If the 32.768 kHz oscillator is not in the system, the frequency of the RTC and Power Manager will be 3.6864 MHz divided by 112 (32.914 kHz). In Sleep, the 3.6864 MHz oscillator consumes hundreds of microamps of extra power when it stays enabled. See

Section 3.5.2, “Power Manager General Configuration Register (PCFR)” on page 3-24 for

information on The Oscillator Power Down Enable (OPDE) bit, which determines if the

3.6864 MHz oscillator is enabled in Sleep Mode. No external capacitors are required.

3.3.2 3.6864 MHz Oscillator

The 3.6864 MHz oscillator provides the primary clock source for the processor. The on-chip PLL frequency multipliers, Synchronous Serial Port (SSP), Pulse Width Modulator (PWM), and the Operating System Timer (OST) use the 3.6864 MHz oscillator as a reference. Out of Hardware Reset, the 3.6864 MHz oscillator also drives the RTC and Power Manager (PM). The user may then enable the 32.768 kHz oscillator, which will drive the RTC and PM after it is stabilized. The

3.6864 MHz oscillator can be disabled during Sleep Mode by setting the OPDE (see Section 3.5.2) bit but only if the 32.768 kHz oscillator is enabled and stabilized (both the OON and OOK bits in the OSCC set). See Section 3.6.3 for more information. No external capacitors are required.

3.3.3 Core Phase Locked Loop

The Core PLL is the clock source of the CPU Core, the Memory Controller, the LCD Controller, and DMA Controller. The Core PLL uses the 3.6864 MHz oscillator as a reference and multiplies its frequency by the following variables:

• L: Crystal Frequency to Memory Frequency Multiplier, set to 27, 36 or 45.

• M: Memory Frequency to Run Mode Frequency Multiplier, set to 1, 2 or 4.

• N: Run Mode Frequency to Turbo Mode Frequency Multiplier, set to 1.0, 1.5, 2.0, or 3.0.

The output frequency selections are shown in Table 3-1, “Core PLL Output Frequencies for

3.6864 MHz Crystal”. See Section 3.6.1 for programming information on the L, M, and N factors.

See Section 3.6.1, “Core Clock Configuration Register (CCCR)” for the hexadecimal settings.

Do not choose a combination that generates a frequency that is not supported in the voltage range and package in which the processor is operating.

SDCLK must not be greater than 100 MHz. If MEMCLK is greater than 100 MHz, the SDCLK to MEMCLK ratio must be set to 1:2 in the Memory Controller.

3-4 Intel® PXA255 Processor Developer’s Manual

Table 3-1. Core PLL Output Frequencies for 3.6864 MHz Crystal

Clocks and Power Manager

27 1

36 1

27 2

36 2

45 2

27 4

Turbo Mode Frequency (MHz) for Values

Configuration Register (CCCR[15:0])

1.00

(Run)

99.5

@1.0 V

132.7

@1.0 V

199.1

@1.0 V

265.4

@1.1 V

331.8

@1.3 V

398.1

@1.3 V

“N” and Core Clock

programming for Values of “N”

1.50 2.00 3.00

—

— — — 66 132.7 66

298.6

@1.1 V

— — — 132.7 132.7 66

— — — 165.9 165.9 83

— — — 196 99.5 99.5

199.1

@1.0 V

398.1

@1.3 V

298.6

@1.1 V

PXbus

Frequency

(MHz)

50 99.5 99.5

— 99.5 99.5 99.5

Note: These are the only supported frequency settings.

3.3.4 95.85 MHz Peripheral Phase Locked Loop

The 95.85 MHz PLL is the clock source for many of the peripheral blocks’ external interfaces. These interfaces require ~48 MHz (UDC/USB, FICP), ~33 MHz (I generated frequency is not exactly the required frequency due to the chosen crystal and the lack of a perfect Least Common Multiple between the units. The chosen frequencies keep each unit’s clock frequency within the unit’s clock tolerance. If a crystal other than 3.6864 MHz is used, the clock frequencies to the peripheral blocks’ interfaces may not yield the desired baud rates (or protocol’s rate).

MEM, LCD Frequency

(MHz)

SDRAM

max

Frequency

(MHz)

C), and ~20 MHz (MMC). The

Table 3-2. 95.85 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal

Unit Name Nominal Frequency Actual Frequency

USB (UDC) 48 MHz 47.923 MHz

FICP 48 MHz 47.923 MHz

C 33 MHz 31.949 MHz

MMC 20 MHz 19.169 MHz

3.3.5 147.46 MHz Peripheral Phase Locked Loop

The 147.46 MHz PLL is the clock source for many of the peripheral blocks’ external interfaces. These interfaces require ~14.75 MHz (UARTs), 12.288 MHz (AC97), and variable frequencies

S). The generated frequency may not exactly match the required frequency due to the choice of

crystal and the lack of a perfect Least Common Multiple between the units. The chosen frequencies

Intel® PXA255 Processor Developer’s Manual 3-5

Clocks and Power Manager

keep each unit’s clock frequency within the unit’s clock tolerance. If a crystal other than

3.6864 MHz is used, the clock frequencies to the peripheral blocks’ interfaces may not yield the desired baud rates (or other protocol’s rate)

Table 3-3. 147.46 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal

Unit Name Nominal Frequency Actual Frequency

UARTs 14.746 MHz 14.746 MHz

AC97 12.288 MHz 12.288 MHz

S 146.76 MHz 147.46 MHz

3.3.6 Clock Gating

The Clocks Manager contains the CKEN register. This register contains configuration bits that can disable the clocks to individual units. The configuration bits are used when a module is not being used. After Hardware Reset, any module that is not being used must have its clock disabled. If a module is temporarily quiescent but does not have clock gating functionality, the CKEN register can be used to disable the unit’s clock.

When a module’s clock is disabled, the registers in that module are still readable and writable. The AC97 is an exception and is completely inaccessible if the clock is disabled.

3.4 Resets and Power Modes

The Clocks and Power Manager Unit determines the processor’s Resets, Power Sequences and Power Modes. Each behaves differently during operation and has specific entry and exit sequences. The resets and power modes are:

• Hardware Reset

• Watchdog Reset

• GPIO Reset

• Run Mode

• Turbo Mode

• Idle Mode

• Frequency Change Sequence

• Sleep Mode

3.4.1 Hardware Reset

To invoke the Hardware Reset and reset all units in the processor to a known state, assert the nRESET pin. Hardware Reset is only intended to be used for power up and complete resets.

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3.4.1.1 Invoking Hardware Reset

Hardware Reset is invoked when the nRESET pin is pulled low by an external source. The processor does not provide a method of masking or disabling the propagation of the external pin value. When the nRESET pin is asserted, Hardware Reset is invoked, regardless of the mode of operation. The nRESET_OUT pin is asserted when the nRESET pin is asserted. To enter Hardware Reset, nRESET must be held low for t state to propagate. Refer to the Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification for details.

DHW_NRESET

3.4.1.2 Behavior During Hardware Reset

During Hardware Reset, all internal registers and units are held at their defined reset conditions. While the nRESET pin is asserted, nothing inside the processor is active except the 3.6864 MHz oscillator. The internal clocks are stopped and the chip is static. All pins return to their reset conditions and the nBATT_FAULT and nVDD_FAULT pins are ignored. Because the memory controller receives a full reset, all dynamic RAM contents are lost during Hardware Reset.

3.4.1.3 Completing Hardware Reset

To complete Hardware Reset, deassert the nRESET pin. All power supplies must be stable for t

D_NRESET

Mechanical, and Thermal Specification for details. After the nRESET pin is deasserted, the following sequence occurs:

before nRESET is deasserted. Refer to the Intel® PXA255 Processor Electrical,

Clocks and Power Manager

to allow the system to stabilize and the reset

1. The 3.6864 MHz oscillator and internal PLL clock generators wait for stabilization.

2. The nRESET_OUT pin is deasserted.

3. The normal boot-up sequence begins. All processor units return to their predefined reset conditions. Software must examine the Reset Controller Status register (RCSR) to determine the cause for the boot.

3.4.2 Watchdog Reset

Watchdog Reset is invoked when software fails to properly prevent the Watchdog Time-out Event from occurring. It is assumed that Watchdog Resets are only generated when software is not executing properly and has potentially destroyed data. In Watchdog Reset all units in the are reset except the Clocks and Power Manager.

3.4.2.1 Invoking Watchdog Reset

Watchdog Reset is invoked when the Watchdog Enable bit (WE) in the OWER is set and the OSMR[3] matches the OS timer counter. When these conditions are met, they invoke Watchdog Reset, regardless of the previous mode of operation. Watchdog Reset asserts nRESET_OUT.

3.4.2.2 Behavior During Watchdog Reset

During Watchdog Reset, all units except the Real Time Clock and parts of the Clocks and Power Manager maintain their defined reset conditions. All pins except the oscillator pins assume their reset conditions and the nBATT_FAULT and nVDD_FAULT pins are ignored. All dynamic RAM contents are lost during Watchdog Reset because the memory controller receives a full reset.

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Refer to Table 2-6, “Pin & Signal Descriptions for the PXA255 Processor” for the pin states during Watchdog and other Resets.

3.4.2.3 Completing a Watchdog Reset

Watchdog resets immediately revert to hardware resets when the nRESET pin is asserted. Otherwise, the completion sequence for watchdog reset is:

1. The 3.6864 MHz oscillator and internal PLL clock generators wait for stabilization. The

32.768 kHz oscillator’s configuration and status are not affected by watchdog reset.

2. The nRESET_OUT pin is deasserted after t Electrical, Mechanical, and Thermal Specification.

3. The normal boot-up sequence begins. All processor units except the RTTR in the RTC and parts of the Clocks and Power Manager return to their predefined reset conditions. Software must examine the RCSR to determine the cause for the reboot.

3.4.3 GPIO Reset

A GPIO Reset is invoked when GP[1] is properly configured as a reset source and is asserted low for greater than four 3.6864-MHz clock cycles. In GPIO Reset all processor units except the RTC, parts of the Clocks and Power Manager, and the Memory Controller return to their predefined, known states.

3.4.3.1 Invoking GPIO Reset

To use the GPIO Reset function, set it up through the GPIO Controller. The GP[1] pin must be configured as an input and set to its alternate GPIO Reset function in the GPIO Controller. The GPIO Reset alternate function is level-sensitive and not edge-triggered. To ensure no spurious resets are generated when the alternate GPIO Reset function is set, follow these steps:

1. GP[1] must be set up as an output with its data register set to a 1.

2. Externally drive the GP[1] pin to a high state.

3. Configure GP[1] as an input.

4. Configure GP[1] for its Alternate (Reset) Function.

DHW_OUT

. Refer to the Intel® PXA255 Processor

The previous mode of operation does not affect a GPIO Reset. When performing a GPIO Reset, nRESET_OUT is asserted. If GP[1] is asserted for less than four 3.6864-MHz clock cycles, the processor may remain in its previous mode or enter into a GPIO reset.

GPIO Reset does not function in Sleep Mode because all GPIO pins’ Alternate Function Inputs are disabled. External wake-up sources must be routed through one of the enabled GPIO wake-up sources (see Section 3.5.3 for details) during Sleep Mode. GP[1] may be enabled as a wake-up source.

3.4.3.2 Behavior During GPIO Reset

During GPIO Reset, most, but not all, internal registers and processes are held at their defined reset conditions. The exceptions are the RTC, the Clocks and Power Manager (unless otherwise noted), and the Memory Controller. During GPIO Reset, the clocks unit continues to operate with its

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previously programmed values, so the processor enters and exits GPIO Reset with the same clock configurations. All pins except the oscillator and Memory Controller pins return to their reset conditions and the nBATT_FAULT and nVDD_FAULT pins are ignored.

GPIO Reset does not reset the Memory Controller Configuration registers. This creates the possibility that the contents of external memories may be preserved if the external memories are properly configured before GPIO Reset is entered. To preserve SDRAM contents during a GPIO Reset, software must correctly configure the Memory Control and the time spent in GPIO Reset must be shorter than the SDRAM refresh interval. The amount of time spent in GPIO Reset depends on the CPU’s mode before GPIO Reset. See Section 6, “Memory Controller” for details.

Refer to Table 2-6, “Pin & Signal Descriptions for the PXA255 Processor” for the states of all the PXA255 processor pins during GPIO reset and other resets.

3.4.3.3 Completing GPIO Reset

GPIO Reset immediately reverts to Hardware Reset when the nRESET pin is asserted. Otherwise, the completion sequence for GPIO Reset is:

1. The GPIO Reset Source is deasserted because the internal reset has propagated to the GPIO Controller and its registers, which are set back to their reset states.

Clocks and Power Manager

2. The nRESET_OUT pin is deasserted.

3. The normal boot-up sequence begins. All processor units except the Real Time Clock, parts of the Clocks and Power Manager, and the Memory Controller return to their predefined reset conditions. Software must examine the RCSR to determine the cause for the reset.

3.4.4 Run Mode

Run Mode is the processor’s normal operating mode. All power supplies are enabled and all functionally enabled clocks are running. Run Mode is entered after any power mode, power sequence, or reset completes its sequence. Run Mode is exited when any other power mode, power sequence, or reset begins.

3.4.5 Turbo Mode

Turbo Mode allows the user to clock the processor core at a higher frequency during peak processing requirements. It allows a synchronous switch in frequencies without disrupting the Memory Controller, LCD Controller, or any peripheral.

3.4.5.1 Entering Turbo Mode

Turbo Mode is invoked when software sets the TURBO bit in the Clock Config (CCLKCFG) Register (See Section 3.7.1). After software sets the TURBO bit, the CPU waits for all instructions currently in the pipeline to complete. When the instructions are completed, the CPU resumes operation at the higher Turbo Mode Frequency.

Software can set or clear other bits in the CCLKCFG in the same write that sets the TURBO bit. The other bits in the register take precedence over Turbo Mode, so, if another bit is set, that mode’s sequence is followed before the CPU enters Turbo Mode. When the CPU exits the other mode, it enters either Run or Turbo Mode, based on the state of the CCLKCFG [TURBO] bit.

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Do not confuse the CCLKCFG Register, which is in Coprocessor 14, with the CCCR (See

Section 3.6.1), which is in the processor’s Clocks and Power Manager.

3.4.5.2 Behavior in Turbo Mode

The processor’s behavior in Turbo Mode is identical to its behavior in Run Mode, except that the processor’s clock frequency relative to the memory and peripherals is increased by N, the value in the CCCR (see Section 3.6.1). Turbo mode is intended for use during peak processing, when there are very few accesses to external memory. The higher Core to external memory clock ratio increases the relative delay for each external memory access. This increased delay lowers the processor’s power efficiency. For optimum performance, software must load applications in the caches in Run Mode and execute them in Turbo Mode.

3.4.5.3 Exiting Turbo Mode

To exit Turbo Mode, software clears the TURBO bit in the CCLKCFG Register. After software clears the TURBO bit, the CPU waits for all instructions in the pipeline to complete. When the instructions are completed, the CPU enters Run Mode.

Other bits in the CCLKCFG may be set or cleared in the write that clears CCLKCFG [TURBO]. All other bits in the register take precedence over Turbo Mode, so the new mode’s proper sequence is followed.

Idle, Sleep, Frequency Change Sequence, and Reset have precedence over Turbo Mode and cause the processor to exit Turbo Mode. When the CPU exits of one of these modes, it enters either Run or Turbo Mode, based on the state of CCLKCFG [TURBO].

3.4.6 Idle Mode

Idle Mode allows the user to stop the CPU core clock during periods of processor inactivity and continue to monitor on- and off-chip interrupt service requests. Idle mode does not change clock generation, so when an interrupt occurs the CPU is quickly reactivated in the state that preceded Idle Mode.

During Idle mode these resources are active:

• System unit modules (real-time clock, operating system timer, interrupt controller, general-

purpose I/O, and clocks and power manager)

• Peripheral unit modules (DMA controller, LCD controller, and all other peripheral units)

• Memory Controller resources

3.4.6.1 Entering Idle Mode

During Idle Mode, the clocks to the CPU core stop. All critical applications must be finished and peripherals must be set up to generate interrupts when they require CPU attention. To enter the Idle Mode, software selects Idle Mode in PWRMODE[M] (See Section 3.7.2). An interrupt immediately aborts Idle Mode and normal processing resumes. After software selects Idle Mode, the CPU waits until all instructions in the pipeline are completed. When the instructions are completed, the CPU clock stops and Idle Mode begins. In Idle Mode, interrupts are recognized as wake-up sources.

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3.4.6.2 Behavior in Idle Mode

In Idle Mode the CPU clocks are stopped, but the remainder of the processor operates normally. For example, the LCD controller can continue refreshing the screen with the same frame buffer data in memory.

When ICCR[DIM] is cleared, any enabled interrupt wakes up the processor. When ICCR[DIM] is set, only unmasked interrupts cause wake-up.

Enabled interrupts are interrupts that are allowed at the unit level. Masked interrupts are interrupts that are prevented from interrupting the core based on the Interrupt Controller Mask Register.

3.4.6.3 Exiting Idle Mode

Idle Mode exits when any Reset is asserted. Reset entry and exit sequences take precedence over Idle Mode. When the Reset exit sequence is completed, the CPU is not in Idle Mode. If the Watchdog Timer is enabled, software must set the Watchdog Match Registers before it sets Idle Mode to ensure that another interrupt will bring the processor out of Idle Mode before the Watchdog Reset is asserted. Use an RTC alarm or another OS timer channel for this purpose.

Any enabled interrupt causes Idle Mode to exit. When ICCR[DIM] is cleared, the Interrupt Controller Mask register (ICMR) is ignored during Idle Mode. This means that an interrupt does not have to be unmasked to cause Idle Mode to exit. Idle Mode exits in the following sequence:

Clocks and Power Manager

1. A valid, enabled Interrupt asserts.

2. The CPU clocks restart and the CPU resumes operation at the state indicated by CCLKCFG [TURBO].

Idle Mode also exits when the nBATT_FAULT or nVDD_FAULT pin is asserted. When either pin is asserted, Idle Mode exits in the following sequence:

1. The nBATT_FAULT or nVDD_FAULT pin is asserted.

2. If the Imprecise Data Abort Enable (IDAE) bit in the Power Manager Control Register (PMCR) is clear (not recommended), the processor enters Sleep Mode immediately.

3. If the IDAE bit is set, the nBATT_FAULT or nVDD_FAULT assertion is treated as a valid interrupt to the clocks module and Idle Mode exits using its normal, interrupt-driven sequence. Software must then shut down the system and enter Sleep Mode. See Section 3.4.9.3,

“Entering Sleep Mode” for more details.

3.4.7 Frequency Change Sequence

The Frequency Change Sequence is used to change the processor clock frequency. During the Frequency Change Sequence, the CPU, Memory Controller, LCD Controller, and DMA clocks stop. The other peripheral units continue to function during the Frequency Change Sequence. This mode is intended to be used to change the frequency from the default condition at initial boot-up. It may also be used as a power-saving feature used to allow the processor to run at the minimum required frequency when the software requires major changes in frequency.

3.4.7.1 Preparing for a Frequency Change Sequence

Software must complete the following steps before it initiates the Frequency Change Sequence:

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1. Configure the Memory Controller to ensure SDRAM contents are maintained during the Frequency Change Sequence. The Memory Controller’s refresh timer must be programmed to match the maximum refresh time associated with the slower of two frequencies (current and desired). The SDRAM divide by two must be set to a value that prevents the SDRAM frequency from exceeding the specified frequency. For example, to change from 100/100 to 133/66, the SDRAM bus must be set to divide by two before the frequency change. To change from 133/66 to 100/100, the SDRAM must be set to one-to-one after the frequency change sequence is completed. See Section 6, “Memory Controller” for more details.

2. Disable the LCD Controller or configure it to avoid the effects of an interruption in the LCD clocks and data from the processor.

3. Configure peripheral units to handle a lack of DMA service for up to 500 µs. If a peripheral unit can not function for 500 µs without DMA service, it must be disabled.

4. Disable peripheral units that can not accommodate a 500 µs interrupt latency. The interrupts generated during the Frequency Change Sequence are serviced when the sequence exits.

5. Program the CCCR (Section 3.6.1, “Core Clock Configuration Register (CCCR)”) to reflect the desired frequency.

3.4.7.2 Invoking the Frequency Change Sequence

To invoke the Frequency Change Sequence, software must set FCS in the CCLKCFG (See

Section 3.7.1). When software sets FCS, it may also set or clear other bits in CCLKCFG. If

software sets the TURBO bit in the same write, the CPU enters Turbo Mode when the Frequency Change Sequence exits.

After software sets the FCS:

1. The CPU clock stops and interrupts to the CPU are gated.

2. The Memory Controller completes all outstanding transactions in its buffers and from the CPU. New transactions from the LCD or DMA controllers are ignored.

3. The Memory Controller places the SDRAM in self-refresh mode.

Note: Program the Memory Controller to ensure the correct self-refresh time for SDRAM, given the

slower of the current and desired clock frequencies.

3.4.7.3 Behavior During the Frequency Change Sequence

In the frequency change sequence, the processor’s PLL clock generator is in the process of locking to the correct frequency and cannot be used. This means that interrupts cannot be processed. Interrupts that occur during the frequency change sequence are serviced after the processor’s PLL has locked. The 95.85 MHz and 147.46 MHz PLL clock generators are active and peripherals, except the memory, LCD, and DMA controllers, may continue to operate normally, provided they can accommodate the inability to process DMA or interrupt requests. DMA or interrupt requests are not recognized until the frequency change sequence is complete.

The Imprecise Data Abort is also not recognized and if nVDD_FAULT or nBATT_FAULT is asserted, the assertion is ignored until the Frequency Change Sequence exits. This means that the processor does not enter Sleep Mode until the Frequency Change Sequence is complete.

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3.4.7.4 Completing the Frequency Change Sequence

The Frequency Change Sequence exits when any Reset is asserted. In Hardware and Watchdog Resets, the Reset entry and exit sequences take precedence over the Frequency Change Sequence and the PLL resumes in its Reset condition. In GPIO Reset, the Reset exit sequence is delayed while the PLL relocks and the frequency is set to the desired frequency of the Frequency Change Sequence.

If the Watchdog Timer is enabled during the Frequency Change Sequence, set the Watchdog Match Register to ensure that the Frequency Change Sequence completes before the Watchdog Reset is asserted.

If Hardware or Watchdog Reset is asserted during the Frequency Change Sequence, the DRAM contents are lost because all states, including Memory Controller configuration and information about the previous Frequency Change Sequence, are reset. If GPIO Reset is asserted during the Frequency Change Sequence, the SDRAM contents will be lost during the GPIO Reset exit sequence if the SDRAM is not in self-refresh mode and the exit sequence exceeds the refresh interval.

Normally, the Frequency Change Sequence exits in the following sequence:

1. The processor’s PLL clock generator is reprogrammed with the desired values, which are in the CCCR, and begins to relock to those values.

Clocks and Power Manager

Note: This sequence occurs even if the before and after frequencies are the same.

2. The internal PLL clock generator for the processor clock waits for stabilization. Refer to the

Intel® PXA250 and PXA210 Application Processors Electrical, Mechanical, and Thermal Specification for details.

3. The CPU clocks restart and the CPU resumes operation at the state indicated by the TURBO bit (either Run or Turbo Mode). Interrupts to the CPU are no longer gated.

4. The FCS bit is not automatically cleared. To prevent an accidental return to the Frequency Change Sequence, software must not immediately clear the FCS bit. The bit must be cleared on the next required write to the register.

5. Values may be written to the CCCR, but they are ignored until the Frequency Change Sequence is re-entered.

6. The SDRAM must transition out of self-refresh mode and into its idle state. See Section 6,

“Memory Controller” for details on configuring the SDRAM interface.

3.4.8 33-MHz Idle Mode

33-MHz idle mode has the lowest power consumption of any idle mode. The run mode frequency selected in the Core Clock Configuration Register (CCCR) directly affects the processor idle mode power consumption. Faster run mode frequencies consume more power. 33-MHz idle mode places the processor a special low speed run mode before entering idle. This is similar to normal idle since the CPU core clock can be stopped during periods of processor inactivity and continue to monitor on- and off-chip interrupt service requests. 33-MHz idle limitations are:

• Peripherals will not function correctly and should be disabled before entering this mode.

• A Frequency Change Sequence must be performed upon entry to and exit from 33-MHz idle

mode.

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• SDRAM is placed in self refresh before entering 33-MHz idle mode, because SDRAM cannot

be refreshed correctly in 33-MHz idle mode. Carefully consider the processor interrupt behavior when the SDRAM in self refresh. To allow the interrupts to occur while SDRAM is in self refresh, set the I and F bits in the CPSR. This allows interrupts to wake the processor from idle mode without jumping to the interrupt handler. When the system’s SDRAM is no longer in self refresh, the I and F bits can be cleared and the interrupt is handled.

• Because nBATT_FAULT and nVDD_FAULT can cause a data abort interrupt, the function of

these pins in 33-MHz idle mode also needs special consideration. Either the Imprecise Data Abort Enable (IDAE) bit in the Power Manager Control Register (PMCR) must be clear, (causing the processor to immediately enter sleep mode if either nBATT_FAULT or nVDD_FAULT are asserted) or take software precautions to avoid starting execution in or trying to use SDRAM while it is in self refresh.

During 33-Mhz idle mode these system unit modules are functional:

• Real-time clock

• Operating system timer

• Interrupt controller

• General purpose I/O

• Clocks and power manager

• Flash ROM/SRAM

Unlike normal idle mode, in 33-MHz idle mode all other peripheral units cannot be used, including SDRAM, LCD and DMA controllers.

3.4.8.1 Entering 33-MHz Idle Mode

During idle mode, the processor core clocks stop. Before the clocks stop, all critical applications must be finished and peripherals turned off. If software is executing from SDRAM, the last three of the following steps must be loaded into the cache before being performed.

1. Set the I and F bits in the CPSR register to mask all interrupts

2. Place the SDRAM into self refresh mode

3. Perform a frequency change sequence to 33MHz mode. The CCCR value for this mode is 0x13F

4. Enter idle mode by selecting the PWRMODE[M] bit (refer to Section 3.7.2)

3.4.8.2 Behavior in 33-MHz Idle Mode

In 33-MHz idle mode the CPU clocks are stopped. While in 33-MHz idle mode these features of the processor all operate normally: the RTC timer, the OS timers including the watchdog timer, and the GPIO interrupt capabilities.

When ICCR[DIM] is cleared, any enabled interrupt wakes up the processor. When ICCR[DIM] is set, only unmasked interrupts cause wake-up.

Enabled interrupts are interrupts that are allowed at the unit level. Masked interrupts are interrupts that are prevented from interrupting the core based on the Interrupt Controller Mask Register (ICMR).

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3.4.8.3 Exiting 33-MHz Idle Mode

The 33-MHz idle mode exit procedure is the same as the exit procedure for normal idle mode. However, because the I and F bits are set in the CPSR, the processor does not immediately jump to the interrupt vector. Instead processing continues with the instruction following the last executed instruction before 33-MHz idle mode was entered. If execution occurs from SDRAM, steps 1 and 2 must have been previously loaded into the instruction cache. The steps below are then taken:

1. Perform a frequency change to a supported run mode frequency, greater or equal to 100 MHz.

2. Take the SDRAM out of self refresh.

3. Clear the I and F bits in the CPSR. Execution immediately jumps to the pending interrupt handler.

3.4.9 Sleep Mode

Sleep Mode offers lower power consumption at the expense of the loss of most of the internal processor state. In Sleep Mode, the processor goes through an orderly shut-down sequence and power is removed from the core. The Power Manager watches for a wake-up event and, after it receives one, re-establishes power and goes through a reset sequence. During Sleep Mode, the RTC and Power Manager continue to function. Pin states can be controlled throughout Sleep Mode and external SDRAM is preserved because it is in self-refresh mode.

Clocks and Power Manager

Because all activity on the processor except the RTC stops when Sleep Mode starts, peripherals must be disabled to allow an orderly shutdown. When Sleep Mode exits, the processor’s state resets and processing resumes in a boot-up mode.

3.4.9.1 Sleep Mode External Voltage Regulator Requirements

To implement Sleep Mode in the simplest manner, the External Voltage Regulator, which supplies power to the processor’s internal elements, must have the following characteristics:

• A power enable input pin that enables the primary supply output connected to VCC and

PLL_VCC. This pin must be connected to the processor’s PWR_EN pin. To support fast sleep walk-up by maintaining power during sleep, the regulator should be software configurable to ignore PWR_EN. When PWR_EN is not used, VCC and PLL_VCC may be powered on before or simultaneously with VCCN and VCCQ. In this configuration, when PWR_EN is deasserted, the core regulator must be able to maintain regulation when the load power is as little as 0.5 mW. Core supply current during sleep will vary with voltage and temperature.

• When core power is enabled during sleep, the power management IC or logic that generates

nVDD_FAULT must assert this signal when any supply including VCC and PLL_VCC falls below the lower regulation limit during sleep. nVDD_FAULT must not be deasserted until all supplies are in regulation again since there is no power supply stabilization delay during the fast sleep walk-up sequence. If nVDD_FAULT is asserted during fast sleep walk-up, then the processor returns to Sleep Mode.

• When configured to disable the core supply to save power during sleep, the core regulator’s

output must be driven to ground when PWR_EN goes low.

• Higher-voltage outputs connected to VCCQ and VCCN are continuously driven and do not

change when the PWR_EN pin is asserted.

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3.4.9.2 Preparing for Sleep Mode

Before Sleep Mode starts, software must take the following steps:

1. The Memory Controller must be configured to ensure SDRAM contents are maintained during Sleep Mode. See Section 6, “Memory Controller” for details.

2. If a graceful shutdown is required for a peripheral, the peripheral must be disabled before Sleep Mode asserts. This includes monitoring DMA transfers to and from peripherals or memories to ensure they are completed. All other peripherals need not be disabled, since they are held in their reset states internally during Sleep Mode.

3. The following Power Manager registers must be set up for proper sleep entry and exit:

— PM GPIO Sleep State registers (PGSR0, PGSR1, PGSR2). To avoid contention on the bus

when the processor attempts to wake up, ensure that the chip selects are not set to 0 during sleep mode. If a GPIO is used as an input, it must not be allowed to float during sleep mode. The GPIO can be pulled up or down externally or changed to an output and driven with the unasserted value.

— PM General Configuration Register Float bits [FS/FP] must be configured appropriately

for the system. The General Configuration Register Float bits must be cleared on wake up. To avoid contention on the bus when the processor attempts to wake up, ensure that the chip selects are not set to 0 during sleep mode. The PCFR[OPDE] bit must be cleared to leave the 3.6864 MHz enabled during sleep if the fast walk-up sleep configuration is selected by setting the PMFW[FWAKE] bit.

— PMFW configuration register must be set to select between the standard and fast sleep

wakeup configurations. Set PMFW[FWAKE] to 1 to disable the 10 ms power supply stabilization delay during sleep wakeup if power is maintained during sleep. This configuration reduces the sleep wakeup time to approximately 650 µs.

4. Before the IDAE bit is set, software must configure an imprecise data abort exception handler to put the processor into sleep mode when a data abort occurs in response to nVDD_FAULT or nBATT_FAULT assertion. This abort exception event indicates that the processor is in peril of losing its main power supply.

5. The following Power Manager registers must be set up to detect wake-up sources and oscillator activity:

— PM GPIO Sleep State registers (PGSR0, PGSR,1 and PGSR2).

— PM Wake-up Enable register (PWER)

— PM GPIO Falling-edge Detect Enable and PM GPIO Rising-edge Detect Enable registers

(PFER and PRER)

— OPDE bit in the Power Manager Configuration Register (PCFR)

— IDAE bit in PMCR

Note: The PCFR[OPDE] bit must be cleared to enable the 3.6864 MHz oscillator during sleep when fast

sleep wakeup is selected by setting the PMFW[FWAKE] bit.

3.4.9.3 Entering Sleep Mode

Software uses the PWRMODE register to enter sleep mode (See Section 3.7.2).

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If the external voltage regulator is failing or the main battery is low or missing, some systems must enter sleep mode quickly. When nBATT_FAULT or nVDD_FAULT is asserted, the system is required to shut down immediately.

To allow the assertion of nVDD_FAULT or nBATT_FAULT to cause an imprecise data abort, set the Imprecise Data Abort Enable (IDAE) bit in the PMCR. Setting the IDAE bit in the PMCR will result in software executing the data abort handler routine as part of entering sleep mode. If the IDAE bit is clear, the processor enters sleep mode immediately without executing the abort handler routine.

Note: Using an exception handler to invoke sleep in response to a power fault event is advantageous

because software can clear the PMFW[FWAKE] bit and configure the power management IC to use PWR_EN to disable the core power supply during sleep to minimize power consumption from a critically low battery.

PSSR[VFS] and PSSR[BFS] can not be used prior to entering Sleep Mode to determine which type of fault occurred, VDD fault or battery fault, respectively. If either nVDD_FAULT or nBATT_FAULT signals are asserted or if both are asserted at the same time (and the IDAE bit of the PMCR is set), the software data abort handler will be called. Since there is only one common data abort handler, software must first determine if one of the two nVDD_FAULT or nBATT_FAULT assertion events resulted in an imprecise data abort by reading Coprocessor 7, Register 4, Bit 5 (PSFS). If the PSFS bit is cleared, neither a nVDD_FAULT or nBATT_FAULT assertion occurred and the data abort handler was called for some other reason. If the PSFS bit is set, this indicates either a nVDD_FAULT or nBATT_FAULT assertion occurred, but it is not possible to determine which of the two faults was asserted. For either case, nVDD_FAULT or nBATT_FAULT assertion, software should shut the system down as quickly as possible by performing the steps outlined below to enter Sleep Mode.

Note: All addresses (data and instruction) used in the abort handler routines should be resident and

accessible in the memory page tables, i.e. system software developers should ensure no further aborts occur while executing an abort handler. The processor does not support recursive (nested) aborts. The system must not assert nBATT_FAULT or nVDD_FAULT signals more than once before nRESET_OUT is asserted. System software can not return to normal execution following a nBATT_FAULT or nVDD_FAULT. If a battery or VDD fault occurs while executing in the abort mode, the abort handler is reentered. This condition of a recursive abort occurrence can be detected in software by reading the Saved Program Status Register (SPSR) to see if the previous context was executing in abort mode.

To enter Sleep Mode, software must complete the following sequence:

1. Software uses external memory and the Power Manager Scratch Pad Register (PSPR) to preserve critical states.

2. Software sets Sleep Mode in PWRMODE[M]. An interrupt immediately aborts Sleep Mode and normal processing resumes.

3. The CPU waits until all instructions in the pipeline are complete.

4. The Memory Controller completes outstanding transactions in its buffers and from the CPU. New transactions from the LCD or DMA controllers are ignored.

5. The Memory Controller places the SDRAM in self-refresh mode.

6. The Power Manager switches the GPIO output pins to their sleep state. This sleep state is programmed in advance by loading the Power Manager GPIO Sleep State registers (PGSR0, PGSR1, and PGSR2). To avoid contention on the bus when the processor attempts to wake up, ensure that the chip selects are not set to 0 during sleep mode.

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Clocks and Power Manager

7. The CPU clock stops and power is removed from the Core.

8. PWR_EN is deasserted.

When the Power Manger get the indication from the Memory Controller that it has finished its outstanding transactions and has put the SDRAM into self-refresh, there are eight core clock cycles before the GPIOs latch the PGSR values and four core clock cycles after that, nRESET_OUT asserts low.

In some systems the Imprecise Data Abort latency lasts longer than the residual charge in the failed power supply can sustain operation. This normally only occurs when the processor is in a Power Mode or Sequence that requires that the processor exit before Sleep Mode starts. Frequency Change Sequence is an example of such a Power Sequence. In these Power Modes and Sequences, the IDAE bit must not be set. This allows the processor to enters Sleep Mode immediately but any critical states in the processor are lost.

If the IDAE bit is not set and the nVDD_FAULT or nBATT_FAULT pin is asserted, the Sleep Sequence begins at Step 4.

3.4.9.4 Behavior in Sleep Mode

In Sleep Mode, all processor and peripheral clocks are disabled, except the RTC. The processor does not recognize interrupts or external pin transitions except valid wake-up signals, Reset signals, and the nBATT_FAULT signal.

If the nBATT_FAULT signal is asserted while in Sleep Mode, GPIO[1:0] are set as the only valid wake-up signals.

The Power Manager watches for wake up events programmed by the CPU before Sleep Mode starts or set by the Power Manager it detects a fault condition. In order to detect a rising-edge or falling-edge on a GPIO pin, the rising- or falling-edge must be held for more than one full

32.768 kHz clock cycle. The Power Manager takes three 32.768 kHz clock cycles to acknowledge the GPIO edge and begin the wake up sequence.

Refer to Table 2-6, “Pin & Signal Descriptions for the PXA255 Processor” on page 2-9 for the PXA255 processor pin states during sleep mode reset and other resets.

3.4.9.5 Exiting Sleep Mode

Sleep Mode exits when Hardware Reset is asserted. Hardware Reset’s entry and exit sequences take precedence over Sleep Mode.

Note: If Hardware Reset is asserted during Sleep Mode, the DRAM contents are lost because all states,

including Memory Controller configuration and information about the previous Sleep Mode, are reset.

Normally, Sleep Mode exits in the following sequence. Any time the nBATT_FAULT pin is asserted, the processor returns to Sleep Mode. The nVDD_FAULT pin is ignored until the external power supply stabilization timer expires.

1. A pre-programmed wake up event from an enabled GPIO or RTC source occurs. If the nBATT_FAULT pin is asserted, the wake up source is ignored.

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2. The PWR_EN signal is asserted and the Power Manager waits for the external power supply to stabilize. If nVDD_FAULT is asserted after the external power supply timer expires, the processor returns to Sleep Mode.

3. If PCFR[OPDE] and OSCC[OON] were set when Sleep Mode started, the 3.6864 MHz oscillator is enabled and stabilizes. Otherwise, the 3.6864 MHz oscillator is already stable and this step is bypassed.

4. The processor’s PLL clock generator is reprogrammed with the values in the CCCR and stabilizes.

5. The Sleep Mode configuration in PWRMODE[M] is cleared.

6. The processor’s internal reset is deasserted and the CPU begins a normal boot sequence. When the normal boot sequence begins, all of the processor’s units, except the RTC and portions of the Clocks and Power Manager and the Memory Controller, return to their predefined reset settings.

7. The nRESET_OUT pin is deasserted. This indicates that the processor is about to perform a fetch from the Reset vector.

8. Clear PSSR[PH] before accessing GPIOs, including chip selects that are muxed with GPIOs.

9. Clear PCFR[FS] and PCFR[FP] if either was set before Sleep Mode was triggered.

10. The SDRAM must transition out of self-refresh mode and into its idle state. See Section 6,

“Memory Controller” for details on configuring the SDRAM interface.

11. Software must examine the RCSR, to determine what caused the reboot, and the Power Manager Sleep Status register (PSSR), to determine what triggered Sleep Mode.

12. If the PSPR was used to preserve any critical states during Sleep Mode, software can now recover the information.

If the nVDD_FAULT or nBATT_FAULT pin is asserted during the Sleep Mode exit sequence, the system re-enters Sleep Mode in the following sequence:

1. Regardless of the state of the IDAE bit:

— All GPIO edge detects and the RTC alarm interrupt are cleared.

— The Power Manager wake-up source registers (PWER, PRER, and PFER) are loaded with

0x0000 0003, their wake-up fault state. This limits the potential wake-up sources to a rising or falling edge on GPIO[0] or GPIO[1]. The wake-up fault state prevents spurious events from causing an unwanted wake-up while the battery is low or the power supply is at risk. The fault state is also the default state after a Hardware Reset.

2. The PLL clock generators are disabled.

3. If the OPDE bit in the PCFR is set and the OON bit in the OSCC is set, the 3.6864 MHz oscillator is disabled. If the oscillator is disabled, Sleep Mode consumes less power. If it is enabled, Sleep Mode exits more quickly.

4. An internal reset is generated to the core and most peripheral modules. This reset asserts the nRESET_OUT pin.

5. The PWR_EN pin is deasserted. If PMFW[FWAKE] is cleared, the system must respond by grounding the VCC and PLL_VCC power supplies to minimize power consumption.

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3.4.10 Power Mode Summary

Tab le 3 -4 shows the actions that occur when a Power Mode is entered. Table 3-5 shows the actions

that occur when a Power Mode is exited. In the tables, an empty cell means that the power mode skips that step. Tabl e 3-6 shows the expected behavior for power supplies in each power mode.

Table 3-4. Power Mode Entry Sequence Table

Step

1 Software writes a bit in CP14 x x x x x

2 The CPU waits until all instructions to be completed x x x x x

3 Wake up sources are cleared and limited to GP[1:0] x

4 The PM places GPIOs in their sleep states x x

5 The Memory Controller finishes all outstanding transactions x x x

6 The Memory Controller places SDRAMs in self-refresh x x x

7 The PLL is disabled x x x

8 If OPDE and OOK bits are set, disable 3.6864 MHz oscillator x x

9 Internal Reset to most modules. nRESET_OUT asserted x x

10 PWR_EN is deasserted. Power is cut off x x

11 Power to most I/O pins is cut off

1: Fault Sleep Mode starts if IDAE is clear and nBATT_FAULT or nVDD_FAULT is asserted.

Description of Action

Table 3-5. Power Mode Exit Sequence Table (Sheet 1 of 2)

Step

1 Wake up source or Interrupt is received x x x

2 Power to I/O pins restored

3 PWR_EN is asserted x x

4 External power ramp x x

5 Enable 3.6864 MHz oscillator if OPDE and OOK are set x x

Wait for 3.6864 MHz oscillator to stabilize if OPDE and OOK

are set

7 Enable PLL with new frequency x x x

8 Wait for PLL stabilization x x x

9 Wait for internal stabilization x x

10 Clear CP14 bit x x

Description of Action

Sleep

Tur bo

Turbo

Idle

Freq Change

Run (from Turbo)

Idle

Freq Change

Run (from Turbo)

Sleep

Fault

Sleep

Fault

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Table 3-5. Power Mode Exit Sequence Table (Sheet 2 of 2)

Clocks and Power Manager

Step

11 Deassert nRESET_OUT x x

12Restart CPU clocks, enable interrupts xxxxxx

1: Fault Sleep Mode starts if IDAE is clear and nBATT_FAULT or nVDD_FAULT is asserted.

Description of Action

Tur bo

Idle

Run (from Turbo)

Sleep

Freq Change

Sleep

Fault

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Table 3-6. Power and Clock Supply Sources and States During Power Modes

Power Mode

Module

Supply Source

Turbo Run Idle

Pw Ck Pw Ck Pw Ck Pw Ck Pw Ck Pw Ck

Freq

Change

Sleep

CPU, Caches, Buffers

Memory Controller

LCD Controller

DMA Controller

General Periphs.

OS timer

Interrupts

Real Time Clock

Power Manager

GP[3:0], PM pads, Osc pads

General IO H

KEY:

T: Tu r b o c l ock R: Run clock V: Module powered off VCC. I: Module powered off internal regulator H: Module powered off VCCQ or VCCN D: Module is dynamic or actively clocked S: Module is static or clocks are gated.

VCC

VCC/

Reg

(V/R)

HV/

Batt

(H/B)

Run/

Turbo

(R/T)

Mem

PLL

3.686

MHz Osc

32.768

kHz Osc

Dynamic/

Static (D/S)

On On On

VOnVOnVOnVOn I On

HDHDHDHDHS

Off

changing

Off Off

3.5 Power Manager Registers

This section describes the 32-bit registers that control the Power Manager.

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3.5.1 Power Manager Control Register (PMCR)

The PMCR is used to select the manner in which Sleep Mode is entered when the nVDD_FAULT or the nBATT_FAULT pin is asserted low. When the IDAE bit is set, an Imprecise Data Abort indication is sent to the CPU. The CPU then performs an abort routine. Software must ensure that the abort routine sets the Sleep Mode configuration in the PWRMODE register (see Section 3.7.2,

“Power Mode Register (PWRMODE)”). The IDAE bit is cleared in any Reset and when Sleep

Mode exits. Software may also clear the IDAE bit when necessary. The PMCR must be protected through Memory Management Unit (MMU) permissions.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-7. PMCR Bit Definitions

0x40F0_0000 PMCR Clocks and Power Manager

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Clocks and Power Manager

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits Name Description

[31:1] —

0IDAE

Reserved.

Read undefined and must always be written with zeroes.

Imprecise Data Abort Enable.

0 – Allow immediate entry to sleep mode when nVDD_FAULT or nBATT_FAULT is

asserted.

1 – Force imprecise data abort signal to CPU to allow software to enter sleep mode

when nVDD_FAULT or nBATT_FAULT is asserted. Recommended mode.

Cleared on hardware, watchdog, and GPIO reset, or when sleep mode exits.

IDAE

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3.5.2 Power Manager General Configuration Register (PCFR)

The PCFR contains bits used to configure functions in the processor. When the OPDE bit is set, it allows the 3.6864 MHz oscillator to be disabled during Sleep Mode. The OPDE bit is cleared in Hardware, Watchdog, and GPIO Resets. The Float PCMCIA (FP) and Float Static Memory (FS) bits control the state of the PCMCIA control pins and the static memory control pins during Sleep Mode.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-8. PCFR Bit Definitions

0x40F0_001C PCFR Clocks and Power Manager

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits Name Description

OPDE

[31:3] —

2FS

1FP

0OPDE

Reserved.

Read undefined and must always be written with zeroes.

Float Static Chip Selects during Sleep Mode.

0 = Static Chip Select pins are not floated in Sleep Mode. nCS[5:1] are driven to the

state of the appropriate PGSR register bits. nCS[1], nWE, and nOE are driven high.

1 = Static Chip Select pins are floated in Sleep Mode. The pins nCS[5:0], nWE, and

nOE are affected.

Cleared on Hardware, Watchdog, and GPIO Resets.

Float PCMCIA controls during Sleep Mode.

0 = PCMCIA pins are not floated in Sleep Mode. They are driven to the state of the

appropriate PGSR register bits.

1 = The PCMCIA signals: nPOE, nPWE, nPIOW, nPIOR, and nPCE[2:1] are floated in

Sleep Mode. nPSKTSEL and nPREG are derived from address signals and assume the state of the address bus during Sleep Mode.

Cleared on Hardware, Watchdog, and GPIO Resets.

3.6864 MHz oscillator power-down enable.

If the 32.7686 kHz crystal is disabled because the OON bit in the Oscillator Configuration Register is 0, OPDE is ignored and the 3.6864 MHz oscillator is not disabled.

0 = Do not stop the oscillator during Sleep Mode. 1 = Stop the 3.6864 MHz oscillator during Sleep Mode.

Cleared on Hardware, Watchdog, and GPIO Resets.

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3.5.3 Power Manager Wake-Up Enable Register (PWER)

Table 3-9 shows the location of all wake up source enable bits in the Power Manager Wake-Up

Enable Register (PWER). If a GPIO is to be used as a wake up source from Sleep, it must be programmed as an input in the GPDR and either one or both of the corresponding bits in the PRER and PFER must be set. When the IDAE bit is zero and a fault condition is detected on the nVDD_FAULT or nBATT_FAULT pin, PWER is set to 0x0000 0003 and only allows GP[1:0] as wake-up sources. When the IDAE bit is set, fault conditions on the nVDD_FAULT or nBATT_FAULT pins do not affect wake-up sources. PWER is also set to 0x0000 0003 in Hardware, Watchdog, or GPIO Resets.

Software should enable wakeups only for those GPIO pins that are configured as inputs during sleep. Any GPIO pins that are configured as outputs during sleep, should have their associated wake enable bits set to logic zero in all three PMU wake enable registers (PWER, PRER, and PFER).

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-9. PWER Bit Definitions

0x40F0_000C PWER Clocks and Power Manager

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

WE9

WE8

WE7

WE6

WE5

WE4

WE3

WE2

WE13

WE12

WE11

WE10

WE15

WERTC

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Bits Name Description

31 WERTC

[30:16] —

[15:0] WEx

Reserved

RTC Sleep Mode Wake-up Enable.

0 – Wake-up due to RTC alarm disabled. 1 – Wake-up due to RTC alarm enabled.

Cleared on hardware, watchdog, and GPIO resets.

Reserved.

Read undefined and must always be written with zeroes.

Sleep Mode Wake-up Enable

0 – Wake-up due to GPx edge detect disabled. 1 – Wake-up due to GPx edge detect enabled.

Set to 0x 0003 on hardware, watchdog, and GPIO resets.

WE14

WE1

WE0

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3.5.4 Power Manager Rising-Edge Detect Enable Register (PRER)

The PRER, shown in Table 3-10, determines whether the GPIO pin enabled with the PWER register causes a wake up from sleep mode on that GPIO pin’s rising edge. When PWER[IDAE] is zero and a fault condition is detected on the nVDD_FAULT or nBATT_FAULT pin, PRER is set to 0x0000_0003. This enables rising edges on GP[1:0] to act as wake up sources. When PWER[IDAE] is set, fault conditions on the nVDD_FAULT or nBATT_FAULT pins do not affect wake-up sources. PRER is also set to 0x0000_0003 in hardware, watchdog, and GPIO resets.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-10. PRER Bit Definitions

0x40F0_0010 PRER Clocks and Power Manager

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

RE9

RE8

RE7

RE6

RE5

RE4

RE3

RE2

RE15

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Bits Name Description

[31:16] —

[15:0] REx

Reserved.

Read undefined and must always be written with zeroes.

Sleep mode Rising-edge Wake up Enable

0 – Wake up due to GPx rising-edge detect disabled. 1 – Wake up due to GPx rising-edge detect enabled.

Set to 0x 0003 on hardware, watchdog, and GPIO resets.

RE14

RE11

RE13

RE12

RE10

RE1

RE0

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3.5.5 Power Manager Falling-Edge Detect Enable Register (PFER)

The PFER, Table 3- 11, determines if the GPIO pin enabled with the PWER causes a wake up from sleep mode on that GPIO pin’s falling edge. When PWER[IDAE] is zero and a fault condition is detected on the nVDD_FAULT or nBATT_FAULT pin, PFER is set to 0x0000_0003. This enables falling edges on GP[1:0] to act as wake up sources. When PWER[IDAE] is set, fault conditions on the nVDD_FAULT or nBATT_FAULT pins do not affect wake-up sources. PFER is also set to 0x0000_0003 during hardware, watchdog, and GPIO resets.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-11. PFER Bit Definitions

0x40F0_0014 PFER Clocks and Power Manager

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FE9

FE8

FE7

FE6

FE5

FE4

FE3

FE2

FE13

FE12

FE11

FE10

FE15

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Bits Name Description

[31:16] —

[15:0] FEx

Reserved.

Read undefined and must always be written with zeroes.

Sleep mode Falling-edge Wake-up Enable

0 – Wake up due to GPx falling-edge detect disabled. 1 – Wake up due to GPx falling-edge detect enabled.

Set to 0x0003 on hardware, watchdog, and GPIO resets.

FE14

FE1

FE0

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3.5.6 Power Manager GPIO Edge Detect Status Register (PEDR)

The PEDR, Table 3-12, indicates which of the GPIO pins enabled through the PWER, PRER, and PFER registers caused a wake up from sleep mode. The bits in PEDR can only be set on a rising or falling edge on a given GPIO pin. If PRER is set, the bits in PEDR can only be set on a rising edge. If PFER is set, the bits in PEDR can only be set on a falling edge. To reset a bit in PEDR to zero, write a 1 to it. The PEDR bits are reset to zero in hardware, watchdog, and GPIO resets.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-12. PEDR Bit Definitions

0x40F0_0018 PEDR Clocks and Power Manager

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

ED9

ED8

ED7

ED6

ED5

ED4

ED3

ED2

ED15

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits Name Description

ED14

ED11

ED13

ED12

ED10

ED1

ED0

[31:16] —

[15:0] EDx

Reserved.

Read undefined and must always be written with zeroes.

Sleep mode Edge Detect Status

0 – Wake up on GPx not detected. 1 – Wake up due to edge on GPx detected.

Cleared by hardware, watchdog, and GPIO resets. Cleared by writing a 1.

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3.5.7 Power Manager Sleep Status Register (PSSR)

The PSSR, shown in Table 3-13, contains the following status flags:

• Software Sleep Status (SSS) flag is set when the sleep mode configuration in the PWRMODE

• Battery Fault Status (BFS) bit is set after wake up any time the nBATT_FAULT pin is asserted

(even when the processor is already in sleep mode).

• VDD Fault Status (VFS) bit is set after wake up when the nVDD_FAULT pin is asserted and

causes the processor to enter sleep mode. The VFS bit is not set if software starts the sleep mode and then the nVDD_FAULT pin is asserted.

• Peripheral Control Hold (PH) bit is set when sleep mode starts and indicates that the GPIO

pins are retaining their sleep mode state values.

• Read Disable Hold (RDH) bit is set in hardware, GPIO, and watchdog resets and sleep mode.

The RDH bit indicates that all the processor’s GPIO input paths are disabled. To allow a GPIO input pin to be enabled, software must reset the RDH bit by writing a one to it. Clearing RDH also disables the 10 K to 60 K GPIO pull-up resistors that are present during and after hardware, GPIO and watchdog reset. Sleep mode disables the GPIO input path, but the pull-up resisters are not re-enabled in this case.

To clear a status flag write a 1 to it. Writing a 0 to a status bit has no effect. Hardware, watchdog, and GPIO resets clear or set the PSSR bits.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-13. PSSR Bit Definitions (Sheet 1 of 2)

0x40F0_0004 PSSR Clocks and Power Manager

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

Bits Name Description

[31:6] — reserved

Read Disable Hold.

0 – GPIO pins are configured according to their GPIO configuration 1 – Receivers of all GPIO pins that can act as inputs are disabled and following a

5RDH

4PH

3—reserved

hardware, GPIO, or watchdog reset, internal GPIO pull-ups are active. Must be cleared by the processor after the peripheral and GPIO interfaces are configured but before they are used.

Set by hardware, watchdog, and GPIO resets and sleep mode. Cleared by writing a 1.

Peripheral Control Hold.

0 – GPIO pins are configured according to their GPIO configuration 1 – GPIO pins are being held in their sleep mode state. Set when sleep mode starts.

Must be cleared by the processor after the peripheral interfaces have been configured but before they are actually used by the processor.

Cleared by hardware, watchdog, and GPIO resets. Cleared by writing a 1.

VFS

RDH

BFS

reserved

SSS

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Table 3-13. PSSR Bit Definitions (Sheet 2 of 2)

0x40F0_0004 PSSR Clocks and Power Manager

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

Bits Name Description

VDD Fault Status.

0 – nVDD_FAULT pin has not been asserted since it was last cleared by a reset or the

CPU.

2VFS

1BFS

0SSS

1 – nVDD_FAULT pin was asserted in Run or idle mode and caused the chip to enter

sleep mode; bit is set only after wake up.

This bit is not set when nVDD_FAULT is asserted while in sleep mode.

Cleared by hardware, watchdog, and GPIO resets.

Battery Fault Status.

0 – nBATT_FAULT pin has not been asserted since it was last cleared by a reset or the

CPU.

1 – nBATT_FAULT pin has been asserted; bit is set only after wake up.

This bit can be set when nBATT_FAULT is asserted while in sleep mode.

Cleared by hardware, watchdog, and GPIO resets.

Software Sleep Status.

0 – Software has not entered sleep mode through the sleep mode bit since the SSS

was last cleared by a reset or the CPU.

1 – Chip was placed in sleep mode by setting the sleep mode bit.

Cleared by hardware, watchdog, and GPIO resets.

RDH

VFS

reserved

3.5.8 Power Manager Scratch Pad Register (PSPR)

BFS

SSS

The PM contains a 32-bit register that can be used to save processor configuration information in any desired format. The PSPR, shown in Table 3-14, is a holding register that is powered during sleep mode and is reset by hardware, watchdog, and GPIO resets. During run and turbo modes, any value can be written to PSPR. The value can be read after sleep mode exits. The value in PSPR can be used to represent the processor’s configuration before sleep mode is invoked.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-14. PSPR Bit Definitions

0x40F0_0008 PSPR Clocks and Power Manager

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits Name Description

Scratch Pad

[31:0] SP

3-30 Intel® PXA255 Processor Developer’s Manual

32-bit word is preserved in sleep mode.

Cleared by hardware, watchdog, and GPIO resets.

Clocks and Power Manager

3.5.9 Power Manager Fast Sleep Walk-up Configuration Register (PMFW)

The PSPR, shown in Table 3-15, provides a single bit called FWAKE which is used to select between the standard and fast sleep walk-up sequences. The PMFW register is reset by a hardware reset, GPIO reset, watchdog reset, but is not cleared by the sleep walk-up sequence. Using an exception handler to invoke sleep in response to a power fault event is advantageous because software can clear the PMFW[FWAKE] bit and configure the power management IC to use PWR_EN to disable the core power supply during sleep to minimize power consumption from a critically low battery. Also, the PCFR[OPDE] bit must be cleared to enable the 3.6864 MHz oscillator during sleep when fast sleep walk-up is selected by setting the PMFW[FWAKE] bit.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-15. PMFW Register Bitmap and Bit Definitions

0x40F0 0034

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31:3] —

[1] FWAKE

[0] —

Power Manager Fast Sleep Wakeup

Configuration Register (PMFW)

Reserved

Read undefined and must always be written with zeroes.

FAST WAKEUP ENABLE

0 – Selects the standard sleep wakeup sequence with a 10 ms power supply

stabilization delay when power is disabled during sleep.

1 – Selects the fast sleep wakeup sequence without a power supply stabilization delay

when power is maintained during sleep.

Cleared by hardware reset.

Reserved

Read undefined and must always be written with zeroes.

Power Manager

3.5.10 Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2)

PGSR0, PGSR1, and PGSR2, shown in Table 3-16, Table 3-17, and Table 3-18 allow software to select the output state of each GPIO pin when the processor goes into sleep mode. When a transition to sleep mode is required (through software or the nBATT_FAULT or nVDD_FAULT pin), the contents of the PGSR registers are loaded into the GPIO output data registers that software normally controls through the GPSR and GPCR registers. Only pins that are already configured as outputs reflect the new state. All bits in the output registers are loaded. When the processor reenters the run mode, these GPIO pins retain the programmed sleep state until software resets PSSR[PH]. If a pin is reconfigured from an input to an output, the register’s last contents are driven onto the pin.

FWAKE

Reserved

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

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Table 3-16. PGSR0 Bit Definitions

0x40F0_0020 PGSR0 Clocks and Power Manager

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SS9

SS8

SS7

SS6

SS5

SS4

SS3

SS31

SS30

SS29

SS28

SS27

SS26

SS25

SS24

SS23

SS22

SS21

SS20

SS19

SS18

SS17

SS16

SS15

SS14

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits Name Description

If programmed as an output, Sleep state of GPx

[31:0] SSx

0 – Pin is driven to a zero during sleep mode 1 – Pin is driven to a one during sleep mode

Cleared by hardware, watchdog, and GPIO resets.

SS11

SS13

SS12

SS10

SS2

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-17. PGSR1 Bit Definitions

0x40F0_0024 PGSR1 Clocks and Power Manager

SS1

SS0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

SS63

SS62

SS61

SS60

SS59

SS58

SS57

SS56

SS55

SS54

SS53

SS52

SS51

SS50

SS49

SS48

SS47

SS46

SS45

SS44

SS43

SS42

SS41

SS40

SS39

SS38

SS37

SS36

SS35

SS34

SS33

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits Name Description

If programmed as an output, Sleep state of GPx

[31:0] SSx

0 – Pin is driven to a zero during sleep mode 1 – Pin is driven to a one during sleep mode

Cleared by hardware, watchdog, and GPIO resets.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

SS32

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Table 3-18. PGSR2 Bit Definitions

0x40F0_0028 PGSR2 Clocks and Power Manager

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

Clocks and Power Manager

reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits Name Description

[31:17] — reserved

If programmed as an output, Sleep state of GPx

[16:0] SSx

0 – Pin is driven to a zero during sleep mode 1 – Pin is driven to a one during sleep mode

Cleared by hardware, watchdog, and GPIO resets.

SS84

SS83

SS82

SS81

SS80

SS79

SS78

SS77

SS76

SS75

SS74

SS73

SS72

SS71

SS70

SS69

SS68

SS67

SS66

3.5.11 Reset Controller Status Register (RCSR)

The CPU uses the RCSR, shown in Table 3-19, to determine a reset’s last cause or causes. The processor can be reset in four ways:

• Hardware reset

• Watchdog reset

• Sleep mode

• GPIO reset

Refer to Table 2-4, “Effect of Each Type of Reset on Internal Register State” on page 2-6 for details of the behavior of different modules during each type of reset.

SS65

SS64

Each RCSR status bit is set by a different reset source and can be cleared by writing a 1 back to the bit. The RCSR status bits for watchdog reset, sleep mode, and GPIO resets have a hardware reset state of zero.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Intel® PXA255 Processor Developer’s Manual 3-33

Clocks and Power Manager

Table 3-19. RCSR Bit Definitions

0x40F0_0030 RCSR Clocks and Power Manager

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bits Name Description

[31:4] — reserved

GPIO Reset.

0 – GPIO reset has not occurred since the last time the CPU or hardware reset cleared

3GPR

2SMR

1WDR

0HWR

this bit.

1 – GPIO reset has occurred since the last time the CPU or hardware reset cleared this

bit.

Cleared by hardware reset and by setting to a 1.

Sleep Mode.

0 – Sleep mode has not occurred since the last time the CPU or hardware reset cleared

this bit.

1 – Sleep mode has occurred since the last time the CPU or hardware reset cleared

this bit.

Cleared by hardware reset and by setting to a 1.

Watchdog Reset.

0 – Watchdog reset has not occurred since the last time the CPU or hardware reset

cleared this bit.

1 – Watchdog reset has occurred since the last time the CPU or hardware reset cleared

this bit.

Cleared by hardware reset and by setting to a 1.

Hardware Reset.

0 – Hardware reset has not occurred since the last time the CPU cleared this bit. 1 – Hardware reset has occurred since the last time the CPU cleared this bit.

Set by hardware reset. Cleared by setting to a 1.

GPR

SMR

WDR

HWR

3.6 Clocks Manager Registers

The Clocks Manager contains three registers:

• Core Clock Configuration Register (CCCR)

• Clock Enable Register (CKEN)

• Oscillator Configuration Register (OSCC)

3.6.1 Core Clock Configuration Register (CCCR)

The CCCR, shown in Table 3-20, controls the core clock frequency, from which the core, memory controller, LCD controller, and DMA controller frequencies are derived. The crystal frequency to memory frequency multiplier (L), memory frequency to run mode frequency multiplier (M), and run mode frequency to turbo mode frequency multiplier (N) are set in this register. The clock frequencies are shown below.

3-34 Intel® PXA255 Processor Developer’s Manual

Memory frequency = 3.6864 MHz crystal freq. * crystal frequency to memory frequency multiplier (L)

Run mode frequency = Memory frequency * memory frequency to run mode frequency multiplier (M)

Turbo mode frequency = run mode frequency * run mode frequency to turbo mode frequency multiplier (N)

The value for L is chosen based on external memory or LCD requirements and can be constant while M and N change to allow run and turbo mode frequency changes without disrupting memory settings. The value for M is chosen based on bus bandwidth requirements and minimum core performance requirements. The value for N is chosen based on peak core performance requirements.

Table 3-20. CCCR Bit Definitions

0x4130_0000

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1

Bits Name Description

31:10 — reserved

[9:7] N

[6:5] M

[4:0] L

Clocks and Power Manager

Core Clock Configuration Register

(CCCR)

reserved N M L

Run Mode Frequency to Turbo Mode Frequency Multiplier

Turbo mode Freq. = Run mode frequency * N

000 – reserved

001 – reserved

010 – Multiplier = 1

011 – Multiplier = 1.5

100 – Multiplier = 2

101 – reserved

110 – Multiplier = 3

111 – res erv e d

Set to 010 on hardware and watchdog resets.

Memory Frequency to Run Mode Frequency Multiplier

Memory Freq. = Crystal Freq. * L

00 – reserved

01 – Multiplier = 1 (Run mode frequency is equal to memory frequency)

10 – Multiplier = 2 (Run mode frequency is 2 times the memory frequency)

11 – Multiplier = 3 (Run mode frequency is 4 times the memory frequency)

Set to 01 on hardware and watchdog resets.

Crystal Frequency to Memory Frequency Multiplier

00000 – reserved

00001 – Multiplier = 27 (Memory Frequency is 99.53MHz from 3.6864 MHz crystal)

00010 – reserved

00011 – Multiplier = 36 (Memory Frequency is 132.71MHz from 3.6864 MHz crystal)

00100 – reserved

00101 – Multiplier = 45 (Memory Frequency is 165.89MHz from 3.6864 MHz crystal)

00 110 t o 11111 – res e rved

Set to 00001 on hardware and watchdog resets.

Clocks Manager

Intel® PXA255 Processor Developer’s Manual 3-35

Clocks and Power Manager

3.6.2 Clock Enable Register (CKEN)

CKEN, shown in Table 3-21, enables or disables the clocks to most of the peripheral units. For lowest power consumption, the clock to any unit that is not being used must be disabled by writing a zero to the appropriate bit.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-21. CKEN Bit Definitions (Sheet 1 of 2)

0x4130_0004 CKEN Clocks Manager

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved

CKEN8

CKEN7

CKEN6

CKEN5

CKEN3

CKEN14

CKEN16

reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1

Bits Name Description

[31:17] — reserved

LCD Unit Clock Enable

16 CKEN16

15 — reserved

14 CKEN14

13 CKEN13

12 CKEN12

11 C KEN11

10 — reserved

9CKEN9

0 – Clock to the unit is disabled 1 – Clock to the unit is enabled.

Set by hardware and watchdog resets

I2C Unit Clock Enable

0 – Clock to the unit is disabled 1 – Clock to the unit is enabled.

Set by hardware and watchdog resets

FICP Unit Clock Enable

0 – Clock to the unit is disabled 1 – Clock to the unit is enabled.

These bits are set by hardware reset or watchdog reset

MMC Unit Clock Enable

0 – Clock to the unit is disabled 1 – Clock to the unit is enabled.

These bits are set by hardware reset or watchdog reset

USB Unit Clock Enable

0 – Clock to the unit is disabled 1 – Clock to the unit is enabled.

Set by hardware and watchdog resets

This bit must be set to allow the 48Mhz clock output on GP7 Alternate Function 1.

NSSP Unit Clock Enable

0 – Clock to the unit is disabled 1 – Clock to the unit is enabled.

Set by hardware and watchdog resets

CKEN11

CKEN13

CKEN12

reserved

CKEN2

CKEN1

CKEN0

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Clocks and Power Manager

Table 3-21. CKEN Bit Definitions (Sheet 2 of 2)

0x4130_0004 CKEN Clocks Manager

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

reserved

CKEN8

CKEN7

CKEN6

CKEN5

CKEN3

CKEN14

CKEN16

reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1

Bits Name Description

I2S Unit Clock Enable

8 CKEN8

7 CKEN7

6 CKEN6

5 CKEN5

4 CKEN4

3 CKEN3

2 CKEN2

1 CKEN1

0 CKEN0

0 – Clock to the unit is disabled 1 – Clock to the unit is enabled.

Set by hardware and watchdog resets

BTUART Unit Clock Enable

0 – Clock to the unit is disabled 1 – Clock to the unit is enabled.

These bits are set by hardware reset or watchdog reset

FFUART Unit Clock Enable

0 – Clock to the unit is disabled 1 – Clock to the unit is enabled.

Set by hardware and watchdog resets

STUART Unit Clock Enable

0 – Clock to the unit is disabled 1 – Clock to the unit is enabled.

Set by hardware and watchdog resets

HWUART Unit Clock Enable

0 – Clock to the unit is disabled 1 – Clock to the unit is enabled.

Set by hardware and watchdog resets

SSP Unit Clock Enable

0 – Clock to the unit is disabled 1 – Clock to the unit is enabled.

Set by hardware and watchdog resets

AC97 Unit Clock Enable

0 – Clock to the unit is disabled 1 – Clock to the unit is enabled.

Set by hardware and watchdog resets

PWM1 Clock Enable

0 – Clock to the unit is disabled 1 – Clock to the unit is enabled.

Set by hardware and watchdog resets

PWM0 Clock Enable

0 – Clock to the unit is disabled 1 – Clock to the unit is enabled.

Set by hardware and watchdog resets

CKEN11

CKEN13

CKEN12

reserved

CKEN2

CKEN1

CKEN0

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Clocks and Power Manager

3.6.3 Oscillator Configuration Register (OSCC)

The OSCC, shown in Table 3-22, controls the 32.768 kHz oscillator configuration. It contains two bits, the set-only 32.768 KHz OSCC[OON] and the read-only 32.768 kHz OSCC[OOK]. OSCC[OON] enables the external 32.768 kHz oscillator and can only be set by software. When the oscillator is enabled, it takes up to 10 seconds for to stabilize. When the oscillator is stabilized, the processor sets OSCC[OOK].

When OSCC[OOK] is set, the RTC and PM are clocked from the 32.768 KHz oscillator. Otherwise, the 3.6864 MHz oscillator is used. The OPDE bit, which allows the 3.6864 MHz oscillator to be disabled in sleep mode, is ignored (treated as if it were clear) if OSCC[OOK] is clear. OSCC[OOK] can only be reset by a hardware reset.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-22. OSCC Bit Definitions

0x4130_0008 OSCC Clocks and Power Manager

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits Name Description

[31:2] — reserved

32.768 KHz OON (write-once only bit)

0 – 32.768 KHz oscillator is disabled. The 3.6864 MHz oscillator (divided by 112) clocks

1OON

0OOK

the RTC and PM.

1 – 32.768 KHz oscillator is enabled. OON can not be cleared once written except by

hardware reset.

Cleared by hardware reset.

32.768 kHz OOK (read-only bit)

0 – 32.768 KHz oscillator is disabled or not stable. The 3.6864 MHz oscillator (divided

by 112) clocks the RTC and PM.

1 – 32.768 KHz oscillator has been enabled (OON=1) and stabilized. It will clock the

RTC and PM.

Cleared by hardware reset.

3.7 Coprocessor 14: Clock and Power Management

Coprocessor 14 contains two registers that control the power modes and sequences:

• CP14 register 6 – CCLKCFG register

OON

OOK

• CP14 register 7 – PWRMODE register

3-38 Intel® PXA255 Processor Developer’s Manual

Intel PXA255 User Manual 2

Specifications and Main Features

Frequently Asked Questions

User Manual

Introduction 1

1.1 Intel XScale® Microarchitecture Features

1.2 System Integration Features

1.2.1 Memory Controller

1.2.2 Clocks and Power Controllers

1.2.3 Universal Serial Bus (USB) Client

1.2.4 DMA Controller (DMAC)

1.2.5 LCD Controller

1.2.6 AC97 Controller

1.2.7 Inter-IC Sound (I2S) Controller

1.2.8 Multimedia Card (MMC) Controller

1.2.9 Fast Infrared (FIR) Communication Port

1.2.10 Synchronous Serial Protocol Controller (SSPC)

1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit

1.2.12 GPIO

1.2.13 UARTs

1.2.13.1 Full Function UART (FFUART)

1.2.13.2 Bluetooth UART (BTUART)

1.2.13.3 Standard UART (STUART)

1.2.13.4 Hardware UART (HWUART)

1.2.14 Real-Time Clock (RTC)

1.2.15 OS Timers

1.2.16 Pulse-Width Modulator (PWM)

1.2.17 Interrupt Control

1.2.18 Network Synchronous Serial Protocol Port

System Architecture 2

2.1 Overview

2.2 Intel XScale® Microarchitecture Implementation Options

2.2.1 Coprocessor 7 Register 4 - PSFS Bit

2.2.2 Coprocessor 14 Registers 0-3 - Performance Monitoring

2.2.3 Coprocessor 14 Register 6 and 7- Clock and Power Management

2.2.4 Coprocessor 15 Register 0 - ID Register Definition

2.2.5 Coprocessor 15 Register 1 - P-Bit

2.3 I/O Ordering

2.4 Semaphores

2.5 Interrupts

2.6 Reset

2.7 Internal Registers

2.8 Selecting Peripherals vs. General Purpose I/O

2.9 Power on Reset and Boot Operation

2.10 Power Management

2.11 Pin List

2.12 Memory Map

2.13 System Architecture Register Summary

Clocks and Power Manager 3

3.1 Clock Manager Introduction

3.2 Power Manager Introduction

3.3 Clock Manager

3.3.1 32.768 kHz Oscillator

3.3.2 3.6864 MHz Oscillator

3.3.3 Core Phase Locked Loop

3.3.4 95.85 MHz Peripheral Phase Locked Loop

3.3.5 147.46 MHz Peripheral Phase Locked Loop

3.3.6 Clock Gating

3.4 Resets and Power Modes

3.4.1 Hardware Reset

3.4.1.1 Invoking Hardware Reset

3.4.1.2 Behavior During Hardware Reset

3.4.1.3 Completing Hardware Reset

3.4.2 Watchdog Reset

3.4.2.1 Invoking Watchdog Reset

3.4.2.2 Behavior During Watchdog Reset

3.4.2.3 Completing a Watchdog Reset

3.4.3 GPIO Reset

3.4.3.1 Invoking GPIO Reset

3.4.3.2 Behavior During GPIO Reset

3.4.3.3 Completing GPIO Reset

3.4.4 Run Mode

3.4.5 Turbo Mode

3.4.5.1 Entering Turbo Mode

3.4.5.2 Behavior in Turbo Mode

3.4.5.3 Exiting Turbo Mode

3.4.6 Idle Mode

3.4.6.1 Entering Idle Mode

3.4.6.2 Behavior in Idle Mode

3.4.6.3 Exiting Idle Mode