Intel® IQ80332 I/O Processor
Evaluation Platform Board Manual
September 2004
Document Number: 274069-001US
Intel® IQ80332 I/O Processor Evaluation Platform Board Manual
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT.
Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
®
Intel
internal code names are subject to change.
THIS SPECIFICATION, THE Intel
WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE
ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. No license,
express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
Copyright © Intel Corporation, 2004
AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic,
DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, iCat, iCOMP, In sight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740,
IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel
NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation,
Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, Netpo rtExpress, Optimizer
logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare,
RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Co mputer Inside, The Journey Inside, This Way In,
TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and
other countries.
The ARM* and ARM Powered logo marks (the ARM marks) are trademarks of ARM, Ltd., and Intel uses these marks under license from ARM, Ltd.
*Other names and brands may be claimed as the property of othe rs.
®
IQ80332 IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY
2 September, 2004 Document Number: 274069-001US
Intel® IQ80332 I/O Processor Evaluation Platform Board Manual
Contents
Contents
1 Introduction....................................................................................................................................9
1.1 Document Purpose and Scope .............................................................................................9
1.2 Other Related Documents ....................................................................................................9
1.3 Electronic Information .........................................................................................................10
1.4 Component References ......................................................................................................10
1.5 Terms and Definitions......................................................................................................... 11
1.6 Intel
1.7 Intel
2 Getting Started.............................................................................................................................15
2.1 Kit Content..........................................................................................................................15
2.2 Hardware Installation..........................................................................................................15
2.3 Factory Settings.................................................................................................................. 17
2.4 Development Strategy ........................................................................................................17
2.5 Target Monitors...................................................................................................................18
2.6 Host Communications Examples........................................................................................19
®
80332 I/O Processor .................................................................................................12
®
IQ80332 I/O Processor Evaluation Platform Board Features ...................................14
2.2.1 First-Time Installation and Test..............................................................................15
2.2.2 Power Requirements .............................................................................................16
2.4.1 Supported Tool Buckets ........................................................................................17
2.4.2 Contents of the Flash.............................................................................................17
2.5.1 RedHat RedBoot....................................................................................................18
2.6.1 Serial-UART Communication.................................................................................19
2.6.2 JTAG Debug Communication ................................................................................19
2.6.3 Network Communication........................................................................................20
2.6.4 GNUPro GDB/Insight.............................................................................................21
2.6.4.1 Communicating with RedBoot................................................................21
2.6.4.2 Connecting with GDB.............................................................................23
3 Hardware Reference Section ......................................................................................................25
3.1 Functional Diagram.............................................................................................................25
3.2 Board Form-Factor/Connectivity......................................................................................... 26
3.3 Power..................................................................................................................................27
3.4 Memory Subsystem............................................................................................................28
3.4.1 DDR SDRAM .........................................................................................................28
3.4.1.1 Battery Backup.......................................................................................28
3.4.2 Flash Memory Requirements.................................................................................29
3.5 Interrupt Routing.................................................................................................................30
3.6 Intel
3.7 Debug Interface ..................................................................................................................35
Document Number: 274069-001US September, 2004 3
®
IQ80332 I/O Processor Evaluation Platform Board Peripheral Bus..........................31
3.6.1 Flash ROM.............................................................................................................32
3.6.2 UART .....................................................................................................................33
3.6.3 Non-Volatile RAM ..................................................................................................33
3.6.4 Audio Buzzer .........................................................................................................33
3.6.5 HEX Display...........................................................................................................33
3.6.6 Rotary Switch.........................................................................................................33
3.6.7 Battery Status ........................................................................................................34
Intel® IQ80332 I/O Processor Evaluation Platform Board Manual
Contents
3.7.1 Console Serial Port................................................................................................ 35
3.7.2 JTAG Debug ..........................................................................................................36
3.7.2.1 JTAG Port ..............................................................................................36
3.8 Board Reset Scheme..........................................................................................................37
3.9 Switches and Jumpers........................................................................................................ 38
3.9.1 Switch Summary....................................................................................................38
3.9.2 Default Switch Settings of S7A1- Visual................................................................38
3.9.3 Jumper Summary ..................................................................................................39
3.9.4 Connector Summary..............................................................................................39
3.9.5 General Purpose Input/Output Header ..................................................................39
3.9.6 Detail Descriptions of Switches/Jumpers...............................................................40
3.9.6.1 Switch S1C2: 80332 Reset ....................................................................40
3.9.6.2 Switch S6A1: BPCI-X Reset .................................................................. 40
3.9.6.3 Switch S8A1: Rotary..............................................................................40
3.9.6.4 Switch S7A1...........................................................................................40
3.9.6.4.1 S7A1-1: PCI-X Bus A Speed Enable corresponding to signal
name PBI_AD340
3.9.6.4.2 S7A1-2: Reset IOP core corresponding to signal name
PBI_AD540
3.9.6.4.3 S7A1-3: Configration Cycle Enable corresponding to signal
name PBI_AD641
3.9.6.4.4 S7A1-4: PCI-X Bus B Speed Enable corresponding to signal
name PBI_AD1041
3.9.6.4.5 S7A1-5: PCI-X Bus B Hot-Plug Reset Disable corresponding
to signal name PBI_AD1141
3.9.6.4.6 Switch S7A1- 6: Hot Plug Capable Disabled corresponding to
signal name PBI_AD1541
3.9.6.4.7 Switch S7A1 - 7: SMBUS Manageability Address Bit 0 corresponding to signal name PBI_AD1742
3.9.6.4.8 Switch S7A1 - 8: SMBUS Manageability Address Bit 3 corresponding to signal name PBI_AD1842
3.9.6.4.9 Switch S7A1- 9:SMBUS Manageability Address Bit 2 corresponding to signal name PBI_AD1742
3.9.6.4.10 Switch S7A1- 10: SMBUS Manageability Address Bit 1 corresponding to signal name PBI_AD1642
3.9.6.5 Jumper J7D1: Flash bit-width ................................................................ 43
3.9.6.6 Jumper J1C1: JTAG Chain....................................................................43
3.9.6.7 Jumper J1D2: UART Control .................................................................43
3.9.6.8 Jumper J7B4: SMBus Header ...............................................................44
3.9.6.9 Jumper J9D3: Buzzer Volume Control...................................................44
4 Software Reference.....................................................................................................................45
4.1 DRAM ................................................................................................................................. 45
4.2 Components on the Peripheral Bus.................................................................................... 45
4.2.1 Flash ROM.............................................................................................................46
4.2.2 Peripheral Bus Memory Map ................................................................................. 47
4.3 Board Support Package (BSP) Examples ..........................................................................48
4.3.1 Intel
®
80332 I/O Processor Memory Map..............................................................48
4.3.2 RedBoot* Intel
4.3.3 RedBoot Intel
4.3.4 RedBoot 80332 DDR Memory Initialization Sequence..........................................50
A IQ80321 and IQ80332 Comparisons........................................................................................... 51
4 September, 2004 Document Number: 274069-001US
®
80332 I/O Processor Memory Map ............................................. 49
®
80332 I/O Processor Files ............................................................49
Intel® IQ80332 I/O Processor Evaluation Platform Board Manual
Contents
B Getting Started and Debugger ...................................................................................................53
B.1 Introduction .........................................................................................................................53
B.1.1 Purpose ................................................................................................................. 53
B.1.2 Necessary Hardware and Software .......................................................................53
B.1.3 Related Documents ...............................................................................................53
B.1.4 Related Web Sites.................................................................................................54
B.2 Setup ..................................................................................................................................55
B.2.1 Hardware Setup.....................................................................................................55
B.2.2 Software Setup ......................................................................................................56
B.3 New Project Setup .............................................................................................................. 57
B.3.1 Creating a New Project.......................................................................................... 57
B.3.2 Configuration .........................................................................................................58
B.4 Flashing with JTAG............................................................................................................. 59
B.4.1 Overview................................................................................................................59
B.4.2 Using Flash Programmer.......................................................................................60
B.5 Debugging Out of Flash......................................................................................................61
B.6 Building an Executable File From Example Code ..............................................................61
B.7 Running the Code|Lab Debugger .......................................................................................62
B.7.1 Launching and Configuring Debugger ...................................................................62
B.7.2 Manually Loading and Executing an Application Program.....................................62
B.7.3 Displaying Source Code ........................................................................................63
B.7.4 Using Breakpoints..................................................................................................63
B.7.5 Stepping Through the Code...................................................................................64
B.7.6 Setting Code|Lab Debug Options ..........................................................................64
B.8 Exploring the Code|Lab Debug Windows ...........................................................................65
B.8.1 Toolbar Icons .........................................................................................................65
B.8.2 Workspace Window ...............................................................................................65
B.8.3 Source Code..........................................................................................................65
B.8.4 4 Debug and Console Windows ............................................................................65
B.8.5 Memory Window ....................................................................................................65
B.8.6 Registers Window ..................................................................................................66
B.8.7 Watch Window .......................................................................................................66
B.8.8 Variables Window ..................................................................................................66
B.9 Debugging Basics ...............................................................................................................67
B.9.1 Overview................................................................................................................67
B.9.2 Hardware and Software Breakpoints .....................................................................67
B.9.2.1 Software Breakpoints............................................................................. 67
B.9.2.2 Hardware Breakpoints ...........................................................................67
B.9.3 C.9.3 Exceptions/Trapping ....................................................................................68
Document Number: 274069-001US September, 2004 5
Intel® IQ80332 I/O Processor Evaluation Platform Board Manual
Contents
Figures
1Intel® 80332 I/O Processor Block Diagram ................................................................................13
2 Serial-UART Communication .....................................................................................................19
3 JTAG Debug Communication.....................................................................................................19
4 Network Communication Example .............................................................................................20
5 Functional Block Diagram...........................................................................................................25
6 Board Form Factor .....................................................................................................................26
7Intel
8 Flash Connection on Peripheral Bus..........................................................................................32
9 JTAG Port Pin-out ...................................................................................................................... 36
10 RESET Sources ......................................................................................................................... 37
11 Default Switch Setting Switch S7A1 ...........................................................................................38
12 Flash Connection to Peripheral Bus ...........................................................................................46
13 Intel
14 Intel
15 Software Flow Diagram ..............................................................................................................56
®
IQ80332 I/O Processor Evaluation Platform Board Peripheral Bus Topology ..................31
®
80332 I/O Processor Memory Map...................................................................................48
®
80332 I/O Processor Hardware Setup Flow Chart ...........................................................55
6 September, 2004 Document Number: 274069-001US
Intel® IQ80332 I/O Processor Evaluation Platform Board Manual
Contents
Examples
1Intel® 80332 I/O Processor Related Documentation List..............................................................9
2 Electronic Information................................................................................................................. 10
3 Component Reference................................................................................................................10
4 Terms and Definitions.................................................................................................................11
5 Summary of Features .................................................................................................................14
6 Form-Factor/Connectivity Features ............................................................................................26
7 Power Features ..........................................................................................................................27
8 Flash Memory Requirements......................................................................................................29
9 External Interrupt Routing to Intel
10 Peripheral Bus Features.............................................................................................................31
11 Flash ROM Features ..................................................................................................................32
12 Rotary Switch Requirements ...................................................................................................... 33
13 Battery Status Buffer Requirements ...........................................................................................34
14 Reset Requirements/Schemes ...................................................................................................37
15 Switch Summary.........................................................................................................................38
16 Switch S7A1 ...............................................................................................................................38
17 Jumper Summary ....................................................................................................................... 39
18 Connector Summary................................................................................................................... 39
19 J2D2 GPIO Header Definition.....................................................................................................39
20 Rotary Switch Settings................................................................................................................40
21 S7A1-1: PCI-X Bus A Speed Enable..........................................................................................40
22 Switch S7A1-2: Reset IOP: Settings and Operation Mode .........................................................40
23 Switch S7A1-3: RETRY: Settings and Operation Mode .............................................................41
24 S7A1-4: PCI-X Bus B Speed Enable: Settings and Operation Mode .........................................41
25 S7A1-5: PCI-X Bus B Hot-Plug Reset Disable: Settings and Operation Mode ..........................41
26 Switch S7A1- 6: Hot Plug Capable Disabled: Settings and Operation Mode .............................41
27 Switch S7A1 - 7: SMBUS Manageability Address Bit 0: Settings and Operation Mode .............42
28 Switch S7A1 - 8: SMBUS Manageability Address Bit 3: Settings and Operation Mode .............42
29 Switch S7A1 - 9: SMBUS Manageability Address Bit 2: Settings and Operation Mode .............42
30 Switch S7A1 - 10: SMBUS Slave Address 0: Settings and Operation Mode .............................42
31 Jumper J7D1: Descriptions.........................................................................................................43
32 Jumper J7D1: Settings and Operation Mode..............................................................................43
33 Jumper J1C1: Descriptions.........................................................................................................43
34 Jumper J1C1: Settings and Operation Mode..............................................................................43
35 Jumper J1D2: Descriptions.........................................................................................................43
36 Jumper J1D2: Settings and Operation Mode..............................................................................43
37 Jumper J7B4: Descriptions......................................................................................................... 44
38 Jumper J7B4: Settings and Operation Mode ..............................................................................44
39 Jumper J9D3: Descriptions.........................................................................................................44
40 Jumper J9D3: Settings and Operation Mode..............................................................................44
41 Peripheral Bus Memory Map ......................................................................................................47
42 Intel
®
IQ80321 Evaluation Platform Board and Intel® IQ80332 I/O processor evaluation platform
board Comparisons51
43 Related Documents ....................................................................................................................53
®
80332 I/O Processor ...........................................................30
Document Number: 274069-001US September, 2004 7
Intel® IQ80332 I/O Processor Evaluation Platform Board Manual
Contents
Revision History
Date Revision Description
27 September 2004 001 Initial Release.
8 September, 2004 Document Number: 274069-001US
Introduction 1
1.1 Document Purpose and Scope
This docume nt describes the Intel® IQ80332 I/O processor evaluation platform board (IQ80332)
using DDR-II 400 MHz SDRAM. The Intel
®
80332 I/O processor (80332) is intended for ra pid,
intelligent I/O development. The 80332 is a multi-function device that integrates the Intel XScale®
core (ARM* architecture compliant) with intelligent peripherals including a PCI Express bus
application bridge.
1.2 Other Related Documents
Table 1 . Intel® 80332 I/O Processor Related Documentation List
Document Number
®
Intel
80332 I/O Processor Developer’s Manual 274065
®
80332 I/O Pr oc es s or Da tas h ee t 274066
Intel
®
80332 I/O Processor Design Guide 273824
Intel
®
80332 I/O Pr oc es s or S pe ci fic a tion Update 273927
Intel
®
80332 I/O Processor JTAG Support White Paper 273963
Intel
®
80332 I/O Pr oc es s or P rod uc t B rie f 302746
Intel
®
80321 Softw a r e Con ve r s ion to t he Intel® 80332 I/O Pr oc es s or Applicatio n N ote 273890
Intel
®
Flash Recovery Utility (FRU) Reference Manual 274071
Intel
IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE JTAG-1149.1-1990) http://www.ieee.org
PCI Local B us Sp ec if ic ation, Rev is io n 2.3 - PCI Special Interest Group
PCI Expre ss Sp ec if ic at ion, Revision 1.0a - PCI Special Interest Group
PCI Express Base Specification 1.0a - PCI Special Interest Group
PCI Express Card Electromechanical Specification 1. 0a - PCI Special Interest Group
PCI Local B us Sp ec if ic ation, Rev is io n 2.3 - PCI Special Interest Group
PCI-X Specification, Revision 1.0b - PCI Special Interest Group
PCI Bus Power Management Interface Specification, Revision 1.1 - PCI Special Interest Group
PCI Bus Hot-Plug Specification, Revision 1.1 - PCI Special Interest Group
http://www.pcisig.com
/specifications
Intel documentation is available from the local Intel Sales Representative or Intel Literature Sales.
To obtain Intel literature write to or call:
Intel Corpo ration
Literature Sales
P.O. Box 5937
Denver, CO 80217-9808
(1-800-548-4725 ) or vis it the Intel website at http://www.intel.com
Evaluation Platform Board Manual 9
Intel® IQ80332 I/O Processor
Introduction
1.3 Electronic Information
Table 2. Electronic Information
Support Type Location/Contact
The Intel World-Wide Web (WWW) Location: http://www.intel.com
Customer Support (US and Canada): 1-916-377-7000
1.4 Component References
Table 3 provides additional information on the major components of 80332.
Table 3. Component Reference
Component Part Number Additional Information
Intel
StrataFlash®
Memory
Intel(R)
Gigabit
Ethernet
Controller
Rotary Switch DR FC 16
Hex Display HDSP-A103
AudioBuzzer
NVSRAM
CPLD
Temperature
Sensor
Program-
mable Reset
IC
Registered
Buffer
Program-
mable PLL
256 bit 1-wire
EEPROM
3.3V
Transceiver
Battery
Charger
28F640J3C
82545EM
DMT 1206
SMT
STK14C88-3
N 35
XC9572XL -
10TQ100C
LM75CIMX-3
MAX6306UK
29D3
IDT74SSTU3
2864BF
IDTCSPU877
BV
DS2430A_TS
OC
MAX561
ADP3801
• Manufacturer: Intel Corporation
• URL: http://developer.intel.com/design/flcomp/prodbref/298044.htm
• Manufacturer: Intel Corporation
• URL: http://developer.intel.com/design/network/products/lan/controllers/82545.htm
• Manufacturer: Grayhill*
• URL:
http://embrace.grayhill.com/embrace/Item/ASP/Item-Detail.asp?PartNo=94HAB16W&Catalog
GroupID=Series94HBinaryCoded&GroupDisplayLabel=&RestSes=No
• Manufacturer: Agilent Technologies*
• URL: http://www.semiconductor.agilent.com/cgi-bin/morpheus/home/home.jsp?pSection=LED
• Manufacturer: RDI*
• URL: http://www.rdi-electronics.com/products/Audio/DMT-1206-SMT.html
• Manufacturer: SIMTEK*
• URL: http://www.simtek.com/product-information/datasheets/256K-PDF/STK14C88-3.pdf
• Manufacturer: XILINK*
• URL: http://www.xilinx.com/bvdocs/publications/ds057.pdf
• Manufacturer: National*
• URL: http://www.national.com/pf/LM/LM75.html
• Manufacturer: Maxim*
• URL: http://www.maxim-ic.com/quick_view2.cfm/qv_pk/1524
• Manufacturer: IDT* (Integrated Device Technology)
• URL: http://www1.idt.com/pcms/products.taf?catID=97&genID=74SSTU32864
• Manufacturer: IDT* (Integrated Device Technology
• URL: http://www1.idt.com/pcms/products.taf?catID=112&genID=CSPU877
• Manufacturer: Maxim*
• URL: http://www.maxim-ic.com/quick_view2.cfm?qv_pk=2913
• Manufacturer: Maxim*
• URL: http://www.maxim-ic.com/quick_view2.cfm?qv_pk=1544
• Manufacturer: Analog Devices*
• URL: http://www.analog.com/UploadedFiles/Data_Sheets/308746738ADP3801_2_0.pdf
10 Evaluation Platform Board Manual
1.5 Terms and Definitions
Table 4. Terms and Definitions
Acronym/Term Definition
ARM Refers to both the microprocessor architecture and the company that licenses it.
CRB Customer Reference Board
ICE
IOP I/O processor
JTAG
PPCI-X Primary PCI-X.
PSU Power Supply Unit
SPCI-X Secondary PCI-X.
In-Circuit Emulator – A piece of hardware used to mimic all the functions of a
microprocessor.
Joint Test Action Group – A hardware port supplied on Intel XScale® microarchitecture
evaluation boards used for in-depth testing and debugging.
Intel® IQ80332 I/O Processor
Introduction
Evaluation Platform Board Manual 11
Intel® IQ80332 I/O Processor
Introduction
1.6 Intel® 80332 I/O Processor
About the 80332. The 80332 is a multi-function device that combines the Intel XScale® core with
intelligent peripherals, and integrates two PCI Express-to-PCI Bridges. The 80332 consolidates into a
single system:
• Intel XScale® core.
• x8 PCI Express Upstream Link.
• Two PCI Express-to-PCI Bridges supporting PCI-X interface on both segments.
• PCI Standard Hot Plug Controller (segment B).
• Address T ranslation Unit (ATU): PCI-to-Internal Bus Application Bridge, interfaced to the
segment A.
• High-Performance Memory Controller.
• Interrupt Controller with 17 external interrupt inputs.
• Two Direct Memory Access (DMA) Controller.
• Peripheral Bus Interface (PBI) Unit.
• Performance Monitor Unit (PMU).
• Application Accelerator Unit (AAU).
• Two I
2
C Bus Interface Units (BIU).
• Two 16550 Compatible UARTs with flow control (4 pins).
• Eight General Purpose Input Output (GPIO) Port s.
The 80332 is an integrated processor that addresses the needs of intelligent I/O applications and helps
reduce intelligent I/O system costs.
PCI Express is an industry standard, high performance, low latency system interconnect. The 80332
PCI Express upstream link is capable of x8 lane widths at 2.5 GHz operation as defined by the PCI
Express Specification, Revision 1.0. The addition of the Intel XScale® core brings intelligence to the
PCI Express-to-PCI Bridges.
The 80332 integrates dual PCI Express-to-PCI-X Bridges with the ATU as an integrated secondary
PCI device. The Upstream PCI Express port implements the PCI-to-PCI Bridge programming model
according to the PCI Express Specification, Revision 1.0. The Primary Address Translation Unit is
compliant with the PCI-X Specification, Revision 1.0a definitions of an ‘application bridge’.
®
For more in depth information in regards to the 80332, please see the Intel
Developer’s Manual.
80332 I/O Processor
12 Evaluation Platform Board Manual
Figure 1. Intel® 80332 I/O Processor Block Diagram
Intel® IQ80332 I/O Processor
Introduction
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Evaluation Platform Board Manual 13
Intel® IQ80332 I/O Processor
Introduction
1.7 Intel® IQ80332 I/O Processor Evaluation Platform
Board Features
Table 5. Summary of Features
Feature Definition
Battery Backup Unit: Battery back up circuit for SDRAM.
Ethernet Intel(R) 82545EM Gigabit Ethernet Controller
Flash ROM: 8 MB Flash ROM 3.3 V – 16-bit Flash I/F.
Form Factor: PCI-X card (312 X 107 mm)
General Purpose I/O: GPIO Pins are used as described in the appropriate section in this document
Hex Display: Two 7-segment Hex LED displays.
JTAG Port: ARM compliant JTAG Header.
Logic Analyzer:
Memory:
Onboard Power:
Power LED: Power on (green).
Primary PCI: PCI Express - x8 lane
RAID Support
Secondary PCI:
Serial Port:
Logic analyzer connectors on the DDRII SDRAM interface.
Interposer Card may be used for the memory bus – Information supplied separately.
• 256 MB (512 Mb x 16) DDRII SDRAM 400 MHz DIMM.
•ECC
•Registered
Board sources +1.25 V, +2.5 V, +3.3 V, +5 V, +12 V, and -12 V from primary PCI
connector.
• All core voltages are derived from 3.3 V supply.
• Auxiliary power for the Secondary PCI slot.
Support for “RAID” Implementation – Ability to make the devices plugged in the
secondary expansion slots “Private”.
Integrated XOR engine and two iSCSI CRC32C off-load engines.
• 1 64-bit PCI-X connector - 133 MHz.
• 1 64 bit 100 MHz PCI-X
• Intel(R) 82545EM Gigabit Ethernet Controller also on the 100 MHz PCI.
Dual RJ11 serial port connectors. The 80332 has two integrated UART serial ports
which are 16550 compatible.
14 Evaluation Platform Board Manual
Getting Started 2
The 80332 is a software development environment for IQ80332. Software updates and additional
offerings from vendors can change frequently. To keep up-to-date, please visit
http://www.intel-ioprocessortools.com/kshowcase/view for the latest updates.
2.1 Kit Content
The 80332 Kit contains the following items:
• IQ80332 with 400 MHz DDRII SDRAM DIMMs
• Code|Lab* Develo pme nt Environment from Accelera ted T echnology Incorpo rated*
• JTAG Emul a t i o n unit
• Serial Cable and RJ11 Adapter
2.2 Hardware Installation
Warning: Static c har ges ca n severe ly da mage the boards . Be sure yo u are pro perly gro unde d before removing
the boar d f rom the anti-static bag.
2.2.1 First-Time Installation and Test
For first-time installation, visually inspect the 80332 for any damage made during shipment. Follow
the host system manufacturer’s instructions for installing a PCI Express adapter card. The board is a
full-length host bus adapter card that requires a PCI Express slot free from obstructions. The IQ80332
has a x8 (read as ‘by eight’) edge connector.
Note: Please note, at this tim e the IQ80332 does NOT work in a passive backplane. This is due to the
nature of the PCI Express linking protocol. For the I/O processor to successfully come out o f reset,
a link must be established on the PCI Express bus. Without another device on a passive backplane
to ‘talk to’, a link is not established.
Evaluation Platform Board Manual 15
Intel® IQ80332 I/O Processor
Getting Started
2.2.2 Power Requirements
The 80332 requires a 3.3 V supply coming through the PCI Express primary connector. Plug the
board into a desktop with a PCI Express slot.
The 80332 has an auxiliary power receptacle (J1A1, see S ection 3.9.4, “Connector Summary”) that
is used to power the secondary PCI-X slot. This connector is compatible with a standard ATX hard
drive power connector.
Caution: Before connecting pow er to the entire system, verify that the auxiliary syst em power to th e
secondary P CI-X slot a nd t he main po wer t o the 8 0332 are both connec ted. Both powe r ra ils sho uld
come up at the s ame ti me. W hen there is not a ca rd pl ug ged in to the se con dary PCI-X slot , th en the
auxiliary power can be left unconnected.
16 Evaluation Platform Board Manual
2.3 Factory Settings
Make sure that the switch/jumper settings are set to proper positions as explained in Section 3.9,
“Switches and Jumpers” on page 38.
2.4 Development Strategy
2.4.1 Supported Tool Buckets
For developing and debugging software application, the production version of the 80332 kit includes
the Code|Lab Development Environment. Support for the Code|Lab development environment is
available from A TI *. Please refer to the enclosed package.
The kit also contains evaluation copies for several Software Development Tools. These tools are for
evaluation purposes and do not include any support. Please contact the vendor directly for additional
information and support. They include, but are not limited to:
• RedHat* GNUPro tools
Intel® IQ80332 I/O Processor
Getting Started
• ARM RealView Developer Suite
• WindRi ver* VxWorks* RTOS and Tornado* Development Tools
• Wasabi Systems NetBSD* ODS
• TimeSys* Linux* RTOS
• Accelerated Technology Inc.*, Nucleus Plus* RTOS and Development Tools
Please contact your Intel representative for the latest updates or visit
http://www.intel-ioprocessortools.com/kshowcase/view.
2.4.2 Contents of the Flash
The production v ersion of the board cont ains an image for R edHat RedBoot* targe t moni tor.
Evaluation Platform Board Manual 17
Intel® IQ80332 I/O Processor
Getting Started
2.5 Target Monitors
2.5.1 RedHat RedBoot
RedBoot* is an acronym for “RedHat Embedded Debug and Bootstrap”, and is the standard
embedded system debug/bootstrap environment from RedHat, replacing the previous generation of
debug firmware: CygMon and GDB stubs. It provides a bootstrap environment for a range of
embedded operating systems, such as embedded Linux and eCos*, and includes facilities such as
network downloading and debugging. It also provides a simple Flash file system for boot images.
RedBoot provides a set of tools for downloading and executing programs on embedded target
systems, as well as tools for manipulating the target system's environment. It can be used for both
product development (debug support) and for end product deployment (Flash and network booting).
Here are some highlights of RedBoot capabilities:
• Boot scripting support
• Simple command line interface for RedBoot configuration and management, accessible via
serial (terminal) or Ethernet (telnet ) (se e Secti on2.6.4, “GNUPro GDB/Insight” on page 21)
• Integrated GDB stubs for connection to a host- based debugger (GBD/Insight) via serial or
Ethernet. (E thernet connectivity is limited to local network only)
• Attribute Configuration - user cont rol of as pects such as system tim e an d date (when
applicable), default Flash image to boot from, default fail-safe image, static IP addre s s, etc.
• Configurable and extensible , s pecifically adapted to the target environment
• Network bootstrap support including setup and download, via BOOTP, DHCP and TFTP
• X/Y-Modem support for image download via serial
• Power On Self Test
18 Evaluation Platform Board Manual
2.6 Host Communications Examples
How to communicate to the host.
2.6.1 Serial-UART Communication
Using a serial connection to communicate with the board (Figure 2). Please note that the evlaution
board is plugged into a host machine, as in the figure below. You can use an additional laptop
computer, but it is not necessary. The host computer, when loaded with the proper software can
communicate with the board.
Figure 2. Serial-UART Communication
Intel® IQ80332 I/O Processor
Getting Started
Laptop computer
2.6.2 JTAG Debug Communication
Using a JTAG Emulator to communicate with the board (Figure 3). Please note that the evaluation
board is plugged into a host machine, as in the figure below. You can use an additional laptop
computer, but it is not necessary. The host computer, when loaded with the proper software can
communicate with the board.
Figure 3. JTAG Debug Communication
Laptop computer
Evaluation Platform Board Manual 19
Intel® IQ80332 I/O Processor
Getting Started
2.6.3 Network Communication
Using a standard network connection, the user can communicate with the board via the ethernet port.
Redboot also allows the user to remotely boot the platform using a BOOTP server through the
network Connection.
Figure 4. Network Communication Example
A
B C D E F
G
H
SELECTED
ON-LINE
20 Evaluation Platform Board Manual
2.6.4 GNUPro GDB/Insight
2.6.4.1 Communicating with RedBoot
Hardware Setu p:
• Host with UNIX/Linux or Win32 installed
• IQ80332 with serial cable
• RedHat RedBoot monitor Flashed to the platform board
Recommended Mapping of UART Ports to Host Com Ports
• Host port connected to the platform board UART.
The following communication tools can be used:
• Win32 using HyperTerminal
• UNIX using Kermit
• Linux using Minicom
• Solaris using Tip
Intel® IQ80332 I/O Processor
Getting Started
RedBoot Monitor startup:
Description: terminal emulator runs on host and communicates with the board via the serial cable.
Start: Power up the IQ80332. While the 'reset' is asse rted, the two 7-segment LEDs se quentially
display “88”, “A0” through “A6”, followed by “SL” (Scrub loop). When RedBoot is
successfully booted, i t displ ays the characters “A1” on the LEDs. When the final s tate of “A1”
does not occur, reset the process or again.
The time for reset is approximately 1 or 2 seconds.
Win32 on Host Connecting with HyperTerminal .
Evaluation Platform Board Manual 21
Intel® IQ80332 I/O Processor
Getting Started
To bring up a HyperT erminal session on a Win32 platform: Go to Start, Programs, Accessories,
Communications, HyperTerminal
• HyperTerminal setup screens:
— “Connection Description” Panel:
• Enter name.
— “Connect To” Panel:
• Select host com2 port (or whichever port you are using).
— Port Sett ings:
• Bits per second : 115200
• Data Bi t s : 8
• Parity: none
• Stop Bits: 1
• Flow Control: none
— Start HyperTerminal:
• Select Call from HyperTerminal panel.
— Reset or power up 80332 board.
— The Ho st sc re en r ead s :
RedBoot(tm) debug environment - built dd:mm:yy, Mon dd 2004
Platform: 80332
Copyright (C) 2004, RedHat, Inc.
RAM: 0xa0000000-0xa2000000
FLASH: 0x00000000 - 0x00800000, 64 blocks of 0x00020000 bytes each.
IP: 192.168.0.1, Default server: 0.0.0.0
RedBoot>
For further information on the GDB/Insight Debugger, refer to the content of the GNUPro CD and/or
the GNUPro Debugging Tools manual. This setup assumes that RedBoot is Flashed on the board.
22 Evaluation Platform Board Manual
2.6.4.2 Connecting with GDB
Below are the GDB commands entered from the command prompt. Be sure system path is set to
access “xscale-elf-gdb.exe”. File name in example “hello”. Bold type represents input by user:
Intel® IQ80332 I/O Processor
Getting Started
>xscale-elf-gdb -nw hello
1
• Start GDB executable, loads debug information and symbol s.
(GDB) set remotebaud 115200
• Set baud rate for the 80332.
Connect COM port:
• When using Windows command prompt:
(GDB) target rem o te co m1
Example: screen output from board to host (GDB) target remote com1:
Remote debugging using com1.
(GDB)
• When using Linux
(GDB) target rem o te /de v/ t tyS0
(GDB) load
• Load the program to the board, may have to wait a few seconds.
(GDB) b reak main
• Set breakpoint at main.
(GDB) continue
• Start the program using 'continue' verse the usual 'run'.
• Program hits break at main() and wait.
1. To be supplied separately.
Evaluation Platform Board Manual 23
Intel® IQ80332 I/O Processor
Getting Started
This Page Left Intentionally Blank
24 Evaluation Platform Board Manual
Intel® IQ80332 I/O Processor
Hardware Reference Section
Hardware Reference Sect ion 3
3.1 Functional Diagram
Figure 5 shows the functional block for the 80332.
Figure 5. Functional Block Diagram
Target Market
ROMB
PCI Express RAID card
HEX
LED
Buzzer
DDR II 400
DDR SDRAM
Battery
Backup
Local Bus
StrataFLASH
8 MB
RS-232
RS-232
I2C
GPIOs
JTAG
Intel®
80332
I/O
Processor
PCI
Express
X8 Edge Connector
PCI-X Bus IOP (100 MHz)
Gig-E
SlotPCI-X 2.0 Bus Slot (266MHz)
Slot
Evaluation Platform Board Manual 25
Intel® IQ80332 I/O Processor
s
Rotary
Switch
Hardware Reference Section
3.2 Board Form-Factor/Connectivity
Table 6 summarizes the form-factor and connectivity features for the 80332.
Table 6. Form-Factor/Connectivity Features
Description
The IQ80332 is a x8 PCI Express card with form factor depicted by Figure 6.
The 80332 connects to the Primary PCI-Express bus of the host machine.
The 80332 has two PCI-X expansion slot.
The 80332 has two serial ports and one RJ-45 Ethernet port.
The 80332 has one JTAG port compliant with ARM Multi-ICE 20-pin connector standard. The JTAG is targeted for the Intel
XScale® core and the CPLD, and is used for software debug purposes.
Figure 6. Board Form Factor
107
Aux
Power
JTAG
RJ-45
Etherne
t
RJ-11
Serial ports
Serial
EEPROM
PCI-X Slot (straddles b oard edge)
82545EM
GbE
Processor
Buffer
PCI-E
Edge
Inte l®
80332
I/O
DDR II DIMM
Peripheral Bus Header
I2C
CPLD
DIP Switch
PCI-X Rt Angle Slot
(Mounted on Back Side of PCB)
312
Flash
Intr/G PIO
Header
Power Statu
Buz
zer
Battery
26 Evaluation Platform Board Manual
3.3 Power
The 80332 draws power from the PCI Express bus. The power requirements for the 80332 are shown
in Table 7 below. The numbers do not include the power required by a PCI-X card mounted on the
expansion slot.
Table 7. Power Features
Voltage Rail Typical Current Maximum Current
+3.3 V TBD mA 6971 mA
+5 V TBD mA 7 mA
+12 V TBD mA 105 mA
Note: The maximum current was calculated, but not measured. This numbers do not include the power
required by a PCI-X card mounted on the expansion slot(s).
Evaluation Platform Board Manual 27
Intel® IQ80332 I/O Processor
Hardware Reference Section
3.4 Memory Subsystem
The Memory Controller of 80332 controls the DDR SDRAM memory subsystem. It features programmable chip selects and support for error correc tion codes (ECC). The memory controller can
be configured for DDR SDRAM at 333 MHz and DDR-II at 400 MHz. The memory controller
supports pi pelined a ccess and arbi tra tion co ntro l to maxim ize perform ance . The memory controll er
interface configuration support includes Unbuffered DIMMs, Registered DIMMs, and discrete
DDR SDRAM devices.
This IQ80332 has DDR-II at 400 MHz DIMM on the board. The memory subsystem of the
evaluation board consists of the SDRAM as well as the Flash memory subsystems.
3.4.1 DDR SDRAM
The DDR SDRAM interface consists of a 64-bit wide data path to support up to 3.2 Gbytes/sec
throughput. An 8-bit Error Correction Code (ECC) is stored into the DDRII SDRAM array along
with the data and is checked when the data is read.
The IQ80332 features on board registered DDRII 400 MHz SDRAM, arranged 512 Mbit x16 in
density (256 MB), and with ECC.
3.4.1.1 Battery Backup
Battery backup is provided to save any information in DDR during a power failure. The evaluation
board contains a 4V Li-ion battery, a char g i ng circuit and a regulator circuit.
DDRII technology provides enabling data preservation through the self-refresh command. When the
processor receives an active Primary PCI-X reset, the self-refresh command issues, driving SCKE
signals low. Upon seeing this condition, the board logic circuit holds SCKE low before the processor
loses power. Batteries maintain power to DDRII and logic, to ensure self-refresh mode. When the
circuit detects PRST# returning to inactive state, the circuit releases the hold on SCKE. Removing the
battery can disable the battery circuit. When the battery remains in the platform when it is de-powered
and/or removed from the chassis, the battery maintains DDRII for about four hours. Once power is
reapplied, the battery is fully charged.
The CPLD contains information in regards to the battery status. Please see Sectio n3.6.7 , “Battery
Status” on pa g e 34 for more details.
28 Evaluation Platform Board Manual
Intel® IQ80332 I/O Processor
Hardware Reference Section
3.4.2 Flash Memory Requirements
T o tal Flash memory size is 8 MB.
Table 8. Flash Memory Requirements
Description
IQ80332 Total Flash size is 8 MB
80332 Flash technology is based on Intel StrataFlash
80332 Flash uses a 16-bit interface
80332 Flash utilizes the 80332 Peripheral Bus
80332 May be programmed using the PCI-X interface – Flash Recovery Utility (FRU) Utility
80332 May be programmed using a RAM based software target monitor – RedHat RedBoot and ARM Firmware Suite
80332 May be programmed using a JTAG emulation/debug device
®
fami ly
Evaluation Platform Board Manual 29
Intel® IQ80332 I/O Processor
Hardware Reference Section
3.5 Interrupt Routing
The 80332 Interrupt routing.
Table 9. External Interrupt Routing to Intel
Interrupt System Resource
HPI# Temperature Sensor, Header
S_INTA# PCI-X Slot INTB#, Header
S_INTB# PCI-X Slot INTC#, Header
S_INTC# PCI-X Slot INTD#, Header
S_INTD# PCI-X Slot INTA#, Header
P_INTA# PCI-X Card Edge INTA#, Header
P_INTB# PCI-X Card Edge INTB#, Header
P_INTC# PCI-X Card Edge INTC#, Header
P_INTD# PCI-X Card Edge INTD#, Header
®
80332 I/O Processor
30 Evaluation Platform Board Manual
Intel® IQ80332 I/O Processor
Hardware Reference Section
3.6 Intel® IQ80332 I/O Processor Evaluation Platform
Board Peripheral Bus
The 80332 populates the peripheral bus as depicted by Figure 7.
Figure 7. Intel
®
IQ80332 I/O Processor Evaluation Platform Board Peripheral Bus Topology
Int el® 80332
I/O Processor PBI Bus
PC 104
Connector
The devices on the bus include Flash ROM, audio buzzer, CPLD, HEX display, NVSRAM, and
rotary switch.
Table 10. Peripheral Bus Features
The bus width can be 8-bit or 16-bit and runs at 66 MHz.
The bus is utilized for attaching debug and Flash devices.
The interfaces/devices that are utilized include an audio buzzer, CPLD, a rotary switch, a HEX Display, and
NVSRAM.
Agilent*
HDSP-A103 Hex
Dis play
Grayhill
HAB16W
Rotary Switch
Description
FLASH 28F640J3C
16-bit
8 Mb
XILINX
XC9572XL-
10TQ100C
CPLD
RDI
DMT-1206-SMT
Audio Buzzer
SIMTEK
STK14C88-3 N 35
NVSRAM
Evaluation Platform Board Manual 31
Intel® IQ80332 I/O Processor
Hardware Reference Section
3.6.1 Flash ROM
Table 11. Flash ROM Features
Flash is an Intel StrataFlash
Flash size is 8 MB
The connection to the peripheral bus is depicted by Figure 8
Figure 8. Flash Connection on Peripheral Bus
®
technology – Part number: 28F640J3C
Description
Intel® 80332
I/O
Processor
FLASH
28F640J3A
CS
16-bit
8 Mb
Intel® 80332 I/O Processor Bus
PCE0
B3236-02
32 Evaluation Platform Board Manual
3.6.2 UART
The 80332 has two integrated UAR Ts. Each asynchronous serial ports supports all the functions of a
16550 UART. The UART signals are connected to a dual RS-232 buffer and then to a RJ-11 serial
port connector mounted on the bracket of the evaluation board. The serial port and GPIO signals are
muxed on the same pins. Jumper J1D2, located next to the serial port buffer can disable the buffer to
allow the signals to be used as GPIO signals. Please see Section 3.9.3, “Jumper Summary” on
page 39 for more details.
3.6.3 Non-Volatile RAM
In addition to the 8MB Flash device, the IQ80332 has a separate 32k by 8 non-volatile RAM device
on the peripheral bus. The NVRAMs address range is from CE87 0000 to CE87 FFFF (in hex).
Please see Section 4.2.2, “Peripheral Bus Memory Map” on page 47 for more details.
3.6.4 Audio Buzzer
The 80332 evaluation board has an audio buzzer that is turned on and off by writing to the Buzzer
Control Register located in the CPLD. Jumper J9D3 adjusts the volume from off, to soft, to loud.
Please see Section 3.9.3, “Jumper Summary” on page 39 for more details. The audio buzzer’s
address range is from CE86 0000 to CE86 FFFF (in hex). Please see Secti on 4.2.2, “Peripher al Bus
Memory Map” on page 47 for more details.
Intel® IQ80332 I/O Processor
Hardware Reference Section
3.6.5 HEX Display
The two pai r s of Agilen t HDSP-A103 seven segment LEDs a re used for displaying POST codes or
other software generated debug codes. Both HEX displays are individually addressed. The left HEX
display address range is CE84 0000 to CE84 FFFF (in hex). The right HEX display address range is
CE85 0000 to CE85 FFFF (in hex). Please see Section 4.2.2, “Peripheral Bus Memory Map” on
page 47 for more details.
3.6.6 Rotary Switch
The 80332 provides a Rotary Switc h (S8A1) for the user to s elect from diff erent boot-up flav ors.
Setting ‘0’ enables private devices on the secondary PCI-X bus. Setting ‘0’ allows Redboot to
configure and use devices in slot A. Position ‘1’ allows the host to see all the devices on the
secondary PCI bus. The default setting is position 0. Other settings are currently not validated with
Redboot. Other settings may be used with other software applications. Please see Section 4.2.2,
“Peripheral Bus Memory Map” on page 47 for more details on addressing the rotary switch.
Table 12. Rotary Switch Requirements
Rotary switch has a 4-bit resolution (16 positions).
The connection to the peripheral bus is depicted by Figure 7.
Default setting is ‘0’. This enables private devices on PCI-X bus.
Position ‘1’ allows host to see all devices on the secondary bus.
Description
Evaluation Platform Board Manual 33
Intel® IQ80332 I/O Processor
Hardware Reference Section
3.6.7 Battery Status
A CPLD on the IQ80332 provides the following status for the battery. Please see Section 4.2.2, “Peripheral
Bus Memory Map” on page 47 for more details on addressing the CPLD.
Table 13. Battery Status Buffer Requirements
Read/
BIT
Write
Name Description
0 R Battery Present
1 R Battery Charged
2 R Battery Discharged
3 R/W Battery Enable
4-7 * Reserved Undefined
• 0 = No backup battery
• 1 = Battery backup is present
• 0 = Battery is not fully charged
• 1 = Battery is fully charged
• 0 = Battery backup is not fully discharged
• 1 = Battery backup is fully discharged
• 0 = Disable battery backup
• 1 = Enable battery backup
34 Evaluation Platform Board Manual
3.7 Debug Interface
3.7.1 Console Serial Port
The platform has two serial ports for debug purposes as described in Section 3.6, “Intel® IQ80332
I/O Processor Evaluation Platform Board Peripheral Bus” on page 31.
Intel® IQ80332 I/O Processor
Hardware Reference Section
Evaluation Platform Board Manual 35
Intel® IQ80332 I/O Processor
1
Hardware Reference Section
3.7.2 JTAG Debug
The 80332 has a 20-pin JTAG connector (J7D2) that is in compliant with ARM Multi-ICE guidelines.
3.7.2.1 JTAG Port
Figure 9. JTAG Port Pin-out
VTref 1
nTRST 3
TDI 5
TMS 7
TCK 9
RTCK 11
TDO 13
nSRST 15
DBGRQ 17
DBGACK 19
Vsupply2
GND4
GND6
GND8
GND10
GND12
GND14
GND16
GND18
GND20
A9457-0
36 Evaluation Platform Board Manual
3.8 Board Reset Scheme
Figure 10 depicts the reset scheme for the 80332. Table 14 list the reset schemes for the 80332.
Table 14. Reset Requirements/Schemes
Primary PCI reset, resets all devices on the board. It occurs during the power-up.
The SRST signal from the JTAG connector is a bi-directional signal that can force a reset similar to the
power-up reset on the board.
Figure 10. RESET Sources
DDR II SDRAM
Reset
Button
Debounce
Power
Delay
JTAG
Con
Voltage
Monitor
TRST
#
SRST
#
M_RST#
RESETIN
#
PWRDELAY
Intel® 80332 I/O
Processor
TRST
#
PWRGD
Isolation
Description
B_RST#
A_RST#
Pwrgood
Intel® IQ80332 I/O Processor
Hardware Reference Section
PCI-X 2.0 Con B
PCI-X Con A
CPLD
RST#
LAN_PWR_GOOD
82545EM
PCI-E Con
Evaluation Platform Board Manual 37
Intel® IQ80332 I/O Processor
Hardware Reference Section
3.9 Switches and Jumpers
3.9.1 Switch Summary
Please note that the term ‘open’ refers to the individual pin of switch S7A1 being pushed in at bottom
(small dot on pin away from the ‘open’ label on the switch). The term ‘closed’ refers to the pin being
pushed in at the top. Please see Figure 11, “Default Switch Setting Switch S7A1” on page 38, for
more details.
Table 15. Switch Summary
Switch Association Description
S1C1 80332 Reset
S6A1 BPCI-X Reset
S7A1-1 APCI-X Bus PCI-XBus A Speed Set Closed
S7A1-2 IOP RESET: Sets IOP Reset-Mode operation Open
S7A1-3 IOP RETRY: Sets IOP RETRY-Mode operation Open
S7A1-4 BPCI-X Bus PCI-X Bus B speed set Closed
S7A1-5 BPCI-X Bus PCI-X Bus B Hot Plug Reset Closed
S7A1-6
S7A1-7 Open
S7A1-8 SMBUS Bus SMBUS Manageability address bit 3 Open
S7A1-9 SMBUS Bus SMBUS Manageability address bit 2 Open
S7A1-10 SMBUS Bus SMBUS Manageability address bit 1 Open
S8A1 CPLD Rotary Switch Position 1
BPCI-X Bus
SMBUS Bus
Hot Plug Capable Disable
SMBUS Manageability address bit 5
3.9.2 Default Switch Settings of S7A1- Visual
Table 16. Switch S7A1
Closed Open Open Closed Closed Closed Open Open Open Open
S7A1
1
S7A1
2
S7A1
3
S7A1
4
S7A1
5
S7A1
6
S7A1
Factory
Default
Closed
S7A1
7
8
S7A1
9
S7A1
10
Figure 11. Default Switch Setting Switch S7A1
38 Evaluation Platform Board Manual
165432
Open
78
10
9
3.9.3 Jumper Summary
Table 17. Jumper Summary
Jumper Description Factory Default
J1C1 JTAG Chain Enable 1-2
J1D2 Disables UART Open
J7B4 SM_SCLK to EEPROM, SM_SDTA to EEPROM 1-2, 3-4
J7D1 16-bit Flash Enable Open
J9D3 Buzzer Volume Open
3.9.4 Connector Summary
Table 18. Connector Summary
Connector Description
J1D1 RJ45 Network Connector for GbE NIC.
J1E1 RJ11 Dual Serial Port Connector.
J1L1, J1M1,
J1M2, J1N1,
J2M1, J2M2
J1R1 Secondary PCI-X Expansion bus Slot
J2A1 Secondary PCI-X Expansion bus Slot.
J2D1 Power header for fan.
J2D2 GPIO tap-in Header
J1B1, J5D1,
J5C1
J2E1 Edge connector for primary PCI Express Bus.
J5B1 DIMM
J7A1 PC104 Mod connector.
J7B1, J7B2 I
J7B3
J7C1 Test header (empty)
J7D2 JTAG CPLD Header.
J9D1 Power header for battery.
SMA connectors
Test headers
2
C 4 pin connectors.
Secondary PCI-X Expansion Slot Power. Please see Section 2.2.2, “Power Requirements”
for more details
Intel® IQ80332 I/O Processor
Hardware Reference Section
3.9.5 General Purpose Input/Output Header
The following table in Section 19, “J2D2 GPIO Header Definiti on” on pa ge 39 shows the GPIO
signal assignments. The GPIO signals are muxed with the serial port signals. The serial port must be
disabled to use the GPIO signals. These pins corespond to Jumer J2D2.
Table 19. J2D2 GPIO Header Definition
Pin Signal Pin Signal Pin Signal
1 GND 4GPIO57GPIO2
2GPIO75GPIO48GPIO1
3GPIO66GPIO39GPIO0
Evaluation Platform Board Manual 39
Intel® IQ80332 I/O Processor
Hardware Reference Section
3.9.6 Detail Descriptions of Switches/Jumpers
3.9.6.1 Switch S1C2: 80332 Reset
This switch resets 80332.
3.9.6.2 Switch S6A1: BPCI-X Reset
This switch resets the PCI-X B segment bus.
3.9.6.3 Switch S8A1: Rotary
Table 20. Rotary Switch Settings
Position Description
0
Factory Default
1
2-F
Enables private devices on the secondary PCI-X slot. Redboot uses this setting to configure
private devices
Disables private devices on the secondary PCI-X slot. This setting allows the host to see all
the devices on the secondary PCI bus.
These settings are meaningless to Redboot. Other applications may use these settings for
configuration or software utilization.
For more information, please see Section 3.6.6, “Rotary Switch” on page 33.
3.9.6.4 Switch S7A1
This 10 pin switch that allows the user to enable or disable various features. Please see specifics
below.
3.9.6.4.1 S7A1-1: PCI-X Bus A Speed Enable corresponding to signal name PBI_AD3
This switch allows the user to force the PCI-X bus A to run at 133 MHz or 100 MHz.
Table 21. S7A1-1: PCI-X Bus A Speed Enable
S7A1-1 Operation Mode
Open Enables 133 MHz on PCI-X bus A
Closed Enables 100 MHz on PCI-X bus A (Default Mode)
3.9.6.4.2 S7A1-2: Reset IOP core corresponding to signal name PBI_AD5
RESET MODE is latched at the de-asserting edge of P_RST# and it determines when the 80332 is held
in reset until the Intel XScale® core Reset bit is cleared in the PCI Configuration and Status Register.
Table 22. Switch S7A1-2: Reset IOP: Settings and Operation Mode
S7A1-2 Operation Mode
Open Don't hold in reset, enable IOP core (Default mode).
Closed Hold IOP core in reset.
40 Evaluation Platform Board Manual
Intel® IQ80332 I/O Processor
Hardware Reference Section
3.9.6.4.3 S7A1-3: Configration Cycle Enable corresponding to signal name PBI_AD6
Configuration Cycle Enable or RETRY is latched at the de-asserting edge of P_RST# and it
determines when the Primary PCI interface disable PCI configuration cycles by signaling a Retry
until the Configuration Cycle Retry bit is cleared in the PCI Configuration and Status Register.
Table 23. Switch S7A1-3: RETRY: Settings and Operation Mode
S7A1-3 Operation Mode
Open Configuration Retry Enabled. - use when booting in a host (Default mode).
Closed Configuration Retry Disabled.
3.9.6.4.4 S7A1-4: PCI-X Bus B Speed Enable corresponding to signal name PBI_AD10
This switch allows the user to enables 133 MHz on PCI-X segment B.
Table 24. S7A1-4: PCI-X Bus B Speed Enable: Settings and Operation Mode
S7A1-4 Operation Mode
Open Enables 133 MHz on PCI-X bus B.
Closed Enables 100 MHz on PCI-X bus B (Default Mode).
3.9.6.4.5 S7A1-5: PCI-X Bus B Hot-Plug Reset Disable corresponding to signal name
PBI_AD11
This switch allows the user to enables or disable Hot-Plug Reset on PCI-X segment B.
Table 25. S7A1-5: PCI-X Bus B Hot-Plug Reset Disable: Settings and Operation Mode
S7A1-5 Operation Mode
Open PCI-X Bus B Hot-Plug Enable, normal reset mode disabled
Closed PCI-X Bus B Hot-Plug Disable, normal reset mode (Default Mode).
3.9.6.4.6 Switch S7A1- 6: Hot Plug Capable Disabled corresponding to signal name
PBI_AD15
This switch allows the user to enable hot plug devices on the secondary PCI-X bus B.
Table 26. Switch S7A1- 6: Hot Plug Capable Disabled: Settings and Operation Mode
S7A1-6 Operation Mode
Open Hot Plug on Bus B Enabled
Closed Disables Hot Plug on Bus B(Default mode)
Evaluation Platform Board Manual 41
Intel® IQ80332 I/O Processor
Hardware Reference Section
3.9.6.4.7 Switch S7A1 - 7: SMBUS Manageability Address Bit 0 corresponding to signal name
PBI_AD17
This allows 80332 to address SMBus Slave Address bit 0 (PBI_A17).
Table 27. Switch S7A1 - 7: SMBUS Manageability Address Bit 0: Settings and Operation Mode
S7A1-6 Operation Mode
Open SMBus Manageablity Address Bit 0 = “1” (Default Mode)
Closed SMBus Manageablity Address Bit 0 = “0”
3.9.6.4.8 Switch S7A1 - 8: SMBUS Manageability Address Bit 3 corresponding to signal name
PBI_AD18
This allows 80332 to address SMBus Slave Address bit 3 (PBI_A18).
Table 28. Switch S7A1 - 8: SMBUS Manageability Address Bit 3: Settings and Operation Mode
S7A1-8 Operation Mode
Open SMBus Manageablity Address Bit 3 = “1” (Default Mode)
Closed SMBus Manageablity Address Bit 3 = “0”.
3.9.6.4.9 Switch S7A1- 9:SMBUS Manageability Address Bit 2 corresponding to signal name
PBI_AD17
This allows 80332 to address SMBus Slave Address2 (PBI_A17).
Table 29. Switch S7A1 - 9: SMBUS Manageability Address Bit 2: Settings and Operation Mode
S7A1-9 Operation Mode
Open SMBus Manageablity Address Bit 2 = “1” (Default Mode)
Closed SMBus Manageablity Address Bit 2 = “0”.
3.9.6.4.10 Switch S7A1- 10: SMBUS Manageability Address Bit 1 corresponding to signal
name PBI_AD16
This allows 80332 to address SMBus Slave Address 1 (PBI_A16).
Table 30. Switch S7A1 - 10: SMBUS Slave Address 0: Settings and Operation Mode
S7A1-10 Operation Mode
Open SMBus Manageablity Address Bit 1 = “1” (Default Mode)
Closed SMBus Manageablity Address Bit 1 = “0”.
42 Evaluation Platform Board Manual
3.9.6.5 Jumper J7D1: Flash bit-width
The Intel® IQ80332 I/O processor evaluation platform board expects an 8-bit Flash enable.
Table 31. Jumper J7D1: Descriptions
Jumper Description Factory Default
J7D1 8-bit Flash Enable Open
Table 32. Jumper J7D1: Settings and Operation Mode
Pins Operation Mode
1-2 Enables 16-bit Flash
NC 8-bit Flash (default mode)
3.9.6.6 Jumper J1C1: JTAG Chain
Table 33. Jumper J1C1: Descriptions
Jumper Description Factory Default
J1C1 JTAG Chain Enable 1-2
Intel® IQ80332 I/O Processor
Hardware Reference Section
Table 34. Jumper J1C1: Settings and Operation Mode
J1C1 Operation Mode
Pins 1, 2 Enables JTAG Chain for IOP only (Default Mode).
Pins 3, 4 Enables JTAG Chain for IOP + CPLD
Pins 5, 6 Enables JTAG Chain for IOP + CPLD + GBE
Pins 7, 8 Enables TRST# pull-down resistor
3.9.6.7 Jumper J1D2: UART Control
Table 35. Jumper J1D2: Descriptions
Jumper Description Factory Default
J1D2 UART Control Open
Table 36. Jumper J1D2: Settings and Operation Mode
J1D2 Operation Mode
Pins 1, 2 Disables UART/RS-232 port
NC Enables UART/RS-232 port (Default Mode)
Evaluation Platform Board Manual 43
Intel® IQ80332 I/O Processor
Hardware Reference Section
3.9.6.8 Jumper J7B4: SMBus Header
Table 37. Jumper J7B4: Descriptions
Jumper Description Factory Default
J7B4 SMBus Header 1-2, 3-4
Table 38. Jumper J7B4: Settings and Operation Mode
J7B4 Operation Mode
Pins 1, 2 Connects SM_SCLK to EEPROM U7B2 (Default Mode).
Pins 3, 4 Connects SM_SDTA to EEPROM U7B2 (Default Mode).
Pins 5, 6 Connects SM_SCLK to GE_SMCLK (for GBE control)
Pins 7, 8 Connects SM_SDTA to GE_SMDAT(for GBE control)r
Pins 9, 10 Connects SM_SCLK to PE_SMCLK (for PCI-E bus control)
Pins 11, 12 Connects SM_SDTA to PE_SM_SDAT (for PCI-E bus control)
3.9.6.9 Jumper J9D3: Buzzer Volume Control
Table 39. Jumper J9D3: Descriptions
Jumper Description Factory Default
J9D3 Buzzer Volume Open
Table 40. Jumper J9D3: Settings and Operation Mode
J9D3 Operation Mode
Pins 2, 3
Pins 1, 2
NC
Buzzer Volume Soft
Buzzer Volume Loud.
Buzzer Volume Off.
44 Evaluation Platform Board Manual
Intel® IQ80332 I/O Processor
Software Reference
Software Reference 4
4.1 DRAM
For DDR SDRAM Sizes and Configurations, see theIntel® 80332 I/O Processor Developer’s
Manual. This section also contains multiple examples of Address Register Programming.
See the Intel
DDR-II configurations.
For all registers relating to DRAM and other MCU relat ed re gis ters, see the Intel
Processor Developer’s Manual.
®
80332 I/O Processor Design Guide, sec tion 8, ta ble 34 for supported DDR333 and
4.2 Components on the Peripheral Bus
The 80332 has a peripheral bus which contains the following peripheral devices:
• Flash ROM
• CPLD
• Audio Buzzer
• Rotary Switch
• Hex Display
Peripheral memory-Mapped Register Locations and all registers associated with PBI or the Peripheral
Bus Interface Unit can be found in the Intel
®
80332 I/O Processor Developer’s Manual.
®
80332 I/O
Evaluation Platform Board Manual 45
Intel® IQ80332 I/O Processor
Software Reference
4.2.1 Flash ROM
The Flash ROM is an 8 MB Intel StrataFlash® (part# 28F640) that sits on the Peripheral Bus and is
accessed using PCE0.
Figure 12. Flash Connection to Peripheral Bus
FLASH
28F640J3A
16-bit
8 Mb
Intel® 80332
CS
PCE0
I/O
Processor
Intel® 80332 I/O Processor Bus
B3236-02
Under normal operation, the very first instruction access by the Intel XScale® core begins at location
0x0 on the 80332 Internal Bus. By default, address 0x0 is pointing to PCE0 where flash is located.
Currently, the Intel Flash Recovery Utility (FRU) cannot be used with the IQ80332. An alternative to
FRU would be to reprogram the flash through JTAG or using Redboot commands, when Redboot is
currently loaded onto the board. For more information on using Redboot to program the flash, please
see Redboot Manual.
46 Evaluation Platform Board Manual
4.2.2 Peripheral Bus Memory Map
The Table 41 is the physical memory map of the devices on the 80332 Peripheral Bus:
Table 41. Peripheral Bus Memory Map
Address Range (in Hex) Size Data Bus Width Description
C000 0000 - C07F FFFF 8 MB 8-bit or 16-bit Flash memory (re-mapped)
CE80 0000 -CE80 FFFF 64 KB 8-bit Product Code
CE81 0000 -CE81 FFFF 64 KB 8-bit Board Stepping
CE24 0000 -CE82 FFFF 64 KB 8-bit CPLD Firmware Revision
CE83 0000 -CE83 FFFF 64 KB 8-bit Discrete LEDs
CE84 0000 -CE84 FFFF 64 KB 8-bit Hex Display Left
CE85 0000 -CE85 FFFF 64 KB 8-bit Hex Display Right
CE86 0000 -CE86 FFFF 64 KB 8-bit Buzzer Control
CE87 0000 -CE87 FFFF 64 KB 8-bit 32KB NV RAM
CE8D 0000 -CE8D FFFF 64 KB 8-bit Rotary Switch
CE8E 0000 -CE8E FFFF 64 KB 8-bit ESN I/O
CE8F 0000 -CE8F FFFF 64 KB 8-bit Battery Status
Intel® IQ80332 I/O Processor
Software Reference
Evaluation Platform Board Manual 47
Intel® IQ80332 I/O Processor
Software Reference
4.3 Board Support Package (BSP) Examples
Examples provided in this section are based on the RedHat* RedBoot software running on the
IQ80332.
4.3.1 Intel® 80332 I/O Processor Memory Map
Figure 13 depicts the memory space for the 80332 (before RedBoot boots):
Figure 13. Intel
®
80332 I/O Processor Memory Map
ADDRESS
0000 0000H
0000 0040H
Memoryless Boot Registers
ATU Outbound Direct Addressing Window
8000 0000H
8800 0000H
9000 0000H
9001 0000H
FFFF E000H
FFFF E900H
ATU Outbound Memory Translation Windows
Code / Data External Memory
ATU Outbound I/O Translation Window
Code/Data
External Memory
Peripheral Memory-Mapped Registers
FFFF FFFFH
48 Evaluation Platform Board Manual
I/O Processor Reserved
Reserved
Address
Space
External Memory
Intel® IQ80332 I/O Processor
Software Reference
4.3.2 RedBoot* Intel® 80332 I/O Processor Memory Map
Virtual Address Physical Address
0x0000 0000 0x0000 0000 2048 SDRAM - 64-bit ECC
0x8000 0000 0x8000 0000 128 ATU Outbound Memory Translation Windows
0x8800 0000 * 128 Unused
0x9000 0000 0x9000 0000 1 ATU OUtbound I/O Translation Window.
0x9010 0000 * 255 Unused
0xA000 0000 0x0000 0000 512 SDRAM - 64 bit ECC Uncached
0xC000 0000 0xC000 0000 8 Flash (PCE0#)
0xC080 0000 * 224 Unused
0xCE80 0000 0xCE80 0000 1 PCE1# - Uncached
0xCE90 0000 * 23 Unused
0xD000 0000 * 512 Unused
0xF00 0000 0xF00 0000 1 Cache flush
0xF010 0000 * 254 Unused
0xFFF0 0000 0xFFF0 0000 1
4.3.3 RedBoot Intel
Size
(MB)
®
PMMR - Intel
Registers. Please see Chapter 17 of the Intel
Processor Developer’s Manual for more details.
®
80332 I/O Processor Files
80332 I/O Processor Memory Mapped
Description
®
80332 I/O
Attached in the kit, find a copy of the RedHat eCos for IQ80332 CD. Once the CD is installed, you
may find:
• The RedBoot initialization code source files from the following location:
From the installed directory:
..\RedHat\eCos\packages\hal\arm\xscale\iq80332\current\include
• The RedBoot binary image files (downloada ble onto Flash) from the following location:
From the installed directory:
..\RedHat\eCos\loaders\iq80332
To access RedHat GNUPro tools including RedBoot binaries and source code, you may also go to the
following location on the Intel site:
• http://developer.intel.com/design/intelxscale/dev_tools/021022/index.ht m
Evaluation Platform Board Manual 49
Intel® IQ80332 I/O Processor
Software Reference
4.3.4 RedBoot 80332 DDR Memory Initialization Sequence
In order to set the correct ECC bits, a DDR memory system (DIMM or discrete components) must be
written to with a known value. This process requires 64-bit writes to the entire DDR memory intended
for use. The following explains the sequence for memory initialization by RedBoot on an 80332 board
with an ECC DIMM. It also includes an example for the scrub (ECC initializatio n ) co d e.
Initialization Sequence:
1. Disable inte rrupts. (Te chnically they are disabled at reset, but for soft reset this is included.
2. Init PBIU (Peripheral Bus Interface Unit) chip selects.
3. Enabl e I cach e .
4. Move Flash to 0xF0000000.
5. Set TT B an d Enable MMU .
6. Read DIM for memory parameters.
7. Set Memory Parameters.
8. Delay.
9. Turn DDRAM on.
10. Delay.
11. Enable Data Cache.
12. Enable BTB.
13. Flush all.
14. Clear ECC error logs.
15. Battery Test.
16. Enable ECC.
17. Scrub loop: W r ite zeros to all m emo ry locations
mov r8, r4 // save DRAM size
mov r0, #-1
mov r1, #-1
mov r2, #-1
mov r3, #-1
mov r4, #-1
mov r5, #-1
mov r6, #-1
mov r7, #-1
ldr r11, = SDRAM_BASE
// scrub Loop
0:
stmia r11!, {r0-r7}
subs r12, r12, #32
bne 0
50 Evaluation Platform Board Manual
Intel® IQ80332 I/O Processor
IQ80321 and IQ80332 Comparisons
IQ80321 and IQ80332 Comparisons A
This appendix provides a brief description for differenc es between IQ80332 and IQ80321. Pl ea se
also refer to application note: Inte l
®
80321 Sof tware Conversion t o the Intel® 80332 I/ O Processor
Application Note.
®
Table 4 2 . Intel
IQ80321 Evaluation Platform Board and Intel® IQ80332 I/O processor
evaluation platform board Comparisons
®
Intel
Features
I/O Processor 80332 Intel
Core/Microprocessor
Technology
Memory Technology DDRII 400 MHz SDRAM DIMM PC1600 DDR SDRAM (100 MHz Clock)
Form Factor
PC/Server/Backplane
Connection
Expansion Card Slot
PCI/PCI-X Bridge
Interrupt Routing
Timers
Local/Peripheral Bus
Flash Memory
Serial Debug Port Two UARTs integrated within the 80332.
Network Debug Port Intel® 82545EM GbE on the 100 MHz PCI-X bus Intel® 82544 GbE on the PCI-X bus
Rotary Switch Same Same
LED HEX Display Same Same
JTAG 20-PIN ARM Compliant 20-PIN ARM Compliant
Logic Analyzer Connection Through PCI-X or PCI Express Various Mictors
Intel XScale® microarchitecture Intel XScale® microarchitecture
PC board that attaches to a PC/Server/Backplane
by a PCI Express slot – Two PCI-X Expansion Slot
PCI Express
One PCI-X 100 MHz/64-bits
One PCI-X 2.0 266 MHz/64-bit
PCI-X to PCI-X Bridge integrated with the
IQ80332l
External interrupts are routed through the XINT
pins on the 80332. Please see Tab l e 9 for more
details.
Internal to 80332 – Refer to Intel
Processor Developer ’s Manual
66 MHz multiplexed bus with two chip-enables,
Synch/Asynchronous (80332 operates in 66 MHz
Asynchronous mode) – Refer to PBI section in
Intel
8-bit or 16-bit, 8 MB accessed through Peripheral
Bus with chip-enable 0 (PCE0)
IQ80332 I/O Processor Evaluation
Platform Board
®
80332 I /O
®
80332 I/O Processor Developer’s Ma nual
®
Intel
IQ80321 Evaluation Platform Board
®
80321 I/O Processor
Extended PC board that attaches to a
PC/Server/Backplane – One PCI-X Expansion Slot
PCI-X 133 MHz/64-Bits or
PCI 66 MHz/64 Bits
One PCI-X 133 MHz/64-bit
IBM PCI-X Bridge
Reference: IBM 133 PCI-X Bridge
http://www.chips.ibm.com/
External interrupts are routed through the XINT
pins on the 80321. They include INTA, INTB form
PCI-X expansion slot, INTA from 82544 GBE, and
UART interrupt – Steering and Status registers are
in 80321 – see Intel
Developer’s Manual
Internal to the 80321 - please refer to the Intel®
80321 I/O Processor Developer’s Manual
2-bit/33-100MHz multiplexed bus with six
chip-enables, Synch/Asynchronous (IQ80321
operates in 33 MHz Asynchronous mode) –
Refer to PBI section in the IIntel
Processor Developer’s Manual.
16-bit, 8 MB accessed through Peripheral Bus
with chip-enable 0 (PCE0))
One UART on the Peripheral bus – 16C550
device
®
80321 I /O Processor
®
80321 I/O
Evaluation Platform Board Manual 51
Intel® IQ80332 I/O Processor
IQ80321 and IQ80332 Com pariso ns
This Page Left Intentionally Blank
52 Evaluation Platform Board Manual
Intel® IQ80332 I/O Processor
Getting Started and Debugge r
Getting Started and Debugger B
B.1 Introduction
This appendix pertains to Code|Lab version 2.3 and later which uses Microsoft's Visual Studio .NET.
For Co de|Lab version 2. 2 and ea rlier, refer t o appendix B.
For more detailed information on JT AG and the 80332, please see the Intel
JTAG Support White Paper.
B.1.1 Purpose
The purpose of this appendix is to help the user setup and become familiar with the IQ80 332
(IQ80332) and other related hardware and software. This appendix steps the user through an example
program using:
• Code|Lab EDE • Code|Lab EDE debugger • Macraigor* Raven* JTAG
This programming also includes:
• software setup • compiling • linking • debugging example code
The user tours the major features of the debugger and explores some of the basics of debugging. By
the end of this exercise, the user has been given a general understanding of the ATI* development
tools and can begin working on new applications.
B.1.2 Necessary Hardware and Software
This example uses the ATI Code|Lab plug-in for Microsoft* Visual Studio, the GNU* Pro compiler,
the Macraigor Raven JTAG connector, and the 80332.
B.1.3 Related Documents
®
80332 I/O Processor
Table 43. Related Documents
®
80332 I/O Processor Devel oper’s Manu al 273517
Intel
®
80200 Processor based on Intel® XScale™ Microarchitecture Developer’s Manual 273411
Intel
Hot-Debug for Intel
ARM Assemblers Guide (http://www.arm.com/support/574FK U/$File/ADS_AssemblerGuide_B.pdf
ADS Debug Target Guide (http://www.arm.com/support/574FWT/$File/ADS_DebugTargetGuide_D.pdf
Code|Lab Debug for ARM
a. This document installs to C:\Ati\docs\codelab debug.pdf.
®
XScale™ Core Debug White Paper 273539
a
Many of these documents load as part of ATI Code|Lab install (Start/Programs/ Accelerated
Technolog y/Documenta tion). This menu conta ins both the ARM* ADS and Code|Lab documents.
Evaluation Platform Board Manual 53
Document Title Document #
)
)
Intel® IQ80332 I/O Processor
Getting Started and Debugger
B.1.4 Related Web Sites
• Macraigor: http://www.ocdemon.net/
• http://developer.intel.com/design/intelxscale/dev_tools/021022/index.htm
• http://developer.intel.com/design/iio/
• http://developer.intel.com/design/iio/papers/273961.htm
54 Evaluation Platform Board Manual
B.2 Setup
r
B.2.1 Hardware Setup
Use Figure 14 and the rest of the Intel® 80332 I/O Processor Evaluation Platform Board Manual, to
set up the hardware.
• Connect the Raven to the host via the parallel port and to the evalua tion board via the 20-pin
JTAG connector.
Note: The parallel port must be configured to EPP mode for the Macraigor Raven to work properly.
The parallel port setting can be changed in the BIOS setup program or in Control Panel. More
information on the Raven can be found at the Macraigor web site. Test software for the Raven is free
and available for download at:
http://www.ocdemon.net/Merchant2/merchant.mv?Screen=CTGY&Store_Code=MTS&Category_C
ode=pinouts.
• Connect a serial cable from the evaluation board to the host.
Note: The serial cable co n nects to the evaluati o n bo ard with an RJ11 co n n ector and connects to the host
computer seria l p o r t via an RJ11 to DB9F adaptor. The serial po r t configuration is covered in the
configuration section below.
Intel® IQ80332 I/O Processor
Getting Started and Debugge r
• The 80332 plugs into a bus master PCI Express slot on the backplane or platform.
Figure 14. Intel
®
80332 I/O Processor Hardware Setup Flow Chart
Host
Serial Cable
JTAG
Evaluation Board
Backplane or PCI-X Platform
Parallel Port Cable
20-Pin JTAG Connecto
Evaluation Platform Board Manual 55
Intel® IQ80332 I/O Processor
Getting Started and Debugger
B.2.2 Software Setup
ATI Code|Lab is a plug-in to Microsoft V isual S tudio .NET, therefore Micr osoft V i sual Stu dio .NET must
already be loaded on t he system. To load A TI Code|Lab , run set up.ex e under th e prog ram direc tory.
Note: Do not install over an old version of ATI Code|Lab. When necessary, uninstall Code|Lab with
Add/Remove program s under the Control Panel be fore reinstalling.
T o view the soft copies of document, Adobe Acrobat Reader is needed. The latest version can be
downloaded at (http://www.adobe.com
Figure 15. Software Flow Diagram
Debug Monitor Code
Resides in the Flash
).
ATI Code| La b
Macraigor DLL
Application Code
Loads into Memory
Evaluation Board
MemoryFlash
56 Evaluation Platform Board Manual
B.3 New Project Setup
B.3.1 Creating a New Project
1. Launch Code|Lab EDE for .NET.
2. On th e Star t Page, select “New Pro j ec t”.
a. The “New Projects” window appears.
b. Select “Code|L ab Projects” under Proje ct Types and name the project “Project80332” in
the name field.
Note: The directory “Project80332” is created under the path specified in the Location box.
c. Click OK.
3. In the Code|Lab EDE Project Wizard Window:
a. Select “RedHat GNU Tools for XS cale” under “Build Toolset”.
b. Select 80332 unde r “Project Template”.
c. Select “Application” under “Project Type”.
Intel® IQ80332 I/O Processor
Getting Started and Debugge r
d. Click “Finish”.
4. Close the “S tart Page” by clicking on the X in the top right corner of the S tart Page window.
5. The new project is now in th e “Solution Explorer” window. When this window is not open,
open it by “View, Solution Explorer”.
6. Right click on “Project80332” and select “S ave Project80332”.
7. From h
These files can be placed in any directory on the hard drive.
8. Add the newly downloaded files to the project:
ttp://developer.intel.com/design/iio/swsup/Tester1LED.htm, download the following
zip file (…/Tester1LED) from the Software Support s ecti on, cont aining the exampl e code file s
to the newly created project folder:
Tester1LED.zip
blink.c
blink.h
led.c
led.h
a. In the “Solution Explorer” window, right click on “Pr oject80332” and select “Add, Add
Existing Item”.
b. In the “Add Exi sting Item” wi ndow, use the drop-down menu under “Look In” to find th e
four files liste d in st ep 7 on the hard drive. Select all four files and click “open”. Th e
“Solution Explorer” window now shows these files under “Project80332”.
Evaluation Platform Board Manual 57
Intel® IQ80332 I/O Processor
Getting Started and Debugger
B.3.2 Configuration
Examine the main menu of Code|Lab EDE for .NET.
• File • Project • code| l ab EDE • Tools • Help
• Edit • View • Build, Debug • Window
Since Code|Lab is a plug-in to Visual Studio, some of these menu items are Visual Studio and some
are specific to Code|Lab. Click on any of these menu items and the drop-down menu displays the
subordinate menu items. Many of these items have defined tool bar symbols, function keys, and
keyboard patterns as alternatives.
Note: Projects can be built under the “code|l ab EDE” menu or unde r the “build” menu. Always use the
“code|lab EDE ” menu to perform Code|Lab project builds. Builds under the “build” menu invoke
the Visual Studio C compiler.
1. On the main menu, sele ct “code|lab EDE, Configuration” .
2. When the “code|la b EDE Configuration” window appears, click on ea ch of the words in the
left box. Notice that the rest of the window changes when you cl ick on different parts of the
menu tree. This is a typical feature of Code|La b EDE for .NET.
3. Click on Toolsets.
4. Click on the drop-down arrow and select “RedHat GNU Tools for XScale”. The build tool
paths now appear in the box and must be modified as sta ted below in bold. Note that the
assembler and the linker are invoked by GCC.
a. “Compiler path: $(ToolDir)\BIN\XSCALE-ELF-GCC.EXE”.
b. “Assembler pa th: $(ToolDir)\BIN\XSCALE-ELF-GCC.EXE”.
c. “Linker path: $(ToolDir)\BIN\XSCALE-ELF-GCC.EXE”.
d. “Librarian path: $(ToolDir)\BIN\XSCALE-ELF-AR.EXE”.
5. In the left box, cl ick on “Debugging, Genera l”. When the checkboxes ar e ava ilable in your
version, set all four debug options to “false”.
6. Click “Apply” and click “OK”.
7. On the main menu, click “code|lab EDE, Pr oject Settings”.
8. When the “c ode |l ab P roj ec t Set ti ng s” win d ow app ea rs, cl ic k on “C /C+ +/ Asse mb ler ” in t he l eft
box. Use the dro p - do wn ar r o w to se le ct “ C com p i le r ” f or “B u il d Tool”.
9. Edit the command line box at the bottom so that it contains the following:
-v -Wall -specs=redboot.specs -gdwarf-2 -O0 -c -mcpu=xscale $(InputRelPath) -o
$(OutDir)\$(InputName)$(OutputExt)
10. Use the drop-down arrow to sele ct “As semble r” for “Build Tool. Edit the command line box at
the bottom so that it contains the following:
-v -specs=redboot.specs -o $(OutDir)\$(InputName)$(OutputExt) $(InputRelPath)
11. In the left box, click on “Linker”. Edit the command line box at the bottom so that it contains
the following:
-v -specs=redboot.specs -o $(OutDir)\$(ProjectName).elf $(ObjectFiles) $(Libraries)
12. Click “Apply” and then click “OK”.
13. In the “Solution Explorer” window, right click “Project80332” and select “Save
Project80332”.
58 Evaluation Platform Board Manual
B.4 Flashing with JTAG
B.4.1 Overview
Code|Lab and Raven are capable of reading from, writing to, and erasing the contents of the Flash on
the evaluation board. The board comes with RedBoot loaded in the Flash. RedBoot is the RedHat
debug monitor which initializes the board and has some debug and diagnostic functions. It is capable
of serial communication with the console of a debug program or with Microsoft HyperTerminal, and
it prepares the board for accepting an application program.
Code|Lab invokes a Flash programmer written by Macraigor. More information on the Flash
programmer is located at:
h
ttp://www.ocdemon.net/Merchant2/merchant.mv?Screen=CTGY&Store_Code=MTS&Categ
ory_C ode=Software.
This Flash programmer only supports certain file formats: Intel Hex, Motorola srec and standard elf
(executable and linking format). RedBoot.s19 and RedBoot.srec are both srec files. TBD.i32 is an
ARM BootMonitor Intel Hex file. BootMonitor is an ARM version of a debug monitor, which is
similar but not identical to RedBoot.
Intel® IQ80332 I/O Processor
Getting Started and Debugge r
Macraigor offers conversion tools to convert existing file types to a supported file type. These
conversion tools are located at:
C:\ATI\codelab\codelab Debug\Macraigor\Flash Programmer
The ReadMe.txt file describes the conversions tools. BinToS19.exe converts binary files to srec files
and MakeIntelHex.exe converts a.out files to Intel Hex files. When using the BinToS19.exe
conversion tool, use 0x0 for the starting address. For example, at the CMD prompt in the directory
where BinToS19.exe is located, the command line looks like this:
C:\ATI\codelab\cod elab Debug\Macraigor\Flash Programmer> bintos19
C:\temp\redboot_ROM.bin 0x0 c:\temp\redboot_ROM.s19
Evaluation Platform Board Manual 59
Intel® IQ80332 I/O Processor
Getting Started and Debugger
B.4.2 Using Flash Programmer
Note: The parallel port must be se t to EPP mod e or the Macraigor Raven does not work pr operly.
Download the RedBoot executable files from the following location:
http://developer.intel.com/design/intelxscale/dev_tools/021022/index.htm
for the IQ80332.
1. Double click on the “Code|Lab Debug” icon on the desktop.
The Connection Window appears.
2. Select Macraigor JTAG Connect
a. Click Setup.
3. Select “ARM XScale”, co rrect LP T port , and “Raven” (do not press OK).
4. Click Additional Options…, chec k Ena ble Option, then press Configure
The Console Options windows now appears.
5. Console Port: (Set appropriately)
Baud Rate: 115200
Data Bits: 8
Parity: None
Stop Bits: 1
Then Press OK, OK, OK (this returns to the Connect window).
RedBo ot D ebug Moni tor
6. Now press Connect.
Assembly code now visible.
7. Select “Memory/Flash…”
The OCDemon Flash Memory Programmer window appears.
8. The Flash programmer needs a file which is architecture specific, in this case. In the Flash
programmer window, select “File/Open”, then choose the file “Xsc ale TBD.ocd” at:
“C:\M G C\Embedded\co delab\ co delab Debug\Ma craigo r\”.
9. Click the Pro gram button.
10. Click Browse and “Files of type:” All Files, then choose the “redboot_ROM.srec” file
(downloaded and unc ompressed from developer. com ).
11. Check box “Erase Target Flash Sector(s) Before Programming”.
12. Click Program.
The Flash now programs and verifies; cli ck Close when 100% complete.
13. Cycle power to the board to see that the LEDs on the board sequence “8.8.”, “A5”, “A6”,
“S.L”, then “A1”.
This is the normal LED sequence of RedBoot. The board may need to be reset more than once.
Explore the other features of the Flash programming window. The contents of the Flash can be
erased, copied to a file on the host, and verified against a file on the host.
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Getting Started and Debugge r
B.5 Debugging Out of Flash
JTAG debuggers can be used on two levels; with or without the source code. When the Flash is
programmed, the debugger can monitor the executable code, halt it, step through it, and monitor the
memory and registers. The executable code is disassembled so that the assembly code can be
examined.
Debugging with source code allows the user to examine the C code that is being executed. This
requires that the source code is available and linked by the debugger to the executable code that is
running on the evaluation board.
B.6 Building an Executable File From Example Code
1. Launch Code|La b EDE and open “Project80332” .
2. Select “code|lab EDE, Rebuild Project”.
Note: A project can have more than one solution, but in this exa mple, there is only one solution for the
project, so there is no difference between “Build Project” and “Build Solution” in this example.
Note: Rebuild cleans and bu ild s. Cl ean de letes the old . o file s in t he p roject an d build c ompil es, lin ks, a nd
produces the exec utable files.
3. When there are errors, careful ly go back through Section B.3.2, “Configuration”.
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B.7 Running the Code|Lab Debugger
This section is provided to get the system up and running in the Code|Lab Debug environment, but it
is not intended as a full-functional tutorial. Please refer to the ATI Code|Lab Debug Reference
Manual for more detailed information.
B.7.1 Launching and Configuring Debugger
1. In EDE, click on the icon that looks like a red bug. The “Connect” window appears.
2. When not configured from S ection B.4.2, “Using Flash Programmer”, go to Section B.4.2 and
perform steps 2-5.
3. Press Connect to enter debug mode.
a. The Code|Lab Debug environment appears with the Assembly window ope n.
Note: Mouseovers are available for most of the toolbar icons. (L eave the mouse over the debug icons
across the top on the toolbar to see a brief explanation of each.)
4. Click on the go icon and let RedBoot boot (takes a minute) until the RedBoot prompt
“RedBoot>” appears in the Console window (cl ick the Console tab at the bottom of the Deb ug
window to view the Console window).
5. From the console window:
a. type “diag”.
b. hit “Enter”.
The RedBoot Diagnostic function is invoked.
Try out a few of the tests as desired.
6. Close the Debugger and E DE environment.
7. Reset the board (cycle power).
B.7.2 Manually Loading and Executing an Application Program
1. Launch the Code| La b Debug En vironment from the deskto p icon.
2. Ensure “File…/Program Load Options/Loa d Exe cutable and Symbols” is che cked.
3. file, pro gram load options, lo ad executable and symb ols.
a. Select “file, open program, browse”.
b. go find c:\<RedBoot downloaded File s>…\Test1LED\O\Test1LED.elf.
4. Hit Go (80, 3, 32, and 21 cycle on the LEDs).
5. Cycle power on the board.
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B.7.3 Displaying Source Code
1. Launch the Code|Lab EDE Debugger a nd open the “Tester1LED” ELF program.
Note: Use th e Fil e/ Recent Pr o g ra ms menu for qui c k ac cess.
2. Select the “Fil es” view in the lower tab of the WorkSpace window.
3. Bring up “blink.c ” and “led.c” source code by doub le-clicking each filename.
4. Use the “Windows” Menu to arrange the windows , or m aximize, minimize, and resize
manually as desired.
5. Press the “Mixed” tab at the bottom of the “blink.c” window. Notice that the assembly along
with ea ch C statement.
6. Press the “Source” tab to revert back to C code only.
B.7.4 Using Breakpoints
Note the small gray circles on the sidebar beside each line of source code. Single-click any of these
gray circles and a red dot appears. The red dot represents a break point. Single-click the red dot to
remove it, or click the “Remove all breakpoints” icon.
Intel® IQ80332 I/O Processor
Getting Started and Debugge r
Place a breakpoint on the following lines of code in “blink.c”:
displayLED(leds[8],leds[0]); /* LED display '80' */
displayLED(leds[0],leds[3]); /* LED display '03' */
displayLED(leds[3],leds[2]); /* LED Display '32' */
displayLED(leds[2],leds[1]); /* LED display '21' */
displayLED(leds[16],leds[ 16]); /* LED display ' ' */
1. Click the “Go” icon.
The yellow arrow stops at th e firs t break point and the HEX displa y does not change.
2. Click the “Go” icon again.
The last instruction has now been executed and an “80” is displa yed.
3. Continue on in th is fashion, watch ing the lines execut e only as they are called, while the
yellow arrow shows exactly what line is up next in execution.
4. Click the “Remove all breakpoints” icon.
5. Press “Go” again and notice that the program loop is infinite.
6. Press the “Halt” icon to stop execution.
7. Close the debugger and cycle power to the board.
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B.7.5 Stepping Through the Code
The “led.c” file contains a function that is called from code in “blink.c”. This exercise steps through
the code and utilizes a few of the most common step tools.
1. Launch the debugger, ope n Tester1LED, and open the “blink.c” and “led.c” files.
2. Set a breakpoint on the following line in “blink.c”: displayLED(leds[8],leds[0]); /* LED
display '80'*/
3. Press Go.
Program execution sit on the first breakpoint.
4. Press the “S tep Over” icon and notice how execution jumps ove r the function call to the next
line of execution.
5. Now try the “St ep Into” icon and note that the pointer has now jumped into the function
“disp la yLED”, w h ich is loc at e d in the “led . c” file.
6. Press the “Step Over” icon again and watch the pointer advance within the function to the next
executable line.
7. Now press the “Step Out of” icon and notice how execution leaves the called function and
waits on the next exe cutable line in “blink.c”.
8. The an i mate icon can also be used to pr o v id e a “Step Into” effe ct th at oc cu r s at a s p ec if i ed
time interval (default of 1 second). This can be modified in the “Settings” section of the
“V iew/Options” menu. Experiment with this as des ired.
9. Use Halt to stop the animate mode before the next breakpoint.
10. Also note that Go can be pressed at any time to continue execution from the current line to the
next breakpoi nt or program end.
B.7.6 Setting Code|Lab Debug Options
Besides the Animate debug time interval setting briefly mentioned in step 8 of the previous exercise,
many useful options can be accessed from the “View/Options” menu.
1. Experiment here by bringing up the Registers window (click and change the view options
between binary and decimal; for example).
Hint: Settings tab, Interface, Radix
2. Also try bringing up the Memory window (click) and change the number of columns between
4 and 2 and notice the changes.
Hint: Settings tab, Memory Window, Number of Columns
Note: Press window icons a second time to remove them from view.
Again, there are many features of the debug environment not discussed here. Please see the Code|Lab
manuals for a full description of debug features.
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B.8 Exploring the Code|Lab Debug Windows
This section discusses some basics of the debug environment. Some of these windows and concepts
have been dealt with during previous exercises in this manual. However, many new windows are also
discussed and basic interaction exercises are given. Begin this section by launching the Code|Lab
Debugger environment and connection via the JTAG port.
B.8.1 Toolbar Icons
Placing the mouse arrow on any icon displays the text function of that icon. When the icon launches a
special window (i.e., Watch, Memory, Call Trace, etc.), the icon brings that window up on the first
click and remove s the w indow when pre ssed again.
B.8.2 Workspace Window
Click on the W orkspace icon. Click on the Files and Browse tabs and examine the contents. Note that
there are more files than the original source files. When you double-click on the source files, blink.c
and led.c, the source window appears for that file. When you double-click on an included file, the
debugger is not be able to find the file.
B.8.3 Source Code
The source code windows are opened by double-clicking on the source files in the Workspace
window under the files tab. Viewing of mixed Assembly and C code or C code only, is controlled by
the tabs at the bottom of these windows.
B.8.4 4 Debug and Console Windows
The Debug window displays debugger activity messages while the Debug tab is displayed. Script
commands can be entered manually at the top of the window. Serial output is displayed while the
Console tab is active. Commands for the running application can be entered at the top of this window.
B.8.5 Memory Window
Click on the Memory window icon. Change the address at the top of the window to 0xffffe100 and
click on the green arrow to the right (or press Enter). This changes the viewable starting address of the
Memory window. The A TU header begins at 0xffffe100 and contains a known number (8086). Also
look at the base and limit registers for the memory and Flash devices, at 0xffffe508 and ffffe688
respectively, since they were initialized by RedBoot. Use the Intel
Manual, to see what the values mean.
Note: The tabs at the bottom allow the selection of two memory regions to observe.
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80332 I/O Processor Developer’ s
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Getting Started and Debugger
B.8.6 Registers Window
Close all the active windows, then bring up the Registers window. Resize the this window and its
columns to get a good view of all the registers. Notice that there is a Flags tab at the bottom of this
window. This is useful for seeing the system flags defined by the CPSR. These are important
especially during conditional code execution (see the ARM Architecture Reference Manual for more
detail), but the flags are not changed during this exercise.
Click on the registers tab of the registers window and click the Animate icon. Notice how the register
values change during program execution (red values are those that were modified during the last
execution cycle). Click the Halt icon at any time, then try right clicking a register row and selecting
“Go To Memory”. Notice how the Memory window is brought up and the address contained in that
register is shown.
Click on the registers tab. Red means that the register value changed since the last fetch as opposed to
black which represents no change. Register values can be manually changed in this window .
B.8.7 Watch Window
It is often useful during the debugging process to keep an eye on a few select program variables.
1. Open the Tester1LED Progra m and bring up “led.c”.
2. Click the “Watch” icon to bring up the Watch window.
3. Now add the “left” and “ri ght” variables from “led. c” to the watch window.
Note: For each variable double click the variabl e name to highlight it, then drag it to the watch window.
4. Click the “Anim ate” icon and obser ve the changes.
Note: When focus goes back to the Assembly window during this process , try putting a breakpoint in
led.c, then hit Go.
B.8.8 Variables Window
The Variables behaves very similarly to the Watch window, except that it shows all active variables.
Bring up the V ar iables window, click Animate, and watch the changes.
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B.9 Debugging Basics
B.9.1 Overview
Debuggers allow developers to interrogate application code by allowing program flow control, data
observation, and data manipulation. The flow control functions include the ability to single-step
through the code, step into functions, step over functions, and run to breakpoint (hardware or
software). The data observation and manipulation functions include access to memory , registers, and
variables. The combination of the flow control and data functions allows the developer to debug
problems as they occur or to validate the application code. As the size of an application grows, the
need to be able to narrow down the cause of a problem to a few lines of code is imperative.
Debuggers have a finite set of capabilities and limitations. Debuggers can give insight that is difficult
to obtain without them, but they can fail when they are not used within the limits of their
functionality. They are intrusive by definition. They are software programs that interact with software
monitors or hardware (JTAG) to control a target program. Ultimately, the debugger works best when
the developer understands what it can and can not do and uses it within those constraints.
B.9.2 Hardware and Software Breakpoints
The following section provides a brief overview of breakpoints. See the Intel® 80332 I/O Pro c e ssor
Developer’s Manual, for more detailed information.
B.9.2.1 Software Breakpoints
Software breakpoints are setup and utilized via debugger utilities (such as Code|Lab). The abilities of
softw are breakpoints were seen i n Section B.7 of this Guide. Program execution can be halted at a
particular line of code, stepped through, and executed again to the next breakpoint via debuggers.
During this process, register values, memory address contents, variable contents, and many other
useful pieces of information can be monitored.
B.9.2.2 Hardware Breakpoints
Hardware breakpoints step and breakpoint in code in either ROM or RAM without altering the code,
stacks, or other target information. Hardware breakpoints handle difficult issues, by providing the
ability to set the processor conditions that cause the program to halt. Use hardware breakpoints to
locate problems such as reentrance, obscure timing, etc.
The 80332 contains two instruction breakpoint address registers (IBCR0 and IBCR1), one data
breakpoint address register (DBR0), one configurable data mask/address register (DBR1), and one
data breakpoint control register (DBCON). The 80332 also supports a 256 entry, trace buffer, that
records program execution information. The registers to control the trace buffer are located in CP14.
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Getting Started and Debugger
B.9.3 C.9.3 Exceptions/Trapping
A debug exception causes the processor to re-direct execution to a debug event handling routine. The
®
80200 processor debug architecture defines the following debug exceptions:
Intel
• instruction breakpoint
• data breakpoint
• software breakpoint
• external debug break
• exception vector trap
• trace-buffer full break
When a debug exception occurs, the processor actions depend on whether the debug unit is
configured for Halt mode or Monitor mode.
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