INTEL P30 DATA SHEET

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Intel Str ataFlash® Embedded Memory (P30)

1-Gbit P30 Family

Product Features

Datasheet

■ High performance

— 85/88 ns initial access — 40 MHz with zero wait states, 20 ns clock-to-

data output synchronous-burst read mode — 25 ns asynchronous-page read mode — 4-, 8-, 16-, and contin uous-word burst mo de — Buffered Enhanced Factory Programm ing

(BEFP) at 5 µs/byte (Typ) — 1.8 V buffered program ming at 7 µs/b yte (Typ)

■ Architecture

— Multi-Level Cell Technology: Highest Density

at Lowest Cost — Asymmetrically-blocked archit ecture — Four 32-KByte parameter block s: top or

bottom configuration — 128-KByte main blocks

■ Voltage and Power

—V

(core) voltage: 1.7 V – 2.0 V

—V — Standby current: 55 µA (Typ) for 256-Mbit — 4-Word synchronous read current:

■ Quality and Reliability

— Operating temperature: –40 °C to +85 °C — Minimum 100,000 erase cycles per block

— ETOX™ VIII process technology (130 nm )

The Intel StrataFlash® Embedded Memory (P30) product is the latest generation of Intel StrataFlash

(I/O) voltage: 1.7 V – 3. 6 V

CCQ

13 mA (Typ) at 40 MHz

• 1-Gbit in SCSP is –30 °C to +85 °C

memory devices. Offered in 64-Mbit up through 1-Gbit densities, the P30 device

■ Security

— One-Time Programmable Registers:

• 64 unique factory device identifier bits

• 64 user-programmable OTP bits

• Additional 2048 user-programmable OTP bits

— Selectable OTP Space in Main Array:

• 4x32KB parameter blocks + 3x128KB main

blocks (top or bottom configurati on) — Absolute write protection: V — Power-transition erase/progra m lockout — Individual zero-latency blo ck locking — Individual block lock-down

■ Software

— 20 µs (Typ) program suspend — 20 µs (Typ) erase suspend

—Intel — Basic Command Set and Exte nded Command

— Common Flash Interface cap able

■ Density and Packaging

— 64/128/256-Mbit densities in 56 -Lead TSOP

— 64/128/256/512-Mbit den sities in 64-Ball

— 64/128/256/512-Mbit and 1-Gbit densities in — 16-bit wide data bus

Flash Data Integrator optimized

Set compatible

package

Intel

® Easy BGA package

Intel® QUAD+ SCSP

= V

brings reliable, two-bit-per-cell storage technology to the embedded flash market segment. Benefits include more density in less space, high-speed interface, lowest cost-per-bit NOR device, and support for code and data storage. Features include high-performance synchronousburst read mode, fast asynchronous access times, low power, flexible security options, and three industry standard package choices.

The P30 product family is manufactured using Intel

130 nm ETOX™ VIII process technology.

Order Number: 306666, Revision: 001

April 2005

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHA TSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING T O F ITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not

finalize a design with this information. StrataFlash® Embedded Memory (P30) Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing

your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet 2 Order Number: 306666, Revision: 001

1-Gbit P30 Family

Contents

1.0 Introduction ...............................................................................................................................7

1.1 Nomenclature .......................................................................................................................7

1.2 Acronyms..............................................................................................................................7

1.3 Conventions..........................................................................................................................8

2.0 Functional Overview ..............................................................................................................9

3.0 Package Information............................................................................................................10

3.1 56-Lead TSOP Package.....................................................................................................10

3.2 64-Ball Easy BGA Package................................................................................................12

3.3 QUAD+ SCSP Packages....................................................................................................13

4.0 Ballout and Signal Descriptions......................................................................................17

4.1 Signal Ballout......................................................................................................................17

4.2 Signal Descriptions.............................................................................................................20

4.3 SCSP Configurations.......................................................... ........... .......... ........... ................22

4.4 Memory Maps.....................................................................................................................24

5.0 Maximum Ratings and Operating Conditio ns ...........................................................29

5.1 Absolute Maximum Ratings................................................................................................29

5.2 Operating Conditions..........................................................................................................30

6.0 Electrical Specifications.....................................................................................................31

6.1 DC Current Characteristics.................................................................................................31

6.2 DC Voltage Characteristics.................................................................................................32

7.0 AC Characteristics................................................................................................................33

7.1 AC Test Conditions........................................................................ .......... ........... ................33

7.2 Capacitance........................................................................................................................34

7.3 AC Read Specifications................................. .....................................................................35

7.4 AC Write Specifications ................................................................. .......... ...........................41

7.5 Program and Erase Characteristics....................................................................................45

8.0 Power and Reset Specifications .....................................................................................46

8.1 Power Up and Down...........................................................................................................46

8.2 Reset Specifications...........................................................................................................46

8.3 Power Supply Decoupling...................................................................................................47

9.0 Device Operations.................................................................................................................48

9.1 Bus Operations...................................................................................................................48

9.1.1 Reads ....................................................................................................................48

9.1.2 Writes.....................................................................................................................49

9.1.3 Output Disable.......................................................................................................49

9.1.4 Standby..................................................................................................................49

9.1.5 Reset .....................................................................................................................49

9.2 Device Commands .............................................................................................................50

9.3 Command Definitions .........................................................................................................51

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 3

1-Gbit P30 Family

10.0 Read Operations....................................................................................................................53

10.1 Asynchronous Page-Mode Read........................................................................................53

10.2 Synchronous Burst-Mode Read..........................................................................................53

10.3 Read Configuration Register ..............................................................................................54

10.3.1 Read Mode.................................................... ........................................................55

10.3.2 Latency Count........................................................................................................55

10.3.3 WAIT Polarity.........................................................................................................57

10.3.4 Data Hold...............................................................................................................58

10.3.5 WAIT Delay............................................................................................................ 59

10.3.6 Burst Sequence.....................................................................................................59

10.3.7 Clock Edge ............................................................................................................59

10.3.8 Burst Wrap .............................................................................................................59

10.3.9 Burst Length ..........................................................................................................60

11.0 Programming Operations .................................................................................................. 61

11.1 Word Programming.............................................................................................................61

11.1.1 Factory Word Programming...................................................................................62

11.2 Buffered Programming........................................................................................................62

11.3 Buffered Enhanced Factory Programming.........................................................................63

11.3.1 BEFP Requirements and Considerations..............................................................64

11.3.2 BEFP Setup Phase................................................................................................64

11.3.3 BEFP Program/Verify Phase.................................................................................64

11.3.4 BEFP Exit Phase...................................................................................................65

11.4 Program Suspend............................................................................. .......... ........... .............65

11.5 Program Resume................................................................................................................66

11.6 Program Protection..................................................................................... ........... .............66

12.0 Erase Operations...................................................................................................................67

12.1 Block Erase.........................................................................................................................67

12.2 Erase Suspend...................................................................................................................67

12.3 Erase Resume....................................................................................................................68

12.4 Erase Protection.................................................................................................................68

13.0 Security Modes.......................................................................................................................69

13.1 Block Locking......................................................................................................................69

13.1.1 Lock Block .............................................................................................................69

13.1.2 Unlock Block..........................................................................................................69

13.1.3 Lock-Down Block...................................................................................................69

13.1.4 Block Lock Status..................................................................................................70

13.1.5 Block Locking During Suspend..............................................................................70

13.2 Selectable One-Time Programmable Blocks......................................................................71

13.3 Protection Registers ...........................................................................................................72

13.3.1 Reading the Protection Registers..........................................................................73

13.3.2 Programming the Protection Registers..................................................................73

13.3.3 Locking the Protection Registers...........................................................................74

14.0 Special Read States .............................................................................................................75

14.1 Read Status Register.................................................. ..................................................... ...75

14.1.1 Clear Status Register.............................................................................................76

14.2 Read Device Identifier ...................................................................... .......... ........... .............76

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet 4 Order Number: 306666, Revision: 001

1-Gbit P30 Family

14.3 CFI Query...........................................................................................................................77

Appendix A Write State Machine..........................................................................................78

Appendix B Flowcharts............................................................................................................85

Appendix C Common Flash Interface ................................................................................93

Appendix D Additional Information...................................................................................100

Appendix E Ordering Information for Discrete Products ........................................101

Appendix F Ordering Information for SCSP Products..............................................102

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 5

1-Gbit P30 Family

Revision History

Revision Date Revision Descriptio n

April 2005 -001 Initial Release

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet 6 Order Number: 306666, Revision: 001

1.0 Introduction

This document provides information about the Intel StrataFlash® Embedded Memory (P30) device and describes its features, operation, and specifications.

1.1 Nomenclature

1.8 V : VCC (core) voltage range of 1.7 V – 2.0 V

1-Gbit P30 Family

3.0 V : V

9.0 V : V

Block : A group of bits, bytes,1-Gbit P30 Family or words within the

Main block : An array block that is usually used to store code and/or data.

Parameter block : An array block that is usually used to store frequently changing

Top parameter device : A device with its parameter blocks located at the highest

Bottom parameter device : A device with its parameter blocks located at the lowest

1.2 Acronyms

(I/O) voltage range of 1.7 V – 3.6 V

CCQ

voltage range of 8.5 V – 9.5 V

flash memory array that erase simultaneously when the Erase command is issued to the device. The 1-Gbit P30 Family has two block sizes: 32-KByte and 128-KByte.

Main blocks are larger than parameter blocks.

data or small system parameters that traditionally would be stored in EEPROM.

physical address of its memory map.

BEFP : Buffer Enhanced Factory Programming CUI : Command User Interface MLC : Multi-Level Cell OTP : One-Time Programmable PLR : Protection Lock Register PR : Protection Register RCR : Read Configuration Register

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 7

1-Gbit P30 Family

RFU : Reserved for Future Use SR : Status Register WSM : Write State Machine

1.3 Conventions

VCC : Signal or voltage connection

: Signal or voltage level

0x : Hexadecimal number prefix 0b : Binary number prefix SR[4] : Denotes an individual register bit. A[15:0] : Denotes a group of similarly named signals, such as address

A5 : Denotes one element of a signal group membership, such as

or data bus.

an individual address bit.

Bit : Binary unit Byte : Eight bits Word : Two bytes, or sixteen bits Kbit : 1024 bits KByte : 1024 bytes KWord : 1024 words Mbit : 1,048,576 bits MByte : 1,048,576 bytes MWord : 1,048,576 words

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet 8 Order Number: 306666, Revision: 001

2.0 Functional Overview

This section provides an overview of the features and capabilities of the 1-Gbit P30 Family device. The P30 family provides density upgrades from 64-Mbit through 1-Gbit. This family of devices

provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage.

Upon initial power up or return from reset, the device defaults to asynchronous page-mode read. Configuring the Read Configuration Register enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides an easy CPU-to-flash memory synchronization.

In addition to the enhanced architecture and interface, the device incorporates technology that enables fast factory program and erase operations. Designed for low-voltage systems, the 1-Gbit P30 Family supports read operations with V

at 1.8 V or 9.0 V. Buffered Enhanced Factory Programming (BEFP) provides the fastest flash

array programming performance with V at 1.8 V, VCC and VPP can be tied together for a simple, ultra low power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when V

PPLK

1-Gbit P30 Family

at 1.8 V, and erase and program operations with

at 9.0 V, which increases factory throughput. With VPP

≤

A Command User Interface (CUI) is the interface between the system processor and all internal operations of the device. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase and program. A Status Register indicates erase or program completion and any errors that may have occurred.

An industry-standard command sequence invokes program and erase automation. Each erase operation erases one block. The Erase Suspend feature allows system software to pause an erase cycle to read or program data in another block. Program Suspend allows system software to pause programming to read other locations. Data is programmed in word increments (16 bits).

The 1-Gbit P30 Family’s protection register allows unique flash device identification that can be used to increase system security. The individual Block Lock feature provides zero-latency block locking and unlocking. In addition, the P30 device also has four pre-defined spaces in the main array that can be configured as One-Time Programmable (OTP).

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 9

1-Gbit P30 Family

3.0 Package Infor mat ion

3.1 56-Lead TSOP Package

Figure 1. TSOP Mechanical Specifications

Pin 1

See Notes 1 and 3

See Note 2

See Detail B

Seating Plane

See Detail A

Detail A

Detail B

Table 1. TSOP Package Dimensions (Sheet 1 of 2)

Product Information Sym

Package Height A - - 1.200 - - 0.047 Standoff A Package Body Thickness A Lead Width b 0.100 0.150 0.200 0.004 0.006 0.008 Lead Thickness c 0.100 0.150 0.200 0.004 0.006 0.008 Package Body Length D Package Body Width E 13.800 14.000 14.200 0.543 0.551 0.559 Lead Pitch e - 0.500 - - 0.0197 -

Millimeters Inches

Min Nom Max Min Nom Max

0.050 - - 0.002 - -

0.965 0.995 1.025 0.038 0.039 0.040

18.200 18.400 18.600 0.717 0.724 0.732

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet 10 Order Number: 306666, Revision: 001

Table 1. TSOP Package Dimensions (Sheet 2 of 2)

1-Gbit P30 Family

Product In f ormation Sym

Terminal Dimension D 19.800 20.00 20.200 0.780 0.787 0.795 Lead Tip Length L 0.500 0.600 0.700 0.020 0.024 0.028 Lead Count N - 56 - - 56 Lead Tip Angle ∅ 0° 3° 5° 0° 3° 5° Seating Plane Coplanarity Y - - 0.100 - - 0.004 Lead to Package Offset Z 0.150 0.250 0.350 0. 006 0.010 0. 014

Millimeters Inches

Min Nom Max Min Nom Max

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 11

1-Gbit P30 Family

3.2 64-Ball Easy BGA Package

Figure 2. Easy BGA Mechanical Specifications

Ball A1 Corner

Ball A1

87654321 A B

C D E F

G H

Top View - Ball side down Bottom View - Ball Side Up

87654321 A B C D

E F G H

Seating

Plane

Note: Drawi ng not to scale

Corner

Table 2. Easy BGA Package Dimensions

Product Informa tion

Package Height (64/128/256-Mbit) Package Height (512-Mbit) Ball Height (64/128/256-Mbit) Ball Height (512-Mbit) Package Body Thickness (64/128/256-Mbit) Package Body Thickness (512-Mbit) Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E

Symbol

A - - 1.200 - - 0.0472

A - - 1.300 - - 0.0512 A1 0.250 - - 0.0098 - A1 0.240 - - 0.0094 - A2 - 0.780 - - 0.0307 A2 - 0.910 - - 0.0358 -

b 0.330 0.430 0.530 0.0130 0.0169 0.0209

D 9.900 10.000 10.100 0.3898 0.3937 0.3976 1

E 12.900 13.000 13.100 0.5079 0.5118 0.5157 1 [e] - 1.000 - - 0.0394 -

N - 64 - - 64 -

Y - - 0.100 - - 0.0039 S1 1.400 1.500 1.600 0.0551 0.0591 0.0630 1 S2 2.900 3.000 3.100 0.1142 0.1181 0.1220 1

Note: Daisy Chain Evaluation Unit information is at Intel® Flash Memory Packaging Technology http://developer.intel.com/

design/flash/packtech.

Millimeters Inches

Min Nom Max Min Nom Max

Notes

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet 12 Order Number: 306666, Revision: 001

1-Gbit P30 Family

3.3 QUAD+ SCSP Packages

Figure 3. 64/128-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x10x1.2 mm)

A1 Index

Mark

B C D E F G

K L M

12345678

Top View - Ball

Down

12345678

A B C D

G H

L M

Bottom View - Ball Up

Draw ing not to s cale.

Dimensions Symb ol Min Nom Max Min N om Max

Millimeters Inches

Package Height A - - 1.200 - - 0.0472 Ball Height A Package Body Thickness A

0.200 - - 0.0079 - -

- 0.860 - - 0.0339 Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 Package Body Width D 9.900 10.000 10.100 0.3898 0.3937 0.3976 Package Body Length E 7.900 8.000 8.100 0.3110 0.3150 0.3189 Pitch e - 0.800 - - 0.0315 Ball (L ead) Count N - 8 8 - - 88 Seating Plane Coplanarity Y - - 0.100 - - 0.0039 Corner to Ball A1 Distance Along E S Corner to Ball A1 Distance Along D S

1.100 1.200 1.300 0.0433 0.0472 0.0512

0.500 0.600 0.700 0.0197 0.0236 0.0276

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 13

1-Gbit P30 Family

Figure 4. 256-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.0 mm)

A1 Index

Mark

A B

C D E F G H J

K L M

1234 5678

Top View - Ball Down

12345678

A B C D

G H

L M

Bottom View - Ball Up

D raw in g not t o sc ale.

Note: Dimensions A1, A2, and b are preliminary

Dimensions Symbol Min Nom M a x Min Nom Max

Package Height A - - 1.0 00 - - 0.039 4 Ball Height A1 0.117 - - 0.0046 - Package Body Thickness A2 - 0.740 - - 0.0291 Ball (Lead) Width b 0.300 0.350 0.400 0.0118 0.0138 0.0157 Package Body Length D 10.900 11.00 11.100 0.4291 0.4331 0.4370 Package Body Width E 7.900 8.00 8.100 0.3110 0.3150 0.3189 Pitch e - 0.80 - - 0.0315 Ball (Lead) Count N - 88 - - 88 Seating Plane Coplanarity Y - - 0.1 00 - - 0.003 9 Corner to Ball A1 Distance Along E S1 1.100 1.200 1.300 0.0433 0.047 2 0.0512 Corner to Ball A1 Distance Along D S2 1.000 1.100 1.200 0.0394 0.0433 0.04 7 2

Millimeters Inches

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet 14 Order Number: 306666, Revision: 001

1-Gbit P30 Family

Figure 5. 512-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.2 mm)

A1 Index

Mark

A B

C D E F G H

K L M

12345678

Top View - Ball Down

12345678

A B C D E F

G H

K L M

Bottom View -Ball Up

Draw ing not to s cale .

Dimensions Symbol Min Nom Max Min Nom Max

Millimeters Inches

Package Height A - - 1.200 - - 0.0472 Ball Height A1 0.200 - - 0.0079 - Package Body Thickness A2 - 0.860 - - 0.0339 Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 Package Body Length D 10.900 11.000 11.100 0.4291 0.4331 0.4370 Package Body Width E 7.900 8.000 8.100 0.3110 0.3150 0.3189 Pitch e - 0.800 - - 0.0315 B a ll (Lead) Count N - 88 - - 8 8 Seating Plane Coplanarity Y - - 0.100 - - 0.0039 C o rner to Ball A1 Distance Along E S1 1. 100 1. 200 1.30 0 0.0433 0. 0472 0. 0512 C o rner to Ball A1 Distance Along D S2 1.000 1. 100 1.20 0 0.0394 0. 0433 0. 047 2

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 15

1-Gbit P30 Family

Figure 6. 1-Gbit, 88-ball (80 active) QUAD+ SCSP Specifications (11x11x1.4 mm)

A1 Index

Mark

A B C D E F G H J

K L M

12345678

Top View - Ball Down

2345678

A B C D E F

G H

Bottom View - B a ll U p

Drawing not to scale.

Dimens ions Symbol Min Nom Max Min N om Max

Millimeters Inches

Package Height A - - 1.400 - - 0.0551 Ball Height A1 0.200 - - 0.0079 - Package Body Thickness A2 - 1.070 - - 0.0421 Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 Package Body Length D 10.900 11.000 11.100 0.4291 0.4331 0.4370 Package Body Width E 10.900 11.000 11.100 0.4291 0.4331 0.4370 Pitch e - 0.800 - - 0.0315 Ball (Lead) Count N - 88 - - 88 Seating Plane Coplanarity Y - - 0.100 - - 0.0039 Corner to Ball A1 Distance A long E S1 2.600 2.700 2.800 0.1024 0.1063 0.1102 Corner to Ball A1 Distance A long D S2 1.000 1.100 1.200 0.0394 0.0433 0.0472

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet 16 Order Number: 306666, Revision: 001

4.0 Ballout and Signal Descriptions

4.1 Signal Ballout

Figure 7. 56-Lead TSOP Pinout (64/128/256-Mbit)

1-Gbit P30 Family

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

1 2 3 4 5 6 7 8 9

Intel StrataFlash®

Embedded Memory (P30)

56-Lead TSOP Pinout

14 mm x 20 mm

Top View

A16

A15 A14 A13 A12 A11 A10

A9 A23 A22 A21

VSS VCC WE# WP#

A20 A19 A18

A8 A7 A6 A5 A4 A3 A2

A24 RFU VSS

Notes:

1. A1 is the least significant addres s bit.

2. A23 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC).

3. A24 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC).

56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

WAIT A17 DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 ADV# CLK RST# VPP DQ11 DQ3 DQ10 DQ2 VCCQ DQ9 DQ1 DQ8 DQ0 VCC OE# VSS CE# A1

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 17

1-Gbit P30 Family

Figure 8. 64-Ball Easy BGA Ballout (64/128/256/512-Mbit)

18234567

A1 A6 A8 A13VPP A18 A22VCC

A2 VSS A9 A14CE# A19 RFUA25

A3 A7 A10 A15A12 A20 A21WP#

A4 A5 A11 VCCQRST# A16 A17VCCQ

RFU OE#DQ0 DQ10 DQ12DQ11 WAITADV#

RFU VSS VCC DQ13VSS DQ7 A24VSS

Easy BGA

Top View- Ball sid e down

RFUDQ8 DQ1 DQ9 DQ4DQ3 DQ15CLK

WE#A23 RFU DQ2 DQ5VCCQ DQ14DQ6

RFU DQ8DQ1DQ9DQ4 DQ3DQ15 CLK

WE# RFUDQ2DQ5 VCCQDQ14 DQ6

Easy BGA

Bottom View- Bal l s ide up

Notes:

1. A1 is the least significant address bi t.

2. A23 is valid for 128 -Mbit densities and above; other wise, it is a no connect (NC).

3. A24 is valid for 256 -Mbit densities and above; other wise, it is a no connect (NC).

4. A25 is valid for 512-Mbit densities; otherwise, it is a no connect (NC).

234

A1A6A8A13 VPPA18A22 VCC

A2VSSA9A14 CE#A19RFU A25

A3A7A10A15 A12A20A21 WP#

A4A5A11VCCQRST#A16A17 VCCQ

RFUOE# DQ0DQ10DQ12 DQ11WAIT ADV#

A23

RFUVSSVCCDQ13 VSSDQ7A24 VSS

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet 18 Order Number: 306666, Revision: 001

Figure 9. 88-Ball (80-Active Ball) QUAD+ SCSP Ballout

Pin 1

12345678

1-Gbit P30 Family

DU DU Depop Depop Depop Depop DU DU

A4 A18 A19 VSS VCC VCC A21 A11

A5 RFUA23VSSRFUCLKA22A12

A3 A17 A24 VPP RFU RFU A9 A13

A2 A7 RFU WP# ADV# A20 A10 A15

A1 A6 RFU RST# WE# A8 A14 A16

A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT F2-CE#

RFU DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 F2-OE#

RFU F1-OE# DQ9 DQ11 DQ4 DQ6 DQ15 VCCQ

F1-CE# RFU RFU RFU RFU VCC VCCQ RFU

VSS VSS VCCQ VCC VSS VSS VSS VSS

DU DU Depop Depop Depop Depop DU DU

12345678

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 19

1-Gbit P30 Family

4.2 Signal Descriptions

This section has signal descriptions for the various P30 packages.

Table 3. TSOP and Easy BGA Signal Descriptions (Sheet 1 of 2)

Symbol Type Name and Func tio n

ADDRESS INPUTS: Device address inputs. 64-Mbit: A[22:1]; 128-Mbit: A[23:1]; 256-Mbit: A[24:1];

A[MAX:1] Input

DQ[15:0]

Input/

Output

ADV# Input

CE# Input

CLK Input

OE# Input

RST# Input

WAIT Output

WE# Input

WP# Input

VPP

Power/

Input

VCC Power

512-Mbit: A[ 25 :1 ]. See Table 5 on page22 and Figure 10 on p age23 for 512-Mbit addressing.

DATA INPUT/OUTPUTS : Inputs data and commands during write cycles; outputs dat a during memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls float when the CE# or OE# are deasserted. Data is in ternally latched during writes.

ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.

In asynchronous mode, the address is latched when ADV# going high or continuously flows through if ADV# is held low.

WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through. FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When

asserted, f lash internal control logic, i nput buffers, decoders, and sen s e amplifiers are active. When deasserted, the associated flash die is deselected, power is reduced to standby lev els, data and WAIT outputs are placed in high-Z state.

WARNING: All chip enables must be high when device is not in use. CLOCK: Synchronizes the device with the syste m’s bus frequency in synchronous-read mode.

During synchronous read operations, addresses ar e latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.

WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS. OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read

cycles. OE# high places the data outputs and W AIT in High-Z. RESET: Active low input. RST# resets internal automation and inhibits write operations. This

provides data protection during power transitions. RST# high enables normal operation. Exit from reset places the device in asynchronous read array mode.

WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration Register bit 10 (RCR[10], WT) determines its polarity when asserted. WAIT’s active output is V

when CE# and OE# are VIL. WAIT is high-Z if CE# or OE# is VIH.

• In synchronous arr ay or non-array read modes, WAIT indicates invalid data when asserted and valid data when deasserted.

• In asy n ch ro nous page mo de , an d al l w rite modes, WAIT is de a s se rt e d .

WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latc hed on the rising edge of WE#.

WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lockdown cannot be unlocked with the Unlock command. WP# high overrides the lock-down function enabling blocks to be erased or programmed using software commands.

Erase and Progr am Power: A valid voltage on this pin all ows erasing or progr amming. Memory

level of V

≤ V

contents cannot be altered when V should not be attempted.

= VCC for in-system prog r am and er ase oper at ions. To accommodate resist or o r di ode dr op s

Set V

from the syste m supply, the V min to perform in-system flash modif ication. VPP may be 0 V during read operations.

can be applied to main blocks for 1000 cy cles maximum and to par ameter blocks for 2500

PPH

VPP can be connected to 9 V for a cumulative total not to ex ceed 80 hours. Extended use of

cycles. this pin at 9 V may reduce block cycling capabili ty.

. Block erase and program at invalid VPP voltages

PPLK

can be as low as V

Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when

≤ V

. Operations at invalid VCC voltages should not be attempted.

LKO

min. VPP must remain abov e V

PPL

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet 20 Order Number: 306666, Revision: 001

1-Gbit P30 Family

Table 3. TSOP and Easy BGA Signal Descriptions (Sheet 2 of 2)

Symbol Type Name and Function

VCCQ Power Output Power Supply: Output-driver source voltage. VSS Power Ground: Con nect to system ground. Do not float any VSS connection.

RFU — DU — Do Not Use: Do not connect to any other signal, or power supply; must be left floating.

NC — No Connect: No internal connection; can be driven or floated.

Reserved for Fu ture Use: Reserve d by In tel f or fu ture de vice f uncti onali ty and enh ancemen t. T hese should be treated in the same way as a Do Not Use (DU) signal.

Table 4. QUAD+ SCSP Signal Descriptions (Sheet 1 of 2)

Symbol Type Name and Function

ADDRESS INPUTS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit: A[23:0];

A[MAX:0] Input

DQ[15:0]

ADV# Input

F1-CE# F2-CE#

CLK Input

F1-OE# F2-OE#

RST# Input

WAIT Output

WE# Input

Input/

Output

Input

512-Mbit: A[24:0]. See Table 6 on page 22, Figure 11 on page23, and Figure 12 on page 23 for 512-Mbit and 1-Gbit

addressing. DA TA INPUT/OUTPUTS: Inputs data and command s dur in g w rit e cy c le s ; ou tp uts data dur i n g

memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls float when the CE# or OE# are deasserted. Data is internally latched during writes.

ADDRESS VALID: Active low input. During synchronous re ad operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge wit h AD V# low, whichever occurs first.

In asynchronous mode, the address is latched when ADV# going high or continuously flows through if ADV# is held lo w.

WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through. FLASH CHIP ENABLE: Active low input . CE# low selects the associated flash memory die. When

asserted, flash internal control logic, input buffers, decod ers, and sense amplifiers are active. When deasserted, the associated flash die is deselected , power is reduced to standby levels, data and WAIT outputs are placed in high-Z state.

See Table 6 on page 22 for CE# assignment definitions.

WARNING: All chip enables must be high when device is not in use. CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode.

During synchronous read operations, addresses are latched on the rising edge of ADV#, or on t he next valid CLK edge with ADV# low, whichever occurs first.

WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS. OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read

cycles. OE# high places the data outpu ts and WAIT in High-Z. F1-OE# and F2-OE # should be tied together for all densities.

RESET: Active low input. RS T# resets internal automation and inhibits write operations. This provides data protection during power transitions. RST# high enables normal operation. Exit from reset places th e device in asynchronous read array mode.

WAIT: Indicates data valid in synchronous array or non-ar ray burst reads. Read C onfiguration Register bit 10 (RCR[10], WT) determines its po larity when asserted. WAIT’s active output is V

when CE# and OE# are VIL. WAIT is high-Z if CE # or O E# is VIH.

• In synchronous array or non-array read modes, WAIT indicates inva lid data when asserted and valid data when deasserted.

• In asynchronous page mode, and all w rite modes, WAI T is deasserted.

WRITE ENABLE: Active low in put. WE# controls writes to the device. Address and data are latched on the rising edg e of WE#.

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 21

1-Gbit P30 Family

Table 4. QUAD+ SCSP Signal Descriptions (Sheet 2 of 2)

Symbol Type Name and Func tio n

WP# Input

VPP

Power/

lnput

VCC Power

VCCQ Power Output Power Supply: Output-driver source voltage. VSS Power Ground: Connect to system ground. Do not float any VSS connection.

RFU —

DU — Do Not Use: Do not connect to any other signal, or power supply; must be left floating. NC — No Connect: No internal connection; can be driven or floated.

Erase and Progr am Power: A valid voltage on this pin all ows erasing or progr amming. Memory

level of V

≤ V

contents cannot be altered when V should not be attempted.

= VCC for in-system prog r am and er ase oper at ions. To accommodate resist or o r di ode dr op s

Set V

from the syste m supply, the V min to perform in-system flash modif ication. VPP may be 0 V during read operations.

can be applied to main blocks for 1000 cy cles maximum and to par ameter blocks for 2500

PPH

VPP can be connected to 9 V for a cumulative total not to ex ceed 80 hours. Extended use of

cycles. this pin at 9 V may reduce block cycling capabili ty.

. Block erase and program at invalid VPP voltages

PPLK

can be as low as V

min. VPP must remain abov e V

PPL

Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when

≤ V

. Operations at invalid VCC voltages should not be attempted.

LKO

Reserved for Future Use: Reserved by Intel for fut ure devi ce fun ctional ity a nd enha ncement. These should be treated in the same way as a Do Not Use (DU) signa l.

PPL

4.3 SCSP Configurations

Table 5. Stacked Easy BGA Chip Select Logic

Stack Combination

1-die F1-CE# 2-die F1-CE# + A25 (V

Table 6. QUAD+ SCSP Chip Select Logic

Stack

Combination

1-die F1-CE# - - 2-die F1-CE# + A24 (V 4-die F1-CE# + A24 (V

Selected Fl ash

Die #1

Selected Flash

Die #1

) F1-CE# + A24 (VIH)- -

) F1-CE# + A24 (VIH) F2-CE# + A24 (VIL) F2-CE# + A24 (VIH)

) F1-CE# + A25 (VIH)

Selected Flash

Die #2

Selected Flash

Die #2

Selected Fl ash

Die #3

Selected Flash

Die #4

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet 22 Order Number: 306666, Revision: 001

Figure 10. 512-Mbit Easy BGA Device Block Diagram

Easy BGA 2-Die (512-Mbit) Device Configuration

F1-CE#

WP#

OE#

WE#

CLK

ADV#

A[MAX:1]

Flash Die #1

(256-Mbit)

Flash Die #2

(256-Mbit)

Figure 11. 512-Mbit QUAD+ SCSP Device Block Diagram

1-Gbit P30 Family

RST# VCC VPP

VCCQ VSS

DQ[15:0] WAIT

QUAD+ 2-Die (512-Mbit) Device Configuration

F1-CE#

WP#

OE#

WE#

CLK

ADV#

Flash Die #1

(256-Mbit)

Flash Die #2

(256-Mbit)

Figure 12. 1-Gbit QUAD+ SCSP Device Block Diagram

QUAD+ 4-Die (1-Gbit) Device Configuration

F1-CE#

WP#

OE#

WE#

CLK

ADV#

Flash Die #1

(256-Mbit)

Flash Die #2

(256-Mbit)

Flash Die #3

(256-Mbit)

Flash Die #4

(256-Mbit)

RST# VCC VPP

VCCQ VSS

DQ[15:0]A[MAX:0] WAIT

F2-CE#

RST# VCC VPP

VCCQ VSS

DQ[15:0]A[MAX:0] WAIT

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 23

1-Gbit P30 Family

4.4 Memory Maps

Table 7 through Table 10 show the P30 memory maps. See Section 11.0, “Programming Operations” on page 61 for Programming Region information.

Table 7. Discrete Top Parameter Memory Maps (all packages)

Programming

Region #

Size

Blk 256-Mbit Blk 128-Mbit

(KB)

32 258 FFC000 - FFFFFF 130 7FC000 - 7FFFFF

...

32 255 FF0000 - FF3FFF 127 7F0000 - FF3FFF 32 63 3F0000 - 3F3FFF

128 254 FE0000 - FEFFFF 126 7E0000 - 7EFFFF 128 62 3E0000 - 3EFFFF

...

128 240 F00000 - F0FFFF 120 780000 - 78FFFF 128 56 380000 - 38FFFF 128 239 EF0000 - EFFFFF 119 770000 - 77FFFF

...

128 224 E00000 - E0FFFF 112 700000 - 70FFFF 128 48 300000 - 30FFFF 128 223 DF0000 - DFFFFF 111 6F0000 - 6FFFFF

...

128 208 D00000 - D0FFFF 104 680000 - 68FFFF 128 40 280000 - 28FFFF 128 207 CF0000 - CFFFFF 103 670000 - 67FFFF

...

128 192 C00000 - C0FFFF 96 600000 - 60FFFF 128 32 200000 - 20FFFF 128 191 BF0000 - BFFFFF 95 5F0000 - 5FFFFF

...

128 176 B00000 - B0FFFF 88 580000 - 58FFFF 128 24 180000 - 18FFFF 128 175 AF0000 - AFFFFF 87 570000 - 57FFFF

...

128 160 A0000 - A0FFFF 80 500000 - 50FFFF 128 16 100000 - 10FFFF 128 159 9F0000 - 9FFFFF 79 4F0000 - 4FFFFF

...

128 144 900000 - 90FFFF 72 480000 - 48FFFF 128 8 080000 - 08FFFF 128 143 8F0000 - 8FFFFF 71 470000 - 47FFFF

...

128 128 800000 - 80FFFF 64 400000 - 40FFFF 128 0 000000 - 00FFFF 128 127 7F0000 - 7FFFFF 63 3F0000 - 3FFFFF

...

128 112 700000 - 70FFFF 56 380000 - 38FFFF

...

Programming

Region #

Size

Blk 64-Mbit

(KB)

32 66 3FC 000 - 3FFFFF

...

128 55 370000 - 37FFFF

...

128 47 2F0000 - 2FFFFF

...

128 39 270000 - 27FFFF

...

128 31 1F0000 - 1FFFFF

...

128 23 170000 - 17FFFF

...

128 15 0F0000 - 0FFFFF

...

128 7 070000 - 07FFFF

...

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet 24 Order Number: 306666, Revision: 001

Table 7. Discrete Top Parameter Memory Maps (all packages)

1-Gbit P30 Family

Programming

Region #

Size

Blk 256-Mbit Blk 128-Mbit

(KB)

128 111 6F0000 - 6FFFFF 55 370000 - 37FFFF

...

... 128 96 600000 - 60FFFF 48 300000 - 30FFFF 128 95 5F0000 - 5FFFFF 47 2F0000 - 2FFFFF

...

... 128 80 500000 - 50FFFF 39 280000 - 28FFFF 128 79 4F0000 - 4FFFFF 38 270000 - 27FFFF

...

... 128 64 400000 - 40FFFF 32 200000 - 20FFFF

128 63 3F0000 - 3FFFFF 31 1F0000 - 1FFFFF

...

... 128 48 300000 - 30FFFF 24 180000 - 18FFFF

128 47 2F0000 - 2FFFFF 23 170000 - 17FFFF

...

... 128 32 200000 - 20FFFF 16 100000 - 10FFFF

128 31 1F0000 - 1FFFFF 15 0F0000 - 0FFFFF

...

... 128 16 100000 - 10FFFF 8 080000 - 08FFFF

128 15 0F0000 - 0FFFFF 7 070000 - 07FFFF

...

... 128 0 000000 - 00FFFF 0 000000 - 00FFFF

...

Programming

Region #

Size

Blk 64-Mbit

(KB)

Table 8. Discrete Bottom Parameter Memory Maps (all packages)

Programming

Region

Size

Blk 256-Mbit Blk 128-Mbit

(KB)

128 258 FF0000 - FFFFFF 130 7F0000 - 7FFFFF

...

... 128 243 F00000 - F0FFFF 123 780000 - 78FFFF 128 56 380000 - 38FFFF

128 242 EF0000 - EFFFFF 122 770000 - 77FFFF

...

... 128 227 E00000 - E0FFFF 115 700000 - 70FFFF 128 48 300000 - 30FFFF

128 226 DF0000 - DFFFFF 114 6F0000 - 6FFFFF

...

... 128 211 D00000 - D0FFFF 107 680000 - 68FFFF 128 40 280000 - 28FFFF

...

Programming

Region

Size

Blk 64-Mbit

(KB)

128 62 3F0000 - 3FFFFF

...

128 55 370000 - 37FFFF

...

128 47 2F0000 - 2FFFFF

...

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 25

1-Gbit P30 Family

Table 8. Discrete Bottom Parameter Memory Maps (all packages)

Programming

Region

Size

Blk 256-Mbit Blk 128-Mbit

(KB)

128 210 CF0000 - CFFFFF 106 670000 - 67FFFF

...

... 128 195 C00000 - C0FFFF 99 600000 - 60FFFF 128 32 200000 - 20FFFF 128 194 BF0000 - BFFFFF 98 5F0000 - 5FFFFF

...

... 128 179 B00000 - B0FFFF 91 580000 - 58FFFF 128 24 180000 - 18FFFF 128 178 AF0000 - AFFFFF 90 570000 - 57FFFF

...

... 128 163 A0000 - A0FFFF 83 500000 - 50FFFF 128 16 100000 - 10FFFF

128 162 9F0000 - 9FFFFF 82 4F0000 - 4FFFFF

...

... 128 147 900000 - 90FFFF 75 480000 - 48FFFF 128 8 080000 - 08FFFF

128 146 8F0000 - 8FFFFF 74 470000 - 47FFFF

...

... 128 131 800000 - 80FFFF 67 400000 - 40FFFF 128 4 010000 - 01FFFF

128 130 7F0000 - 7FFFFF 66 3F0000 - 3FFFFF 32 3 00C000 - 00FFFF

...

... 128 115 700000 - 70FFFF 59 380000 - 38FFFF 32 0 000000 - 003FFF

128 114 6F0000 - 6FFFFF 58 370000 - 37FFFF

...

... 128 99 600000 - 60FFFF 51 300000 - 30FFFF

128 98 5F0000 - 5FFFFF 50 2F0000 - 2FFFFF

...

... 128 83 500000 - 50FFFF 43 280000 - 28FFFF

128 82 4F0000 - 4FFFFF 42 270000 - 27FFFF

...

... 128 67 400000 - 40FFFF 35 200000 - 20FFFF 128 66 3F0000 - 3FFFFF 34 1F0000 - 1FFFFF

...

... 128 51 300000 - 30FFFF 27 180000 - 18FFFF 128 50 2F0000 - 2FFFFF 26 170000 - 17FFFF

...

... 128 35 200000 - 20FFFF 19 100000 - 10FFFF 128 34 1F0000 - 1FFFFF 18 0F0000 - 0FFFFF

...

... 128 19 100000 - 10FFFF 11 080000 - 08FFFF

...

Programming

Region

Size

Blk 64-Mbit

(KB)

128 39 270000 - 27FFFF

...

128 31 1F0000 - 1FFFFF

...

128 23 170000 - 17FFFF

...

128 15 0F0000 - 0FFFFF

...

128 10 070000 - 07FFFF

...

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet 26 Order Number: 306666, Revision: 001

Table 8. Discrete Bottom Parameter Memory Maps (all packages)

1-Gbit P30 Family

Programming

Region

Size

Blk 256-Mbit Blk 128-Mbit

(KB)

128 18 0F0000 - 0FFFFF 10 070000 - 07FFFF

...

128 4 010000 - 01FFFF 4 010000 - 01FFFF

32 3 00C000 - 00FFFF 3 00C000 - 00FFFF

...

32 0 000000 - 03FFFF 0 000000 - 00FFFF

...

Programming

Region

Table 9. 512-Mbit Memory Map (Easy BGA and QUAD+ SCSP)

Flash Die # Die Stack Config. Size (KB)

32 258 FFC000 - FFFFFF

...

Flash Die #2

(Top Parameter)

32 255 FF0000 - FF3FFF

128 254 FE0000 - FEFFFF

...

128 0 000000 - 00FFFF

512-Mbit Flash (2x256-Mbit w/ 1CE)

Blk Address Rang e

...

Size

Blk 64-Mbit

(KB)

...

128 258 FF0000 - FFFFFF

...

Note: Refer to 256-Mbit Memory Map (Tabl e 7 and Table 8) for Pr ogramming Region Information.

Flash Die #1 (Bott om

Parameter)

128 4 010000 - 01FFFF

32 3 00C000 - 00FFFF

...

32 0 000000 - 003FFF

...

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 27

1-Gbit P30 Family

Table 10. 1-Gbit Memory Map (QUAD+ SCSP o nly)

Flash Die # Die Stack Config. Size (KB)

32 258 FFC000 - FFFFFF

...

Flash Die #4

(Top Parameter)

Flash Die #3

(Bottom Parameter)

Flash Die #2

(Top Parameter)

32 255 FF0000 - FF3FFF

128 254 FE0000 - FEFFFF

...

128 0 000000 - 00FFFF

128 258 FF0000 - FFFFFF

...

128 5 020000 - 02FFFF

32 3 00C000 - 00FFFF

...

32 0 000000 - 003FFF

32 258 FFC000 - FFFFFF

...

32 255 FF0000 - FF3FFF

128 254 FE0000 - FEFFFF

...

1-Gbit Flash (4x256-Mbit w/ 2CE)

Blk Address Range

...

128 0 000000 - 00FFFF

128 258 FF0000 - FFFFFF

...

Note: Refer to 256-Mbit Memory Map (Table 7 and Table 8) for Programming Region Information.

Flash Die #1

(Bottom Parameter)

128 4 010000 - 01FFFF

32 3 00C000 - 00FFFF

...

32 0 000000 - 003FFF

...

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet 28 Order Number: 306666, Revision: 001

1-Gbit P30 Family

5.0 Maximum Ratings and Operating Conditions

5.1 Absolute Maximum Ratings

Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.

These are stress ratings only.

Parameter Maximum Rating Notes

Temperat ur e under bias –40 °C to +85 °C 1 Storage temperatur e –65 °C to +125 °C Voltage on any signal (except VCC, VPP) –0.5 V to +4.1 V 2 VPP voltage –0.2 V to +10 V 2,3,4 VCC voltage –0.2 V to +2.5 V 2 VCCQ voltage –0.2 V to +4.1 V 2 Output short circuit current 100 mA 5

Notes:

1. Temperature for 1-Gbit SCSP is –30 °C to +85 °C.

2. Voltages shown are specifie d with respect to V signals and –0.2V on V periods < 20 ns. Maximum DC voltage on V overshoot to V

+ 0.5V, which, during transitions, may overshoot to V

is V

3. Maximum DC voltage on V

4. Program/erase voltage is typically 1.7 V – 2.0 V. 9.0 V can be applied for 80 hours maximum total, to

5. Output shorted for no mor e than one second. No more than one output shorted at a time.

CCQ

any blocks for 1000 cycles maximum. 9.0 V program/erase voltage may reduce block cycling capability.

+ 2.0 V for periods < 20 ns. Maximum DC voltage on input/output signals and V

, V

, and VPP. During transitions, this level may undershoot to –2.0 V for

CCQ

may overshoot to +11.5 V for perio ds < 20 ns.

. Minimum DC voltage is –0.5 V on input/output

is VCC + 0.5 V, w hich, during transitions, may

+ 2.0 V for periods < 20 ns.

CCQ

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 29

1-Gbit P30 Family

5.2 Operating Conditions

Note: Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond

the “Operating Conditions” may affect device reliability.

Table 11. Operating Conditions

Symbol Parameter Min Max Units Notes

Operating Temperat u re –40 +85 °C 1,2

Block

Erase

Cycles

NOTES:

1. T

2. Temperature for 1-Gbit SCSP is –30 °C to +85 °C.

3. In typical operation, the VPP program voltage is V

VCC Supply Voltage 1.7 2.0

I/O Supply Voltage

CCQ

PPLVPP PPH

PPH

Volt age Supply (Logic Level) 0.9 3.6 Factory word programming V Maximum VPP Hours VPP = V Main and Parameter Blocks V

Parameter Blocks V

= Case Temperature

hours.

CMOS inputs 1.7 3 .6 TTL inputs 2.4 3.6

PPH

= V

PPH

= V

PPH

. VPP can be connected to 8.5 V – 9.5 V for 80

PPL

8.5 9.5

-80Hours

100,000 -

-1000

CyclesMain Blocks V

-2500

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet 30 Order Number: 306666, Revision: 001

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