The NX440LX motherboard may contain design defects or errors known as errata. Characterized errata that may cause the NX440LX motherboard’s behavior to deviate from
published specifications are documented in the NX440LX Motherboard Specfication Update.
674633-001
Revision History
RevisionRevision HistoryDate
-001First Release.August, 1997
This product specification applies only to standard NX440LX motherboards with BIOS identifier
4N4XL0X0.86A.
Changes to this specification will be published in the NX440LX Motherboard Specification Update
before being incorporated into a revision of this document.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
The NX440LX motherboard may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call in North America 1-800-879-4683, Europe 44-0-1793-431-155, France 44-0-1793-421-777,
Germany 44-0-1793-421-333, other Countries 708-296-9333.
†
Third-party brands and names are the property of their respective owners.
Copyright Intel Corporation, 1997. All rghts reserved.
The NX440LX motherboard is a versatile platform that offers a wide variety of features. Many of
the options, however, are implemented – at least in part – on the riser. Throughout this manual,
‡
symbol is used to indicate such an option. Because there is no standard riser, no detailed
the
description of an implementation can be given. See Section 6.1 to obtain the reference design for
the NLX riser.
The NX440LX motherboard supports Pentium
266, and 300 MHz. The motherboard features:
•
NLX v1.2 form factor
•
Minimal jumper design
Main Memory
•
Three 168-pin DIMM sockets
•
Support for up to 384 MB of synchronous DRAM (SDRAM)
•
Support for 66 MHz SDRAM
•
Support for ECC and non-ECC memory
II family of microprocessors operating at 233,
Chipset and PCI/IDE Interface
•
Intel 82440LX AGPset PCI/A.G.P. Controller (PAC)
•
Integrated PCI bus mastering controller using PIIX4
•
Dual channel EIDE interface
•
Real-time clock
‡
I/O Features
•
SMC FDC37C677 I/O controller
•
Floppy drive interface
•
Integrates standard I/O functions: one multi-mode parallel port, two FIFO serial ports, and
‡
keyboard and mouse controller
•
Support for one Universal Serial Bus (USB) interface on the motherboard and another on the
‡
riser
•
Support for consumer infrared
‡
Audio Subsystem
•
Yamaha OPL3-SA3 audio codec component
•
Wavetable upgrade header
Graphics Subsystem
•
Optional Cirrus Logic CL-GD5465 A.G.P. graphics accelerator with 2 MB of RAMBUS
(RDRAM) video memory expandable to 4 MB using a 2 MB video upgrade module
The motherboard is designed to fit into a standard NLX form factor chassis. Figure 3 illustrates the
mechanical form factor for the motherboard. Location of the I/O connectors, riser slot, and
mounting holes are in strict compliance with the NLX specification (see Section 6.2). Dimensions
are given in inches.
8.70
8.50
0.260
0.0
0.50
0.0
0.349
0.509
1.849
2.108
6.575
9.234
0.260
10
8.80
12.80
4.207.60
Figure 3. Motherboard Dimensions
13.00
0.20
OM06251
Motherboard Description
1.3 I/O Shield
The back panel I/O shield for the NX440LX motherboard must meet specific dimensional and
material requirements. Systems based on this motherboard need the back panel I/O shield in order
to pass emission certification testing. Figure 4 shows the critical dimensions for both options of
the I/O shield, and indicates the position of each cutout. Dimensions are given in inches.
The motherboard supports a single Pentium II processor. The processor’s VID pins automatically
program the motherboard’s voltage regulator to the required processor voltage. The motherboard
operates with processors that run internally at 233, 266, or 300 MHz and have either a 256 KB or
512 KB second-level cache.
The processor implements MMX technology and maintains full backward compatibility with the
8086, 80286, Intel386, Intel486, and Pentium processor. The processor’s numeric coprocessor
significantly increases the speed of floating-point operations and complies with ANSI/IEEE
standard 754-1985.
1.4.1 Microprocessor Packaging
The processor is packaged in a Single Edge Contact (S.E.C.) cartridge. The S.E.C. cartridge
includes the processor core, the second-level cache, a thermal plate, and a back cover.
The processor connects to the motherboard through the Slot 1 processor connector, a 242-pin edge
connector. When the processor is mounted in Slot 1, it is secured by a retention mechanism
attached to the motherboard. The processor’s heatsink is stabilized by a heatsink support that is
attached to the motherboard.
1.4.2 Second-Level Cache
The second-level cache is located on the substrate of the S.E.C. cartridge. The cache includes burst
pipelined synchronous static RAM (PBSRAM) and tag RAM. There can be two or four BSRAM
components totaling 256 KB or 512 KB in size. All supported onboard memory can be cached.
1.4.3 Microprocessor Upgrades
The motherboard can be upgraded with Pentium II processors that run at higher processor speeds.
After upgrading the processor, use the BIOS configuration mode to set the proper speed for the
processor. See Section 1.15.2 for information about configuration mode.
12
Motherboard Description
1.5 Memory
1.5.1 Main Memory
The motherboard has three, dual inline memory module (DIMM) sockets. Minimum memory size
is 16 MB; maximum memory size is 384 MB. The BIOS automatically detects memory type, size,
and speed.
The motherboard supports the following memory features:
• 168-pin DIMMs with gold-plated contacts
• 66 MHz unbuffered SDRAM only
• Non-ECC (64-bit) and ECC (72-bit) memory
• 3.3 V memory only
• Single- or double-sided DIMMs in the following sizes:
DIMM SizeNon-ECC ConfigurationECC Configuration
16 MB2 Mbit x 642 Mbit x 72
32 MB4 Mbit x 644 Mbit x 72
64 MB8 Mbit x 648 Mbit x 72
128 MB16 Mbit x 6416 Mbit x 72
Memory can be installed in one, two, or three sockets. Memory size can vary between sockets.
1.5.2 SDRAM
Synchronous DRAM (SDRAM) improves memory performance through memory access that is
synchronous with the memory clock. This simplifies the timing design and increases memory
speed because all timing is dependent on the number of memory clock cycles.
NOTE
✏
To function properly, SDRAM DIMMs must meet the Intel 4-clock, 66 MHz, unbuffered SDRAM
specification for either 64-bit or 72-bit SDRAM. See Section 6.2 for information about these
specifications.
Error checking and correcting (ECC) memory detects multiple-bit errors and corrects single-bit
errors. When ECC memory is installed, the BIOS supports both ECC and non-ECC mode. ECC
mode is enabled in the Setup program. The BIOS automatically detects if ECC memory is
installed and provides the Setup option for selecting ECC mode. If non-ECC memory is installed,
the Setup option for ECC mode does not appear.
The following table describes the effect of using Setup to put each memory type in each supported
mode. Whenever ECC mode is selected in Setup, some performance loss occurs.
Memory Error Detection Mode Established in Setup Program
ECC DisabledECC Enabled
Non-ECC DIMM
ECC DIMM
No error detectionN/A
No error detectionSingle-bit error correction, multiple-bit error
detection
1.6 Chipset
The Intel 440LX is designed for the Pentium II processor. It consists of the Intel 82443LX
PCI/A.G.P. controller (PAC) and the Intel 82371AB PCI/ISA IDE Xcelerator (PIIX4) bridge chip.
1.6.1 Intel 82443LX PCI/A.G.P. Controller
The PAC provides bus-control signals, address paths, and data paths for transfers between the
processor’s host bus, PCI bus, Accelerated Graphics Port (A.G.P.), and main memory. The PAC
comes in a 492-pin BGA package and features:
• Processor interface control
Processor host bus speed up to 66 MHz
32-bit addressing
GTL+ compliant host bus
• Integrated DRAM controller
Supports synchronous DRAM (SDRAM)
64/72-bit path-to-memory
Auto detection of memory type
Supports 4-, 16-, 64-Mbit DRAM devices
Symmetrical and asymmetrical DRAM addressing
Supports 3.3 V DRAMs
• Accelerated Graphics Port Interface
Complies with A.G.P. specification (see Section 6.2 for specification information)
Supports 3.3 V A.G.P. devices with data transfer rates up to 133 MHz
Synchronous coupling to the host-bus frequency
14
Motherboard Description
• Fully-synchronous PCI bus interface
Complies with PCI specification (see Section 6.2 for specification information)
PCI-to-DRAM access greater than 100 MB/sec
‡
Supports five
PCI bus masters in addition to the host and PCI-to-ISA I/O bridge
Delayed transactions
PCI parity generation and checking support
• Data Buffering
Host-to-DRAM, PCI-to-DRAM, and A.G.P.-to-DRAM write-data buffering
Write-combining for host-to-PCI burst writes
Supports concurrent host, PCI, and A.G.P. transactions to main memory
• Supports system management mode (SMM)
1.6.2 Intel 82371AB PCI ISA IDE Xcelerator (PIIX4)
The PIIX4 is a multifunction PCI device implementing the PCI-to-ISA bridge, PCI IDE
functionality, Universal Serial Bus (USB) host/hub function, and enhanced power management.
The PIIX4 comes in a 324-pin MBGA package that features:
• Multifunction PCI-to-ISA bridge
Supports the PCI bus at 33 MHz
Complies with PCI specification (see Section 6.2 for specification information)
Full ISA or extended I/O (EIO) bus support
• USB controller
‡
Two
Supports legacy keyboard and mouse
Supports UHCI design guide revision 1.1 interface
• Integrated dual-channel enhanced IDE interface
Supports up to four IDE devices
PIO Mode 4 transfers at up to 14 MB/sec
Supports Ultra DMA/33 synchronous DMA mode transfers up to 33 MB/sec
Bus master mode with an 8 x 32-bit buffer for bus master PCI IDE burst transfers
• Enhanced DMA controller
Two 8237-based DMA controllers
Supports PCI DMA with three PC/PCI channels and distributed DMA protocols
Fast type-F DMA for reduced PCI bus usage
• Interrupt controller based on 82C59
Supports 15 interrupts
Programmable for edge/level sensitivity
Supports serial IRQs
• Power management logic
Sleep/resume logic
Supports wake-on-modem through Ring Indicator input
Supports remote wakeup
• Real-Time Clock
256 byte battery-backed CMOS SRAM
Includes date alarm
• 16-bit counters/timers based on 82C54
1.6.3 Accelerated Graphics Port (A.G.P.)
The Accelerated Graphics Port (A.G.P.) is a high-performance interconnect for graphic-intensive
applications, such as 3D applications. A.G.P. is independent of the PCI bus and is intended for
exclusive use with graphical-display devices. A.G.P. provides these performance features:
• Pipelined-memory read and write operations that hide memory access latency
• Demultiplexing of address and data on the bus for near 100 percent bus efficiency
• AC timing for 133 MHz data transfer rates, allowing data throughput of 500 MB/sec
A.G.P. complies with the 66 MHz PCI specification. See Section 6.2 for information about the
A.G.P. and PCI specifications.
NOTE
✏
Due to the location of the third DIMM socket, only half-length AGP cards are supported.
The optional CL-GD5465 supports the A.G.P. for higher bandwidth between the system memory
and the graphics subsystem. It is a member of the Laguna family of RAMBUS-based graphics
accelerators, offering 3D-graphics capability while maintaining a high level of 2D performance.
The features include:
• 64-bit graphics engine with integrated 3D game acceleration
• High-performance 64-bit GUI accelerator
• Video playback acceleration
†
• Integrated VGA
• Integrated 230-MHz palette DAC and clock synthesizer
controller
16
Motherboard Description
Table 1.Video Resolution
Resolution SupportedNo. of Colors
640 x 480, 800 x 600, 1024 x 768, 1280 x 1024, 1600 x 1200256 (8 bit)
640 x 480, 800 x 600, 1024 x 768, 1280 x 102465,536 (16 bit)
640 x 480, 800 x 600, 1024 x 76816,777,216 (24 bit)
640 x 480, 800 x 600, 1024 x 768, 1280 x 1024, 1600 x 1200256 (8 bit)
640 x 480, 800 x 600, 1024 x 768, 1280 x 102465,536 (16 bit)
640 x 480, 800 x 600, 1024 x 76816,777,216 (24 bit)
640 x 480, 800 x 600, 1024 x 76816,777,216(32 bit)
640 x 480, 800 x 600, 1024 x 768, 1280 x 1024, 1600 x 1200256 (8 bit)
640 x 480, 800 x 600, 1024 x 768, 1280 x 102465,536 (16 bit)
640 x 480, 800 x 600, 1024 x 76816,777,216 (24 bit)
640 x 480, 800 x 600, 1024 x 768, 1280 x 1024256 (8 bit)
640 x 480, 800 x 600, 1024 x 76865,536 (16 bit)
1.6.4 Universal Serial Bus (USB)
The motherboard can support two‡ USB ports; however, it is shipped with only one connector.
The second is supported through the NLX riser. If you need to connect more than one USB device,
you can connect an external hub to the USB port. The motherboard fully supports the universal
host controller interface (UHCI) and uses UHCI-compatible software drivers. See Section 6.2 for
information about the USB specification. USB features include:
• Self-identifying peripherals that can be plugged in while the computer is running
• Automatic mapping of function to driver and configuration
• Supports isochronous and asynchronous transfer types over the same set of wires
• Supports up to 127 physical devices per USB port
• Bandwidth and low latencies appropriate for telephony, audio, and other applications
• Error-handling and fault-recovery mechanisms built into the protocol
NOTE
✏
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B or other regulatory EMI requirements, even if no device or a low-speed (sub-channel)
USB device is attached to the cable. Use shielded cable that meets the requirements for high-speed
(fully-rated) devices.
1.6.5 IDE Support
The motherboard has two independent bus-mastering capable PCI IDE interfaces. These interfaces
support PIO Mode 3, PIO Mode 4, ATAPI devices (e.g., CD-ROM), and Ultra DMA/33
synchronous-DMA mode transfers. The BIOS supports logical block addressing (LBA) and
extended cylinder head sector (ECHS) translation modes. The BIOS automatically detects the IDE
device transfer rate.
Programmed I/O operations usually require a substantial amount of processor bandwidth.
However, in multitasking operating systems, the bandwidth freed by bus mastering IDE can be
devoted to other tasks while disk transfers are occurring.
1.6.6 Real-Time Clock, CMOS SRAM, and Battery
The real-time clock is compatible with DS1287 and MC146818 components. The clock provides a
time-of-day clock and a multicentury calendar with alarm features and century rollover. The realtime clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are reserved for
BIOS use.
The time, date, and CMOS values can be specified in the Setup program. The CMOS values can
be returned to their defaults by using the Setup program.
An external coin-cell battery powers the real-time clock and CMOS memory. When the computer
is not plugged into a wall socket, the battery has an estimated life of three years. When the
computer is plugged in, the 5 V standby current from the power supply extends the life of the
battery. The clock is accurate to ± 13 minutes/year at 25 ºC with 5 V applied.
1.7 I/O Interface Controller
• Enhanced Ultra I/O SMC FDC37C677
5 Volt operation
ISA Plug-and-Play compatible register set
• Two serial ports or one serial port and one infrared port
• One floppy controller
• FIFO support on both serial and floppy interfaces
• One parallel port with ECP and EPP support
†
• PS/2
• Supports BIOS setup for various configuration options
style mouse and keyboard interfaces
1.7.1 Serial Ports
The motherboard has two 9-pin D-Sub serial port connectors located on the back panel. The
NS16C550-compatible UARTs allow data transfers at speeds up to 115.2 Kbits/sec using BIOS
support.
1.7.2 Parallel Port
The connector for the multimode bi-directional parallel port is a 25-pin D-Sub connector located on
the back panel of the motherboard. In the Setup program, there are four options for parallel port
operation:
• Compatible (standard mode)
• Bi-directional (PS/2 compatible)
• Bi-directional Enhanced Parallel Port (EPP). A driver from the peripheral manufacturer is
required for operation. See Section 6.2 for EPP compatibility
• Bi-directional high-speed Extended Capabilities Port (ECP)
‡
18
Motherboard Description
1.7.3 Floppy Controller
The I/O controller is software compatible with the 82077 floppy drive controller. The floppy
connector is located on the riser card. In the Setup program, the floppy interface can be configured
for the following floppy drive capacities and sizes:
PS/2 keyboard and mouse connectors are located on the back panel of the motherboard. The +5 V
lines to these connectors are protected with a PolySwitch
reestablishes the connection after an over-current condition is removed. While this device
eliminates the possibility of having to replace a fuse, power to the computer should be turned off
before connecting or disconnecting a keyboard or mouse.
NOTE
✏
You can plug the mouse and keyboard into either connector.
The keyboard controller contains code which provides the traditional keyboard and mouse control
functions, and also supports Power On/Reset password protection. A Power On/Reset password
can be specified in the Setup program.
The keyboard controller supports the following hot-key sequence:
• <Ctrl><Alt><Del> Software reset. This key sequence resets the computer’s software by
jumping to the beginning of the BIOS code and running the Power-On Self Test (POST).
†
circuit that, like a self-healing fuse,
1.7.5 Optional Infrared
There is no infrared header on the motherboard; however, the edge connector does accommodate
infrared signals from the riser. If either IrDA
Configuration Submenu to change the mode for Serial Port B from COM2 to infrared applications.
†
or ASK-IR† is available, use the BIOS Peripheral
1.8 Audio Subsystem
1.8.1 OPL3-SA3 Audio System
The optional onboard audio subsystem features the Yamaha OPL3-SA3 (YMF715) device. The
features of the device include:
• A 16-bit audio codec
• OPL3 FM synthesis
• An integrated 3D enhanced stereo controller including all required analog components
• Stereo analog-to-digital and digital-to-analog converters
• Analog mixing, anti-aliasing, and reconstruction filters
• Supports 16-bit address decoding
• Line In, line out, and microphone connectors
• ADPCM, A-law, or µlaw digital audio compression and decompression
• Full digital control of all mixer and volume control functions
• Plug and Play compatible
†
• Sound Blaster Pro
NOTE
✏
Using the front panel line in, line out, and microphone connectors (if available on the riser)
disables the back panel connectors.
and Microsoft Windows Sound System compatible
20
Motherboard Description
1.8.2 Audio Subsystem Resources
The following table shows the IRQ, DMA channel, and base I/O address options for the audio
subsystem. Options are listed in order of preference specified by Yamaha. These options are
automatically chosen by the Plug and Play interface, so there are no default settings. Onboard
audio can be enabled or disabled in the Setup program.
Table 2.Audio Subsystem Resources
IRQ
Resource
Sound Blaster
(DMA playback, DMA shared with
Windows Sound System capture)
Windows Sound System
(DMA playback)
MPU-401
(IRQ shared with Sound Blaster)
MIDI / Game Port201h
†
AdLib
†
(Options)
10
7
5,7, 10,11
5
11
5,7, 10,11
DMA Channel
(Options)
1
0,1,3
0
0,1,3
I/O Address
(Options)
220-22Fh
240-24Fh
16 bytes on 16-byte
boundary in the
range of 220-280h
530-537h
E80-E87h
8 bytes on 8-byte
boundary in the
range of 530-F48h
330-331h
300-301h
2 bytes on 2-byte
boundary in the
range of 300-334h
1 byte on 1-byte
boundary in the
range of 201-20Fh
388-38Dh
6 bytes on 8-byte
boundary in the
range of 388-3F8h
1.8.3 Audio Drivers and Utilities
Audio software and utilities are available from Intel’s World Wide Web site (see Section 6.1).
Audio driver support is provided for the Microsoft Windows
†
Microsoft Windows NT
(versions 3.51 and 4.0), and IBM OS/2† Warp† (versions 3.0 and 4.0)
The audio connectors include the following connectors:
• Back panel connectors: Line In, Mic In, Line Out
• CD-ROM audio
• Hardware wavetable
1.8.4.1 CD-ROM Audio Connector
An optional 1 x 4-pin Creative Labs-type connector (J9N1) is available for connecting an internal
CD-ROM drive to the audio mixer. The connector is designed for audio add-in cards and is
compatible with most cables supplied with Creative Labs CD-ROM drives. Audio signals from the
riser are supported on the edge connector.
1.8.4.2 Hardware Wavetable Headers
Two 2 x 3-pin headers (J9M1, J7N1) are available for a wavetable add-in module. An optional
OPL4-ML reference design module that can be plugged into the motherboard may be licensed from
Yamaha Corporation. Compatible wavetable module cards are available from several vendors.
1.9 Hardware Monitor
The optional management extension hardware provides low-cost instrumentation capabilities on a
National Semiconductor LM78/79 chip. The features include:
• Integrated temperature sensor
• Fan speed sensors
• Power supply voltage monitoring to detect levels above or below acceptable values
• Remote reset capabilities from a remote peer or server through LANDesk
Version 3.0 and service layers
See Section 6.2 for information about the management extension hardware specification. For more
information, please check the following web site: http://www.national.com/pf/LM/
Client Manager,
1.10 Tamper Detection
If the riser is equipped with a tamper detection switch, the motherboard will emit a continuous
beep anytime the cover is opened and the A/C power cord is still connected. This warning is
intended to remind the user that 5 V standby power is still applied within the system. To avoid this
warning, unplug the power cord before opening the cover. The act of removing the cover will still
be recorded by circuitry on the motherboard, to be subsequently reported to any management suite
software in use.
CAUTION
Disconnecting the power cord can leave the system without an adequate electrical ground. Use
proper procedures to prevent electrostatic discharge (ESD) which could damage your system.
22
Motherboard Description
1.11 Onboard Networking
The onboard networking subsystem is an Ethernet† LAN interface that provides both 10Base-T and
100Base-TX connectivity. Onboard LAN can be enabled or disabled in the Setup program.
Features include:
• 32-bit direct bus mastering on the PCI bus
• Shared memory structure in the host memory that copies data directly to/from host memory
• 10Base-T and 100Base-TX capability using a single RJ-45 connector
• IEEE 802.3µ Auto-Negotiation for the fastest available connection
• Jumperless configuration; the LAN subsystem is completely software configurable
• Remote wake up controller
1.11.1 Intel 82557 LAN Controller
This device is the heart of the LAN subsystem. It provides the following functions:
• CSMA/CD protocol engine
• PCI compatibility
• DMA engine for movement of commands, status, and network data across the PCI bus
• Standard MII interface for access to IEEE 802.3µ -compliant physical layer devices
The physical layer interface provides the following:
• Integrated 10/100 Mbit/sec single chip solution
• Complete 10/100 Mbit/sec media independent interface compliance with MDI support
• Full duplex operation available in both 10 and 100 Mbit/sec modes
• 25 MHz clock for 10 and 100 Mbit/sec modes
• Single magnetics module for 10 and 100 Mbit/sec operation
• IEEE 802.3µ Auto-Negotiation support for 10Base-T, 10Base-T FDX, 100Base-TX FDX,
100Base-TX FDX-FC
• Parallel detection algorithm for legacy support of non-Auto-Negotiation enabled link partner
• Glueless interface to TX solution with single magnetics module
• LED function mapping support via MDI interface
• Support for a LAN activity LED on an NLX riser
‡
1.11.3 Remote Wakeup Controller
The Remote Wakeup ASIC performs the Wake on LAN† function of the motherboard via the
onboard LAN interface. When the system is powered off, the Remote Wakeup ASIC and the
82555 PHY remain powered by a 5 V standby voltage. The ASIC monitors network traffic at the
MII interface and when it detects a Magic Packet
system.
†
it asserts a wakeup signal that powers up the
If an external network interface card (NIC) with remote wakeup capabilities is added to the
system
‡
the NIC’s remote wakeup header must be connected to the header on an NLX riser.
The software for the LAN subsystem, including setup/diagnostic software and a readme file viewer
that lists supported drivers, is available on the web site. See Section 6.1.
1.12 Motherboard Connectors
The following figure shows the connectors on the motherboard.
Onboard
Video
Configuration
Jumper
J1J1
A. G. P.
J1K1
DIMM Sockets(3)
J1D1, J2D1
J2D2
J7N1
1
5
Yamaha Wavetable
J9M1
2
1
J9N1
4
6
Creative
Labs
CD-ROM
Supplemental Gold Finger
Edge Connector
A-channel
RAMBUS
Memory
Interface
Riser Gold Finger
Edge Connector
4
1
24
Configuration
Jumper
J1A1
Fan
1
3
J2B1
Slot 1
Connector
J4D1
Figure 5. Motherboard Connectors
OM06256
Motherboard Description
Table 3.CD Audio Connector (J9N1)
PinSignal Name
1Ground
2CD_IN-Left
3Ground
4CD_IN-Right
Table 4.Accelerated Graphics Port (J1K1)
PinSignal NamePinSignal NamePinSignal NamePinSignal Name
The following figure illustrates the onboard video configuration jumper at J1J1.
Onboard
Video
Configuration
J1J1
3
1
OM06521
Figure 7. Onboard Video Configuration Jumper Block
Table 7.Onboard Video Configuration Jumper Block (J1J1)
FunctionJumperConfiguration
Enable1-2Enables onboard video.
Disable2-3Disables onboard video and allows use of an add-in A.G.P. card or any video
on the riser.
NOTE
✏
Due to the location of the third DIMM socket, only half-length A.G.P. cards are supported.
28
Motherboard Description
1.15 Configuration Jumper
The following figure shows the location of the configuration jumper block on the motherboard.
Configuration
Jumper
3
1
J1A1
OM06252
Figure 8. Single Configuration Jumper Block
Table 8.Configuration Jumper Table (J1A1)
FunctionJumperConfiguration
Normal1-2The BIOS uses current configuration information and passwords for booting.
Configure2-3After the POST runs, Setup is run automatically, using BIOS defaults. The
maintenance menu is displayed.
RecoverynoneThe BIOS attempts to recover the BIOS configuration. A recovery diskette is
required.
CAUTION
Moving the jumper with the power on can damage your computer. Always turn off the power and
unplug the power cord from the computer before changing the jumper.
1.15.1 Normal Mode
This mode is for normal computer booting and operations. To enable this mode, pins 1 and 2 must
be connected on the configuration jumper (J1A1). The BIOS uses the current bus/processor
frequency ratio, configuration information, and passwords to boot the computer. Access to the
Setup program can be restricted using a supervisor or user password.
This mode is for configuring special BIOS settings, including processor speed and special
maintenance options. This mode is used when upgrading the BIOS, upgrading the processor, or
clearing the passwords. To enable this mode, pins 2 and 3 must be connected on the configuration
jumper (J1A1). In this mode, Setup automatically executes after the POST runs. No password is
required, and this mode overrides any passwords that are set. The Maintenance menu is the first
menu displayed. This menu provides options for setting the processor speed and clearing
passwords. All other Setup screens are available. Configure mode uses the default BIOS settings
for booting, not the current user or supervisor settings. The default settings include using the
lowest bus/processor frequency ratio the processor supports. User and supervisor settings are
preserved and used when the computer is rebooted.
For the configuration changes to take effect after exiting the Setup program, power down the
computer, set the configuration jumper to normal mode (see Section 1.15.1), and boot the
computer.
1.15.3 Recovery Mode
This mode is for recovering BIOS data. To enable this mode, no pins are connected on the
configuration jumper (J1A1). After the computer is powered-on, the BIOS attempts to upgrade or
recover the BIOS data from a floppy diskette in the floppy drive. If a diskette is not in the boot
drive, the BIOS runs the POST, does not boot the operating system, and displays a message that
the jumper is not properly installed. If the recovery fails with a diskette in the boot drive, a beep
code indicates that the recovery failed.
For the configuration changes to take effect after a successful recovery, power down the computer,
set the configuration jumper to normal mode (see Section 1.15.1), and boot the computer.
30
Motherboard Description
1.16 NLX Card Edge Connector
The NLX riser connector on the motherboard consists of a 340 (2x170) position and a
supplemental 26 (2x13) position gold finger contact. All edge connector pin definitions are
defined in the NLX specification, version 1.2.
According to the NLX specification, the motherboard edge connector provides the following:
• PCI signals (the motherboard supports up to four PCI devices)
• ISA signals
• 2 IDE channels
• 1 floppy drive
• Infrared signals
• Miscellaneous front panel signals
• Power connection for the motherboard
See Section 6.2 for information about the NLX Specification.
Table 9, Table 10, and Table 11 specify the pinouts located on the primary connector; Table 12
specifies the pinouts located on the supplemental connector. All edge connector pin definitions are
defined in the NLX specification, version 1.2.
X5FP_SPKR_EN **AUDIOIThis signal indicates if headphones have
been plugged into the front panel LINE OUT
jack. The signal is connected to one of the
wipers on the audio jack and is HIGH when
the headphones are plugged into the front
audio jack and LOW when they are not. The
signal is pulled high through a pull-up on the
motherboard (Typically 100K).
X6VOL_DN# **AUDIOIConnects to Volume Down switch on front
panel, appropriate pull-up resistor on
motherboard. The motherboard provides
debounce protection and a pull-up resistor.
X7GNDPWRNAGroundNA
X8SMI# **SYSISystem Management Interrupt that is an
input to the motherboard.
X9RESERVEDRESNAReservedNA
X10RESERVEDRESNAReservedNA
X11RESERVEDRESNAReservedNA
X12AGNDPWRNALow pass filtered ground for audio circuitry on
the riser.
X13MODEM_MICAUDIOOPre-amplified microphone mono output signal
Table 12.Signals, NLX Riser with Supplemental Connector
PinSignal NameTypeI/O *DescriptionSignal Type
Y5FP_MIC_EN **AUDIOIThis signal indicates if a microphone has
been plugged into the front panel MIC_IN
jack. The signal is connected to a wiper on
the MIC_IN jack and is LOW when the
microphone is plugged in and HIGH when it
is not. The signal is pulled LOW through a
pull down on the motherboard (Typically
100K).
Y6VOL_UP# **AUDIOIConnects to Volume Up switch on front
panel, appropriate pull-up resistor on
motherboard. The motherboard provides
debounce protection and a pull-up resistor.
Y7AC_RST# **AC’97OAC’97 master H/W reset.TTL
Y8AC_SD_IN **AC’97ISerial, time division, multiplexed, AC’97 input
stream to the motherboard from the codec
on the riser (output from the codec).
Y9GROUNDPWRNADigital (main motherboard) ground plane.NA
Y10AC_SD_OUT **AC’97OSerial, time division, multiplexed, AC’97
output from the motherboard to the codec on
the riser (input to the codec).
Y11AC_SYNC **AC’97O48KHz fixed rate sample sync signal from
the motherboard to the codec on the riser.
Y12AC_BIT_CLK **AC’97I12.288 MHz serial data clock.TTL
Y13MODEM_SPKRAUDIOOAnalog mono output signal from telephony
device to motherboard.
*I/O column: relative to motherboard, “O” = output, from motherboard to riser; “I” = input, from riser to motherboard.
**These signals are not supported.
(continued)
TTL
TTL
TTL
TTL
TTL
Analog
1V RMS
1.17 Reliability
The Mean Time Between Failures (MTBF) data is calculated from predicted data at 55 ºC.
Motherboard MTBF: 186,417 hours
Tables 14 and 15 list voltage and current specifications for a computer that contains the
motherboard, a 266 MHz Pentium II processor, 16 MB RAM, 512 KB cache, 3.5-inch floppy
drive, 2.1 GB IDE hard drive, and a 8X IDE CD-ROM drive. This information is provided only as
a guide for calculating approximate power usage with additional resources added.
Values for the Windows 95 desktop mode are measured at 640 x 480 x 256 colors and 60 Hz
refresh rate. AC watts are measured with a typical 145 W supply, nominal input voltage and
frequency, with true RMS wattmeter at the line input.
Table 14. DC Voltage
DC VoltageAcceptable Tolerance
+3.3 V± 4%
+5 V± 5%
+5 V SB (standby)± 5%
-5 V± 5%
+12 V± 5%
-12 V± 5%
Table 15. Power Usage
DC (amps) at:
ModeAC (watts) +3.3 V+5 V-5 V+12 V-12 V
DOS prompt, APM disabled631.2 A4.5 A0.1 A0.7 A0.2 A
Windows 95 desktop, APM disabled641.0 A5.3 A0.1 A0.6 A0.2 A
Windows 95 desktop, APM enabled, in
System Management Mode (SMM)
301.0 A1.0 A0.1 A0.2 A0.2 A
For typical configurations, the motherboard is designed to operate with at least a 200 W NLX
power supply (see Section 6.2 for the specification). Use a higher wattage supply for heavily
loaded configurations. The power supply must comply with the NLX power supply
recommendations.
40
Motherboard Description
1.20 Regulatory Compliance
This printed circuit assembly complies with the following safety and EMI regulations when
correctly installed in a compatible host system.
1.20.1 Safety
1.20.1.1 UL 1950 - CSA 950-95, 3rd edition, Dated 07-28-95
The Standard for Safety of Information Technology Equipment including Electrical Business
Equipment. (USA & Canada)
1.20.1.2 CSA C22.2 No. 950-93, 3rd Edition
The Standard for Safety of Information Technology Equipment including Electrical Business
Equipment. (Canada)
Generic Immunity Standard; Currently compliance is determined via testing to IEC 801-2, -3,
and -4. (Europe)
1.20.2.5 VCCI Class 2 (ITE)
Implementation Regulations for Voluntary Control of Radio Interference by Data Processing
Equipment and Electronic Office Machines. (Japan)
1.20.2.6 ICES-003, Issue 2
Interference-Causing Equipment Standard, Digital Apparatus. (Canada)
1.20.3 Product Certification Markings
This printed circuit assembly has the following product certification markings:
• European CE Marking: Consists of a marking on the board and shipping container.
• UL Recognition Mark: Consists of the UL File No. E139761 on the component side of the
board and the PB No. on the solder side of the board. Board material flammability is
94V-1 or -0.
• Canadian Compliance: Consists of small c followed by a stylized backward UR on component
side of board.
42
2 Motherboard Resources
NOTE
✏
For more detailed information about the resources used for onboard audio, see the Audio
Subsystem section in Chapter 1.
2.1 Memory Map
Table 16. Memory Map
Address Range (decimal) Address Range (hex) SizeDescription
1024 K - 393216 K100000 - 18000000383 MBExtended memory
1008 K - 1024 KFC000 - FFFFF16 KBBoot block
1000 K - 1008 KFA000 - FBFFF8 KBESCD (Plug and Play configuration and
DMI)
996 K - 1000 KF9000 - F9FFF4 KBReserved for BIOS
992 K - 996 KF8000 - F8FFF4 KBOEM Logo or Scan User Flash
928 K - 992 KE8000 - F7FFF64 KBPOST BIOS
896 K - 928 KE0000 - E7FFF32 KBPOST BIOS (Available as UMB)
800 K - 896 KC8000 - DFFFF96 KBAvailable high DOS memory (open to ISA
and PCI bus)
640 K - 800 KA0000 - C7FFF160 KBVideo memory and BIOS
639 K - 640 K9FC00 - 9FFFF1 KBExtended BIOS data (movable by memory
08- or 16-bitsAudio
18- or 16-bitsAudio / Parallel Port
28- or 16-bitsFloppy Drive
38- or 16-bitsParallel Port (for ECP or EPP) / Audio
4Reserved - Cascade Channel
516-bitsOpen
616-bitsOpen
716-bitsOpen
0377, bits 6:07 bitsSecondary IDE channel status port
0378 - 037F8 bytesLPT1
0388- 038D6 bytesAdLib (FM synthesizer)
03B4 - 03B52 bytesVideo (VGA)
03BA1 byteVideo (VGA)
03BC - 03BF4 bytesLPT3
03C0 - 03CA11 bytesVideo (VGA)
03CC1 byteVideo (VGA)
03CE - 03CF2 bytesVideo (VGA)
03D4 - 03D52 bytesVideo (VGA)
03DA1 byteVideo (VGA)
03E8 - 03EF8 bytesCOM3
03F0 - 03F56 bytesFloppy Channel 1
03F61 bytePrimary IDE channel command port
03F7 (Write)1 byteFloppy channel 1 command
03F7, bit 71 bitFloppy disk change channel 1
03F7, bits 6:07 bitsPrimary IDE channel status port
03F8 - 03FF8 bytesCOM1
04D0 - 04D12 bytesEdge/level triggered PIC
0530 - 05378 bytesWindows Sound System
0604 - 060B8 bytesWindows Sound System
LPTn + 400h8 bytesECP port, LPTn base address + 400h
0CF8 - 0CFB*4 bytesPCI configuration address register
0CF9**1 byteTurbo and reset control register
0CFC - 0CFF4 bytesPCI configuration data register
0E80 - 0E878 bytesWindows Sound System
0F40- 0F478 bytesWindows Sound System
0F86 - 0F872 bytesYamaha OPL3-SA3 configuration
FF00 - FF078 bytesIDE bus master register
FFA0 - FFA78 bytesPrimary bus master IDE registers
FFA8 - FFAF8 bytesSecondary bus master IDE registers
(continued)
*DWORD access only
**Byte access only
NOTE
✏
See the Audio section(s) in Chapter 1 for specific I/O addresses that can be used by the audio
components on your motherboard. This table does not list I/O addresses that may be used by
add-in cards in the system.
NMII/O Channel Check
0Reserved, Interval Timer
1Reserved, Keyboard Buffer Full
2Reserved, Cascade Interrupt From Slave PIC
3COM2*
4COM1*
5LPT2 (Plug and Play option) / Audio / User available
6Floppy Drive
7LPT1*
8Real Time Clock
9User available
10User available
11Windows Sound System* / User available
12Onboard Mouse Port (if present, else user available)
13Reserved, Math Coprocessor
14Primary IDE (if present, else user available)
15Secondary IDE (if present, else user available)
Device
Number (hex)
Function
Number (hex)Description
‡
‡
*Default, but can be changed to another IRQ
46
2.6 PCI Interrupt Routing Map
Motherboard Resources
This section describes interrupt sharing and how the interrupt signals are connected between the
‡
PCI expansion slots
and onboard PCI devices. The PCI specification specifies how interrupts can
be shared between devices attached to the PCI bus. In most cases, the small amount of latency
added by interrupt sharing does not affect the operation or throughput of the devices. In some
special cases where maximum performance is needed from a device, a PCI device should not share
an interrupt with other PCI devices. Use the following information to avoid sharing an interrupt
with a PCI add-in card.
PCI devices are categorized as follows to specify their interrupt grouping:
• INTA: By default, all add-in cards that require only one interrupt are in this category. For
almost all cards that require more than one interrupt, the first interrupt on the card is also
classified as INTA.
• INTB: Generally, the second interrupt on add-in cards that require two or more interrupts is
classified as INTB. (This is not an absolute requirement.)
• INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC and a
fourth interrupt is classified as INTD.
The PIIX4 PCI-to-ISA bridge has four programmable interrupt request (PIRQ) input signals. Any
PCI interrupt source (either onboard or from a PCI add-in card) connects to one of these PIRQ
signals. Because there are only four signals, some PCI interrupt sources are mechanically tied
together on the motherboard and therefore share the same interrupt. Table 21 lists the PIRQ
‡
signals and shows how the signals are connected to the PCI expansion slots
For example, assume an add-in card has one interrupt (group INTD) into the second PCI slot. In
this slot, an interrupt source from group INTA connects to the PIRQD signal, which is already
connected to the onboard video and USB PCI sources. The add-in card shares an interrupt with
these onboard interrupt sources.
Now, however, plug an add-in card that has one interrupt (group INTA) into the first PCI slot.
Plug a second add-in card that has two interrupts (groups INTA and INTB) into the second PCI
slot. INTA in the first slot is connected to signal PIRQA. INTA in the second slot is connected to
signal PIRQB, and INTB is connected to signal PIRQC. With no other cards added, the three
interrupt sources on the first two cards each have a PIRQ signal to themselves. Typically, they will
not share an interrupt.
The PIIX4 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 7, 9, 11, 14,
15). Typically, a device that does not share a PIRQ line will have a unique interrupt. However, in
certain interrupt-constrained situations, it is possible for two or more of the PIRQ lines to be
connected to the same IRQ signal.
48
3 Overview of BIOS Features
The motherboard uses an Intel/Phoenix BIOS, which is stored in flash memory and can be
upgraded using a disk-based program. In addition to the BIOS, the flash memory contains the
Setup program, Power-On Self Test (POST), Advanced Power Management (APM) software, the
PCI auto-configuration utility, and Windows 95-ready Plug and Play. See Section 6.2 for the
supported versions of these specifications.
This motherboard supports system BIOS shadowing, allowing the BIOS to execute from 64-bit
onboard write-protected DRAM.
The BIOS displays a message during POST identifying the type of BIOS and a the revision code.
The initial production BIOS is identified as 4N4XL0X0.86A.
3.1 BIOS Upgrades
A new version of the BIOS can be upgraded from a diskette using the iFLASH.EXE utility that is
available from Intel. This utility does BIOS upgrades as follows:
• Updates the flash BIOS from a file on a disk
• Updates the language section of the BIOS
• Makes sure that the upgrade BIOS matches the target system to prevent accidentally installing
a BIOS for a different type of system.
BIOS upgrades and the iFLASH.EXE utility are available from Intel through the Intel World Wide
Web site. See Section 6.1 for information about this site.
NOTE
✏
Please review the instructions distributed with the upgrade utility before attempting a BIOS
upgrade.
The 2-Mbit flash component is organized as 256 KB x 8 bits and is divided into areas as described
in Table 22. The table shows the addresses in the ROM image in normal mode (the addresses
change in BIOS Recovery Mode).
Table 22. Flash Memory Organization
Address (Hex)SizeDescription
FFFFC000 - FFFFFFFF16 KBBoot Block
FFFFA000 - FFFFBFFF8 KBVital Product Data (VPD) Extended System Configuration Data
(ESCD) (DMI configuration data / Plug and Play data)
FFFF9000 - FFFF9FFF4 KBUsed by BIOS (e.g., for Event Logging)
FFFF8000 - FFFF8FFF4 KBOEM logo or Scan Flash Area
FFFC0000 - FFFF7FFF224 KBMain BIOS Block
3.3 Plug and Play: PCI Autoconfiguration
The BIOS automatically configures PCI devices and Plug and Play devices. PCI devices may be
onboard or add-in cards. Plug and Play devices are ISA add-in cards built to meet the Plug and
Play specification. Autoconfiguration lets a user insert or remove PCI or Plug and Play cards
without having to configure the system. When a user turns on the system after adding a PCI or
Plug and Play card, the BIOS automatically configures interrupts, the I/O space, and other system
resources. Any interrupts set to Available in Setup are considered to be available for use by the
add-in card.
PCI interrupts are distributed to available ISA interrupts that have not been assigned to an ISA card
or to system resources. The assignment of PCI interrupts to ISA IRQs is non-deterministic. PCI
devices can share an interrupt, but an ISA device cannot share an interrupt allocated to PCI or to
another ISA device. Autoconfiguration information is stored in the extended system configuration
data (ESCD) format.
For information about the versions of PCI and Plug and Play supported by this BIOS, see
Section 6.2. Copies of the specifications can be obtained from the Intel World Wide Web site (see
Section 6.1).
50
Overview of BIOS Features
3.4 PCI IDE Support
If Auto is selected as a primary or secondary IDE device (see Section 4.2.2) in Setup, the BIOS
automatically sets up the two local-bus IDE connectors with independent I/O channel support. The
IDE interface supports hard drives up to PIO Mode 4 and recognizes any ATAPI devices, including
CD-ROM drives and tape drives (see Section 6.2 for the supported version of ATAPI). The BIOS
determines the capabilities of each drive and configures them so as to optimize capacity and
performance. To take advantage of the high-capacity storage devices, hard drives are automatically
configured for logical block addressing (LBA) and to PIO Mode 3 or 4, depending on the
capability of the drive. To override the autoconfiguration options, use the specific IDE device
options in Setup. The ATAPI specification recommends that ATAPI devices be configured as
shown in Table 23.
Table 23. Recommendations for Configuring an ATAPI Device
Primary CableSecondary Cable
Configuration
Normal, no ATAPIATA
Disk and CD-ROM for enhanced IDE systemsATAATAPI
Legacy IDE system with only one cableATAATAPI
Enhanced IDE with CD-ROM and a tape or two CD-ROMsATAATAPIATAPI
Drive 0Drive 1Drive 0Drive 1
3.5 ISA Plug and Play
If Plug and Play operating system (see Section 4.3) is selected in Setup, the BIOS autoconfigures
only ISA Plug and Play cards that are required for booting (IPL devices). If Plug and Play
operating system is not selected in Setup, the BIOS autoconfigures all Plug and Play ISA cards.
3.6 ISA Legacy Devices
Since ISA legacy devices are not autoconfigurable, the resources for them must be reserved.
Resources can be reserved in the Setup program.
Desktop Management Interface (DMI) is an interface for managing computers in an enterprise
environment. The main component of DMI is the management information format (MIF) database,
which contains information about the computing system and its components. Using DMI, a system
administrator can obtain the system types, capabilities, operational status, and installation dates for
system components. The MIF database defines the data and provides the method for accessing this
information. The BIOS enables applications such as Intel LANDesk Client Manager to use DMI.
The BIOS stores and reports the following DMI information:
• BIOS data, such as the BIOS revision level
• Fixed-system data, such as peripherals, serial numbers, and asset tags
• Resource data, such as memory size, cache size, and processor speed
• Dynamic data, such as event detection and error logging
OEMs can use a utility that programs flash memory so the BIOS can report on system and chassis
information. This utility is available through Intel sales offices. See Section 6.1 for information
about contacting a local Intel sales office. See Section 6.2 for information about the latest DMI
specification.
DMI does not work directly under non-Plug and Play operating systems (e.g., Windows NT).
However, the BIOS supports a DMI table interface for such operating systems. Using this support,
a DMI service-level application running on a non-Plug and Play OS can access the DMI BIOS
information.
3.8 Advanced Power Management (APM)
The BIOS supports APM and standby mode. See Section 6.2 for the version of the APM
specification that is supported. The energy saving standby mode can be initiated in the following
ways:
• Time-out period specified in Setup
• Suspend/resume switch connected to the front panel sleep connector
• From the operating system, such as the Suspend menu item in Windows 95
In standby mode, the motherboard reduces power consumption by using SMM capabilities,
spinning down hard drives, and reducing power to or turning off VESA
monitors. Power-management mode can be enabled or disabled in Setup (see Section 4.5).
While in standby mode, the system retains the ability to respond to external interrupts and service
requests, such as incoming faxes or network messages. Any keyboard or mouse activity brings the
system out of standby mode and immediately restores power to the monitor.
The BIOS enables APM by default; but the operating system must support an APM driver for the
power-management features to work. For example, Windows 95 supports the power-management
features upon detecting that APM is enabled in the BIOS.
†
DPMS-compliant
52
Overview of BIOS Features
3.9 Language Support
Five languages will be available: American English, German, Italian, French, and Spanish. The
BIOS includes extensions to support the Kanji character set and other non-ASCII character sets.
Translations of other languages may become available at a later date.
The default language is American English, which is always present unless another language is
programmed into the BIOS using the flash memory update utility. See Section 3.1 for information
about the BIOS update utility.
3.10 Boot Options
In the Setup program, the user can choose to boot from a floppy drive, hard drive, CD-ROM, or the
network. The default setting is for the floppy drive to be the primary boot device and the hard
drive to be the secondary boot device. By default the third and fourth devices are disabled.
Booting from CD-ROM is supported in compliance to the El Torito bootable CD-ROM format
specification. See Section 6.2 for information about the El Torito specification. Under the Boot
menu in the Setup program, CD-ROM is listed as a boot device. Boot devices are defined in
priority order. If the CD-ROM is selected as the boot device, it must be the first device.
The network can be selected as a boot device. This selection allows booting from a network add-in
card with a remote boot ROM installed.
3.11 OEM Logo or Scan Area
A 4 KB flash-memory user area at memory location FFFF8000h-FFFF8FFFh is for displaying a
custom OEM logo during POST. A utility is available from the Intel web site (see Section 6.1) to
assist with installing a logo into the flash memory. Contact Intel customer support for further
information. See Section 6.1 for information on contacting Intel customer support.
3.12 USB Support
The USB connectors allow any of several USB devices to be attached to the computer. Typically,
the device driver for USB devices is managed by the operating system. However, because
keyboard and mouse support may be needed in the Setup program before the operating system
boots, the BIOS supports USB keyboards and mice.
3.13 BIOS Setup Access
Access to the Setup program can be restricted using passwords. User and supervisor passwords
can be set using the Security menu in Setup. The default is no passwords enabled. See Section 4.4
for information about setting user and supervisor passwords.
Some types of failure can destroy the BIOS. For example, the data can be lost if a power outage
occurs while the BIOS is being updated in flash memory. The BIOS can be recovered from a
diskette using the BIOS recovery mode (see Section 1.15.3).
To create a BIOS recovery diskette, a bootable diskette must be created and the recovery files
copied to it. The recovery files are available from Intel, contact Intel customer support for further
information. See Section 6.1 for information on contacting Intel customer support.
54
4 BIOS Setup Program
The Setup program is for viewing and changing the BIOS settings for a computer. Setup is
accessed by pressing the <F2> key after the Power-On Self Test (POST) memory test begins and
before the operating system boot begins. Table 24 shows the menus available from the menu bar at
the top of the Setup screen.
Table 24. Setup Menu Bar
Setup Menu ScreenDescription
MaintenanceSets the processor speed and clears the Setup passwords.
MainAllocates resources for hardware components.
AdvancedSets advance features available through the chipset.
SecuritySets passwords and security features.
PowerSets power management features.
BootSets boot options and power supply controls.
ExitSaves or discards changes.
Table 25 shows the function keys available for menu screens.
Table 25. Setup Function Keys
Setup KeyDescription
<F1> or <Alt-H>Brings up a help screen for the current item.
<Esc>Exits the menu.
<←> or <→>
<↑> or <↓>
<Home> or <End>Moves cursor to top or bottom of the window.
<PgUp> or <PgDn>Moves cursor to top or bottom of the window.
<F5> or <->Selects the previous value for a field.
<F6> or <+> or <Space>Selects the next value for a field.
<F9>Load the default configuration values for the current menu.
<F10>Save the current values and exit Setup.
<Enter>Executes command or selects the submenu.
< + > and < - >Moves a device up and down the boot order list.
Selects a different menu screen.
Moves cursor up or down.
This menu is for setting the processor speed and clearing the Setup passwords. Setup only displays
this menu in configure mode. See Section 1.15.2 for information about setting configure mode.
Table 26. Maintenance Menu
FeatureOptionsDescription
Processor Speed
Clear All PasswordsNoneClears the user and supervisor passwords.
• 233
• 266
• 300
Specifies the processor speed in megahertz.
4.2 Main Menu
This menu reports processor and memory information, and is for configuring the language, system
date, system time, floppy options, and IDE devices.
Table 27. Main Menu
FeatureOptionsDescription
Processor TypeNoneDisplays processor type.
Processor SpeedNoneDisplays processor speed.
Cache RAMNoneDisplays size of L2 cache.
Total MemoryNoneDisplays the total amount of RAM on the motherboard.
BIOS VersionNoneDisplays the version of the BIOS.
Language
System TimeHour, minute,
System DateMonth, day, and
Floppy Options,
submenu
Primary IDE Master,
submenu
Primary IDE Slave,
submenu
Secondary IDE
Master, submenu
Secondary IDE
Slave, submenu
• English (US)
(default)
• Italiana
• Français
• Deutsche
• Español
and second
year
NoneConfigures the diskette drives. When selected, displays the
NoneReports type of a connected IDE device. When selected, displays
NoneReports type of a connected IDE device. When selected, displays
NoneReports type of a connected IDE device. When selected, displays
NoneReports type of a connected IDE device. When selected, displays
Selects the current default language used by the BIOS.
Specifies the current time.
Specifies the current date.
Floppy Options submenu. See Section 4.2.1.
the Primary IDE Master submenu. See Section 4.2.2.
the Primary IDE Slave submenu. See Section 4.2.2.
the Secondary IDE Master submenu. See Section 4.2.2.
the Secondary IDE Slave submenu. See Section 4.2.2.
56
4.2.1 Floppy Options Submenu
This submenu is for configuring floppy drives.
Table 28. Floppy Options Submenu
FeatureOptionsDescription
Diskette A:
Diskette B:
Floppy Write Protect
• Disabled
• 360 KB, 5.25 inch
• 1.2 MB, 5.25 inch
• 720 KB, 3.5 inch
• 1.44/1.25 MB, 3.5 inch
(default)
• 2.88 MB, 3.5 inch
• Disabled (default)
• 360 KB, 5.25 inch
• 1.2 MB, 5.25 inch
• 720 KB, 3.5 inch
• 1.44/1.25 MB, 3.5 inch
• 2.88 MB, 3.5 inch
• Disabled (default)
• Enabled
BIOS Setup Program
Specifies the capacity and physical size
of the diskette drive A.
Specifies the capacity and physical size
of the diskette drive B.
Disables or enables write protect for the
diskette drive(s).
This submenu is for configuring the IDE device features for the following:
• Primary IDE master
• Primary IDE slave
• Secondary IDE master
• Secondary IDE slave
Table 29. IDE Device Configuration Submenus
FeatureOptionsDescription
Type
Cylinders1 to
Heads1 to 16Specifies number of disk heads.
Sectors1 to 64Specifies number of disk sectors.
Maximum CapacityNoneReports maximum capacity for the hard disk.
Multi-Sector Transfers
LBA Mode Control
None
•
ATAPI Removable
•
CD-ROM
•
IDE Removable
•
User
•
Auto (default)
•
XXXX
Disabled
•
2 Sectors
•
4 Sectors
•
8 Sectors
•
16 Sectors (default)
•
Disabled
•
Enabled (default)
•
Specifies the IDE configuration mode for IDE
devices.
User allows the cylinders, heads, and sectors
fields to be changed.
Auto automatically fills in the values for the
cylinders, heads, and sectors fields.
Specifies number of disk cylinders.
Value calculated from number of cylinders, heads,
and sectors.
Specifies number of sectors per block for
transfers from the hard drive to memory.
Check the hard drive’s specifications for optimum
setting of this feature.
Enables or disables logical block addressing (LBA)
in place of the Cylinders, Heads, and Sectors
fields.
58
32 Bit I/O
Transfer Mode
Ultra DMA
Disabled (default)
•
Enabled
•
Standard
•
Fast PIO 1
•
Fast PIO 2
•
Fast PIO 3
•
Fast PIO 4 (default)
•
Disabled (default)
•
Mode 0
•
Mode 1
•
Mode 2
•
CAUTION
Changing the LBA Mode Control after a
hard drive was formatted can corrupt data
on the hard drive.
Enables or disables 32 bit IDE data transfers
between the processor and the IDE device.
Specifies method for transferring data between
the hard drive and system memory.
Specifies the ultra DMA mode for the hard drive.
4.3 Advanced Menu
This menu is for setting advance features that are available through the computer’s chipset.
Table 30. Advanced Menu
FeatureOptionsDescription
Plug & Play O/S
Reset Configuration Data
Memory Cache
Resource Configuration,
submenu
Peripheral Configuration,
submenu
Keyboard Features,
submenu
Video Configuration,
submenu
DMI Event Logging,
submenu
• No
• Yes (default)
• No (default)
• Yes
• Disabled
• Enabled (default)
NoneConfigures memory blocks and IRQs for legacy ISA
NoneConfigures peripheral ports and devices. When
NoneConfigures keyboard features. When selected,
NoneConfigures video features. When selected,
NoneConfigures DMI Events Logging. When selected,
Specifies if a Plug and Play operating system is being
used.
No lets BIOS configure all devices.
Yes lets the operating system configure Plug and
Play devices. Not required with a Plug and Play
operating system.
Clears the BIOS configuration data on the next boot.
Enables or disables the memory cache.
devices. When selected, displays the Resource
Configuration submenu. See Section 4.3.1.
selected, displays the Peripheral Configuration
submenu. See Section 4.3.2.
displays the Keyboard Features submenu. See
Section 4.3.3.
displays the Video Configuration submenu.
See Section 4.3.4.
displays the DMI Events Logging submenu. See
Section 4.3.5.
An * (asterisk) next to an IRQ indicates an IRQ conflict.
Reserves specific
upper memory blocks
for use by legacy ISA
devices.
Indicates if ECC
memory is present.
Reserves specific
IRQs for use by
legacy ISA devices.
60
4.3.2 Peripheral Configuration Submenu
This submenu is for the configuring the computer peripherals.
Table 32. Peripheral Configuration Submenu
FeatureOptionsDescription
Serial Port A
Serial Port B
Mode
Parallel Port
Mode
Floppy Disk
Controller
IDE Controller
Audio
LAN
Legacy USB
Support
• Disabled
• Enabled
• Auto (default)
• Disabled
• Enabled
• Auto (default)
• Normal (default)
• IrDA
• ASK-IR
• Disabled
• Enabled
• Auto (default)
• Output Only
• Bi-directional (default)
• EPP
• ECP
• Disabled
• Enabled (default)
• Disabled
• Primary
• Secondary
• Both (default) (primary
and secondary)
• Disabled
• Enabled (default)
• Disabled
• Enabled (default)
• Disabled (default)
• Enabled
Used to configure serial port A.
Auto assigns the first free COM port, normally COM1,
the address 3F8h and the interrupt IRQ4.
An * (asterisk) indicates a conflict with another device.
Used to configure serial port B.
Auto assigns the first free COM port, normally COM2,
the address 2F8h and the interrupt IRQ3.
An * (asterisk) indicates a conflict with another device.
If either serial port address is set, that address will not
appear in the list of options for the other serial port.
If an ATI mach32
active as an add-in card, the COM4, 2E8h address will
not appear in the list of options for either serial port.
Sets the mode for Serial Port B for normal (COM2) or
infrared applications.
Configures the parallel port.
Auto assigns LPT1 the address 378h and the interrupt
IRQ7.
An * (asterisk) indicates a conflict with another device.
Selects the mode for the parallel port.
Output Only operates in AT
Bi-directional operates in bi-directional PS/2-compatible
mode.
EPP is Extended Parallel Port mode, a high-speed bi-
directional mode.
ECP is Enhanced Capabilities Port mode, a high-speed
bi-directional mode.
Configures the floppy disk controller.
Configures the IDE controller.
Enables or disables the onboard audio subsystem.
Enables or disables the onboard LAN subsystem.
Enables or disables BIOS support for USB keyboards
and mice.
Sets the power on state of the Numlock feature
on the numeric keypad of the keyboard.
Enables the key click option.
Selects the key repeat rate.
Selects the delay before key repeat.
4.3.4 Video Configuration Submenu
Table 34. Video Configuration Submenu
FeatureOptionsDescription
Palette Snooping
• Disabled (default)
• Enabled
4.3.5 DMI Event Logging Submenu
Table 35. DMI Event Logging Submenu
FeatureOptionsDescription
Event Log CapacityNoneIndicates if there is space available in the event log.
Event Log ValidityNoneIndicates if the contents of the event log are valid.
View DMI Event LogNoneEnables viewing of DMI event log.
Clear All DMI Event Logs
Event Logging
ECC Event Logging
Mark DMI Events as readNoneMarks all DMI events as read.
• No (default)
• Yes
• Disabled
• Enabled (default)
• Disabled (default)
• Enabled
Controls the ability of a primary PCI graphics
controller to share a common palette with an ISA
add-in video card.
Clears the DMI Event Log after rebooting.
Enables logging of DMI events.
62
4.4 Security Menu
This menu is for setting passwords and security features for the computer.
Table 36. Security Menu
FeatureOptionsDescription
User Password IsNoneReports if there is a user password set.
Supervisor Password IsNoneReports if there is a supervisor
Set User PasswordPassword can be up to seven
alphanumeric characters.
Set Supervisor PasswordPassword can be up to seven
alphanumeric characters.
Unattended Start
• Disabled (default)
• Enabled
BIOS Setup Program
password set.
Sets the user password.
Sets the supervisor password.
Sets the unattended start feature.
When enabled, the computer boots,
but the keyboard is locked. Enter the
user password unlocks the computer.
The user password is required to boot
from a floppy diskette.
4.5 Power Menu
This menu is for setting power management features for the computer.
Table 37. Power Menu
FeatureOptionsDescription
Power Management
Inactivity Timer
Hard Drive
VESA Video Power Down
• Disabled
• Enabled (default)
• Off (default)
• 1 Minute
• 2 Minutes
• 4 Minutes
• 6 Minutes
• 8 Minutes
• 12 Minutes
• 16 Minutes
• Disabled
• Enabled (default)
• Disabled
• Enabled (default)
Enables or disables the BIOS power
management feature.
Sets the amount of time before the
computer enters standby mode.
Enables the hard disks to be power
managed during standby and
suspend modes.
Enables power management for
video during standby and suspend
modes.
This menu is for setting the boot features for the computer.
Table 38. Boot Menu
FeatureOptionsDescription
Restore on AC/Power
Loss
On Modem Ring
On LAN
Quick Boot Mode
Scan User Flash Area
First Boot Device
Second Boot Device
Third Boot Device
Fourth Boot Device
Fifth Boot Device
Hard Drive, submenuNoneLists drives available. When selected, displays the
Removable Devices,
submenu
• Stay Off
• Last State (default)
• Power On
• Stay Off
• Power On (default)
• Stay Off
• Power On (default)
• Enabled (default)
• Disabled
• Enabled
• Disabled (default)
• Hard Drive
• Removable devices
• ATAPI CD-ROM
• LANDesk (R)
Services Agent
• Network boot
NoneLists available removable devices. When selected,
Specifies action following a power failure if computer is
powered on.
Stay Off keeps power off until power button pressed.
Power On restores previous power state before power
was lost.
Specifies action of computer when power is off and an
incoming call is detected on an installed modem.
Specifies action of computer when power is off and
LAN activity is detected on.
Enables the computer to boot without running certain
POST tests.
Enables the BIOS to scan the flash memory for user
binaries.
Specifies the boot sequence from the available
devices. To specify boot sequence:
1. Select the boot device with <↑> or <↓>.
2. Press <+> to move the device up the list or <-> to
move the device down the list.
The operating system assigns drive letters to the
devices in the order listed. The order can be changed
and therefore the drive lettering for these devices.
Hard Drive submenu. See Section 4.6.1.
displays the Removable Devices submenu. See
Section 4.6.2.
4.6.1 Hard Drive Submenu
Table 39. Hard Drive Submenu
OptionsDescription
• Installed hard drive
• Bootable ISA Cards
64
Specifies the boot sequence for the hard drives attached to the computer. To
specify boot sequence:
1. Select the boot device with <↑> or <↓>.
2. Press <+> to move the device up the list or <-> to move the device down
the list.
The operating system assigns drive letters to the devices in the order listed.
The order can be changed and therefore the drive lettering for these devices.
4.6.2 Removable Devices Submenu
Table 40. Removable Devices Submenu
OptionsDescription
• Legacy Floppy Drives
Specifies the boot sequence for the removable devices attached to the
computer. To specify boot sequence:
1. Select the boot device with <↑> or <↓>.
2. Press <+> to move the device up the list or <-> to move the device down
the list.
The operating system assigns drive letters to the devices in the order listed.
The order can be changed and therefore the drive lettering for these devices.
4.7 Exit Menu
This section describes how to exit the Setup program. The screen features have no options.
Table 41. Exit Menu
BIOS Setup Program
FeatureDescription
Exit Saving ChangesExits Setup and saves the changes in CMOS RAM.
Exit Discarding ChangesExits Setup program without saving any changes. Any changes made in
Setup are not saved.
Load Setup DefaultsReturns all of the Setup options to their defaults. The default Setup values are
loaded from the ROM table.
Load Custom DefaultsLoads the setup settings from the Custom Defaults.
Save Custom DefaultsNormally, the BIOS reads the setup settings from flash memory. If this
memory is corrupted, the BIOS uses the custom defaults. If no custom
defaults are set, the BIOS uses the factory defaults.
Discard ChangesDiscards any changes made without exiting Setup. The option values that
were present when the computer was turned on are used.
Fixed Disk 0 Failure or
Fixed Disk 1 Failure or
Fixed Disk Controller Failure
Incorrect Drive A type - run
SETUP
Incorrect Drive B type - run
SETUP
Invalid NVRAM media typeProblem with NVRAM (CMOS) access.
Keyboard controller errorThe keyboard controller failed test. Try replacing the keyboard.
Keyboard errorKeyboard not working.
Keyboard error nnBIOS discovered a stuck key and displays the scan code nn for the stuck
Keyboard locked - Unlock key
switch
Monitor type does not match
CMOS - Run SETUP
Operating system not foundOperating system cannot be located on either drive A: or drive C:. Enter
Parity Check 1Parity error found in the system bus. BIOS attempts to locate the
Parity Check 2Parity error found in the I/O bus. BIOS attempts to locate the address
Press <F1> to resume, <F2> to
Setup
nnnn
Drive A: or B: is present but fails the POST diskette tests. Ensure that
the drive controller is enabled, the drive is correctly installed, and the
drive type is properly defined in Setup.
Extended memory not working or not configured properly at offset
The hex number
Extended, or Shadow memory) that failed the memory test. Each 1 in the
map indicates a failed bit.
Fixed disk is not working or not configured properly. Check to see if fixed
disk is installed properly. Run Setup be sure the fixed-disk type is
correctly identified and enabled.
Type of floppy drive for drive A: not correctly identified in Setup.
Type of floppy drive for drive B: not correctly identified in Setup.
key.
Unlock the system to proceed.
Monitor type not correctly identified in Setup.
Setup and see if fixed disk and drive A: are properly identified.
address and display it on the screen. If it cannot locate the address, it
displays ????.
and display it on the screen. If it cannot locate the address, it displays
????.
Displayed after any recoverable error message. Press <F1> to start the
boot process or <F2> to enter Setup and change any settings.
Real time clock errorReal-time clock fails BIOS test. May require motherboard repair.
Shadow RAM Failed at offset:
nnnn
System battery is dead Replace and run SETUP
System cache error - Cache
disabled
System CMOS checksum bad run SETUP
System RAM Failed at offset:
nnnn
System timer errorThe timer test failed. Requires repair of system motherboard.
(continued)
Shadow RAM failed at offset
was detected.
The CMOS clock battery indicator shows the battery is dead. Replace
the battery and run Setup to reconfigure the system.
RAM cache failed the BIOS test. BIOS disabled the cache.
System CMOS RAM has been corrupted or modified incorrectly, perhaps
by an application program that changes data stored in CMOS. Run Setup
and reconfigure the system either by getting the default values and/or
making your own selections.
System RAM failed at offset
was detected.
nnnn
of the 64 KB block at which the error
nnnn
of the 64 KB block at which the error
5.2 Port 80h POST Codes
During the POST, the BIOS generates diagnostic progress codes (POST codes) to I/O port 80h. If
the POST fails, execution stops and the last POST code generated is left at port 80h. This code is
useful for determining the point where an error occurred.
Displaying the POST codes requires an add-in card (often called a POST card). The POST card
can decode the port and display the contents on a medium such as a seven-segment display. These
cards can be purchased from JDR Microdevices or other sources.
The following table provides the POST codes that can be generated by the BIOS. Some codes are
repeated in the table because that code applies to more than one operation.
Table 43. Port 80h Codes
CodeDescription of POST Operation
02hVerify real mode
03hDisable non-maskable interrupt (NMI)
04hGet processor type
06hInitialize system hardware
08hInitialize chipset with initial POST values
09hSet IN POST flag
0AhInitialize CPU registers
0BhEnable CPU cache
0ChInitialize caches to initial POST values
0EhInitialize I/O component
0FhInitialize the local bus IDE
10hInitialize power management
68
continued
☛
Error Messages and Beep Codes
Table 43.Port 80h Codes
CodeDescription of POST Operation Currently In Progress
11hLoad alternate registers with initial POST valuesnew
12hRestore CPU control word during warm boot
13hInitialize PCI bus mastering devices
14hInitialize keyboard controller
16hBIOS ROM checksum
17hInitialize cache before memory autosize
18h8254 timer initialization
1Ah8237 DMA controller initialization
1ChReset programmable interrupt controller
20hTest DRAM refresh
22hTest keyboard controller
24hSet ES segment register to 4 GB
26hEnable A20 line
28hAutosize DRAM
29hInitialize POST memory manager
2AhClear 512 KB base RAM
2ChRAM failure on address line
2EhRAM failure on data bits
2FhEnable cache before system BIOS shadow
30hRAM failure on data bits
32hTest CPU bus-clock frequency
33hInitialize POST dispatch manager
34hTest CMOS RAM
35hInitialize alternate chipset registers
36hWarm start shut down
37hReinitialize the chipset (MB only)
38hShadow system BIOS ROM
39hReinitialize the cache (MB only)
3AhAutosize cache
3ChConfigure advanced chipset registers
3DhLoad alternate registers with CMOS valuesnew
40hSet Initial CPU speed new
42hInitialize interrupt vectors
44hInitialize BIOS interrupts
45hPOST device initialization
46hCheck ROM copyright notice
47hInitialize manager for PCI option ROMs
48hCheck video configuration against CMOS RAM data
CodeDescription of POST Operation Currently In Progress
49hInitialize PCI bus and devices
4AhInitialize all video adapters in system
4BhDisplay QuietBoot screen
4ChShadow video BIOS ROM
4EhDisplay BIOS copyright notice
50hDisplay CPU type and speed
51hInitialize EISA motherboard
52hTest keyboard
54hSet key click if enabled
56hEnable keyboard
58hTest for unexpected interrupts
59hInitialize POST display service
5AhDisplay prompt "Press F2 to enter SETUP"
5BhDisable CPU cache
5ChTest RAM between 512 and 640 KB
60hTest extended memory
62hTest extended memory address lines
64hJump to UserPatch1
66hConfigure advanced cache registers
67hInitialize multiprocessor APIC
68hEnable external and processor caches
69hSetup System Management Mode (SMM) area
6AhDisplay external L2 cache size
6ChDisplay shadow-area message
6EhDisplay possible high address for UMB recovery
70hDisplay error messages
72hCheck for configuration errors
74hTest real-time clock
76hCheck for keyboard errors
7AhTest for key lock on
7ChSet up hardware interrupt vectors
7EhInitialize coprocessor if present
80hDisable onboard Super I/O ports and IRQs
81hLate POST device initialization
82hDetect and install external RS232 ports
83hConfigure non-MCD IDE controllers
84hDetect and install external parallel ports
85hInitialize PC-compatible PnP ISA devices
(continued)
70
continued
☛
Error Messages and Beep Codes
Table 43.Port 80h Codes
CodeDescription of POST Operation Currently In Progress
86hRe-initialize onboard I/O ports
87hConfigure motherboard configurable devices
88hInitialize BIOS Data Area
89hEnable Non-Maskable Interrupts (NMIs)
8AhInitialize extended BIOS data area
8BhTest and initialize PS/2 mouse
8ChInitialize floppy controller
8FhDetermine number of ATA drives
90hInitialize hard-disk controllers
91hInitialize local-bus hard-disk controllers
92hJump to UserPatch2
93hBuild MPTABLE for multiprocessor boards
94hDisable A20 address line (Rel. 5.1 and earlier)
95hInstall CD ROM for boot
96hClear huge ES segment register
97hFix up multiprocessor table
98hSearch for option ROMs
99hCheck for SMART Drive
9AhShadow option ROMs
9ChSet up power management
9EhEnable hardware interrupts
9FhDetermine number of ATA and SCSI drives
A0hSet time of day
A2hCheck key lock
A4hInitialize typematic rate
A8hErase F2 prompt
AahScan for F2 key stroke
AchEnter SETUP
AehClear IN POST flag
B0hCheck for errors
B2hPOST done - prepare to boot operating system
B4hOne short beep before boot
B5hTerminate QuietBoot
B6hCheck password (optional)
B8hClear global descriptor table
B9hClean up all graphics
BahInitialize DMI parameters
BBhInitialize PnP Option ROMs
CodeDescription of POST Operation Currently In Progress
BChClear parity checkers
BDhDisplay MultiBoot menu
BehClear screen (optional)
BFhCheck virus and backup reminders
C0hTry to boot with INT 19h
C1hInitialize POST Error Manager (PEM)
C2hInitialize error logging
C3hInitialize error display function
C4hInitialize system error handler
E0hInitialize the chipset
E1hInitialize the bridge
E2hInitialize the processor
E3hInitialize system timer
E4hInitialize system I/O
E5hCheck force recovery boot
E6hChecksum BIOS ROM
E7hGo to BIOS
E8hSet huge segment
E9hInitialize multiprocessor
EahInitialize OEM special code
EbhInitialize PIC and DMA
EchInitialize memory type
EdhInitialize memory size
EehShadow boot block
EfhSystem memory test
F0hInitialize interrupt vectors
F1hInitialize runtime clock
F2hInitialize video
F3hInitialize beeper
F4hInitialize boot
F5hClear huge segment
F6hBoot to mini-DOS
F7hBoot to full DOS
(continued)
72
Error Messages and Beep Codes
5.3 BIOS Beep Codes
Beep codes represent a terminal error. If the BIOS detects a terminal error condition, it outputs an
error beep code, halts the POST, and attempts to display a port 80h code on the POST card’s LED
display.
Table 44. Beep Codes
Beeps80h CodeDescription
1B4hOne short beep before boot
1-298hSearch for option ROMs
1-2-2-316hBIOS ROM checksum
1-3-1-120hTest DRAM refresh
1-3-1-322hTest 8742 keyboard controller
1-3-4-12ChRAM failure on address line
1-3-4-32EhRAM failure on data bits
1-4-1-130hRAM failure on data bits
2-1-2-346hCheck ROM copyright notice
2-2-3-158hTest for unexpected interrupts
EPPEnhanced Parallel PortIEEE 1284 standard, Mode [1 or 2], v1.7
Version 2.1, June 16, 1997
American Megatrends Inc., Award Software International
Inc., Dell Computer Corporation, Intel Corporation,
Phoenix Technologies Ltd., SystemSoft Corporation
http://www.ptltd.com/techs/specs.html
Version 1.0, January 25, 1995
Phoenix Technologies Ltd., IBM Corporation. The El
Torito specification is available on the Phoenix Web site
Revision 1.0, January 15, 1996
Compaq Computer Corporation, Digital Equipment
Corporation, IBM PC Company, Intel Corporation,
Microsoft Corporation, NEC, Northern Telecom
http://www.intel.com/
76
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