Intel E7500 MCH, Intel E7501 MCH Thermal Design Manual
Intel® E7500 and Intel® E7501
Chipsets MCH
Thermal Design Guide for Embedded Applications
March 2003
Order Number: 273819-002
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future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
®
The Intel
published specifications. Current characterized errata are available on request.
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E7500 and Intel® E7501 Chipsets MCH may contain design defects or errors known as errata which may cause the product to deviate from
2 Thermal Design Guide
Contents
Contents
1.0 Introduction....................................................................................................................................5
1.1 Document Goals....... .................................................. ..........................................................5
1.2 Document Scope.................................................................................................................. 5
1.3 Design Flow.......................................................................................................................... 5
1.4 Definition of Terms................................................................................................................6
1.5 Reference Documents........................................................................................................ ..6
2.0 Packaging Technology .................................................................................................................7
3.0 Thermal Simulation .......................................................................................................................9
4.0 Thermal Specifications ...............................................................................................................11
4.1 Power..................................................................................................................................11
4.2 Die Temperature.................................................................................................................11
5.0 Therm al Metrology ......................................................................................................................13
5.1 Die Temperature Measurements........................................................................................13
5.1.1 90° Angle Attach Methodology ..............................................................................13
5.1.2 0° Angle Attach Methodol o g y............ ......................................................... ...........14
5.2 Power Simulat ion Software....... ...................................................................................... ....16
6.0 Referen ce Th erm al So lution....................................................................................................... 17
6.1 Operating Environment and Thermal Performance ............................................................17
6.2 Mechanical Design Envelope .............................................................................................18
6.3 Thermal Solution Assembly................................................................................................19
6.3.1 Retention Method A ...............................................................................................20
6.3.1.1 Heat Sink Orientations...........................................................................20
6.3.1.2 B oard Lev el Keep-out Dimens ions ........................................................ 20
6.3.1.3 Heat Sink Clip........................................................................................22
6.3.1.4 Solder-Down Anch o rs........ ....................................................................22
6.3.2 Retention Method B ...............................................................................................22
6.3.2.1 Heat Sink Orientations...........................................................................23
6.3.2.2 B oard Lev el Keep-Ou t Dimensions........................................................23
6.3.2.3 Heat Sink Push-Pin................................................................................24
6.3.3 Mechanical Interface Material................................................................................24
6.3.4 Thermal Interface Material..................................................................................... 24
6.4 Reliability Requirements.....................................................................................................25
7.0 Con clu sion...................................................................................................................................27
A Thermal Solution Component Suppliers...................................................................................29
A.1 Extru d ed Pi n Fin Heat Sink.......................................... ...............................................................29
A.2 Materials for Retention Method A...............................................................................................29
A.3 Materials for Retention Method B...............................................................................................29
A.4 Attach Hardware.........................................................................................................................30
B Mechanical Drawings..................................................................................................................31
Thermal Design Guide 3
Contents
Figures
1 Thermal Design Process..............................................................................................................5
2Intel
®
E7500 and Intel® E7501 Chipsets MCH Package Dimensions..........................................7
3 90° Angle Attach Methodology...................................................................................................14
4 0° Ang l e Att a ch Met h odology.....................................................................................................15
5 0° Ang l e Att a ch Heat Si nk Modification s............ ........................................................................15
6 Thermal Solution Deci sion Flowchart.........................................................................................16
7 Theta ja versus Airflow for the Reference Thermal Solution......................................................18
8 Reference Heat Sink Volumetric Envelope for the MCH............................................................ 19
9 Reference Thermal Solution Assembly Using Retention Method A ...........................................20
10 Heat Sink Retention Mechanism Layout for Retention Method A ..............................................21
11 Retention Mechanism Compone nt Keep-out Zones fo r Retention Metho d A.............................21
12 Reference Thermal Solution Assembly Using Retention Method B...........................................22
13 Board Component Keep-o ut for Retention Method B. ................................................................23
14 Heat Sink Mechanical Gasket, Optional Two-Pie ce . ..................................................................24
15 MCH Heat Sink...... .....................................................................................................................32
16 Heat Sink Clip.......... ..................................................................................................... ..............33
17 Push-pin.....................................................................................................................................34
Tables
1 Definition of Terms .......................................................................................................................6
2 Refer e n ce Documents..................................................................................................................6
3Intel
4 Theta ja Required versus Device and Configuration..................................................................17
5 Reliability Requirements.............................................................................................................25
6 Mechanical Drawing List.............................................................................................................31
®
E7500 and Intel® E7501 Chipsets MCH Thermal Speci fications .....................................11
Revision History
Date Revision Description
Revised Table 3, “Intel
March 2003 002
November 2002 001 Initial rele ase of this document.
MCH Thermal Specifications.”
Revised Table 4, “Theta ja Required versus Dev ice and
Configuration.”
4 Thermal Design Guide
®
E7500 and Intel® E7501 Chipsets
Intel® E7500 and Intel® E7501 Chipsets MCH Thermal Design Guide
1.0 Introduction
1.1 Document Goals
The objective of thermal management is to ensure that the temperatures of all components in a
system are maint ai ned within f u nction al limit s . The func tional te mper ature li mit i s the ra nge withi n
which the electric al circuits may be expec ted to meet specified performance requirements.
Operation outs ide the functional li mi t ma y degrade system performance , ca us e logic errors, or
cause component and /or s ystem damage. Temperatures exceeding the maximum operating limits
may result in irreversible changes in the operating characteristics of the component. Th e goal of
this document is to provide an understanding of the operating limits of the Intel
E7501 chipset MCHs and describe a re ference thermal solution for embedded applications.
1.2 Document Scope
This document addres ses thermal design and specifications for the Intel E7500 and I ntel E7501
chipset MCH components on ly. For thermal design information on other chipset components, refer
to the respective com ponent thermal design gu ides. For the Intel
®
PCI-64 Hub 2 (P64H2) Thermal Design Guidelines.
Intel
®
E7500 and Intel®
®
P64H2, refer to the
For general thermal enabling of the Intel E7501 chipset, refer to the Intel
and Intel
®
E7505 Chipsets MCH Thermal Design Guidelines.
1.3 Desig n Flo w
To develop a reliable, cost-effective thermal solution, several tools have been provided to the
system designer. Figure 1 shows the design process implicit to this document and the tools
appropriate for eac h st ep.
Figure 1. Thermal Design P roc ess
Step 1 : Thermal Simulation
Step 1 : Thermal Simulation
• Therma l model
• Therma l model
• Therma l model user’s gui de
• Therma l model user’s gui de
Step 2: Heat Sink Selection
• Thermal reference
• Thermal reference
•
• Mechanical reference
®
E7500, Intel® E7501,
Step 3: Thermal Validatio n
Step 3: Thermal Validatio n
• Thermal testing software
• Thermal testing software
•
•
Software user’s guide
Thermal Design Guide 5
Intel® E7500 and Intel® E7501 Chipsets MCH Thermal Design Guide
1.4 D ef initio n of Terms
Table 1 lists the definitions of terms us ed in this document.
Table 1. Definition of Term s
Term Definition
BGA
ICH3-S
MBGA Mini Ball Grid Array. A version of the BGA wit h a small er ball pitch.
MCH
FC-BGA
P64H2 Bus Controller Hub. The chip set component tha t interfaces the PCI-X buses.
T
case-nhs
T
die-nhs
T
die-hs
TDP
Ball Grid Array. A package type defined by a resin-fiber substrate, onto which a die is
mounted, bo nd ed and encap s ul at ed in mol di ng com po un d. Th e pri ma ry el ectr i cal in ter fac e is
an array of solder balls attached to the substrate opposite the die and molding compound.
I/O Controller Hub. The chipset component that contains the primary PCI interface, LPC
interface, USB , ATA-100, and other legacy functions.
Memory Controller Hub. The chipset component that contains the processor interface and
the memory inte rfa ce .
Flip Ch ip Bal l Gr id A r ray. A packagi ng t echno l ogy us ed fo r th e Int e l
chipset MCHs.
The maximum package case te mperature without any package thermal soluti on. This
temperature is measured at the geometric center of the top of the package case.
The maximum die temperature withou t any package thermal solution. This temperature is
measured at the geometric cente r of the top of the package die.
The maximum die temperatur e with the reference thermal solution attached. This
temperature is measured at the geometric center of the top of the package die.
Thermal Design Power. Thermal solutions should be designed to dissipate this target power
level.
1.5 Reference Documents
Table 2 lists the reference documents an d related document number or source.
®
E7500 and In te l® E7501
Table 2. Reference Documents
Document Document Number
®
Intel
E7500, Intel® E7501, and Intel® E7505 Chipsets MCH Thermal
Design Guidelines
Low Voltage Intel
Thermal Design Guidelines
®
Intel
Xeon™ Processor MP Thermal Design Guidelines 298650
®
PCI-64 Hub 2 (P64H2) Thermal Design Guidelines Contact your local Intel Representative
Intel
®
82801CA I/O Controlle r Hub 3 (ICH3-S) Datasheet 290733
Intel
®
E7500 and Intel® E7501 Chipset Flother m * Model and User’s
Intel
Guide
Thermal Design Su ggestions for Various Fo rm Factors Available at http://www.formfactors.org
®
Intel
E7500 Chipset MCH Thermal Testing Software Contact your local Intel Representative
®
Xeon™ Processor Thermal Design Guidelines 298348
Intel
®
XeonTM Processor for Embedded Applications
Contact your local Intel Representative
298647
273764
6 Thermal Design Guide
Intel® E7500 and Intel® E7501 Chipsets MCH Thermal Design Guide
2.0 Packaging Technology
The Intel® E7500 and Intel® E7501 chipsets consist of thre e individual components, the memory
controller hub (MCH), bus controller hub (P64H2), and I/O controller hub (ICH3-S). Th e Inte l
E7500 and E7501 MCHs utilize a 42.5 mm, 6-layer FC-BGA package shown in Figure 2. Refer to
the Intel
component and to the Intel
on the ICH3-S component.
Figure 2. Intel
®
PCI-64 Hub 2 (P64H2) Thermal Design Guidelines for information on the P64H2
®
E7500 and Intel® E7501 Chipsets MCH Package Dimensions
®
82801CA I/O Controller Hub 3 (ICH3-S) Datasheet for information
®
NOTE: Dimensions are in mm.
Thermal Design Guide 7
Intel® E7500 and Intel® E7501 Chipsets MCH Thermal Design Guide
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8 Thermal Design Guide
Intel® E7500 and Intel® E7501 Chipsets MCH Thermal Design Guide
3.0 Thermal Simulatio n
Intel provides thermal simulation models of the Intel® E7500 chipset MCH and associated user’s
guides to aid sys tem designers in simulating, analyz ing, and optimizing their thermal so lutions in
an integrated system-level environment. The models are for use with the commercially available
Computation al Fluid Dynamics (CFD)-based thermal analys is tool FLOTHERM* (version 3.1 or
higher) by F lom erics Inc. Contact your Intel Field Sales represe ntative to order the therm al models
and user’s guides. The Intel E7500 chi pset MCH thermal model may also be us ed for simulating
the Intel
E7501 chipset MCH.
Thermal Design Guide 9
Intel® E7500 and Intel® E7501 Chipsets MCH Thermal Design Guide
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10 Thermal Design Guide
Intel® E7500 and Intel® E7501 Chipsets MCH Thermal Design Guide
4.0 Thermal Specifications
4.1 Power
See Table 3 for TDP specifications for the Intel® E7500 MCH and the Intel® E7501 chips et MCH.
FC-BGA packages have poor heat transfer capability into the board and have minimal the rma l
capability without thermal solutions. Intel recommends that sys tem designers pl an for one or more
heat sinks when using the Intel E7500 or Intel E7 501 chipset components.
4.2 Die Temper ature
To ensure proper operation and reliability of the Intel E7500 and Intel E7501 chipset MCHs, the
die temperature s must be at or below the values speci f ied in Table 3. Refer to Section 5.0 for
guidelines on accurately measuring package die temperatures.
Table 3. Intel
Intel
Intel
(Paired with Intel
Intel
configuration)
Intel E7501 Chipset MCH
(Paired with Intel Xeon processor or Low Voltage
Intel
configuration)
Intel E7501 Chipset MCH
(Paired with Intel
channel memory configuration)
Intel E7501 Chipset MCH
(Paired with Intel Pentium M processor, single
channel memory configuration)
†T
®
E7500 and Intel® E7501 Chipsets MCH Thermal Specifications
Device
®
E7500 Chipset MCH 102° C 7.5 W
®
E7501 Chipset MCH
Xeon processor, dual channel memory
Xeon processor, single chan ne l me mo r y
die-hs
®
Xeon™ proces sor or Low Voltage
®
Pentium® M proces sor, dual
is defined as the maximum die temperature with the ref erence thermal solution attached.
Parameter (Maximum)
†
T
die-hs
105° C 8.5 W
105° C 7.8 W
105° C 7.1 W
105° C 6.2 W
TDP
Thermal Design Guide 11
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