Intel Intel® Core i7 User Manual
Intel® Core™ i7 Processor with
Intel® QM57 Express Chipset
Development Kit User Guide
December 2009
Revision 001
323094
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*Other names and brands may be claimed as the property of others.
Copyright © 2009, Intel Corporation. All Rights Reserved.
2 323094 Dev Kit Manual
Contents
1 About This Manual .............................................................................................. 7
1.1 Content Overview .................................................................................... 7
1.2 Text Conventions .................................................................................... 7
1.3 Glossary of Terms and Acronyms............................................................... 9
1.4 Related Documents ................................................................................ 14
1.5 Development kit Technical Support .......................................................... 14
1.5.1 Online Support......................................................................... 14
1.5.2 Additional Technical Support ...................................................... 14
2 Getting Started ................................................................................................ 15
2.1 Development Kit Contents ...................................................................... 15
2.2 Additional Required Hardware Not Included In This Kit ............................... 16
2.3 Additional Required Software Not Included In This Kit ................................ 16
2.4 Workspace Preparation .......................................................................... 16
2.5 System Setup ....................................................................................... 17
2.6 System Power-Up .................................................................................. 18
2.7 System Power-Down .............................................................................. 18
2.8 System BIOS ........................................................................................ 18
2.8.1 Configuring the BIOS ................................................................ 18
2.8.2 Programming BIOS Using a Bootable USB Device ......................... 19
2.9 Instructions to flash BIOS on SPI ............................................................ 20
3 Development Board Features ............................................................................. 21
3.1 Block Diagram ...................................................................................... 21
3.2 Mechanical Form Factor .......................................................................... 21
3.3 Development Board Features Table .......................................................... 21
3.4 Driver Key Features ............................................................................... 23
3.5 BIOS Key Features ................................................................................ 24
3.6 System Thermal Management ................................................................. 24
3.7 System Features and Operation .............................................................. 24
3.7.1 Processor ................................................................................ 25
3.7.2 Chipset ................................................................................... 29
3.7.3 Displays .................................................................................. 35
3.7.4 Debugging Interfaces ............................................................... 38
3.7.5 Power Management .................................................................. 38
3.7.6 Power Measurement Support ..................................................... 38
3.7.7 Power Supply Usage and Recommendation .................................. 43
4 Development Board Physical Hardware Reference ................................................ 44
4.1 Primary Features ................................................................................... 44
4.2 Connectors ........................................................................................... 47
4.2.1 Back Panel Connectors .............................................................. 48
4.3 Configuration Settings............................................................................ 48
4.4 Power On and Reset Push Buttons ........................................................... 51
4.5 LEDs .................................................................................................... 52
4.6 Other Headers ...................................................................................... 53
Dev Kit Manual 3 323094
4.6.1 H8 Programming Header ........................................................... 53
4.6.2 Expansion Slots and Sockets ..................................................... 53
5 Daughter and Plug-in Cards ............................................................................... 63
5.1 PCIe* Add-in Card ................................................................................. 63
5.2 PCI Expansion Card ............................................................................... 63
5.3 Port 80-83 Add-in Card .......................................................................... 64
6 Heatsink Installation Instructions ....................................................................... 66
Figures
Figure 1. System Block Diagram ........................................................................ 21
Figure 2. VID Override Circuit ............................................................................ 26
Figure 3. Block Diagram of On-board LAN Implementations ................................... 30
Figure 4. BCLK Frequency Select Circuit .............................................................. 34
Figure 5. Platform Clocking Circuit ...................................................................... 35
Figure 6. Intel® Core™ i7 Processor Based Low-Power Platform Display Interfaces .. 37
Figure 7. Component Locations – Top View .......................................................... 44
Figure 8. Component Locations – Bottom View ..................................................... 45
Figure 9. Back Panel Connector Locations ............................................................ 48
Figure 10. PCIe* Add-in Card............................................................................. 63
Figure 11. PCI Expansion Card ........................................................................... 64
Figure 12. Port 80-83 Interposer Card ................................................................ 64
Figure 13. Block Diagram of Port 80-83 Add-in Card ............................................. 65
Figure 14. Disassembled Fan/heatsink Assembly .................................................. 66
Figure 15. Bottom View of the CRB with Backplate in Place .................................... 67
Figure 16. Top View of Board With Pins Installed, Through the Board, And
Into the Backplate (Backplate not visible) ..................................................... 68
Figure 17. Applying Thermal Grease to the Top of Processor Package .................... 69
Figure 18. Squeeze Activation Arm Downward, Toward the Board ......................... 70
Figure 19. Installing Fan/heatsink (Slide the fan/heatsink away from
compression assembly handle) .................................................................... 71
Figure 20. Fan/heatsink Power Plugged Into Board .............................................. 72
Figure 21. Completed Intel® Core™ i7 Processor CRB With Fan/heatsink
Assembly Installed .................................................................................... 73
Tables
Table 1. Text Conventions ................................................................................... 8
Table 2. Terms ................................................................................................... 9
Table 3. Acronyms ........................................................................................... 11
Table 4. Related Documents .............................................................................. 14
Table 5. Development Kit Feature Set Summary .................................................. 22
Table 6. Supported DIMM Module Configurations .................................................. 27
Table 7. Hardware Straps for processor PCI Express* Interface Usage .................... 28
Table 8. PCI Express* Ports ............................................................................... 30
Table 9. Selection of I/O Voltage for the Intel® High Definition Audio ...................... 31
Table 10. SATA Ports ........................................................................................ 31
Table 11. USB Port Mapping .............................................................................. 32
Table 12. Jumper Setting for SPI Programming .................................................... 33
Table 13. Power Management States .................................................................. 38
4 323094 Dev Kit Manual
Table 14. Digital Multimeter ............................................................................... 39
Table 15. Power Measurement Resistor for Power Rails ......................................... 39
Table 16. Component Location .......................................................................... 45
Table 17. Connectors on the motherboard ........................................................... 47
Table 18. Back Panel Connectors ........................................................................ 48
Table 19. Configuration Jumper/Switches Settings ............................................... 48
Table 20. Power-on and Reset Push Buttons ........................................................ 52
Table 21. Development lit LEDs .......................................................................... 52
Table 22. H8 Programming jumpers ................................................................... 53
Table 23. Expansion Slots and Sockets ............................................................... 54
Table 24. Fan Connector (J4C1) ......................................................................... 54
Table 25. Front Panel Connector......................................................................... 54
Table 26. eDP Support Connector ....................................................................... 55
Table 27. SATA Port 0 „Direct Connect‟ Connector Pinout (J8J1) ............................. 55
Table 28. SATA Ports 1 and 2/eSATA Ports 3 and 4 Pinout (J7G2, J7G1, J6J1, J7J1) . 56
Table 29. SATA Power Connector (J6H1) ............................................................. 56
Table 30. SPI Programming Header (J8E1) .......................................................... 56
Table 31. HAD Header for MDC Interposer (J9E4) ................................................. 57
Table 32.HAD Header for MDC Interposer (J9E7) .................................................. 57
Table 33. HAD Header for External HDMI Support (J8F1) ...................................... 58
Table 34. LED Header (J8G3) ............................................................................. 58
Table 35. Descriptor Security Override (J8F4) ...................................................... 59
Table 36. Controller Link Header (J8G2) .............................................................. 59
Table 37. TPM Header/Port 80 Add-in-Card Header (J9A1) .................................... 60
Table 38. LPC Hot Docking (J9E5) ...................................................................... 60
Table 39. LPC Side Band Header (J9G2) .............................................................. 61
Table 40. Jumper settings for Port 80-80 card ..................................................... 65
Dev Kit Manual 5 323094
Document
Number
Revision
Number
Description
Revision Date
323094
001
Public release.
December 2009
Revision History
§
6 323094 Dev Kit Manual
1 About This Manual
This manual describes the use of the Intel® Core™ i7 Processor with Intel® QM57 Express
Chipset Development kit (Development kit). This manual has been written for OEMs, system
evaluators, and embedded system developers. This manual assumes basic familiarity in the
fundamental concepts involved with installing and configuring hardware for a personal
computer system. This document defines all jumpers, headers, LED functions, their locations
on the development kit, and other subsystem features and POST codes. This manual assumes
basic familiarity in the fundamental concepts involved with installing and configuring hardware
for a personal computer system.
For the latest information about the Dev Kit and platform design collateral, please visit:
http://tigris.intel.com/scripts-edk/viewer/UI_CLCatalog.asp?edkId=8381
1.1 Content Overview
This manual is arranged into the following sections:
About This Manual contains a description of conventions used in this manual. The last few
sections explain how to obtain literature and contact customer support.
Getting Started describes the contents of the development kit. This section explains the basics
steps necessary to get the board running. This section also includes information on how to
update the BIOS.
Development Board Features describes details on the hardware features of the development
board. It explains the Power Management and Testability features.
Development Board Physical Hardware Reference provides a list of major board components
and connectors. It gives a description of jumper settings and functions. The chapter also
explains the use of the programming headers.
Daughter and Plug-in Cards contains information on add-in cards available from Intel that can
be used with the development board.
1.2 Text Conventions
Throughout this document:
Intel
Intel
®
Core™ i7-620M Processor, Intel® Core™ i7-610E Processor, Intel® Core™ i7620LE Processor, Intel® Core™ i7-620UE Processor, Intel® Core™ i5-520M Processor,
and Intel® Core™ i5-520E Processor, Intel® Celeron® P4500 processor, and Intel®
Celeron® P4505 processor may be referred to as the Processor or CPU.
®
QM57 Series Chipset may be referred to as the Chipset or PCH.
The notations listed in Table 1 may be used throughout this manual.
Dev Kit Manual 7 323094
Notation
Definition
#
The pound symbol (#) appended to a signal name indicates that the signal
is active low. (e.g., PRSNT1#)
Variables
Variables are shown in italics. Variables must be replaced with correct
values.
INSTRUCTIONS
Instruction mnemonics are shown in uppercase. When you are
programming, instructions are not case-sensitive. You may use either
uppercase or lowercase.
Numbers
Hexadecimal numbers are represented by a string of hexadecimal digits
followed by the character H. A zero prefix is added to numbers that begin
with A through F. (For example, FF is shown as 0FFH.) Decimal and binary
numbers are represented by their customary notations. (That is, 255 is a
decimal number and 1111 is a binary number. In some cases, the letter B
is added for clarity.)
Units of Measure
A
GByte
KByte
K
mA
MByte
MHz
ms
mW
ns
pF
W
V
µA
µF
µs
µW
The following abbreviations are used to represent units of measure:
amps, amperes
gigabytes
kilobytes
kilo-ohms
milliamps, mill amperes
megabytes
megahertz
milliseconds
milliwatts
nanoseconds
picofarads
watts
volts
microamps, microamperes
microfarads
microseconds
microwatts
SIGNAL NAMES
Signal names are shown in uppercase. When several signals share a
common name, an individual signal is represented by the signal name
followed by a number, while the group is represented by the signal name
followed by a variable (n). For example, the lower chip-select signals are
named CS0#, CS1#, CS2#, and so on; they are collectively called CSn#.
A pound symbol (#) appended to a signal name identifies an active-low
signal. Port pins are represented by the port abbreviation, a period, and
the pin number (e.g., P1.0).
Table 1. Text Conventions
8 323094 Dev Kit Manual
Term/Acronym
Definition
Aggressor
A network that transmits a coupled signal to another network.
Anti-etch
Any plane-split, void or cutout in a VCC or GND plane.
Bus Agent
A component or group of components that, when combined, represent a
single load on the AGTL+ bus.
Crosstalk
The reception on a victim network of a signal imposed by aggressor
network(s) through inductive and capacitive coupling between the
networks.
Backward Crosstalk - Coupling that creates a signal in a victim network
that travels in the opposite direction as the aggressor‟s signal.
Forward Crosstalk - Coupling that creates a signal in a victim network that
travels in the same direction as the aggressor‟s signal.
Even Mode Crosstalk - Coupling from a signal or multiple aggressors when
all the aggressors switch in the same direction that the victim is
switching.
Odd Mode Crosstalk - Coupling from a signal or multiple aggressors when
all the aggressors switch in the opposite direction that the victim is
switching.
Duck Bay 3
PCI Express* interposer card that provides Express-card support
Flight Time
Flight time is a term in the timing equation that includes the signal
propagation delay, any effects the system has on the TCO (time from
clock-in to data-out) of the driver, plus any adjustments to the signal at
the receiver needed to ensure the setup time of the receiver. More
precisely, flight time is defined as:
The time difference between a signal at the input pin of a receiving agent
crossing the switching voltage (adjusted to meet the receiver
manufacturer‟s conditions required for AC timing specifications; i.e.,
ringback, etc.) and the output pin of the driving agent crossing the
switching voltage when the driver is driving a test load used to specify the
driver‟s AC timings.
Maximum and Minimum Flight Time - Flight time variations are caused by
many different parameters. The more obvious causes include variation of
the board dielectric constant, changes in load condition, crosstalk, power
noise, variation in termination resistance, and differences in I/O buffer
performance as a function of temperature, voltage, and manufacturing
process. Some less obvious causes include effects of Simultaneous
Switching Output (SSO) and packaging effects.
Maximum flight time is the largest acceptable flight time a network will
experience under all conditions.
Minimum flight time is the smallest acceptable flight time a network will
experience under all conditions.
Infrared Data
Assoc.
The Infrared Data Association (IrDA) has outlined a specification for serial
communication between two devices via a bi-directional infrared data
Table 2. Terms
1.3 Glossary of Terms and Acronyms
Table 2 defines conventions and terminology used throughout this document.
Dev Kit Manual 9 323094
Term/Acronym
Definition
port. The Development kit has such a port and it is located on the rear of
the platform between the two USB connectors.
IMVP6.5
The Intel® Mobile Voltage Positioning specification for the Intel® Core™ i5
Processor. It is a DC-DC converter module that supplies the required
voltage and current to a single processor.
Inter-Symbol
Interference
Inter-symbol interference is the effect of a previous signal (or transition)
on the interconnect delay. For example, when a signal is transmitted
down a line and the reflections due to the transition have not completely
dissipated, the following data transition launched onto the bus is affected.
ISI is dependent upon frequency, time delay of the line, and the reflection
coefficient at the driver and receiver. ISI may impact both timing and
signal integrity.
Mott Canyon IV
This Add-in Card enables Intel® High Definition Audio functionality
Network
The network is the trace of a Printed Circuit Board (PCB) that completes
an electrical connection between two or more components.
Overshoot
The maximum voltage observed for a signal at the device pad, measured
with respect to VCC.
Pad
The electrical contact point of a semiconductor die to the package
substrate. A pad is only observable in simulations.
Pin
The contact point of a component package to the traces on a substrate,
such as the motherboard. Signal quality and timings may be measured at
the pin.
Power-Good
“Power-Good,” “PWRGOOD,” or “CPUPWRGOOD” (an active high signal)
indicates that all of the system power supplies and clocks are stable.
PWRGOOD should go active at a predetermined time after system
voltages are stable and should go inactive as soon as any of these
voltages fail their specifications.
Ringback
The voltage to which a signal changes after reaching its maximum
absolute value. Ringback may be caused by reflections, driver oscillations,
or other transmission line phenomena.
System Bus
The System Bus is the microprocessor bus of the processor.
Setup Window
The time between the beginning of Setup to Clock (TSU_MIN) and the
arrival of a valid clock edge. This window may be different for each type
of bus agent in the system.
Simultaneous
Switching Output
Simultaneous Switching Output (SSO) effects are differences in electrical
timing parameters and degradation in signal quality caused by multiple
signal outputs simultaneously switching voltage levels in the opposite
direction from a single signal or in the same direction. These are called
odd mode and even mode switching, respectively. This simultaneous
switching of multiple outputs creates higher current swings that may
cause additional propagation delay (“push-out”) or a decrease in
propagation delay (“pull-in”). These SSO effects may impact the setup
and/or hold times and are not always taken into account by simulations.
System timing budgets should include margin for SSO effects.
Stub
The branch from the bus trunk terminating at the pad of an agent.
Trunk
The main connection, excluding interconnect branches, from one end.
System
Management Bus
A two-wire interface through which various system components may
communicate.
10 323094 Dev Kit Manual
Term/Acronym
Definition
Undershoot
The minimum voltage extending below VSS observed for a signal at the
device pad.
VCC (CPU core)
VCC (CPU core) is the core power for the processor. The system bus is
terminated to VCC (CPU core).
Victim
A network that receives a coupled crosstalk signal from another network
is called the victim network.
Acronym
Definition
AC
Audio Codec
ACPI
Advanced Configuration and Power Interface
ADD2
Advanced Digital Display 2
ADD2N
Advanced Digital Display 2 Normal
AIC
Add-In Card
AMC
Audio/Modem Codec.
AMT
Advanced Management Technology
ASF
Alert Standard Format
AMI
American Megatrends Inc. (BIOS developer)
ATA
Advanced Technology Attachment (disk drive interface)
ATX
Advance Technology Extended (motherboard form factor)
BGA
Ball Grid Array
BIOS
Basic Input/Output System
CK-SSCD
Spread Spectrum Differential Clock
CMC
Common Mode Choke
CMOS
Complementary Metal-Oxide-Semiconductor
CPU
Central Processing Unit (processor)
CRB
Customer Reference Board
DDR
Double Data Rate
DMI
Direct Memory Interface
DPST
Display Power Saving Technology
ECC
Error Correcting Code
EEPROM
Electrically Erasable Programmable Read-Only Memory
EHCI
Enhanced Host Controller Interface
EMA
Extended Media Access
Table 3 defines the acronyms used throughout this document.
Table 3. Acronyms
Dev Kit Manual 11 323094
Acronym
Definition
EMI
Electro Magnetic Interference
ESD
Electrostatic Discharge
EV
Engineering Validation
EVMC
Electrical Validation Margining Card
ERB
Early Engineering Reference Board
FCBGA
Flip Chip Ball Grid Array
FDD
Floppy Disk Drive
FIFO
First In First Out - describes a type of buffer
FIR
Fast Infrared
FS
Full-speed. Refers to USB
FSB
Front Side Bus
FWH
Firmware Hub
GMCH
Graphics Memory Controller Hub
GPIO
General Purpose IO
HDA
Intel® High Definition Audio
HDMI
High Definition Media Interface
HS
High-speed. Refers to USB
ICH
I/O Controller Hub
IDE
Integrated Drive Electronics
IMVP
Intel Mobile Voltage Positioning
IP/IPv6
Internet Protocol/Internet Protocol version 6
IrDA
Infrared Data Association
ISI
Inter-Symbol Interference
KBC
Keyboard Controller
LAI
Logic Analyzer Interface
LAN
Local Area Network
LED
Light Emitting Diode
LOM
LAN on Motherboard
LPC
Low Pin Count (often used in reference to LPC bus)
LS
Low-speed. Refers to USB
LVDS
Low Voltage Differential Signaling
MC
Modem Codec
MDC
Mobile Daughter Card
ME
Manageability Engine
MHz
Mega-Hertz
12 323094 Dev Kit Manual
Acronym
Definition
OS
Operating System
OEM
Original Equipment Manufacturer
PCB
Printed Circuit Board
PCIe
PCI Express*
PCH
Platform Controller Hub
PCM
Pulse Code Modulation
PEG
PCI Express* Graphics
PGA
Pin Grid Array
PLC
Platform LAN Connect
PLL
Phase Locked Loop
POST
Power On Self Test
RAID
Redundant Array of Inexpensive Disks
RTC
Real Time Clock
SATA
Serial ATA
SIO
Super Input/Output
SKU
Stock Keeping Unit
SMC
System Management Controller
SMBus
System Management Bus
SO-DIMM
Small Outline Dual In-line Memory Module
SPD
Serial Presence Detect
SPI
Serial Peripheral Interface
SPWG
Standard Panels Working Group - http://www.spwg.org/
SSO
Simultaneous Switching Output
STR
Suspend To RAM
TCO
Total Cost of Ownership
TCP
Transmission Control Protocol
TPM
Trusted Platform Module
TDM
Time Division Multiplexed
TDR
Time Domain Reflectometry
UDP
User Datagram Protocol
UHCI
Universal Host Controller Interface
USB
Universal Serial Bus
VGA
Video Graphics Adapter
VID
Voltage Identification
VREG or VR
Voltage Regulator
Dev Kit Manual 13 323094
Acronym
Definition
XDP
eXtended Debug Port
Document Title
Document No
Calpella Platform Design Guide For
Arrandale and Intel(r) Series 5 Chipset
398905
Calpella+ECC Platform Design Guide
Addendum
411043
Arrandale Processor External Design
Specification – Volumes One and Two
403777 and 403778
Mobile Intel® 5 Series Chipset and Intel®
3400 Series Chipset External Design
Specification
401376
Calpella+ECC] Platform - Fort Sumter CRB
OrCAD Schematic – Rev. 1.1
409593
[Calpella+ECC] Platform -Fort Sumter CRB
PDF Schematic – Rev. 1.11
409572
[Calpella] Platform, Eaglemont-2 Add-inCard – User Guide – Rev. 1.0
414150
[Calpella] Platform, Thimble Peak 2 Add In
Card – Schematics / Diagrams – Rev. 1.0
417149
1.4 Related Documents
Table 4 provides a summary of publicly available documents related to this development kit.
For additional documentation, please contact your Intel Representative.
Table 4. Related Documents
1.5 Development kit Technical Support
1.5.1 Online Support
Intel‟s web site (http://www.intel.com/) provides up-to-date technical information and product
support. This information is available 24 hours per day, 7 days per week, providing technical
information whenever you need it.
1.5.2 Additional Technical Support
If you require additional technical support, please contact your Intel Representative or local
distributor.
14 323094 Dev Kit Manual
2 Getting Started
The development kit‟s motherboard is populated with the Intel® Core™ i7 Processor, the Intel®
QM57 Express Chipset and other system board components and peripheral connectors. This
section identifies the development kit‟s key components, features and specifications. It also
details basic development board setup and operation.
2.1 Development Kit Contents
The following hardware, software and documentation is included in the development kit. Check
for damage that may have occurred during shipment. Contact your sales representative if any
items are missing or damaged.
Letter to the Customer
Development kit User‟s Manual (this document)
Software CD-ROM, which includes (see the readme.txt file for a complete list of CD-
ROM contents):
o System BIOS
o BIOS installation utilities
o Chipset drivers
o Intel Embedded Graphics Drivers
o Intel
Pre-assembled development system, which includes:
o Development board
o Plexiglass stand with Acrylic pad
o Mounting screws and standoffs (installed)
o Intel
o Processor thermal solution and CPU back plate
o Intel
o QM57 heatsink (installed)
o One Type 2032, 3 V lithium coin cell battery
o One 1GB DDR3 SO-DIMM
o One Port 80 display card
o One Power Supply
o One 80 G SATA Hard Disk Drive
o One SATA DVD-ROM Drive
o SATA Cabling (Data and power)
One PCI Extension Card (codename Thimble Peak 2)
®
Active Management Technology (AMT) software installation kit
®
Core™ i5 Processor (installed)
®
QM57 Express Chipset (installed)
One 2x8 PCIe Add-in card (codename NOWATA)
Current drivers required for this development kit are available at http://platformsw.intel.com.
Dev Kit Manual 15 323094
2.2 Additional Required Hardware Not Included In
This Kit
The following additional hardware may be necessary to successfully set up and operate the
system:
VGA Monitor: Any standard VGA or multi-resolution monitor may be used. The setup
instructions in this chapter assume the use of a standard VGA monitor, TV, or flat
panel monitor.
Keyboard: The kit can support either a PS/2 or USB style keyboard.
Mouse: The kit can support either a PS/2 or USB style mouse.
Hard Disk Drives (HDDs) and Optical Disc Drives (ODD): Up to six SATA drives
and two IDE devices (master and slave) may be connected to the kit. An optical disc
drive may be used to load the OS. All these storage devices may be attached to the
board simultaneously.
Video Adapter: Integrated video is output from the VGA connector on the back panel
of the kit. Alternately, an on board HDMI connector, On board DP connector or LVDS
displays can be used for desired display options. Check the BIOS and the graphics
driver, where appropriate, for the proper video output settings.
Network Adapter: A Gigabit network interface is provided on the kit. The network
interface will not be operational until after all the necessary drivers have been
installed. A standard PCI/PCI Express* adapter may be used in conjunction with, or in
place of, the onboard network adapter.
Note: You must supply appropriate network cables to utilize the LAN connector or any other installed
network cards.
Other Devices and Adapters: The system functions much like a standard desktop
computer motherboard. Most PC-compatible peripherals can be attached and
configured to work with the motherboard.
2.3 Additional Required Software Not Included In
This Kit
The following additional software may be necessary to operate this system:
Operating System: The user must supply any needed operating system installation files and
licenses.
Application Software: The user must supply any needed application software.
2.4 Workspace Preparation
Caution: The development kit is shipped as an open system (not in a chassis) to provide flexibility in
changing hardware configurations and peripherals in a lab environment. Because the board is
not in a protective chassis, the user is required to take the following safety precautions in
handling and operating the board.
16 323094 Dev Kit Manual
1. The power supply cord is the main disconnect device to main power (AC power). The
socket outlet should be installed near the equipment and should be readily accessible.
2. To avoid shock, ensure that the power cord is connected to a properly wired and
grounded receptacle.
3. Ensure that any equipment to which this product will be attached is also connected to
properly wired and grounded receptacles.
4. Use a flame retardant work surface and take note of closest fire extinguisher and
emergency exits.
5. Ensure a static-free work environment before removing any components from their
anti-static packaging. Wear an ESD wrist strap when handling the development board
or other kit components. The system is susceptible to electrostatic discharge (ESD)
damage, and such damage may cause product failure, physical harm, and/or
unpredictable operation.
2.5 System Setup
Please follow the steps outlined below to ensure the successful setup and operation of your
development kit system.
These steps should already be completed in the kit:
1. One (or more) DDR3 DIMMs in memory sockets, populating J4V1 and/or J4W1.
2. The processor in socket U7J2 is locked in place (make sure to align the chip to the pin
1 marking)
3. The (default) configuration jumpers are as shown in Table 19.
4. RTC battery is populated in BT5G1.
5. The cable from the ATX power supply is inserted into J4J1.
6. The hard disk drive (HDD) is attached with the supplied cable SATA.
7. The optical driver (ODD) is a attached with the supplied SATA cable.
The following steps need to be completed by the user:
1. Connect either a PS/2 keyboard in J1A1 (bottom) or a USB keyboard in one of the
USB connectors.
2. Connect either a PS/2 mouse in J1A1 (top) or a USB mouse in one of the USB
connectors.
3. If using external graphics, plug a PCI graphics card in PCI-E x1 slot J6C2 or a PCI
Express Graphics card in the PCI-E x16 slot J5C1 and connect a monitor to the card
4. Connect an Ethernet cable (optional), one end of the cable to the motherboard, the
other end to a live Ethernet hub.
5. Connect the monitor to the VGA connector. Also take care to plug the monitor‟s power
cable into the wall.
6. Install the heatsink/fan for the processor at U7J2, and the fan-power cable must be
plugged into J4C1. Fan/heatsink installation is discussed in Appendix B Heatsink.
Installation Instructions.
Dev Kit Manual 17 323094
2.6 System Power-Up
Having completed the steps outlined above, you are now absolutely ready to power up the
development kit:
1. Press the power button located at SW1E1.
2. As the system boots, press F2 to enter the BIOS setup screen.
3. Check time, date, and configuration settings. The default settings should be sufficient
for most users with the exception of Intel SpeedStep Technology. This feature is
disabled by default and can be enabled in setup.
4. Press F4 to save and exit the BIOS setup.
5. The system reboots and is ready for use.
Install operating system and necessary drivers:
Depending on the operating system chosen, drivers for components included in this
development kit can be found in http://platformsw.intel.com. Please note that not all drivers
are supported across all operating systems.
2.7 System Power-Down
Powering down the board:
There are three options for powering down the development kit. Those three options are:
Use OS-controlled shutdown through the OS menu (e.g., Microsoft Windows XP*: Start
Shut Down)
Press the power button on the motherboard at SW1E1 to begin power-down.
If the system hangs, it is possible to asynchronously shut the system down by holding
the power button down continuously for 4 seconds.
Note: Intel does not recommend powering down the board by removing power at the ATX power
supply by either unplugging the power supply from the AC source/wall or by unplugging the
DC power at the board.
2.8 System BIOS
A version of the AMI* BIOS is pre-loaded on the development kit board.
2.8.1 Configuring the BIOS
The default BIOS settings may need to be modified to enable or disable various features of the
development board. The BIOS settings are configured through a menu-driven user interface
which is accessible during the Power On Self Test (POST). Press the F2 key or Delete key
during POST to enter the BIOS interface.
For AMI* BIOS POST codes, visit: www.ami.com,
For BIOS updates please contact your Intel Sales Representative or visit:
https://platformsw.intel.com.
18 323094 Dev Kit Manual
2.8.2 Programming BIOS Using a Bootable USB Device
The flash chips which store the BIOS and BIOS extensions on the development board are
connected to the SPI bus and are soldered down with solder. One method of programming
these devices is through software utilities as described below. The software files and utilities
needed to program the BIOS are contained on the included CD-ROM.
1. Follow these steps to program the system BIOS using a bootable USB Device.
2. Prepare the workspace as outlined in Section 2.4.
3. Setup the system as outlined in Section 2.5.
4. Unplug the hard disk drive (HDD) SATA cable from the board at connector J6J3 so that
the board will boot from the bootable USB key.
5. Copy the following files and utilities to a Bootable USB Device, preferably a USB flash
memory stick.
BIOS Image Files:
spifull.bin
BIOS Programming Software Utilities:
fpt.exe (DOS SPI Flash Utility)
fparts.txt (helper file)
MAC Address Programming Software Utility:
eeupdate.exe
BIOS collateral can be obtained from https://platformsw.intel.com.
6. Record the 12 digit MAC Address of the board from the sticker near the CPU.
7. Insert the Bootable USB Key into one of the USB Ports on the motherboard.
8. Switch on the power supply (to “1”).
9. Press the Power (PWR) Button on the development board.
10. Wait for the system to boot from the USB Key to a DOS prompt.
11. From the DOS prompt (C:>), Run the following:
a. fpt –f spifull.bin
b. Make sure there are no warnings or errors
12. From DOS, run the following to reprogram the MAC address:
a. eeupdate /nic=1 /mac=xxxxxxxxxxxx where: xxxxxxxxxxxx is the MAC Address
from the sticker
b. Make sure there are no warnings or errors
13. From DOS, Run the following to update the Keyboard and System Controller flash:
a. kscupdate ksc.bin
b. Make sure there are no warnings or errors
14. Power the system down by pressing the PWR button.
15. Clear the CMOS by performing the following:
a. Shunt the CMOS CLR jumper (J5F2 – near the on-board battery)
b. Press the PWR button on the board. The board will not power on, but a couple of
LEDs will flash.
c. Switch the power supply off to power down the board
d. Remove the CMOS CLR jumper (J5F2).
16. Unplug the bootable USB Key.
Verify Correct BIOS Installation:
1. Switch the power supply back on
2. Press the PWR button on the board to power-up the system.
Dev Kit Manual 19 323094
3. Boot to BIOS Configuration screen by pressing F2 at the BIOS splash screen.
4. In the BIOS Main screen, check that the “Project Version” lists the correct version of
the BIOS.
5. Press the PWR key on the board to power the system back down, or you may simply
exit the BIOS menu and continue booting into the operating system.
BIOS update is now complete:
The system is now ready for normal operation.
2.9 Instructions to flash BIOS on SPI
The Intel® Core™ i7 Processor with Intel® QM57 Express Chipset Development kit requires the
use of a two-partition SPI image for SPI-0 and SPI-1 respectively. The Descriptors sit on SPI-0
while the BIOS on SPI-1.
1. Remove all the power supplies to the board.
2. Connect the Dediprog* SF100 at J8E1.
3. Set jumpers J8D1 and J8D2 at 1-2.
4. Set jumper J8D3 and J9E2 at 1-2 for SPI-0 and flash the .bin image corresponding to
SPI-0.
5. Set the jumper J8D3 at 2-3 and J9E2 at 1-2 for SPI-1 and flash the .bin image
corresponding to SPI-1.
6. Set the jumper J9E2 at 2-3 for SPI-1 and flash the .bin image corresponding to SPI-2.
7. Once the programming is successful on the SPI, set J8D1 and J8D2 at 1-X and J8D3 at
1-X and 3-X.
8. Remove the Dediprog connector.
9. Set the SPI.
20 323094 Dev Kit Manual
D
I
M
M
TPM
SIO
SMC/
KBC
LPC
LPC
LPC Hot
Dock
Serial
14 USB ports
SATA PORT 0
SATA PORT 2
SATA PORT 4
USB 2.0/1.0
XDP
CRT VGA
LVD
CRT VGA
Infrared
Dual Channel DDR3
800/1067/1333/ 1.5V
DMI X 4
PS/2 ports
Scan
matrix
SATA PORT 1
SATA PORT 3
SATA PORT5
FDI
Legacy Block
HDA
header
PCIe x1 Slot1
PCIe x1 Slot2
PCIe x1 Slot3
PCIe x1 Slot4
PCIe x1 Slot5
High Definition Audio Bus
C Link
PEG x16 /eDP
PCIe* Graphics
(GEN1/GEN2)
(eDP)
Digital Display
Interface
PCI
SPI Bus
Intel® 82577
e-SATA
SATA Cable
e-SATA
SATA
SATA Cable
PCI Edge
PCI expansion card
SPI Flash
SPI Flash SPI Flash
IMVP6.5
Docking
Connector
PCI-e (port 7)
PCI-e (port 8)
PCI-e (port 6)
X16 CON
(DP/HDMI)
ADD2-N(SDVO)
Docking
Connector
SMBUS
LVDS
D
I
M
M
Intel®
Core™
i7
Intel®
QM57
Express
Chipset
3 Development Board Features
3.1 Block Diagram
The block diagram of the Intel® Core™ i7 Processor with Intel® QM57 Express Chipset
Development kit is shown in Figure 1.
Figure 1. System Block Diagram
3.2 Mechanical Form Factor
The development kit conforms to the ATX 2.2 form factor.
3.3 Development Board Features Table
Development kit features are summarized in Table 5.
Dev Kit Manual 21 323094
Description
Comments
Processor
Intel® Core™ i5
Soldered to board
Chipset
Intel® 5 Series Chipset
1071 pin BGA footprint
Memory
Two DDR3 DIMM slots
Maximum 8GB of DDR Memory (RAM) of
ECC and non-ECC using 2Gb1 technology
Supports DDR3 frequency of up to
1066MT/s
Notes:
4Gb (x16 width only) technology support is
under investigation
External
Graphics
PCIe* Slot
One x16 PCIe slot supported.
2x8 PCIe* supported through Nowata Add-
in card.
eDP supported through PCI graphics add-in
card
Video
24-bit dual channel LVDS
Interface
Connectors and cables from previous
development kits can be used.
Display Ports
3 – Display port Lanes on Chipset. 1 On-
Board DP Connector. Other 2 ports can be
supported through PCI graphics add-in card.
CRT
On Board right-angled CRT Connector
Similar to the earlier platforms
HDMI
1 On-Board HDMI Connector (Optional
Routing through Display Port D of Chipset).
Three additional HDMI ports are available
through the Eaglemont 2 external card.
PCI
Three 5V PCI slots supported
through PCI extension card.
PCI revision 2.3 compliant (33MHz)
No PCI slots on motherboard, only one
goldfinger on board.
PCI
Express*
8 PCIe lanes
PCI Express 2.0 base revision compliance
Five lanes to x1 PCIe ports
One lane to LAN
Two Lanes to Docking
On-Board
LAN
Intel® 82577 Gigabit Ethernet PHY
BIOS (SPI)
2x SPI flash devices
Support for multi vendor SPI
Support multi package (SOIC-8 and
SOIC-16)
ATA/
Storage
6 SATA Ports
2 Cable Connector and 1 Direct Connect
Connector. 2 eSATA connectors and 1 to
docking. RAID 0/1 support.
Table 5. Development Kit Feature Set Summary
22 323094 Dev Kit Manual
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