Intel Intel386 EX, Intel386 EXTB, Intel386 EXTC User Manual

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Intel386™ EXTB Embedded Microprocessor  Intel386 Embedded Microprocessor

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EXTC

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Intel386

EX Embedded Microprocessor User’s Manual

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Intel386 EX

Embedded

Microprocessor

User’s Manual

1996

Information in this document is provided in connection with Intel products. Intel assumes no liabilit y whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products.

Intel retains the right to make changes to these specifications at any time, without notice. Microcontroller products may have minor variations to this specifi cation known as errata.

*Other brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order. Copies of d ocuments which have a n orderi ng number a nd are re ferenced in this documen t, or o ther Inte l litera ture, may be

obtained from:

Intel Corporation Literature Sales P.O. Box 7641 Mt. Prospect, IL 60056-7641

or call 1-800-548-4725

CONTENTS

CHAPTER 1

GUIDE TO THIS MANUAL

1.1 MANUAL CONTENTS.............................. ....................................... .............................. 1-1

1.2 NOTATIONAL CONVENTIONS..................................................................................... 1-3

1.3 SPECIAL TERMINOLOGY............................................................................................ 1-4

1.4 RELATED DOCUMENTS... .................................. ............... ........................ .................. 1-5

1.5 ELECTRONIC SUPPORT SYSTEMS.................. ....................................... .................. 1-6

1.5.1 FaxBack Service ................................. ...................... ...................... ........................ .. 1-6

1.5.2 Bulletin Board System (BBS) ....................................................................................1-7

1.5.3 CompuServe Forums ..................... ................................ ........................ ...................1-7

1.5.4 World Wide Web .......................................................................................................1-7

1.6 TECHNICAL SUPPORT................................................................................................ 1-7

1.7 PRODUCT LITERATURE.................................................... .......................................... 1-8

CHAPTER 2

ARCHITECTURAL OVERVIEW

2.1 Intel386 EX EMBEDDED PROCESSOR CORE............................................................ 2-1

2.2 INTEGRATED PERIPHERALS...................................................................................... 2-3

CHAPTER 3

CORE OVERVIEW

3.1 Intel386 CX PROCESSOR ENHANCEMENTS......... ........................... ......................... 3-1

3.1.1 System Management Mode ......................................................................................3-1

3.1.2 Additional Address Lines ..........................................................................................3-1

3.2 Intel386 CX PROCESSOR INTERNAL ARCHITECTURE................... ......................... 3-2

3.2.1 Core Bus Unit ............................................................................................................3-4

3.2.2 Instruction Prefetc h Unit ........................ ............ ................. ............... ................. .......3-4

3.2.3 Instruction Decode Unit .............................................................................................3-4

3.2.4 Execution Unit ................................ ............................................................. ..............3-5

3.2.5 Segmentation Unit ....................................................................................................3-5

3.2.6 Paging Unit .................................................. ............................................................. 3-5

3.3 CORE Intel386 EX PROCESSOR INTERFACE............................................................ 3-6

CHAPTER 4

SYSTEM REGISTER ORGANIZATION

4.1 OVERVIEW ............................. ...................................................................................... 4-1

4.1.1 Intel386 Processor Core Architecture Registers ................ ................. ......................4-2

4.1.2 Intel386 EX Processor Peripheral Registers .............................................................4-2

4.2 I/O ADDRESS SPACE FOR PC/AT SYSTEMS.................. ......................................... . 4-2

4.3 EXPANDED I/O ADDRESS SPACE .............................................................................. 4-3

4.4 ORGANIZATION OF PERIPHERAL REGI STERS........................................................ 4-5

4.5 I/O ADDRESS DECODING TECHNIQUES..................................... .............................. 4-6

4.5.1 Address Configurati on Register ................................................................................4-6

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Intel386™ EX MICROPROCESSOR USER’S MANUAL

4.5.2 Enabling and Disabling the Expanded I/O Space .......... ............ ............ ...................4-8

4.5.2.1 Programming REMAPCFG Example .................................... ...............................4-8

4.6 ADDRESSING MODES............................ ........................... ............................. ............. 4-9

4.6.1 DOS-compatible Mode ............................. ....................................... ..........................4-9

4.6.2 Nonintrusive DOS Mode .........................................................................................4-11

4.6.3 Enhanced DOS M ode ........................... .................... ................. .............................4-11

4.6.4 Non-DOS Mode ......................................................................................................4-11

4.7 PERIPHERAL REGISTER ADDRESSES.................................................................... 4-15

CHAPTER 5

DEVICE CONFIGURATIO N

5.1 INTRODUCTION .................................................. ....................................... .................. 5-1

5.2 PERIPHERAL CONFIGURATION................................................................................. 5-3

5.2.1 DMA Controller, Bus Arbiter, and Refresh Unit Configuration ..................................5-3

5.2.1.1 Using The DMA Unit with External Devices . ........................................................5-3

5.2.1.2 DMA Service to an SIO or SSIO Peripheral .........................................................5-3

5.2.1.3 Using The Timer To Initiate DMA Transfers ................ ............ ............ ............ ..... 5-4

5.2.1.4 Limitations Due To Pin Signal Multiplexing .................................... ......................5-4

5.2.2 Interrupt Control Unit C onfigurati on .................. ............... ............ ....... ............... ....... 5-7

5.2.3 Timer/counter Unit Configuration ............................................................................5-11

5.2.4 Asynchronous Serial I/O Configuration ...... ....... ............... ............ ....... ............... ..... 5-14

5.2.5 Synchronous Serial I/O Configurati on ....... .. .......... ..... ....... ..... ........ .... ........ ....... .....5-18

5.2.6 Chip-select Unit and Clock and Power Management Unit Configuration . ............... 5-19

5.2.7 Core Configuration ..................................................................................................5-21

5.3 PIN CONFIGURATION ......................................... ................................ ....................... 5-23

5.4 DEVICE CONFIGURATION PROCEDURE ........................ .................................. ...... 5-28

5.5 CONFIGURATION EXAMPLE ..................................................................................... 5-28

5.5.1 Example Design Requirements ....................................................... ........................5-28

5.5.2 Example Design Solution ................................................................................. .. .....5-29

CHAPTER 6

BUS INTERFACE UNIT

6.1 OVERVIEW ............................. ...................................................................................... 6-1

6.1.1 Bus Signal Descriptions ............................................................................................6-3

6.2 BUS OPERATION ......................................................................................................... 6-5

6.2.1 Bus States .................................................................................................................6-7

6.2.2 Pipelining ..................................................................................................................6-8

6.2.3 Data Bus Transfers and Operand Alignment ............................................................6-9

6.2.4 Ready Logic ..................................................................................................... ....... 6-10

6.3 BUS CYCLES.............. ................................................................................ ................ 6-13

6.3.1 Read Cycle .............................................. .................................. .............................6-13

6.3.2 Write Cycle ................. ...................... ...................... ...................... ...................... ..... 6-16

6.3.3 Pipelined Cycle .......................................................................................................6-19

CONTENTS

6.3.4 Interrupt Acknowledge Cycle ......................................... .........................................6-23

6.3.5 Halt/Shutdown Cycle ...................................................... .........................................6-26

6.3.6 Refresh Cycle .........................................................................................................6-28

6.3.7 BS8 Cycle ..................... .............................................................................. ............6-31

6.3.7.1 Write Cycles ....................................................................................................... 6-31

6.3.7.2 Read Cycles ........................................ ....................................... ........................6-31

6.4 BUS LOCK................................................................. .................................................. 6-34

6.4.1 Locked Cycle Activators ................. ................. ...................... ................. .................6-34

6.4.2 Locked Cycle Timing ...................................................... ............................. ............6-34

6.4.3 LOCK# Signal Duration ...........................................................................................6-35

6.5 EXTERNAL BUS MASTER SUPPORT ( USING HOLD, HLDA).................................. 6-35

6.5.1 HOLD/HLDA Timing ................................................................................................6-36

6.5.2 HOLD Signal Latency .............................................................................................6-37

6.6 DESIGN CONSIDERATIONS ...................................................................................... 6-38

6.6.1 Interface To Intel387™ SX Math Coprocessor .......................................................6-38

6.6.1.1 System Configuration .........................................................................................6-39

6.6.1.2 Software Considerations ....................................................................................6-40

6.6.2 SRAM/FLASH Interface ..........................................................................................6-41

6.6.3 PSRAM Interface ....................................................................................................6-42

6.6.4 Paged DRAM Interface ...........................................................................................6-43

6.6.5 Non-Paged DRAM Interface ........................... ................................ ........................6-44

CHAPTER 7

SYSTEM MANAGEMENT MODE

7.1 SYSTEM MANAGEMENT MODE OVERVIEW ............................................................. 7-1

7.2 SMM HARDWARE INTERFACE................................................................................... 7-1

7.2.1 System Management Interrupt Input (SMI#) .............................................................7-1

7.2.2 SMM Active Output (SMIACT#) ................................................................................7-2

7.2.3 System Management RAM (SMRAM) ......................................................................7-2

7.3 SYSTEM MANAGEMENT MODE PROGRAMMING AND CONFIGURATION ............. 7-3

7.3.1 Register Status During SMM .....................................................................................7-3

7.3.2 System Management Interrupt ..................................................................................7-4

7.3.2.1 SMI# Priority . ....... ....... ............ ............... ............ .......... ............ ............ .......... ....... 7-7

7.3.2.2 System Management Interrupt During HALT Cycle .............................................7-8

7.3.2.3 HALT Restart . ........................... ........................... ............................. ...................7-9

7.3.2.4 System Management Interrupt During I/O Instru ction . ..... ....... ..... ....... ..... ....... .....7-9

7.3.2.5 I/O Restart ..........................................................................................................7-10

7.3.3 SMM Handler Interruption .......................................................................................7-10

7.3.3.1 Interrupt During SMM Handler ...........................................................................7-10

7.3.3.2 HALT During SMM Handler ............................................................... .................7-11

7.3.3.3 Idle Mode and Powerdown M o de During SMM ..................................................7-12

7.3.3.4 SMI# During SMM Operation . ............................................... .............................7-12

7.3.4 SMRAM Programming ........................................................................... .................7-12

7.3.4.1 Chip-select Unit Support for SMRAM .................................................................7-12

Intel386™ EX MICROPROCESSOR USER’S MANUAL

7.3.4.2 SMRAM State Dump Area ............................................... ..................................7-14

7.3.5 Resume Instruction (RSM) ... ...................................................................................7-15

7.4 THE Intel386 EX PROCESSOR IDENTIFIER REGI STERS ................................. ...... 7-15

7.5 PROGRAMMING CONSIDERATIONS........................................................................ 7-16

7.5.1 System Management Mode Code Example ............................................................7-16

CHAPTER 8

CLOCK AND POWER MANAGEMENT UNIT

8.1 OVERVIEW ............................. ...................................................................................... 8-1

8.1.1 Clock Gener ation Logic . ........................... ............................. ........................... .........8-1

8.1.2 Power Management Logic .................. ......................................................................8-3

8.1.2.1 SMM Interaction with Power Management Modes ...............................................8-4

8.1.2.2 Bus Interface Unit Operation During Idle Mode ....................................................8-5

8.1.2.3 Watchdog Timer Unit Operation During Idle Mode ..............................................8-5

8.1.3 Clock and Power Managem ent Registers and Signals .................................... ......... 8-6

8.2 CONTROLLING THE PSCLK FREQUENCY ....................................... ......................... 8-7

8.3 CONTROLLING POWER MANAGEMENT MODES. .................................................... 8-8

8.3.1 Idle Mode .. ......................................................................... ....................................... 8-9

8.3.2 Powerdown Mode ............................... ................. ........................ ...........................8-10

8.3.3 Ready Generation During HALT .............................................................................8-10

8.4 DESIGN CONSIDERATIONS ...................................................................................... 8-11

8.4.1 Reset Considerations ..............................................................................................8-11

8.4.2 Power-up Considerations ........................................................................................8-12

8.4.2.1 Built-in Self Test ................... ............ ....... ............... ............ .......... ............ ..........8-12

8.4.2.2 JTAG Reset ........................ .................................. ....................................... .......8-12

8.4.3 Powerdown Mode and Idle Mode Considerations ...................................................8-13

8.5 PROGRAMMING CONSIDERATIONS........................................................................ 8-13

8.5.1 Clock and Power Management Unit Code Example ...............................................8-13

CHAPTER 9

INTERRUPT CONTROL UNIT

9.1 OVERVIEW ............................. ...................................................................................... 9-1

9.2 ICU OPERATION........................................................................ ................................... 9-4

9.2.1 Interrupt Sources ................................................... ...................... ...................... ....... 9-4

9.2.2 Interrupt Prior ity ........................ ....... .......... ....... ........ ....... ....... .......... ....... .......... .......9-6

9.2.2.1 Assigning an Interrupt Level .................................................................................9-6

9.2.2.2 Determining Priority .................................................................................. ............9-7

9.2.3 Interrupt Vectors ........ ......................................................................... ...................... 9-8

9.2.4 Interrupt Process .......................................................................................................9-9

9.2.5 Poll Mode ............................................................. ...................................................9-14

9.3 REGISTER DEFINITIONS .... ................................................................................. ...... 9-15

9.3.1 Port 3 Configuration Register (P3CFG) ..................................................................9-18

9.3.2 Interrupt Configurati on Register (INTCFG) ......................................... .................... 9-19

CONTENTS

9.3.3 Initialization Command Word 1 (ICW1) . .................... ...................... ........................9-20

9.3.4 Initialization Command Word 2 (ICW2) .................. ..................................... ............9-21

9.3.5 Initialization Command Word 3 (ICW3) .................. ..................................... ............9-22

9.3.6 Initialization Command Word 4 (ICW4) .................. ..................................... ............9-24

9.3.7 Operation Command Word 1 (OCW1) ....................................................................9-25

9.3.8 Operation Command Word 2 (OCW2) ....................................................................9-26

9.3.9 Operation Command Word 3 (OCW3) ....................................................................9-27

9.3.10 Interrupt Request Register (IRR) ............................................................................9-28

9.3.11 In-Service Register (ISR) .......... ............ ............ .......... ............ ............ .......... ..........9-28

9.3.12 Poll Status Byte (POLL) ..........................................................................................9-28

9.4 DESIGN CONSIDERATIONS ...................................................................................... 9-29

9.4.1 Interrupt Acknowledge Cycle ......................................... .........................................9-29

9.4.2 Interrupt Detection . ............................................................ ..................................... 9-29

9.4.3 Spurious Interrupts ......................... ....................................... ..................................9-30

9.4.4 Cascading Interrupt Controllers ..............................................................................9-30

9.5 PROGRAMMING CONSIDERATIONS........................................................................ 9-32

9.5.1 Interrupt Control Unit C ode Examples ....................................................................9-32

CHAPTER 10

TIMER/COUNTER UNIT

10.1 OVERVIEW ......................................... ....................................... ................................. 10-1

10.1.1 TCU Signals and Registers .....................................................................................10-3

10.2 TCU OPERATION ....................................................................................................... 10-5

10.2.1 Mode 0 – Interrupt on Terminal Count ....................................................................10-6

10.2.2 Mode 1 – Hardware Retriggerable One-shot ..........................................................10-8

10.2.3 Mode 2 – Rate Generator .....................................................................................10-10

10.2.4 Mode 3 – Square Wave ........................................................................................10-12

10.2.5 Mode 4 – Software-triggered Strobe ........................................................... .......... 10-16

10.2.6 Mode 5 – Hardware-triggered Strobe ................ ....................................................10-18

10.3 REGISTER DEFINITIONS......................................................................................... 10-20

10.3.1 Configuring the Input and Output Signals .. ...........................................................10-20

10.3.1.1 Hardware Control of GATE

10.3.1.2 Software Control of GATE

............................................................................10-20

............................................................................. .10-20

10.3.2 Initializing the Counters . .............. ................. ...................... ...................... .............10-24

10.3.3 Writing the Counters ...................... ............................................................. ..........10-26

10.3.4 Reading the Counter ........................................................................................ ..... 10-27

10.3.4.1 Simple Read ....................... ............................................................... ...............10-27

10.3.4.2 Counter-latch Command ..................... ....................................... ......................10-27

10.3.4.3 Read-back Command ......................................................................................10-30

10.4 PROGRAMMING CONSIDERATION S...................................................................... 10-33

10.4.1 Timer/Counter Unit Code Examples .....................................................................10-34

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Intel386™ EX MICROPROCESSOR USER’S MANUAL

CHAPTER 11

ASYNCHRONOUS SERIAL I/O UNIT

11.1 OVERVIEW ......................................... ....................................... ................................. 11-1

11.1.1 SIO Signals ............................................................... .................................. ............1 1-3

11.2 SIO OPERATION ........................................................... ............................................. 11-4

11.2.1 Baud-rate G enerator .................................. ............ ............ .......... ............ ............ ... 1 1-4

11.2.2 SIO

11.2.3 SIO

11.2.4 Modem Control .....................................................................................................11-12

11.2.5 Diagnostic Mode ............................ ....................................... ................................11-12

11.2.6 SIO Interrupt and DMA Sources .................................... .......................................11-13

11.2.6.1 SIO Interrupt Sources ......................................................................................11-13

11.2.6.2 SIO DMA sources ............................... .............................................................11-13

11.2.7 External UART Support ........................................................................................11-14

11.3 REGISTER DEFINITIONS......................................................................................... 11-15

11.3.1 Pin and Port Configuration Registers (PINCFG and P

11.3.2 SIO and SSIO Configuration Register (SIOCFG) .................................................11-21

11.3.3 Divisor Latch Registers (DLL

11.3.4 Transmit Buffer Register (TBR

11.3.5 Receive Buffer Register (RBR

11.3.6 Serial Line Control Register (LCR

11.3.7 Serial Line Status Register (LSR

11.3.8 Interrupt E nable Register (IER

11.3.9 Interrupt ID Register (IIR

11.3.10 Modem Control Register (MCR

11.3.11 Modem Status Register (MS R

11.3.12 Scratch Pad Register (SCR

11.4 PROGRAMMING CONSIDERATION S...................................................................... 11-32

11.4.1 Asynchronous Ser ial I/O Unit Code Examples ....... ......................... ................. .....11-33

Transmitter .....................................................................................................11-6

Receiver .........................................................................................................11-9

CFG [n = 1–3]) ................11-17

and DLHn) ............. ............... ..... ..... ................. .... .11-22

) ............ ...............................................................11-23

) ...........................................................................11-24

) ............ ..........................................................11-25

) .......................................................................11-26

) ......................................................... ............. .....11-27

) ............. ................. ............ ............... ........................ ...11-28

) .................... ................................ ................. .....11-29

) ...........................................................................11-31

) ...............................................................................11-32

CHAPTER 12

DMA CONTROLLER

12.1 OVERVIEW ......................................... ....................................... ................................. 12-1

12.1.1 DMA Terminology ...................................................................................................12-3

12.1.2 DMA Signals ...........................................................................................................1 2-4

12.2 DMA OPERATION....................................................................................................... 12-5

12.2.1 DMA Transfers ........................................................................................................12-5

12.2.2 Bus Cycle Options for Data Transf ers .....................................................................12-5

12.2.2.1 Fly-By Mode .......................................................................................................12-5

12.2.2.2 Two-Cycle Mode ................................................................................................12-6

12.2.2.3 Programmable DMA Transfer Direction .............................................................1 2-6

12.2.2.4 Ready Generation For DMA Cycles ...................................................................1 2-7

12.2.2.5 DMA Usage of the 4-Byte Temporary Register ..................................................12-7

12.2.3 Starting DMA Transfers ..........................................................................................12-9

viii

CONTENTS

12.2.4 B u s Control Arbitratio n .............. .. ..... ... .. ..... .. ..... ..... ... .. ..... .. ..... ... ..... .. .. ..... ..... ... .. .....12-9

12.2.5 Ending DMA Transfers ......................................... .................................................12-10

12.2.6 Buffer-transfer Modes ...........................................................................................12-12

12.2.6.1 Single Buffer-Transfer Mode ............................................................................12-12

12.2.6.2 Autoinitialize Buffer-Transfer Mode ........................... ................. .............. ........12-12

12.2.6.3 Chaining Buffer-Transfer Mode ........................................................................12-12

12.2.7 Data-transfer Modes ...................................................... .......................................12-13

12.2.7.1 Single Data-transfer Mode ...............................................................................12-14

12.2.7.2 Block Data-transfer Mode ................................................................................12-18

12.2.7.3 Demand Data-transfer Mode ...................................................... ......................12-21

12.2.8 Cascade Mode .............. ....................................... ............................... ............. .....12-25

12.2.9 DMA Interrupts ......................................................................................................12-26

12.2.10 8237A Compatibility ..............................................................................................12-27

12.3 REGISTER DEFINITIONS......................................................................................... 12-28

12.3.1 Pin Configuration Register (PINCFG) ...................................................................12-31

12.3.2 DMA Configuration Register (DMACFG) ..............................................................12-32

12.3.3 Channel Registers .................. ............................................................... ...............12-33

12.3.4 Overflow Enable Register (DMAOVFE) ............... .................................................12-34

12.3.5 Command 1 Register (DM ACMD1) .................................................................. .....12-35

12.3.6 Status Register (DMASTS) ...................................................................................12-36

12.3.7 Command 2 Register (DM ACMD2) .................................................................. .....12-37

12.3.8 Mode 1 Register (DMAMOD1) ............................. ....................................... ..........12-38

12.3.9 Mode 2 Register (DMAMOD2) ............................. ....................................... ..........12-40

12.3.10 Software Request Register (DMASRR) ................................................................12-42

12.3.11 Channel Mask and Group Mask Registers (DMAMSK and DMAGRPMSK) .........12-44

12.3.12 Bus Size Register (DMABSR) ...............................................................................12-46

12.3.13 Chaining Register (DMACHR) ............................. .................................................12-47

12.3.14 Interrupt Enable Register (DMAIEN) ........................................................... ..........12-48

12.3.15 Interrupt Status Register (DMAIS) ........................................................................12-49

12.3.16 Software Commands .............. ........................ ...................... ...................... ..........12-50

12.4 DESIGN CONSIDERATIONS .. .................................................................................. 12-50

12.5 PROGRAMMING CONSIDERATION S...................................................................... 12-50

12.5.1 DMA Controller Code Examples ...........................................................................12-51

CHAPTER 13

SYNCHRONOUS SERIAL I/O UNIT

13.1 OVERVIEW ......................................... ....................................... ................................. 13-1

13.1.1 SSIO Signals ............................................ .................................. .............................13-4

13.2 SSIO OPERATION........................................ .............................................................. 13-5

13.2.1 Baud-rate G enerator .................................. ............ ............ .......... ............ ............ ... 1 3-5

13.2.2 Transmitt er ............... .......... .....................................................................................13-6

13.2.2.1 Transmit Mode using Enable Bit ........................................................................13-7

13.2.2.2 Autotransmit Mode ...........................................................................................13-12

13.2.2.3 Slave Mode .............. ................. .......................................................................13-12

Intel386™ EX MICROPROCESSOR USER’S MANUAL

13.2.3 Receiver ............ .............................................. ......................................................13-12

13.3 REGISTER DEFINITIONS......................................................................................... 13-16

13.3.1 Pin Configuration Register (PINCFG) ...................................................................13-17

13.3.2 SIO and SSIO Configuration Register (SIOCFG) .................................................13-18

13.3.3 Prescale Clock Register (CLKPRS) ................................................ ......................13-19

13.3.4 SSIO Baud-rate Control R egister (SSIOBAUD) ........................... ...................... ... 13-20

13.3.5 SSIO Baud-rate Count Down Register (SSIOCTR) ..............................................13-21

13.3.6 SSIO Control 1 Register (SSIOCON1) .............. ...................... ...................... ........ 13-21

13.3.7 SSIO Control 2 Register (SSIOCON2) .............. ...................... ...................... ........ 13-23

13.3.8 SSIO Transmit Holding Buff er (SSIOTBUF) .................. .......................................13-24

13.3.9 SSIO Receive Holding Buffer (SSIORBUF) . ........................................................ .13-25

13.4 DESIGN CONSIDERATIONS .. .................................................................................. 13-25

13.5 PROGRAMMING CONSIDERATION S...................................................................... 13-26

13.5.1 SSIO Example Code ................................ ....................................... ......................13-26

CHAPTER 14

CHIP-SELECT UNIT

14.1 OVERVIEW ......................................... ....................................... ................................. 14-1

14.2 CSU UPON RESET..................................................................................................... 14-2

14.3 CSU OPERATION....................................................................................................... 14-2

14.3.1 Defining a Channel’s Address Block .......................................................................14-2

14.3.2 System Management Mode Support ........................ ....................................... .....14-10

14.3.3 Bus Cycle Length Control ................................................ ................... ................. .14-11

14.3.4 Bus Size Control ................ ............................. ......................................................14-11

14.3.5 Overlapping Regions .......................... ..................................................................14-11

14.4 REGISTER DEFINITIONS......................................................................................... 14-13

14.4.1 Pin Configuration Register (PINCFG) ...................................................................14-15

14.4.2 Port 2 Configuration Register (P2CFG) ................................................................14-16

14.4.3 Chip-select Address Registers ..............................................................................14-17

14.4.4 Chip-select Mask Registers ..................................................................................14-19

14.5 DESIGN CONSIDERATIONS .. .................................................................................. 14-21

14.6 PROGRAMMING CONSIDERATION S...................................................................... 14-22

14.6.1 Chip-Select Unit Code Example .......... ........................................................ .......... 14-22

CHAPTER 15

REFRESH CONTROL UNIT

15.1 DYNAMIC MEMORY CONTROL................... .............................................................. 15-1

15.1.1 Refresh Methods .....................................................................................................15-1

15.2 REFRESH CONTROL UNIT OVERVIEW ................................................................... 15-2

15.2.1 RCU Signals ...........................................................................................................1 5-4

15.2.2 Refresh Intervals .....................................................................................................15-4

CONTENTS

15.2.3 Refresh Addresses .................................................................................................15-4

15.2.4 B u s Arbitrati on ......... .. ..... ... ..... .. .. ..... ..... ... .. ..... .. ..... ..... ... .. ..... .. ..... ... .... ... .. ..... ..... .. ...15-5

15.3 RCU OPERATION....................................................................................................... 15-5

15.4 REGISTER DEFINITIONS........................................................................................... 15-6

15.4.1 Refresh Clock Interval Register (RFSCIR) ..............................................................15-7

15.4.2 Refresh Control Register (RFSCON) ......................................................................15-8

15.4.3 Refresh Base Address Register (RFSBAD) ............................................................1 5-9

15.4.4 Refresh Address Register (RFSADD) ...................................................................15-10

15.5 DESIGN CONSIDERATIONS .. .................................................................................. 15-11

15.6 PROGRAMMING CONSIDERATION S...................................................................... 15-14

15.6.1 Refresh Control Unit Example Code .....................................................................15-14

CHAPTER 16

INPUT/OUTPUT PORTS

16.1 OVERVIEW ......................................... ....................................... ................................. 16-1

16.1.1 Port Fu nctio nality ....... ..... ........ .... ........ ....... ..... ....... ..... ....... ..... ........ .... ........ ....... .....16-2

16.2 REGISTER DEFINITIONS........................................................................................... 16-6

16.2.1 Pin Configuration ....................................................................................................16-7

16.2.2 Init ializati o n Sequence ..........................................................................................16-10

16.3 DESIGN CONSIDERATIONS .. .................................................................................. 16-10

16.3.1 Pin Status During and After Reset ..................................... ...................... ............. 16-10

16.4 PROGRAMMING CONSIDERATION S...................................................................... 16-11

16.4.1 I/O Ports Code Example ................................. ...................... .............. ............. .....16-11

CHAPTER 17

WATCHDOG TIMER UNIT

17.1 OVERVIEW ......................................... ....................................... ................................. 17-1

17.1.1 WDT Signals ...........................................................................................................17-3

17.2 WATCHDOG TIMER UNIT OPERATION................................... ................................. 17-3

17.2.1 Idle and Powerdown modes ....................................................................................1 7-4

17.2.2 General-purpose Timer Mode .................................................................................17-4

17.2.3 Software Watchdog Mode ..................................................... ..................................17-5

17.2.4 Bus Monitor Mode .................................... ...............................................................1 7-5

17.3 DISABLING THE WDT ................................................................................................ 17-6

17.4 REGISTER DEFINITIONS........................................................................................... 17-7

17.5 DESIGN CONSIDERATIONS .. .................................................................................. 17-12

17.6 PROGRAMMING CONSIDERATION S...................................................................... 17-12

17.6.1 Writing to the WDT Reload Registers (WDTRLDH and WDTRLDL) ....................17-12

17.6.2 Minimum Counter Rel o ad Value ......... ........................... .......................................17-12

17.6.3 Watchdog Timer Unit Code Examples ....... ............... ................. ................. ..........17-12

Intel386™ EX MICROPROCESSOR USER’S MANUAL

CHAPTER 18

JTAG TEST-LOGIC UNIT

18.1 OVERVIEW ......................................... ....................................... ................................. 18-1

18.2 TEST-LOGIC UNIT OPERATION................................... ............................................. 18-3

18.2.1 Test Access Port (TAP) ..........................................................................................18-3

18.2.2 Test Access Port (TAP) Controller ..........................................................................18-4

18.2.3 Instructi on Register (IR) ............ ............ ................. ............ ................. ............... ..... 1 8-7

18.2.4 Data Registers ........................................................................................................18-8

18.3 TESTING................ ................................................................................................... 18-10

18.3.1 Identifying the Device ................................................ ............................................18-10

18.3.2 Bypassing De vices on a Board ................ ............................... .................... ..........18-10

18.3.3 Sampling Device Operation and Preloading Data .................................................18-10

18.3.4 Testing the Interconnections (EXTEST) ................................................................18-10

18.3.5 Disabling the Output Drivers .................................................................................18-11

18.4 TIMING INFORMATION ............................................................ ................................ 18-12

18.5 DESIGN CONSIDERATIONS .. .................................................................................. 18-14

APPENDIX A

SIGNAL DESCRIPTIONS

APPENDIX B

COMPATIBILITY WITH THE PC/AT* ARCHITECTURE

B.1 HARDWARE DEPARTURES FROM PC/AT SYSTEM ARCHITECTURE................... B-1

B.1.1 DMA Unit ............................................................................................................ .... B-1

B.1.2 Industry Standard Bus (ISA) Signals ......................................................................B-2

B.1.3 Interrupt Control Unit .............................................................................................. B-4

B.1.4 SIO Units .................................................................................... ............................ B-4

B.1.5 CPU-only Reset ...................................................................................................... B-4

B.1.6 HOLD, HLDA Pins ..................................................................................................B-4

B.1.7 Port B ...................................................................................................................... B-5

B.2 SOFTWARE CONSIDERATIONS FOR A PC/AT SYSTEM ARCHITECTURE............ B-5

B.2.1 Embedded Basic Input Output System (BIOS) .......... ... ............ .. ... ........................ . B-5

B.2.2 Embedded Disk Operating System (DOS) .................................. ............ ............ .... B-5

B.2.3 Microsoft* Windows* .................... ...........................................................................B-5

APPENDIX C

EXAMPLE CODE HEADER FILES

C.1 REGISTER DEFINITIONS FOR CODE EXAMPLES ................................................... C-1

C.2 EXAMPLE CODE DEFINES......................................................................................... C-6

xii

CONTENTS

APPENDIX D

SYSTEM REGISTER QUICK REFERENCE

D.1 PERIPHERAL REGISTER ADDRESSES..................................................................... D-1

D.2 CLKPRS ............. .. ............ .................................. .......................................................... D-7

D.3 CS D.4 CS D.5 CS D.6 CS D.7 DLL

D.8 DMABSR ..................... .................................. ...................... ........................ ............... D-13

D.9 DMACFG. .................... ........................ ...................... ...................... ........................... D-14

D.10 DMACHR............................ ...................... ...................... ...................... ...................... D-15

D.11 DMACMD1.................................... ........................ ...................... ...................... .......... D-16

D.12 DMACMD2.................................... ........................ ...................... ...................... .......... D-17

D.13 DMAGRPMSK ........ ...................... ........................ ....................................... ............... D-18

D.14 DMAIEN.............................. ........................... ............................. ................................ D-19

D.15 DMAIS ......................... ............................................................................................... D-20

D.16 DMAMOD1 .................. ........................ ....................................... ...................... .......... D-21

D.17 DMAMOD2 .................. ........................ ....................................... ...................... .......... D-22

D.18 DMAMSK............................ ...................... ...................... ...................... ...................... D-23

D.19 DMA

D.20 DMAOVFE.......................... ...................... ...................... ....................................... ..... D-25

D.21 DMASRR...................................... ........................ ...................... ...................... .......... D-26

D.22 DMASTS............................................................ .................. ................... .................... D-27

D.23 ICW1 (MASTER AND SLAVE) ................. ....................................... ........................... D-28

D.24 ICW2 (MASTER AND SLAVE) ................. ....................................... ........................... D-29

D.25 ICW3 (MASTER).............................................................................. .. ......................... D-29

D.26 ICW3 (SLAVE)............................................... .... ......................................................... D-30

D.27 ICW4 (MASTER AND SLAVE) ................. ....................................... ........................... D-30

D.28 IDCODE.............................. ........................... ............................. ................................ D-31

D.29 IER D.30 IIR

D.31 INTCFG ...................................................................................................................... D-34

D.32 IR....................... ...................... ....................................... ...................... ...................... D-35

D.33 LCR D.34 LSR D.35 MCR D.36 MSR

ADH (UCSADH)..................................................................................................... D-8

ADL (UCSADL)...................................................................................................... D-9

MSKH (UCSMSKH)............................................................................................. D-10

MSKL (UCSMSKL) .............................................................................................. D-11

AND DLHn................ ........................................................................................ D-12

BYCn, DMAnREQn AND DMAnTARn.................. ............................. ............... D-24

..................................................................................... ............................. .......... D-32

.............................. ............................. ........................... ....................................... D-33

.................. ......................................................................................................... D-36

.................. ......................................................................................................... D-37

.................................................................... ........................... ........................... D-38

.................................................................... ........................... ........................... D-39

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Intel386™ EX MICROPROCESSOR USER’S MANUAL

D.37 OCW1 (MASTER AND SLAVE).................................................................................. D-40

D.38 OCW2 (MASTER AND SLAVE).................................................................................. D-41

D.39 OCW3 (MASTER AND SLAVE).................................................................................. D-42

D.40 P1CFG............... ................. ............................... .................. ............................. .......... D-43

D.41 P2CFG............... ................. ............................... .................. ............................. .......... D-44

D.42 P3CFG............... ................. ............................... .................. ............................. .......... D-45

D.43 PINCFG. ............................. ........................... ............................. ........................... ..... D-46

D.44 P D.45 P D.46 P

DIR. ..................................... ....................................... ....................................... ..... D-47

LTC.......................... ............................. .................................................................. D-48

PIN ................................. ....................................... ................................................. D-48

D.47 POLL (MASTER AND SLAVE) ...................... ...................... ........................ ............... D-49

D.48 PORT92 ................................ .................... ................. ................................................. D-50

D.49 PWRCON .................... ........................ ...................... ....................................... .......... D-51

D.50 RBR

n ..........................................................................................................................

D-52

D.51 REMAPCFG ................................. ........................ ...................... ...................... .......... D-53

D.52 RFSADD......... .................... ................. ..................................................... .................. D-54

D.53 RFSBAD................. ........................................... .................. ............................. .......... D-54

D.54 RFSCIR ...................................................................................................................... D-55

D.55 RFSCON................. ............................. ................................ ................. ................... ... D-55

D.56 SCR

.................................................................... ........................... ........................... D-56

D.57 SIOCFG.................. ............................. ....................................................................... D-57

D.58 SSIOBAUD .............................. ............................. ........................... ........................... D-58

D.59 SSIOCON1 .............................. ............................. ........................... ........................... D-59

D.60 SSIOCON2 .............................. ............................. ........................... ........................... D-60

D.61 SSIOCTR............................ ........................... ............................. ................................ D-61

D.62 SSIORBUF ......................... ........................................................................................ D-61

D.63 SSIOTBUF................... ........................ ...................... ...................... ........................... D-62

D.64 TBR

.................. ......................................................................................................... D-62

D.65 TMRCFG ................................. ...................... ...................... ........................ ............... D-63

D.66 TMRCON............................ ...................... ...................... ...................... ...................... D-64

D.67 TMR

.................................................................... ........................... ........................... D-65

D.68 UCSADH................. ............................. ................................ ................. ................... ... D-67

D.69 UCSADL................. ........................................... .................. ............................. .......... D-67

D.70 UCSMSKH................... ........................ ...................... ...................... ........................... D-67

D.71 UCSMSKL .............. ................... .................... ................. ............................... ............. D-67

D.72 WDTCNTH AND WDTCNTL....................................................................................... D-68

D.73 WDTRLDH AND WDTRLDL....................................................................................... D-69

D.74 WDTSTATUS.............................................................................................................. D-70

xiv

CONTENTS

APPENDIX E

INSTRUCTION SET SUMMARY

E.1 INSTRUCTION ENCODING AND CLOCK COUNT SUMMARY.................................. E-1

E.2 INSTRUCTION ENCODING....................................................................................... E-22

E.2.1 32-bit Extensions of the Instruction Set ................................................................E-23

E.2.2 Encoding of Instruction Fields .................................. .................................. ........... E-24

E.2.2.1 Encoding of Operand Length (w) Field .........................................................E-24

E.2.2.2 Encoding of the General Register (reg) Field ........... .................................... E-24

E.2.2.3 Encoding of the Segment Register (sreg) Field ............................................ E-25

E.2.2.4 Encoding of Address Mode ..........................................................................E-26

E.2.2.5 Encoding of Operation Direction (d) Field .................................................... E-30

E.2.2.6 Encoding of Sign-Extend (s) Field ................................................................E-30

E.2.2.7 Encoding of Conditional Test (tttn) Field ...................................................... E-30

E.2.2.8 Encoding of Control or De bug or Test Register (eee) Field ......................... E-31

GLOSSARY

INDEX

Intel386™ EX MICROPROCESSOR USER’S MANUAL

FIGURES

Figure Page

2-1 Intel386™ EX Embedded Processor Block Diagram .......................................... .........2-2

3-1 Instructio n Pipelining .................... ............ ............ ................. ............... ................. .......3-2

3-2 The Intel386™ CX Process o r Internal Block Diagram .......................................... .......3-3

4-1 PC/AT I/O Address Space (10-bit Decode).................... ........................... ................. ..4-3

4-2 Expanded I/O Address Space ( 16-bit Decode) ............................................................4-4

4-3 Address Configuration Register (REMAPCFG)............................................................4-7

4-4 Setting the ESE Bit Code Example ........ ...................... ................. ...................... .........4-8

4-5 DOS-Compatible Mode ..............................................................................................4-10

4-6 Example of Nonintrusive DOS-Compatible Mode ......................................................4-12

4-7 Enhanced DOS M ode . ............... ................. .................................. ................. ............4-13

4-8 NonDOS Mode.................................................................. .........................................4-14

5-1 Peripheral and Pin Connect ions. .................................. ....................................... .........5-2

5-2 Configuratio n of DMA, Bus Arbiter, and Refresh Unit.. .............. ...................... ............ 5-5

5-3 DMA Configuration Register (DMACFG)......................................................................5-6

5-4 Interrupt C ontrol Unit Co nfigurati on..... .......... ....... .......... ....... ........ ....... ....... .......... .......5-9

5-5 Interrupt Configuration Re gister (INTCFG)............................ ..................................... 5-10

5-6 Timer/Counter Uni t Configuration...............................................................................5-12

5-7 Timer Configuration Register (TMRCFG) . ..................................................................5-13

5-8 Serial I/O Unit 0 Configuration....................................................................................5-15

5-9 Serial I/O Unit 1 Configuration....................................................................................5-16

5-10 SIO and SSIO Configuration Register ( SIOCFG). .............................. ........................5-17

5-11 SSIO U nit Configuratio n.............................................................................................5-18

5-12 C onfigurati on of Chip-select Unit and Clock and Power Management Unit ...............5-20

5-13 Core Configuration .....................................................................................................5-21

5-14 Port 9 2 Configuration Register (PORT92) ..................................................................5-22

5-15 Pin Configuration Register (PINCFG).........................................................................5-24

5-16 Port 1 Configuration Register (P1CFG)......................................................................5-25

5-17 Port 2 Configuration Register (P2CFG)......................................................................5-26

5-18 Port 3 Configuration Register (P3CFG)......................................................................5-27

6-1 Basic External Bus Cycles............................................................................................6-6

6-2 Simplified Bus State Diagram (Does Not Include Address Pipelining or Hold states)..6-8

6-3 Ready Logic ...............................................................................................................6-11

6-4 Basic Internal and External Bus Cycles.............. ................................ ........................6-12

6-5 Nonpipelined Addr e ss Read Cycles........................ ...................... ...................... .......6-15

6-6 Nonpipelined Address Write Cycles.................................. .................................. ....... 6-18

6-7 Complete Bus States (Including Pipelined Address)..................................................6-20

6-8 Pipelined Address Cycles...........................................................................................6-21

6-9 Interrupt Acknowledge Cycles ...................................... ..............................................6-25

6-10 Halt C ycle.............................. ....................................... ..............................................6-27

6-11 B asic Refresh Cycle..................................................... ............................. .................6-29

6-12 Refresh Cycle During HOLD/HLDA............................................................................6-30

6-13 1 6-bit Cy cles to 8-bit Devices (Using BS8#)........................................... .................... 6-33

6-14 LOCK# Signal During Address Pipelining ..................................................................6-35

6-15 Intel386 EX Processor to Intel387 SX Math Coprocessor Interface ...........................6-39

xvi

CONTENTS

FIGURES

Figure Page

6-16 Intel 386 EX Processor to SRAM/FLASH Interface.....................................................6-41

6-17 Intel 386 EX Processor to PSRAM Int erface............ ....................................... ............6-42

6-18 Intel386 EX Processor to Paged DRAM Interface......................................................6-43

6-19 Intel 386 EX Processor and Non-Paged DRAM Interface ...........................................6-44

7-1 Standard SMI# .............................................................................................................7-5

7-2 SMIACT# Latency .......................................................................................................7-6

7-3 SMI# During HALT ......................................................................................................7-8

7-4 SMI# During I/O Instruction.......... ................... ...................... ................. ......................7-9

7-5 SMI# Timing. .............................. .................................. ....................................... .......7-10

7-6 Interrupted SMI# Service............................................................................................7-11

7-7 HALT During SMM Handler................................ ....................................... .................7-12

8-1 Clock and Power Management Unit Connections.............................. ..........................8-2

8-2 Clock Synchronization. ........................... ........................... ...........................................8-3

8-3 SMM Interaction with Idle and Powerdown Modes.......................................................8-5

8-4 Clock Prescale Register (CLKPRS) ........................ ....................................... ..............8-7

8-5 Power Control Register (PWRCON).............................................................................8-8

8-6 Timing Diagram, Entering and Leaving Idle Mode ......... .......... ...................... ..............8-9

8-7 Timing Diagram, Entering and Leaving Powerdown Mode ....................... .................8-11

8-8 Reset Synchronization Circuit............................................................................. ....... 8-12

9-1 Interrupt C ontrol Unit Co nfigurati on..... .......... ....... .......... ....... ........ ....... ....... .......... .......9-3

9-2 Methods for Changing the Default Interrupt Structure..................................................9-7

9-3 Interrupt Process – Master Request from Non-slave Source.................... .................9-11

9-4 Interrupt Process – Slave Request............................................................ .................9-12

9-5 Interrupt Process – Master Request from Slave Source............................................9-13

9-6 Port 3 Configuration Register (P3CFG)......................................................................9-18

9-7 Interrupt Configuration Re gister (INTCFG)............................ ..................................... 9-19

9-8 Initializati o n Command Word 1 Register (ICW1)........................................................9-20

9-9 Initializati on Command Word 2 Register (ICW2)........................................................9-21

9-10 Initializatio n Command Word 3 Register (ICW3 – Master).........................................9-22

9-11 Initializatio n Command Word 3 Register (ICW3 – Slave)...........................................9-23

9-12 Initializatio n Command Word 4 Register (ICW4) ................................ ........................9-24

9-13 Operati on Comma nd Word 1 (OCW1) ................................................................ .... ...9-25

9-14 Operati on Comma nd Word 2 (OCW2) ................................................................ .... ...9-26

9-15 Operati on Comma nd Word 3 (OCW3) ................................................................ .... ...9-27

9-16 Poll Status Byte (POLL) .............................................................................................9-28

9-17 Inter rupt A cknowledge Cycle.............................. ................................ ........................9-29

9-18 S purious Interrupts........... ...................... ...................... ...................... ........................9-30

9-19 C ascading External 82C59A Interrupt Controllers............... .......................................9-31

10-1 Timer/Counter Unit Signal Connections.....................................................................10-2

10-2 Mode 0 – Basic Operation..........................................................................................10-7

10-3 Mode 0 – Disabling the Count....................................................................................10-7

10-4 Mode 0 – Writing a New Count...................................................................................10-8

10-5 Mode 1 – Basic Operation..........................................................................................10-9

10-6 Mode 1 – Retriggering the One-shot..........................................................................10-9

xvii

Intel386™ EX MICROPROCESSOR USER’S MANUAL

FIGURES

Figure Page

10-7 Mode 1 – Writing a New Count.................................................................................10-10

10-8 Mode 2 – Basic Operation........................................................................................10-11

10-9 Mode 2 – Disabling the Count..................................................................................10-11

10-10 Mode 2 – Writing a New Count.................................................................................10-12

10-11 Mode 3 – Basic Operat ion (Even Count)..................................................................10-13

10-12 Mode 3 – Basic Operat ion (Odd Count)...................................................................10-14

10-13 Mode 3 – Disabling the Count..................................................................................10-14

10-14 Mode 3 – Writing a New C ount (With a Trigger).......................................................10-15

10-15 Mode 3 – Writing a New Count (Without a Trigger)..................................................10-15

10-16 Mode 4 – Basic Operation........................................................................................10-16

10-17 Mode 4 – Disabling the Count..................................................................................10-17

10-18 Mode 4 – Writing a New Count.................................................................................10-17

10-19 Mode 5 – Basic Operation........................................................................................10-18

10-20 Mode 5 – Retriggering the Strobe ............................................................................ 10-19

10-21 Mode 5 – Writing a New Count Value......................................................................10-19

10-22 Timer Configuration Register (TMRCFG) . ................................................................10-21

10-23 Port 3 Configuration Register (P3CFG)....................................................................10-22

10-24 Pin Configuration Register (PINCFG).......................................................................10-23

10-25 Timer Control Register (TMRCON – Control Word Format) .....................................10-25

10-26 Timer

10-27 Timer Control Register (TMRCON – Counter-latch Format)................................... .10-28

10-28 Timer

10-29 Timer Control Register (TMRCON – Read-back F ormat) ........................................10-30

10-30 Timer

11-1 Serial I/O Unit 1 Configuration...... .............................................. ................................ 11-2

11-2 SIO 11-3 SIO 11-4 SIO 11-5 SIO 11-6 SIO

11-7 Pin Configuration Register (PINCFG).......................................................................11-17

11-8 Port 1 Configuration Register (P1CFG)....................................................................11-18

11-9 Port 2 Configuration Register (P2CFG)....................................................................11-19

11-10 Port 3 Configuration Register (P3CFG)....................................................................11-20

11-11 SIO and SSIO Configur ation Register (SIOCFG) . ............................................... ..... 11-21

11-12 Divisor Latch Registers (DLL 11-13 Transmit Buffer Register (TBR 11-14 Receive Buffer Register (RBR 11-15 Serial Line Control Register (LCR 11-16 Serial Line Status Register (LSR 11-17 Interrupt Enable Register (IER 11-18 Interrupt ID Register (IIR

11-19 Modem Control Signals – Diagnostic Mode Connections ............. ................. ..........11-29

11-20 Modem Control Signals – Internal Connections.......................................................11-29

Baud-rate Generator Clo ck Sources.................................................................11-4

Transmitter........................................................................................................11-7

Data Transmission Process Flow......................................................................11-8

Receiver............................................................................................................11-9

Data Reception Process Flow.........................................................................11-11

and DLHn) ...............................................................11-22

)..............................................................................11-23

).................... ........................... ................. ...............11-24

).........................................................................11-25

)......... ........................... .......................................11-26

)............ ................. ................. ................. ...............11-27

)................ ........................... .......................... ..................11-28

xviii

CONTENTS

FIGURES

Figure Page

11-21 Modem Control Register (MCR 11-22 Modem Status Register (MS R 11-23 Scratch Pad Register (SCR

12-1 DMA Unit Block Diagram............................................................................................12-2

12-2 DMA Temporary Buffer Operation for a Read Transfer..............................................12-8

12-3 DMA Temporary Buffer Operation for A Write Transfer .............................................12-8

12-4 Start of a Two-cycle DMA Transfer Initiated by DRQ

12-5 C hanging the Priority of t h e DMA Channel and External Bus Requests ..................12-10

12-6 Buffer Transfer Ended by an Expir ed Byte Count ......................... ...................... .....12-11

12-7 Buffer Transfer Ended by the EOP# Input................................................................12-11

12-8 Single Data-transfer Mode with Single Buffer-transfer Mode ...................................12-15

12-9 Single Data-transfer Mode with Autoinitialize Buffer-transfer Mode.......... ...............12-16

12-10 Single Data-transfer Mode wi th Chaining Buffer-transfer Mode...............................12-17

12-11 Block Data-transfer Mode with Single Buffer-transfer Mode....................................12-19

12-12 Block Data-transfer Mode with Autoinitialize Buffer-transfer Mode................ ..........12-20

12-13 Buffer Transfer Suspended by the Deactivati on of DRQ

12-14 Demand Data-transfer Mode with Single Buffer-transfer Mode....... ............ ............ .12-22

12-15 Demand Data-transfer Mode with Autoinitialize Buffer-transfer Mode.....................12-23

12-16 Demand Data-transfer Mode with Chaining Buffer-transfer Mode ...........................12-24

12-17 Cascade Mode..... ........................ ............ .......... ............ .......... ............ .......... ..........12-26

12-18 Pin Configuration Register (PINCFG).......................................................................12-31

12-19 DMA Configuration Register (DMACFG)..................................................................12-32

12-20 DMA Channel Address and Byte Count Registers

(DMA

REQn, DMAnTARn, DMAnBYCn) .................. ...............................................12-33

12-21 DMA Overflow Enable Register (DMAOVFE)...........................................................12-34

12-22 DMA Command 1 Register (DMACMD1). ................................ ................................12-35

12-23 DMA Status Register (DMASTS) .... ..........................................................................12-36

12-24 DMA Command 2 Register (DMACMD2). ................................ ................................12-37

12-25 DMA Mode 1 Register (DMAMOD1)........................................................................12-39

12-26 DMA Mode 2 Register (DMAMOD2)........................................................................12-41

12-27 DMA Software Request Register (DMASRR – write format)....................................12-42

12-28 DMA Software Request Register (DMASRR – read format)....................................12-43

12-29 DMA Channel Mask Register (DMAMSK)................................................................12-44

12-30 DMA Group Channel Mask Register (DMAGRPMSK).............................................12-45

12-31 DMA Bus Size Register (DMABSR).........................................................................12-46

12-32 DMA Chaining Register (DMACHR).........................................................................12-47

12-33 DMA Interrupt Enable Register (DMAIEN)...............................................................12-48

12-34 DMA Interrupt Status Register (DMAIS)...................................................................12-49

13-1 Transmitter and Receiver in Master Mode ..................... .................... ..................... ...13-2

13-2 Transmitter i n Master Mode, Receiver in Slave Mode.. ..............................................13-2

13-3 Transmitter in Slave Mode, Receiver in Master Mode................................................13-3

13-4 Transmitter and Receiver in Slave Mode. ..................................................................13-3

13-5 Clock Sources for the Baud-rate Generator..................................................... .......... 1 3-5

13-6 SSIO Transmitter with Autotransmit Mode Enabled...................................................13-7

). ............................................................................11-30

).................... ............... ................. ...........................11-31

)............ ................................ .......................................11-32

...............................................12-9

............. ................. ..........12-21

xix

Intel386™ EX MICROPROCESSOR USER’S MANUAL

FIGURES

Figure Page

13-7 SSIO Transmitter with Autotransmit Mode Disabled..................................................13-8

13-8 Transmit Data by Polling............................................................................................13-9

13-9 Interrupt S ervice Routine for Transmitting Data Using Interrupts.............................13-10

13-10 Transmitter Master Mode, Single Word Transfer (Enabled when Cl ock is High) .....13-11

13-11 Transmitter Master Mode, Single Word Transfer (Enabled when Cl ock is Low)......13-11

13-12 Receive Data by Polling ........................................................... .. ..............................13-13

13-13 Interrupt S ervice Routine for Receiving Data Using Int errupts.................................13-14

13-14 Receiver Master Mode, Single Word Transf er .................... ...................... ...............13-15

13-15 Pin Configuration Register (PINCFG).......................................................................13-17

13-16 SIO and SSIO Configur ation Register (SIOCFG) . ............................................... ..... 13-18

13-17 Clock Prescale Register (CLKPRS) ............ ............................. ................................13-19

13-18 SSIO Baud-rate Control Register (SSIOBAUD) .......................................... ............. 13-20

13-19 SSIO Baud-rate Count Down Register (SSIOCTR)..................................................13-21

13-20 SSIO Control 1 Register (SSIOCON1)................................................. ................... . 13-22

13-21 SSIO Control 2 Register (SSIOCON2)................................................. ................... . 13-23

13-22 SSIO Transmit Holding Buffer (SSIOTBUF)....................................... ......................13-24

13-23 SSIO Receive Holding Buffer (SSIORBUF) ............................................................. 13-25

14-1 C hannel Address Comparison Logic............................ ............................. .................14-3

14-2 Determining a Channel’s Address Block Size............................................................1 4-4

14-3 Bus Cycle Length Adj ustments for Overlapping Regions.................................... .....14-12

14-4 Pin Configuration Register (PINCFG).......................................................................14-15

14-5 Port 2 Configuration Register (P2CFG)....................................................................14-16

14-6 Chip-select High Address Register (CS 14-7 Chip-select Low Address Register (CS 14-8 Chip-select High Mask Regist ers (CS 14-9 Chip-select Low Mask Registers (CS

15-1 Refresh Control Unit Connections..............................................................................15-3

15-2 Refresh Clock Interval Register (RFSCIR).................................................................15-7

15-3 Refresh Control Register (RFSCON) .. .......................................................................15-8

15-4 Refresh Base Address Register (RFSBAD)...............................................................15-9

15-5 Refresh Address Register (RFSADD)......................................................................15-10

15-6 Connections to Ensure Refresh of All Rows in a n 8-Bit Wide PSRAM Device ........15-11

15-7 RAS# Only Refresh Logic: Paged Mode...................... ....................................... ..... 15-13

15-8 RAS# Only Refresh Logic: Non-Paged Mode..........................................................15-14

16-1 I/O Port Block Diagram........................................................................... ....................16-2

16-2 Logic Diagram of a Bi-directional Port........................................................................ 16-3

16-3 Port 16-4 Port Direction Register (P 16-5 Port Data Latch Register (P 16-6 Port Pin State Register (P

17-1 Watchdog Timer Unit Connecti ons . ............. ................. ................. ................. ............17-2

17-2 WDT Counter Value Registers (WD TCNTH and WDTCNTL)....................................17-8

17-3 WDT Status Register (WDTSTATUS)........................................................................17-9

Configuration Register (PnCFG)......................................................................16-7

DIR ) ........ ..... ............ ..... ............ ............ ..... ............ ..........16-8

LTC)..................................... .........................................16-8

PIN ) ... ..... ..... ............ ............ ............ ..... ............ ............ ...16-9

ADH, UCSADH) .......................................14-17

ADL, UCSADL) .........................................14-18

MSKH, UCSMSKH)........................... ..........14-19

MSKL, UCSMSKL).......................................14-20

CONTENTS

FIGURES

Figure Page

17-4 WDT Reload Value Registers (WDTRLDH and WDTRLDL)....................................17-10

17-5 Power Control Register (PWRCON).........................................................................17-11

18-1 Test Lo gic Unit Connections . ................. ................................................................. ... 18-2

18-2 TAP Controller (Finite-State Machine)...... ..... ................................................... ..... .....18-6

18-3 Instructio n Register (IR)................ ............ ................. ............ ................. ............... ..... 1 8-7

18-4 Identification Code Register (IDCODE)................................. ................. ....................18-8

18-5 Internal and External Timing for Loading t he Instructio n Register............................18-12

18-6 Internal and External Timing for Loading a Data Register........................................18-13

B-1 Derivation of AEN Signal in a Typi cal PC/AT System .. ........................................... .... B-3

B-2 Derivation of AEN Signal for I ntel386™ EX processor-based Systems . .....................B-3

E-1 General Instruction Format............... .........................................................................E-22

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Intel386™ EX MICROPROCESSOR USER’S MANUAL

TABLES

Table Page

2-1 PC-compatible Peripherals............................................................ ...............................2-3

2-2 Embedded Application-specific Peripherals.................................................................2-4

4-1 Peripheral Register I/O Address Map in Slot 15 . ..........................................................4-5

4-2 Peripheral Register Addresses ...................................................................................4-15

5-1 Master’s IR3 Connections................. ........................... ................................................5-8

5-2 Master’s IR4 Connections................. ........................... ................................................5-8

5-3 Signal Pairs on Pins without a Multiplexer..................................................................5-23

5-4 Example Pin Configuration Registers............................................................. ............ 5-30

5-5 Example DMACFG Configuration Register................................................................5-31

5-6 Example TMRCFG Configuration Register........................................ ........................5-32

5-7 Example INTCFG Configuration Register ............... ...................................................5-33

5-8 Example SIOCFG Configuration Register............... ...................................................5-33

5-9 Pin Configuration Register Design Woksheet......... ................. ............ ............ ..........5-34

5-10 DMACFG Register Design Worksheet.......................................................................5-35

5-11 TMRCFG Register Design Worksheet .......................................................................5-36

5-12 INTCFG Register Design Worksheet .........................................................................5-37

5-13 SIOCFG R egister Design Worksheet ............................................ .............................5-37

6-1 Bus Interface Unit Signals............................................................. .. .............................6-3

6-2 Bus Status Definitio ns .................... ................. ............... ............ ............ ................. ..... 6-5

6-3 Sequence of Nonaligned Bus Transfers.....................................................................6-10

7-1 CR0 Bits Cleared Upon Entering SMM ........................................................................7-3

7-2 SMM Processor State Initialization Values...................................................................7-4

7-3 Relative Priority of Exceptions and Interrupts...................... .........................................7- 7

8-1 Clock and Power Managem ent Registers ............... ....................................... ..............8-6

8-2 Clock and Power Management Signals........................................................................8-6

9-1 82C59A Master and Slave Interrupt Sources...............................................................9-5

9-2 ICU Registers................... ....................................... .................................. .................9-16

10-1 TCU Signals. ..............................................................................................................10-3

10-2 TCU Associated Registers .........................................................................................10-4

10-3 Operati ons Caused by GATE

10-4 GATEn Connection Options................................................................................ ..... 10-20

10-5 Minimum and Maximum Initial Counts......................................................................10-26

10-6 Results of Multiple Read-back Commands Without Reads......................................10-33

11-1 SIO Signals ............................................ ....................................................................11-3

11-2 Maximum and Minimum Output Bit Rates..................................................................11-5

11-3 Divisor Values for Common Bit Rates. .......................................................................11-5

11-4 Status Signal Priorities and S ources......................................................... ...............11-13

11-5 SIO Registers................... .................................. ....................................... ...............11-15

11-6 Access to Multi plexed Registers...............................................................................11-16

12-1 DMA Signals...............................................................................................................12-4

12-2 Operations Performed During Transfer......................................................................12-6

12-3 DMA Registers .........................................................................................................12-28

12-4 DMA Software Commands. ......................................................................................12-50

13-1 SSIO Signals............. ............................................................... ..................................1 3-4

n...................................................................................10-6

xxii

CONTENTS

TABLES

Table Page

13-2 Maximum and Minimum Baud-rate Output Frequencies ............................. ........ .......13-6

13-3 SSIO Registers.................................. ............................................................. ..........13-16

14-1 CSU Signals .............................................................................................................14-13

14-2 CSU Registers. .........................................................................................................14-14

15-1 RCU Signals...............................................................................................................15-4

15-2 RCU Registers ...........................................................................................................15-6

16-1 Pin Multiplexing ..........................................................................................................16-5

16-2 I/O Port Registers... ....................................................................................................16-6

16-3 Control Register V alues for I/O Port Pin Configurati o ns...... ....... .......... ....... ........ .......16-7

17-1 WDT Signals ..............................................................................................................17-3

17-2 WDT Registers...........................................................................................................17-7

18-1 Test Access Port Dedicated Pins...............................................................................18-3

18-2 TAP Controller State Descriptions ............... ............ .................................. .............. ...18-4

18-3 Example TAP Controller State Selections......................... .............. ...........................18-5

18-4 Test-logic Unit Instructions........... .............................................................................. 18-7

18-5 Boundary-scan Register Bit Assignments..................................................................18-9

A-1 Signal Description Abbreviations................................................................................. A-1

A-2 Description of Signals Available at t he Device Pins....................................................A-2

A-3 Pin State Abbreviations. ..............................................................................................A-8

A-4 Pin States After Reset and During Idle, Powerdown, and Hold..... .............................. A-9

D-1 Peripheral Register Addresses.............................................. ......................................D-1

E-1 Instruction Set Summary................ ......................................................................... .... E-2

E-2 Fields Within Instructions...........................................................................................E-23

E-3 Encoding of Operand Length (w) Field......................................................................E-24

E-4 Encoding of reg Field When w Field is not Present in Instruction ............................. E-24

E-5 Encoding of reg Field When w Field is Present in Instruction ................................... E-25

E-6 Encoding of the Segment Regi ster (sreg) Field.................................. ....................... E-25

E-7 Encoding of 16-bit Address Mode with “mod r/m” Byte.............................................E-27

E-8 Encoding of 32-bit Address Mode with “mod r/m” Byte (No s-i-b Byte Pr esent).... .... E-28

E-9 Encoding of 32-bit Address Mode (“mod r/m” Byte and s-i-b Byte Present)..............E-29

E-10 Encoding of Operation Direction (d) Field.................................................................E-30

E-11 Encoding of Sign-Extend (s) Field.............................................................................E-30

E-12 Encoding of Conditional Test (tttn) Field.. ................................................................. E-30

E-13 When Interpreted as Control Register Field ............ .. ..... ..... ..... .. ..... ..... ..... .. ..... ..... .... E-31

E-14 When Interpreted as Debug Register Field...............................................................E-31

E-15 When Interpreted as Test Register Field...................................................................E-31

xxiii

GUIDE TO THIS MANUAL

CHA PT ER 1

GUIDE TO THIS MANUAL

This manual describes the Intel386™ EX Embedded Processor. It is intended for use by hardware designers famili ar wi th the pri nciples of micro process ors and with t he Intel386 p roces sor architecture.

This chapter is organized as follows:

• Manual Contents (see below )

• Notational Conventions (page 1-3)

• Special Terminology (page 1-4)

• Related Documents (page 1-5)

• Electronic Support Systems (page 1-6)

• Technical Support (page 1-7)

• Product Li terature (page 1-8)

1.1 MANUAL CONTENTS

This manual contains 1 8 chapters and 5 appendixe s, a glossa ry, and an index. This section summarizes the contents of the remaining chapters and appendixes. The remainder of this chapter describes notational conventions and special terminology used throughout the manual and provides references to related documentation.

Chapter 2 — Architectur al Ove rvi ew — des cribe s t he devi ce fea tures and some p otent ial applicati ons.

Chapter 3 — Core Overview — describes the differences between this device and the Intel386 SX processor core.

Chapter 4 — System Register Organization — describes the organization of the system registers, the I/O address space, address decoding, an d addressing mo des.

Chapter 5 — Device Configuration — explains how to configure the device for various applications.

Chapter 6 — Bus Interface Unit — describes the bus interface logic, bus states, bus cycles, and instruction pipelining.

Chapter 7 — System Management Mode — describes Intel’s System Management Mode (SMM).

Chapter 8 — Clock and Power Management Unit — describes the clock generation circuitry, power manageme nt mo des, and system rese t logic.

™

1-1

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

Chapter 9 — Interrupt Control Unit — describes the interrupt sources and priority options and explains how to program the interrupt control unit.

Chapter 10 — Timer/Counter Unit — describes the timer/co unters and thei r available count formats and operating modes.

Chapter 11 — Asynchronous Serial I/O (SIO) Unit — explains how to use the universal asynchronous receiver/transmitters (UAR Ts) to transmit and receive serial data.

Chapter 12 — DMA Controller — describes how the enhanced direct memory access controller allows internal and external devices to transfer data directly to and from the system and explains how bus control is arbitrat ed.

Chapter 13 — Synchronous Serial I/O (SSIO) Uni t — expl ains how to transmit an d receive data synchronously.

Chapter 14 — Chip-select Unit — explains how to use the chip-select channels to access various external memory and I/O devices.

Chapter 15 — Refresh Control Unit — desc ribes how the refresh control unit generates periodic refresh requests and refresh addresses to simplify the interface to dynamic memory devices.

Chapter 16 — Input/Output Ports — describes the general-purpose I/O ports and explains how to configure each pin to serve either as an I/O pin or as a pin controlled by an internal peripheral.

Chapter 17 — Watchdog Timer Unit — explains how to use the watchdog timer unit as a software watchdog, bus monitor, or general-purpose timer.

Chapter 18 — JTAG Test-logic Unit — des cri bes t he i n dependent test -logic unit and expl ai ns how to test the device logic and board-level connectio ns.

Appendix A — Signal Descriptions — describes the device pins and signals and lists pin states after a system reset and during powerdown, idle, and hold.

Appendix B — Co m patib ility wi th PC/AT* Architecture — des cribe s the w ays i n whic h the device is compatible with the standard PC/AT architecture and the ways in which it departs from the standard.

Appendix C — Example Code Header Files — contains the header files called by the code examples that are included in several chapters of this manual.

Appendix D — System Register Quic k Referen ce — contains an alphabetical list of registers. Appendix E — Instruction Set Summary — lists all instructions and their clock counts. Glossary — define s term s with spec ial meaning us ed thr oughout this manual. Index — lists key topics with page number references.

1-2

GUIDE TO THIS MANUAL

1.2 NOTAT IONAL CONV E NTI ONS

The following notations are used throughout this manual. # The pound symbol (#) appended to a signal name indicates that the signal

is active low.

Variables Variables are shown in italics. Variables must be replaced with correct

values.

New Terms New terms are shown in italics. See the Glossary for a brief definition of

commonly used terms.

Instruction s Instruction mnemonics are shown in upper case. When you are

programming, instructions are not case sensitive. You may use either upper or lower case.

Numbers Hexadecima l numbers are represente d by a string of hexadecimal digits

followed by the character H. A zero prefix is added to numbers that begin with A through F. (For example, FF is shown as 0FFH.) Decimal and binary numbers are represented by their customary notations. (That is, 255 is a decimal number and 1111 1111 is a binary number. In some cases, the letter B is added for clarity.)

Units of Measure The following abbreviations are used to represent units of measure:

A amps, amperes Gbyte gigabytes Kbyte kilobytes KΩ kilo-ohms mA milliamps, milliamperes Mbyte megabytes MHz megahertz ms milliseconds mW milliwatts ns nanoseconds pF picofarads W watts Vvolts

µA microamps, microamperes µF microfarads µs microseconds µW microwatts

1-3

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

numbers separa ted b y a colon (exampl e: 7:0 or 15:0). The first bit shown (7 or 15 in the example) is the most-significant bit and the second bit shown (0) is the least-significant bit.

lowercase, italic character, it represents more than one register. For example, PnCFG represents three registers: P1CFG, P2CFG, and P3CFG.

Signal Names Signal names are shown in upper case. When several signals share a

common name, an individual signal is represented by the signal name followed by a number, while the group is represented by the signal name followed by a variabl e (n). For example, the lower chi p-se lec t signal s are named CS0#, CS1#, CS2#, and s o on; they are c ollectively c alled CSn#. A pound symbol (#) appended to a signa l name identifies a n active-low signal. Port pins are represented by the port abbreviatio n, a period, and the pin number (e.g., P1.0, P1.1).

1.3 SPECIAL T ERMINOLOGY

The following terms have special meanings in this manual. Assert and Deassert The terms asse rt and deassert refer to the act of making a signal

active and inactive, respe ctive ly. The ac t ive pola rity (high/l ow) is defined by the signal name. Active-low signals are designated by a pound symbol (#) suffix; a ctive-high s ignals have no suff ix. To assert RD# is to drive it low; to assert HOLD is to drive it high; to deassert RD# is to drive it high; to deassert HOLD is to drive it low.

DOS I/O Address Integrated perip herals that are compa tible with PC/AT syst em

architecture can be mappe d into DOS (or PC/AT) addresses 0H– 03FFH. In this manual, the terms DOS address and PC/AT address

are synonymous.

Expanded I/O Address All peripheral registers reside at I/O addresses 0F000H–0FFFFH.

PC/AT-compat ibl e integrat ed periphe rals can also be mapped into DOS (or PC/AT) address space (0H–03FFH).

PC/AT Address Integrated peripherals that are compa tible with PC/AT system

architecture can be mappe d into PC/AT (or DOS) addresses 0H– 03FFH. In this manual, the terms DOS address and PC/AT address

are synonymous.

Processor and CPU Processor refers to the Intel3 86 EX process or including the

integrated peripheral s. CP U refers to the processor core, which is based on the static Intel386 SX processor.

1-4

GUIDE TO THIS MANUAL

Reserved Bits Reserved bits are not used in this device, but they may be used in

future implement ations. Follow thes e guidel ine s to ensure compatibility wi th future devices:

• Avoid any software depe ndence on the state of undefined

• Use a read-mo dify-write sequence to load registers .

• Mask undefined bit s when testing the val ues of defined bits.

• Do not depend on t he stat e of undefined bits when storing

undefined bits to memory or to another register.

• Do not depend on the ability to retain informat i on written to

undefined bits.

Set and Clear The terms set and clear refer to the value of a bit or the act of giving

it a value. If a bit is set, its value is “1”; setting a bit gives it a “1” val ue . I f a bit is clear, its value is “0”; clearin g a bit gives it a “0” value.

1.4 RELATED DOCUMENTS

The following document s contain addit iona l informatio n that is useful in designin g systems that incorporate the Intel386 EX processor. To order documents, please call Intel Li terature Fulfi llment (1-800-548-4725 in the U .S. and Canada; +44(0) 1793-431155 in Europe).

Document Name Order Number

Intel386™ EX Embedded Microprocessor Intel386™ SX Micro pro cessor Intel386™ SX Micro pro cessor Programmer’s Reference Manual Intel386™ SX Micro pro cessor Hardware Reference Manual Development T ools Buyer’ s Guide for the Intel386™ Em be dded Proces sor Fam ily Intel386™ EX Microprocessor Pin Multiplexing Map

Packaging

datashe et

datasheet

272420 240187 240331 240332 272326 272520 272587 240800

You may also want to refer to Standard 1149.1—1990, IEEE Standard Test Access Port and Boundary-Scan Architecture and its supplement, Standard 1149.1a—1993.

1-5

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

1.5 ELECTRONIC SUPPORT SYSTEMS

Intel’ s FaxBack* service and application BBS provide up-to-date technical information. Intel also maintains several forums on CompuServe and offers a variety of information on the World Wide Web. These systems are available 24 hours a day, 7 days a week, providing technical information whenever you need it.

1.5.1 FaxBack Service

FaxBack is an on-demand publishing system that sends documents to your fax machine. Y ou can get product announcement s, change notifications, product literature, device characteristics, de sign recommenda tions, and quality and reliabil ity information from F axBack 2 4 hours a day, 7 days a week.

1-800-525-3019 (US or Canada) +44-1793-432509 (E urope) +65-256-5350 (Singapore ) +852-2-844-4448 (Hong Kong) +886-2-514-0815 (Taiwan) +822-767-2594 (Korea) +61-2-975-3922 (Aust ralia) 1-503-264-6835 (Worldwide)

Think of the FaxB ack servi ce as a lib rary of techni cal doc um ent s that y ou can acce ss wi th your phone. Just dial the telephone number and respond to the system prompts. After you select a document, the system sends a copy to your fax machine .

Each document has an order number and is listed in a subject catalog. The first time you use FaxBack, you should order the appropriate subject catalogs to get a complete list of document order numbers. Catalogs are updated twice monthly. In addition, daily update catalogs list the title, status, and order number of each document that has been added, revi sed, or deleted duri ng the past eight weeks . To receive the update for a subject catalog, enter the subject catalog number followed by a zero. For example, for the complete microcontroller and flash catalog, request document number 2; f or the daily up date to the microcontrol ler and flash catalog, request docum ent number 20.

The following catalogs and information are available at the time of publication:

1. Solutions OEM subscriptio n form

2. Microcontrolle r and flash catalog

3. Developme nt tools catalog

4. Systems catalog

5. Multime dia catalo g

6. Multibus and iRMX

1-6

software catalog and BBS file listings

GUIDE TO THIS MANUAL

7. Microprocessor, PCI, and peripheral catalog

8. Quality and reliability and change notification catalo g

9. iAL (Intel Architectu re Labs) technology catalog

1.5.2 Bulletin Board System (BBS)

The bulletin board system (BBS) lets you download files to your computer. The application BBS has the latest ApBUILDER software, hyperte xt manual s and datas heets, softwa re drivers, firm ware upgrades, code examples, application notes and utilities, and quality and reliability data.

The system supports 1200- through 19200-baud modems. Typical modem settings are 14400 baud, no parity, 8 data bits, and 1 stop bit (14400, N, 8, 1).

To acces s the BBS, use a terminal program to dial the telephone n umber given below for your area; once you are co nnected, respond to the system prompts. During your first session, enter your name and location. The system operator will set up your acce ss acco unt withi n 24 ho urs. At that time, you can access the files on the BBS.

503-264-7999 U.S., Canada , Japan , Asia Pacifi c (up to 19.2 Kbau d ) 44(0)1793-432955 Europe

NOTE

If you ha ve problems accessing the BBS, use the se settings for your modem: 2400, N, 8, 1. Refer to your termina l software docum entat ion for instructio ns on changing these settings.

1.5.3 CompuServe Forums

The CompuServe forums provide a means for you to gather information, share discoveries, and debate issues. Ty pe “go intel” for access. For information about CompuServe access and service fees, call CompuServe at 1-800-848-8199 (U.S.) or 61 4-529-1340 (outside the U.S.).

1.5.4 World Wide Web

We offer a variet y of information through the World Wide Web (http://www.int el.com/). Se lect “Embedded Design Products” from the Intel home page.

1.6 TE CHNICAL S UPPO RT

In the U.S. and Canada, technical support representatives are availabl e to answer your questions between 5 a.m. and 5 p.m. PST. You can also fax your questions to us. (Please include your voice telephone number and indicate whether you prefer a response by phone or by fax). Outside the U.S. and Canada, please contact your local dist ribut or.

1-800-628-8686 U.S. and Canada 916-356-7599 U.S. and Canada 916-356-6100 (fax) U.S. and C anada

1-7

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

1.7 PROD UCT LITERA T URE

You can order product literature from the following Intel literature centers.

1-800-548-4725 U.S. and Canada 708-296-9333 U.S. (from overseas) 44(0)1793-431155 Europe (U.K.) 44(0)1793-421333 Germany 44(0)1793-421777 France 81(0)120-47-88-32 Japan (fax only)

1-8

ARCHITECTURAL OVERVIEW

CHA PT ER 2

ARCHITEC TURAL OVERV IEW

The Intel386™ EX embedded processor (Figure 2-1) is based on the static I ntel386 SX processor.

This highly integrated device retains those personal computer functions that are useful in embedded applications and i ntegrates peri pherals that are typic ally needed i n embed ded systems . The

Intel386 EX processor provides a PC-com patible devel opm ent platform in a device t hat i s opti -

mized for embedded applications. Its integrated peripherals and power management options make the Intel38 6 EX process or ideal for portable system s.

The integrated peripherals of the Intel386 EX processor are compatible with the standard desktop PC. This allows existing PC softwa re, including most of the industry’s leading desktop and embedded operating systems, to be easily implemented on an Intel386 EX processor-based platform.

Using PC-compatible peripherals also allows for the deve lopm ent a n d debugging of applicatio n software on a standard PC platform.

Typic al applications using the Intel386 EX processor i nclude automated man ufacturing equipment, cellular telephones, telecommunications equipment, fax machines, hand-held data loggers, high-precision industrial flow controllers, interactive t el evision, medical equipment , modems, and smart copiers.

This chapter is organized as follows:

• Intel386 EX Embedded Processor Core (see belo w)

• Integrated Peripherals (page 2-3)

2.1 Intel386 E X EMBEDDE D P ROCE SS OR CORE The Intel38 6 EX processor contains a modular, fully static Intel386 CX central processing unit

(CPU). The Intel3 86 CX processor is an enhanc ed Intel386 SX proce ssor with the addition o f System Manag ement Mode (SMM) and two additional address lines. The Intel386 EX processor has a 16-bit data bus and a 26-bit address bus, supporti ng up to 6 4 Mbytes of memory address space and 64 Kbytes of I/O address space. The performance of the Intel386 EX processor closely reflects the Intel386 SX CPU performance at the same speeds.

Chapter 3, “CORE OVERVIEW” describes differences betwee n the Intel3 86 EX processor core and the Intel38 6 SX process or. Pleas e refer to the Inte l386™ SX Microprocessor Programmer ’s Reference Manual (order number 2 40331) f or applications and system programm ing information; descriptions of protected, real, and virtual-8086 modes; and details on the instruction set.

2-1

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

Intel386™ CX Core



Core Enhancements

- A20 Gate

- CPU Reset

- SMM

Address

Data

Address

Bus Interface

Unit

Chip-select

Unit

JTAG Unit

Clock and Power

Management Unit

DRAM Refresh

Control Unit

Watchdog Timer Unit

Bus Monitor

Asynchronous Serial I/O

2 channels

(16450 compatible)

Synchronous Serial I/O

1 channel, full duplex

2-2

Timer/counter Unit

3 channels

(82C54 compatible)

I/O Ports

INTR

Interrupt Control Unit

DMA Controller

2 channels

(8237A compatible)

and Bus Arbiter Unit

Figure 2-1. Intel386™ EX Embedded Processor Block Diagram

A2849-02

ARCHITECTURAL OVERVIEW

2.2 INTEGRATED PERIPHERALS

The Intel386 EX processor integrates both PC-compatible peripherals (T able 2-1) and peripherals that are specifi c to embed ded applic ati ons (Table 2-2).

Table 2-1. PC-compati ble Peripherals

Name Descripti on

Interrupt Control Unit (ICU)

Timer/count er Unit (TCU)

Asynchronous Serial I/O (SIO) Unit

Direct Memory Access (DMA) Controller

Consists of two 82C59A programmable interrupt controllers (PICs) configured as master and slave. You may cascade up to six external 82C59A PICs to expand the external interrupt lines to 52. Refer to Cha pter 9, “INTERRUPT CONTROL UNIT.”

Provides three independent 16-bit down counters. The programmable TCU is functionally equivalent to three 82C54 counter/timers with enhancements to allow remapping of peripheral addresses and interrupt assignments. Refer to Chapter 10, “TIMER/COUNTER UNIT.”

Features two independent universal asynchronous receiver and transmitter (UART) units which are functio nall y equiva lent to Nation a l Semicon ductor’s NS1645 0. Each channel contains a baud-rate generator, transmitter, receiver, and modem control unit. Receive and transmi t int erru pt signal s can be conne cted to the ICU controll er and DMA controller. Refer to Chapter 11, “ASYNCHRONOUS SERIAL I/O UNIT.”

Transfers internal or external data between any combination of memory and I/O devices for the entire 26-bit address bus. The two independent channels operate in 16- or 8-bit bus mode. Buffer chaining allows data to be transferred into noncontiguous memory buffe r s. Th e DMA chann els can be tie d to any of th e ser ia l d evices to support high data rates, minimizing processor interruptions. Provides a special two-cycle mode that uses only one channel for memory-to-memory transfers. Bus arbitration logic resolves priority conflicts between the DMA channel s, the refresh contro l unit, an d an exte rna l bus master. SIO and SSIO interrupts can be connected to DMA for high-speed transfers. Backward compatible with 8237A. Refer to Chapter 12, “DMA CONTROLLER.”

2-3

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

Table 2-2. Embedded Application-specific Peripherals

Name Descript ion

System Management Mode (SMM)

Clock and Power Management Unit

Synchronous Serial I/O (SSIO) unit

Chip-select Unit (CSU)

Refresh Control Unit (RCU)

Parallel I/O Ports

The Intel386 EX processor provides a mechanism for system management with a combinatio n of hardware and CPU microco de enhan cem ents. An extern ally gen erate d system management interrupt (SMI#) allows the execution of system-wide routines that are independent and transparent to the operating system. The system management mode (SMM) architectural extensio ns to the Intel386 CPU are describ e d in Chapter 7, “SYSTEM MANAGEMENT MODE.”

An external clock source provides the input frequency. The clock and power management unit generates separate internal clock signals for core and peripherals (half the input frequency), divides the internal clock by two for baud clock inputs to the SIO and SSIO, and divides the internal clock by a programmable divisor to provide a prescaled clock signal (various freq uen cies) for the TCU and SSIO.

Power management provides idle and powerdown modes (idle stops the CPU clock but leaves the peripheral clocks running; powerdown stops both CPU and peripheral clocks). An external clockout signal is also provided. Refer to Chapter 8, “CLOCK AND POWER MANAGEMENT UNIT.”

Provides simultaneous, bidirectional high speed serial I/O. Consists of a transmit channel, a receive channel, and a baud rate generator. Built-in protocols are not included, because these can be emulated using the CPU. SSIO interrupts can be connecte d to the DMA unit for high-speed transfers. Refer to Chapter 13, “SYNCHRONOUS SERIAL I/O UNIT.”

Programmable, eight-channel CSU allows direct access to up to eight devices. Each channel can operate in 16- or 8-bit bus mode and can generate up to 31 wait states. The CSU can interface with the fastest memory or the slowest peripheral device. The minimum address bloc k for memory add ress-con figure d chan nels is 2 K byte s. The size of these address blocks can be increased by powers of 2 Kbytes for memory addresses and by multiples of 2 bytes for I/O addresses. Supports SMM memory addressing and provides ready generation and programmable wait states. Refer to Chapter 14, “CHIP-SELECT UNIT.”

Provides a means to generate periodic refresh requests and refresh addresses. Consists of a programmable interva l timer unit, a control unit, and an address generation unit. Bus arbitrati on log ic ensure s that refr esh req uest s have the highest prio rit y. The refresh control unit (RCU) is provided for applications that use DRAMs with a simple EPLD-based DRAM controller or PSRAMs that do not need a separate controller. Refer to Chapter 15, “REFRESH CONTROL UNIT.”

Three I/O ports facili tate da ta transfe r betwe en the proces sor and surroun ding system circuitry. The Intel386 EX processo r is unique in that several functi ons are mul tiple xed with each other or with I/O ports. This ensu res maxim u m use of availa ble pins an d mainta in s a small package. Each multiplexed pin is individually programmable for peripheral or I/O function. Refer to Chapter 16, “INPUT/OUTPUT PORTS.”

Watchdog Timer (WDT) Unit

JTAG Testlogic Uni t

When enabled, the WDT functions as a general purpose 32-bit timer, a software timer, or a bus monitor. Refer to Chapter 17, “WATCHDOG TIMER UNIT.”

The test-logic unit simplifies board-level testing. Consists of a test access port and a boundary-scan register. Fully compliant with Standard 1149.1–1990,

Access Port and Boundary-Scan Architecture

Refer to Chapter 18, “JTAG TEST-LOGIC UNIT.”

2-4

IEEE Standard Test

and its supplement, Standard 1149 .1a–1993.

CORE OVERVIEW

CHA PT ER 3

CORE OV ERVIEW

The Intel386™ EX processor core is based upon th e Inte l386 CX pro cessor , which is an enhanced version of the Intel386 SX processor. This chapter describes the Intel386 CX processor enhancements over the Intel386 SX processor, internal architecture of the Intel386 CX processor, and the core interface on the Intel386 EX processor.

This chapter is organized as follows:

• Intel386 CX Processor Enhanceme nts (see below)

• Intel386 CX Processor Internal Architec ture (page 3-2)

• Core Intel386 EX Processor Interface (page 3-6)

3.1 Intel386 CX PROCESS OR ENHANCE M ENT S

The Intel386 CX processor, based on the Intel386 SX processor, adds system management mode and two additional address lines for a total of 26 address lines.

3.1.1 System Management Mode

The Intel386 CX processor core provides a mechanism for system management with a combination of hardwa re and CPU m icrocode en hancements. An external ly generat ed System Management Interr upt (SMI#) allows the execution of syste m wide r outine s whic h are i nde pendent an d transparent to the operat i ng syste m. The Syst em Mana ge me nt Mode (SM M ) archit ec ture exte nsions to the Intel386 SX processor consi st of the following elem ents :

• Interrupt input pin (SMI#) to invoke SMM

• One output pin to identify execution state (SMIACT#)

• One new instruction (RSM, exec utable only from SMM) to exit SMM

• SMM also added one to four execution cloc ks to the following inst r uctions: IN, IN S, RE P

INS, OUT, REP OUT, POPA, HALT, M OV CR0, and SRC. INTR and NMI also need an additional two clocks for interr upt latency. T hese cycles were added due to the microcode modification for the SMM implementation. R efer to Appendix E for the exact execution times. Otherwise , 100% of the Intel386 SX proc essor inst ruct ions exec ute on the Intel386 CX processor core.

Please refer to Chapter 7 for more details on System Managem ent Mode.

3.1.2 Additional Address Lines

T wo additional address lines were added to the Intel386 CX processor core for a total of 26. This expands the physical address space from 16 Mbytes to 64 M bytes.

3-1

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

3.2 Intel386 CX PROCESS OR INTE RNAL ARCHITE CTURE

The internal architecture of the Intel386 CX processor consists of functional units that operate in parallel. Fetchi ng, de coding, execution, memory manageme nt and bus accesses for several instructions are perf or med simultaneously. This parallel operation is called pipelined instr uction processing. With pipelining, each instruction is performed in stages, and the processing of several instructions at different stages may overlap, as shown in Figure 3-1. The pipelined processing of the Intel386 CX processor results in higher performance and enhanced throughput rate over nonpipelined processors.

Elapsed Time

Typical

Processor

Intel386™ SX CPU/Intel376™ CPU

386™ SX CPU/376™ CPU

Bus Unit

Decode

Unit

Execution

Unit

MMU

Fetch 1 Decode 1 Execute 1 Fetch 2 Decode 2 Execute 2

Fetch 1

Fetch 2 Fetch 3

Decode 1 Decode 2 Decode 3 Decode 4 Decode 5

Execute 1

Addr &

Fetch 4

MMU

Store

Result 1

Execute 2 Execute 3 Execute 4

Fetch 5 Fetch 6

Addr &

MMU

Figure 3-1. I nstruction Pipel ining

A2850-01

3-2

Figure 3-2 shows the internal architecture of the Intel386 CX processor.

CORE OVERVIEW

Barrel

Shifter,

Adder

Multiply/

Divide

File

Effective Address Bus

Protection

Test Unit

Status Flags

ALU

Control

ALU

Segmentation Unit

3-Input

Adder

Descriptor

Limit and 

Attribute

PLA

Internal Control Bus

Displacement Bus

Decode

and

Instruction

Decoder

Sequencing

3 Decoded

Control

ROM

Instruction

Queue

Control Instruction

Predecode

Linear Address Bus

Code

Stream

Paging Unit

Adder

Page

Cache

Control and

Attribute

PLA

Prefetcher

Limit

Checker

16 Byte

Code

Queue

Instruction

Prefetch

Core Plus

Unit

HOLD, INTR, NMI,

Request

Prioritizer

Physical Address Bus

ERROR#,BUSY#, RESET, HLDA, SMI#, SMIACT#, PEREQ

Control

Address

Driver

Pipeline/ Bus Size

Control

Code fetch / Page Table Fetch

MUX/

Transceivers

BE0#, BE1#, A25:1

M/IO#, D/C#, W/R#, LOCK#, ADS#, NA#, READY#

D15:0

Figure 3-2. The Intel386™ CX Processor Internal Block Diagram

32Dedicated ALU Bus

A2851-02

3-3

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

The six functional units of the Intel386 CX processor are:

• Core Bus Unit

• Instructi on Prefetc h Unit

• Instructi on Dec ode Unit

• Execution Unit

• Segmentat ion Unit

• Paging Unit

3.2.1 Core Bus Unit

The Core Bus Uni t provides the inte r face between t he proce ssor an d its en vironment. It accept s internal requests for instr uc tion fe tches (from the Instruction Prefetch Unit ) a nd data transfers (from the Execution Unit), and prioritizes the requests. At the same time, it generates or processes the signals to perform the curre nt b us cycle. These signal s inc lude the address, data , and control outputs for accessing exte rnal memory an d I/O. The Core Bus Unit also controls the interfac e to external bus masters and coproce ssors.

3.2.2 Instruction Prefetch Unit

The Instruction Prefetch Unit performs the program look ahead function of the CPU. When the Core Bus Unit is not performing bus cycles to execute an instruction, the Instruction Prefetch Unit uses the Core Bus Unit to fetch sequenti al ly along the i nstructi on byte stre am . These prefetche d instructions are stored in the Instruction Queue to awai t processing by the Instruction Dec ode Unit.

Instruction prefetches are given a lower prio rity than data transfers; assuming zero wait state memory access, prefetch activity never delays execution. On the other hand, when there is no data transfer requested, prefetching uses bus cycles that would otherwise be idle.

3.2.3 Instruction Decode U nit

The Instruction De code Unit takes i nstruction strea m bytes from the Prefet ch Queue and translates them into mi croco de. The decode d instruct ions are the n stored in a three-de ep Instructi on Queue (FIFO) to await processing by the Execution Unit. Immediate data and opcode offsets are also taken from the Prefet ch Q ueue. The decode unit works in paral lel with the other units and begins decoding when there is a free slot in the FIFO and there are bytes in the prefetch queue. Opcodes can be decoded at a rate of one byte per clock. Immediate data and offsets can be decoded in one clock regardless of their length.

3-4

CORE OVERVIEW

3.2.4 Execution Unit

The Executi o n U nit exe cutes the instruc tions from the Instruc tion Queue an d therefore comm u nicates with all other units required to complete the instruction. The functions of its three subun its are given below.

• The Control Unit contains micr ocode and special parallel har dware tha t speeds multip ly,

divide, and effective add ress calc ula tion .

• The Data Unit contains the (Arit hme tic Logic Unit) ALU, a file of eight 32-bit general-

purpose registers, and a 64-bit barrel shifter (which performs multiple bit shifts in one clock). The Data Unit performs data operations requested b y the Control Unit.

• The Protection Test Unit checks for segmenta tion violat ions u nder the control of the

microcode.

To spee d the execut ion of memo ry reference instruct ions, the E xecution Un it partially o verlaps the execution of any memory reference instr uction with the previous inst ruct ion.

3.2.5 Segmentatio n Uni t

The Segmentation Unit translates logical addresses into linear addresses at the request of the Execution Unit. The on-chip Segme nt Des cript or Cache st ores the currently used segme nt desc riptors to speed this translation. At the same time it performs the translation, the Segmentation Unit checks for bus-cycle segmentation violations. (These checks are separate from the static segmentation violatio n checks performed by the Protection Test Unit.) The translated linear add ress is truncated to a 24-bit physical address.

3.2.6 Paging Unit

When the Intel386 CX processor paging mechanism is enabled, the Paging Unit translates l inear addresses generated b y the Se gment ation U nit or the Inst ruction Prefetch Unit into physi ca l addresses. (When paging is not enabled, the physic al address is the same as the linear address, and no translation is necessa r y.) The Page Descriptor Cache stores recentl y used Page Direc t ory an d Page T able entries in its Translation Lookaside Buffer (TLB) to speed this translation. The Paging Unit forwards physical addresses to the Core Bus Unit to perform memory and I/O accesses.

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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

3.3 CORE Intel386 EX PROCE S SOR INT ER FACE

The Intel386 EX processor peripherals are connected to the Intel386 CX processor core through an internal Bus Interface Unit (BIU ). The BIU controls internal peripheral accesse s and external memory and I/O accesses. Because i t has the BIU between the Intel38 6 CX processor core and the external bus, the Intel38 6 EX process or bus timings are n ot identical to those of the Intel386 CX processor or Intel386 SX processor.

The Intel386 CX processo r numeric coprocessor interface is mainta ined and brought out to the Intel386 EX processor pins. The same I/O addresses used on the Intel386 SX processor a re used on the Intel386 EX processor, even though there are more address lines. The A23 line is high for coprocessor cycles. Re fer to “Interfa ce To Intel387™ SX Math C oprocessor” o n page 6-38 for more details.

3-6

SYSTEM REGISTER ORGANIZATION

CHA PT ER 4

SYSTEM REGISTER ORGANIZATION

This chapter provides an overview of the system registers incorporated in the Intel386™ EX processor, focus ing on register o rganization from a n address architecture viewp oint. The chapte rs that cover the individual peripheral s de scribe the regist ers in detail.

This chapter is organized as follows:

• Overview (see below)

• I/O Address Space for PC/AT Systems (page 4-2)

• Expanded I/O Address Space (page 4-3)

• Organization of Peripheral Re gisters (page 4 -5)

• I/O Address Decodin g Techniques (page 4-6)

• Addressi n g Modes (page 4-9 )

• Peripheral Register Addresses (page 4-15)

4.1 OVERVIEW

The Intel386 EX processor has register res ources in the following categories:

• Intel386 processor core architecture registers:

— General purpose registers — Segm ent regi sters — Instruct i on pointe r and flags — Control registers — System address registers (protected mode) — Debug registers — Test regi s ters

• Intel386 EX processor peripheral registers:

— Confi gura tio n space control regist ers — I nterrupt control unit regist ers — Timer/c o u nter u nit regist ers — DMA uni t re gisters (8237A-compatibl e and enhanced function registers) — Asynchronous serial I/O (SIO) re gisters — Clock genera tio n selector registe rs

4-1

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

— Power mana gement control registers — Chip-sel ec t unit contr ol registers — Refresh control unit registers — Watchdog timer control registers — Synchronous serial I/O control registers — Parallel I/O port control registers

4.1.1 Intel386 Processor Core Architecture Reg ister s

These regist ers are a superset of the 8086 and 80286 processor registers. All 16-bit 8086 and 80286 registers are contained within the 32-bit Intel386 processor core registers. A detailed description of the Int el386 proce ssor arc hitec ture base registe rs can be found in the Intel386™ SX Microprocessor Programmer’s Refere nce Manual (order number 240331).

4.1.2 Intel386 EX Processor Peripheral Reg ister s

The Intel386 EX proce ssor contains s om e periphe ral s that a re commo n an d compat ible wi th the

PC/AT

system architecture and others that are useful for embedded applications. The peripheral registers control access to these peripherals and enable you to configure on-chip system resources such as timer/counters, power manageme nt, chip select s, and watchdog timer.

All peripheral registers reside physically in the expanded I/O address space (addr ess es 0F000H– 0FFFFH). Peripherals that are compa tible with PC/AT system archit ecture can also be mapped into DOS I/O addre ss space (addresses 0H–03FFH, 10-bit decode). The following rules apply for accessing peripheral registers after a system reset:

• Registers within the DOS I/O address space are accessible.

• Registers within the expanded I/O address space are accessible only after the expanded I/O

address space is enabled.

4.2 I/O ADD RES S SP ACE FOR P C/AT SYSTEMS

The Intel386 EX processo r’s I/ O address space is 64 Kbytes. On PC/AT platforms, the DOS operating system and applications assume that only 1 Kbyte of the total 64-Kbyte I/O address space is used. The first 256 bytes (addresses 00000H–00FFH) are reserved for platform (motherboard) I/O resources such as the interrupt and DMA controllers, and the remaining 768 bytes (addresses 0100H–03FFH) are available for “general” I/O peripheral card resources. Since only 1 K byte of the address space is supported, add -on I/O peripheral cards typically deco de only the lower 10 address lines. Because the upper address lines are not decoded, the 256 platform address locations and the 768 bus address locations are repeated 64 times (on 1-Kbyte boundaries), covering the entire 64-Kbyt e address space. (See Figure 4-1.)

Generally, add-on I/O peripheral cards do not use the I/O addresses reserved for the platform resources. Software running on the platform can use any of the 64 repetitions of the 256 address locations rese rved for accessing platform resources.

4-2

General Slot I/O

Platform I/O (Reserved)

General Slot I/O

Platform I/O (Reserved)

SYSTEM REGISTER ORGANIZATION

FFFFH (64K)

FD00H

FC00H (63K)

0C00H (3K)

0900H

0800H (2K)

General Slot I/O

0500H

Platform I/O (Reserved)

0400H (1K)

General Slot I/O

0100H (256)

Platform I/O (Reserved)

0000H (0)

A2498-01

Figure 4-1. PC/AT I/O Address Space (10-bit Decode)

4.3 EXPANDED I/O ADDRESS SPACE

The Intel386 EX processor’s I/O address scheme is similar to that of the Extended Industry Standard Architecture (EISA) bus and the Enhanced - Industry Standard Architecture (E-ISA) bus. Both standards maintain backward software compatibility with the ISA architecture. The ISA Platform I/O (0-100H) is accessed with a 16-bit address decode and is located in the first 256 I/O locations. The General Slot I/O that is typically used by add-in boards is repeated throughout the 64 K b yte I/O address range due t o the ir 10 -bit only de code. This allows 63 of the 64 repe tition s of the first 256 address locations of every 1 Kbyte block to be allocated to specific slots. Each slot is 4 Kbyte in size, allowing for a total of 16 slots. The partitioning is such that four groups of 256 address locations are assigned to each slot, for a total of 1024 specific address locations per slot.

4-3

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

(See Figure 4-2.) Thus, each slot has 1 Kbyte addresses (in four 256-byte segments) that can potentially contain ext ended periphera l registers.

FFFFH (64K)

General Slot I/O

Slot 15

General Slot I/O

Slot 15

General Slot I/O

Slot 15

General Slot I/O

Slot 15

General Slot I/O

Slot 1

General Slot I/O

Slot 1

General Slot I/O

Slot 1

General Slot I/O

FC00H (63K)

F800H (62K)

F400H (61K)

F000H (60K)

1FFFH (8K)

1C00H (7K)

1800H (6K)

1400H (5K)

4-4

Slot 1

General Slot I/O

Slot 0

General Slot I/O

Slot 0

General Slot I/O

Slot 0

General Slot I/O

Slot 0

ISA Platform I/O

1000H (4K)

0C00H (3K)

0800H (2K)

0400H (1K)

0000H (0K)

Figure 4-2. Expanded I /O Address Space (16-bit Decode)

A2499-02

SYSTEM REGISTER ORGANIZATION

The Intel386 EX processor uses slot 15 for the registers needed for integrated peripherals. Using this slot avoids conflicts with other devices in an EISA system, since EISA systems typically do not use slot 15.

4.4 ORGANIZAT IO N OF PERIPHE RAL RE GIST ERS

The registers associated with the integrated peripherals are physically located in slot 15 of the I/O space. There are s ixt een 4 Kbyte address slots i n I/O space. Slot 0 refers to 0H–0FFFH; s lot 1 5 refers to 0F000H–0FFFFH. Table 4-1 shows the address map for the peripheral registers in slot

15. Note that the I/O addresses fall in address ranges 0F000H–0F0FFH, 0F400H–0F4FFH, and 0F800H–0F8FFH; utilizing the unique sets of 256 I/O addresses in Slot 15.

Table 4-1. Peripheral Register I/O Address Map in Slot 15

DMA Controller 1 0F000H – 0F01FH Master Int errupt Controller 0F020 H – 0F0 3 F H Programmable Interval Timer 0F040H – 0F05FH DMA Page Registers 0F080H – 0F09FH Slave Interrupt Controller 0F0A0H – 0F0BFH Math Copr ocessor 0F0F0H – 0F0FFH Chip Select Unit 0F400H – 0F47FH Synchronous Serial I/O Unit 0F480H – 0F49FH DRAM Refresh Control Unit 0F4A0H – 0F4BFH Watchdog Timer Unit 0F4C0H – 0F4CFH Asynchronous Serial I/O Channel 0 (COM1) 0F4F8H – 0F4FFH Clock Generation and Power Management Unit 0F800H – 0F80FH External/Internal Bus Interface Unit 0F810H – 0F81FH Chip Configuration Registers 0F820H – 0F83FH Parallel I/O Ports 0F860H – 0F87FH Asynchronous Serial I/O Channel 1 (COM2) 0F8F8H – 0F8FFH

4-5

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

4.5 I/O ADDRESS DECODING TECHNIQUES

One of the key features of t he Intel386 EX processor is that it is configurable for compatibility with the standard PC/AT archit ec ture. In a PC/AT system, the platfo rm I/O resources are locate d in the slot 0 I/O address space. For the Intel386 EX processor, this means that PC/AT-compatible internal peripheral s shoul d be re flected i n slot 0 of the I/ O spa ce f or DOS opera ting syst em a nd application software to access and manipulate the m properly.

This discussion leads to the concepts of D OS I/O space and expanded I/O s pace. DOS I/O Space DOS I/O space refers to the lower 1 Kbyte of I/O addresses, where

only PC/AT-compatible peripherals can be mapped.

Expanded I/O Space Expanded I/O space refers to the top 4 K bytes of I/O addresse s,

where all peripheral regist ers are physical ly loca ted. The rem ai nde r of this section explains how special I/O address decoding sche mes manipulate regist er addresses within these two I/O spaces.

4.5.1 Address Configura tion Register

I/O address locations 22H and 23H in DOS I/O space offer a special case. These address locations are not used to access any periphe ral re gisters in a PC/AT system. The Intel386 SL microprocessor and other integrated PC solutions use them to enable extra address space required for configuration registers specific to these products. On the Intel386 EX processor, these address locations are used t o hide the peri p heral regi sters in the expanded I/O spac e. The e xpanded I/O s pace can be enabled (registers visible) or disabled (registers hidden).

The 16-bit regi ster at I/O location 22H c an also be use d to contr ol mapping of various internal peripherals in I/O address space. This register, REMAPCFG, is defined in Figure 4-3.

The remap bits of this register control whether the internal PC compatible peripherals are mapped into the DOS I/O space. Setting the peripheral bit makes the peripheral accessible only in expanded I/O space. Cleari n g the perip heral bit make s the periphera l accessi ble in both DOS I/O spa ce and expanded I/O space. To access the REMAPCFG register, you must first enable the expanded I/O address spa ce as des cribed in t he ne xt section. At re se t, t his regis ter is c leare d, mapping internal PC/AT-compati ble peripheral s into DOS I/O space.

4-6

SYSTEM REGISTER ORGANIZATION

Address Configuration Register REMAPCFG

15 8

ESE——— ————

7 0

— S1R S0R ISR IMR DR — TR

Bit

Number

15 ESE 0 = Disables expanded I/O space

14–7 — Reserved. 6 S1R 0 = Makes serial channel 1 (COM2) accessible in both DOS I/O space

5 S0R 0 = Makes serial channel 0 (COM1) accessible in both DOS I/O space

4 ISR 0 = Makes the slave 82C59A interrupt controller accessible in both DOS

3 IMR 0 = Makes the master 82C59A interrupt controller accessible in both

2 DR 0 = Makes the DMA address accessible in both DOS I/O space and

Bit

Mnem oni c

1 = Enables expanded I/O space

and expanded I/O space

1 = Remaps serial channel 1 (COM2) address into expanded I/O space

and expanded I/O space

1 = Remaps serial channel 0 (COM1) address into expanded I/O space

I/O space and expand ed I/O space

1 = Remaps slave 82C59A interrupt controller address into expanded

I/O space

DOS I/O space and expanded I/O space

1 = Remaps master 82C59A interrupt controller address into expanded

I/O space

expanded I/O space

1 = Remaps DMA address into expanded I/O space

Expanded Addr: PC/AT Address: Reset Sta te:

Func tion

0022H 0022H 0000H

1 — Reserved. 0 TR 0 = Makes the timer control unit accessible in both DOS I/O space and

Figure 4-3. Address Configuration Register (REMAPCFG)

expanded I/O space

1 = Remaps timer control unit address into expanded I/O space

4-7

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

4.5.2 Enabling and Dis abl ing the E xpan ded I/O Space

The Intel386 EX processor’s expanded I/O space is enabled by a specific write sequence to I/O addresses 22H and 23H (Figure 4-4). Once the expanded I/O space is enabled, internal peripherals (timers, DMA, inte rrupt control lers and seria l comm unication channe ls) can be mapped out of DOS I/O space (using the REMAPCFG re giste r) and registe rs associated wit h other internal peripherals (such as the chip-select unit, power management unit, watchdog timer) can be accessed.

4.5.2.1 Programming REMAPCFG Example

The expanded I/O space enable (ESE ) bit in the R EMAPC FG register c an be s et only by three sequential write operations to I/O addresses 22H and 23H as described in Figure 4-4. Once ESE is set, REMAPCFG and a ll the on-chip registers in the expanded I/O address range 0F000H– 0FFFFH can be accessed. The remap bits in REMAPCFG are still in effect even after the ESE bit is cleared.

;;disable interrupts

CLI ; Enable expanded I/O space of Intel386(tm) EX processor ; for peripheral initialization.

MOV AX, 08000H ; Enable expanded I/O space

OUT 23H, AL ; and unlock the re-map bits

XCHG AL, AH

OUT 22H, AL

OUT 22H, AX

;; at this point PC/AT peripherals can be mapped out ;; For example, ;; Map out the on-chip DMA channels from the DOS I/O space (slot 0)

MOV AL, 04H

OUT 22H, AL ; Disables expanded I/O space

MOV AL, 00H

OUT 23H, AL ;; Re-enable Interrupts

STI

Figure 4-4. Setting the ESE Bit Code Example

The REMAPCFG register is write-protected until the expanded I/O space is enabled. When the enabling writ e sequence is executed, it sets the ESE bi t. A program can check this bit to see whether it has access to t he expanded I/O space regist ers. Cleari ng the ESE bit disabl es the expanded I/O space. This can be done by a byte write w ith a value of 0 to I/O address 23H. This again locks the REMAPCFG regi ster and makes it read- only.

4-8

SYSTEM REGISTER ORGANIZATION

4.6 ADDRESSING MODES

Combinati ons of the va lue of ESE bit and the indivi d ual remap bit s i n the REM APC FG regi ster yield four different peripheral addressing modes for I/O address decoding.

4.6.1 DOS-compatible Mode

DOS-compatible mode is achieved by clearing ESE and all the peripheral remap bits. In this mode, all PC/AT-compatible peripheral s are mapped into the DOS I/O spac e. Only address lines A9:0 are decoded for internal peripherals. Accesses to PC/ AT-compati ble periphe rals a re valid, while all other internal periphera ls are inacces sibl e (see Fig ure 4-5).

This mode is useful for accessing the internal timer, interrupt controller, s erial I/O ports, or DMA controller in a DOS-compatible environment.

4-9

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

3FFH

On-chip UART-0

On-chip UART-1

FFFFH

REMAPCFG

23H

22H

On-chip 8259A-2

On-chip Timer

00000 000

On-chip 8259A-1

On-chip DMA

DOS I/O Space

F000H

Expanded I/O Space

Note:

Shaded area indicates that expanded I/O space peripherals are not accessible

A2495-02

4-10

Figure 4-5. DOS-Compatible Mode

SYSTEM REGISTER ORGANIZATION

4.6.2 Nonintrusi ve DOS Mo de

This mode is achieved by firs t setting the ESE bit (using t he th ree sequent ial writes), se tting the individual periphera ls’ remap bits, and the n clearin g the ESE bit. Periphera ls whose remap bits are set are mapped out of DOS I/ O spac e. L ike DOS-compatible mode , only address lines A9:0 are decoded internally . This mode is useful for connecting an external peripheral instead of using the integrated peripheral . For exam ple, a system might use an exte rnal 8237A DMA rather than using the internal DMA unit. For this configuration, set the ESE bit, set the remap bit associated with the DMA unit and then clear the ESE bit. In this case, the external 8237A is accessible in the DOS I/O space, while the internal DMA can be accessed only after the expanded I/O space is enabled. (See Figure 4-6.)

4.6.3 Enhanced DOS Mode

This mode is achieved by setting the ESE bit and clearing all PC/AT-compatible peripherals’ remap bits. Address lines A15:0 are decoded internally. The expanded I/O spac e is enabled and the PC/AT-c ompatible inter nal peripherals are acce ssible in either DOS I/O spac e or expanded I/O space. (See Figure 4 -7.) If an application freq uently requires the additiona l peripherals, but at the same time wants to ma intain DOS c ompatibility for ease of developme nt, this is the most useful mode.

4.6.4 Non-DOS Mode

This mode is achieved by setting the ESE bit and setting all peripherals’ remap bits. Address lines A15:0 are deco ded internally. The expanded I/O space is enabled and all peripherals can be accessed only in expanded I/O space. This mode is useful for systems that don’t require DOS compatibility and have other custom peri phe ral s in slot 0 of the I/O space. (See Figure 4-8.)

For all DOS peripherals, the lower 10 bits in the DOS I/O space and in the expanded I/O space are identical (except the UART s, whose lower 8 bits are identical). This makes correlation of their respective offsets in DOS and expanded I/O spaces eas ier. Al so, the UARTs have fi xed I/O addresses. This differs from standard PC/AT configurations, in which these address ranges are programmable.

4-11

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

3FFH

On-chip UART-0

On-chip UART-1

FFFFH

On-chip 8259A-2

On-chip Timer

REMAPCFG

23H

22H

00000 010

On-chip 8259A-1

Expanded I/O Space

Note:

Internal DMA

DOS I/O Space

Shaded area indicates that the on-chip DMA and expanded I/O space peripherals are not accessible

Figure 4-6. Example of Nonintrusive DOS-Compatible Mode

F000H

A2496-02

4-12

SYSTEM REGISTER ORGANIZATION

3FFH

On-chip UART-2

On-chip UART-1

On-chip 8259A-2

On-chip Timer

FFFFH

Other Peripherals

UART-0

UART-1

Timer

REMAPCFG

23H

22H

00000 000

On-chip 8259A-1

On-chip DMA

DOS I/O Space

Figure 4-7. Enhanced DOS Mode

8259A-2

8259A-1

On-chip DMA

F000H

Expanded I/O Space

A2501-02

4-13

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

3FFH

Other Peripherals

FFFFH

UART-0

REMAPCFG

23H

22H

01111 011

DOS I/O Space

UART-1

Timer

8259A-2

8259A-1

On-chip DMA

F000H

Expanded I/O Space

A2502-02

4-14

Figure 4-8. NonDOS Mode

SYSTEM REGISTER ORGANIZATION

4.7 PERIPHERAL REGISTER ADDRESSES

Tabl e 4-2 lists the addresse s and names of all user-accessible peripheral regis ters. I/O Regis ters can be accessed as bytes or wo rds. Word acce sses to byte regi sters res ult in two sequenti a l 8-bit I/O transfers. The default (reset) value of each register is shown in the Reset Va lu e column. An X in this column signifies that the register bits are undefined. Some address values do not access registers, b ut are decoded to provide a logic control si gnal. These addresses are listed as Not a re g ister in the Reset column.

Table 4-2. Peripheral Register Addresses (Sheet 1 of 6)

Expanded

Address

F000H 0000H Byte DMA0TAR0/1 (Note 1) XX F001H 0001H Byte DMA0BYC0 /1 (Note 1) XX F002H 0002H Byte DMA1TAR0/1 (Note 1) XX F003H 0003H Byte DMA1BYC0 /1 (Note 1) XX F004H 0004 H Reser ved F005H 0005 H Reser ved F006H 0006 H Reser ved F007H 0007 H Reser ved F008H 0008H Byt e DMACMD1/ DMA STS 00H F009H 0009H Byte DMASRR 00H F00AH 000AH Byte DMAMSK 04H F00BH 000BH Byt e DMAMOD1 00H F00CH 000CH B yt e DMACLRBP Not a register F00DH 000DH B yt e DMACLR Not a register F00EH 000EH Byte DMACLRMS K Not a re g ister F00FH 000FH B yte DMAGRPMSK 03H

PC/AT

Address

Access Type

(Byte/Word)

DMA Controller and Bus Arbiter

F010H Byte DMA0REQ0/1 XX F011 H Byte DMA0REQ2/3 XX F012H Byte DMA1REQ0/1 XX F013H Byte DMA1REQ2/3 XX F014H Reser ved F015H Reser ved F016H Reser ved F017H Reser ved

NOTES:

1. Byte pointer in flip-flop in DMA determines which register is accessed.

2. Shaded rows indicate reserved areas.

4-15

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

Table 4-2. Peripheral Register Addresses (Sheet 2 of 6)

Expanded

Address

F018H Byte DMABSR X1X10000B F019H Byte DMACHR/DMAIS 00H F01AH Byte DMACMD2 08H F01BH Byte DMAMOD2 00H F01CH Byte DMAIEN 00H F01DH Byte DMAOVFE 0AH F01EH Byte DMACLRTC Not a register

F020H 0020H Byte ICW1m/IRRm/ISRm/

F021H 0021H Byte ICW2m/ICW3m/ICW4m/

0022H 0022 H Wo rd REMAPCFG 0000H

F040H 0040H Byte TMR0 XX F041H 0041H Byte TMR1 XX

PC/AT

Address

Access Type

(Byte/Word)

Master Interrupt Controller

Addres s Confi gura tio n Regis te r

Timer/counter Unit

OCW2m/OCW3m

OCW1m/POLLm

F042H 0042H Byte TMR2 XX F043H 0043H Byte TMRCON XX

DMA Page Registers

F080H Reserved F081H 0081H Reserved F082H 0082H Reserved F083H 0083H Byte DMA1T AR2 XX F084H Reserved F085H Byte DMA1TAR3 XX F086H Byte DMA0TAR3 XX F087H 0087H Byte DMA0TAR2 XX F088H Reserved F089H 0089H Reserved F08AH 008AH Reserved F08BH 008BH Reserved F08CH Reserved

NOTES:

1. Byte pointer in flip-flop in DMA determines which register is accessed.

2. Shaded rows indicate reserved areas.

4-16

SYSTEM REGISTER ORGANIZATION

Table 4-2. Peripheral Register Addresses (Sheet 3 of 6)

Expanded

Address

F08DH Reserved F08EH Reserved F08FH Reserved F098H Byte DMA0BYC2 XX F099H Byte DMA1BYC2 XX F09AH Reserved F09BH Reserved

F092H 0092H Byte PORT92 XXXXXX10B

F0A0H 00A0H Byte ICW1s/IRRs/ISRs/

F0A1H 00A1H Byte ICW2s/ICW3s/ICW4s/

F400H Word CS0ADL 0000H F402H Word CS0ADH 0000H

PC/AT

Address

Access Type

(Byte/Word)

A20GATE and Fast CPU Reset

Slave Interrupt Controller

Chip-select Unit

OCW2s/OCW3s

OCW1s/POLLs

F404H Word CS0MSKL 0000H F406H Word CS0MSKH 0000H F408H Word CS1ADL 0000H F40AH Word CS1ADH 0000H F40CH Word CS1MSKL 0000H F40EH Word CS1MSKH 0000H F410H Word CS2ADL 0000H F412H Word CS2ADH 0000H F414H Word CS2MSKL 0000H F416H Word CS2MSKH 0000H F418H Word CS3ADL 0000H F41AH Word CS3ADH 0000H F41CH Word CS3MSKL 0000H F41EH Word CS3MSKH 0000H F420H Word CS4ADL 0000H F422H Word CS4ADH 0000H

NOTES:

1. Byte pointer in flip-flop in DMA determines which register is accessed.

2. Shaded rows indicate reserved areas.

4-17

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

Table 4-2. Peripheral Register Addresses (Sheet 4 of 6)

Expanded

Address

F424H Word CS4MSKL 0000H F426H Word CS4MSKH 0000H F428H Word CS5ADL 0000H F42AH Word CS5ADH 0000H F42CH Word CS5MSKL 0000H F42EH Word CS5MSKH 0000H F430H Word CS6ADL 0000H F432H Word CS6ADH 0000H F434H Word CS6MSKL 0000H F436H Word CS6MSKH 0000H F438H Word UCSADL FF6FH F43AH Word UCSADH FFFFH F43CH Word UCSMSKL FFFFH F43EH Word UCSMSKH FFFFH

F480H Word SSI OTBUF 0000H F482H Word SSIORBUF 0000H F484H B yte SSIOBAUD 00H

PC/AT

Address

Access Type

(Byte/Word)

Synchro nous Serial I/O Unit

F486H B yte SSIOCON1 C0H F488H B yte SSIOCON2 00H F48AH Byte SSIOCTR 00H

Refresh Control Unit

F4A0H Word RFSBAD 0000H F4A2H Word RFSCIR 0000H F4A4H Word RFSCON 0000H F4A6H Word RFSADD 00FFH

Watchdo g Tim er Unit

F4C0H Word WDTRLDH 003FH F4C2H Word WDTRLDL FFFFH F4C4H Word WDTCNTH 003FH F4C6H Word WDTCNTL F FFFH F4C8H Word WDTCLR Not a reg ister

NOTES:

1. Byte pointer in flip-flop in DMA determines which register is accessed.

2. Shaded rows indicate reserved areas.

4-18

SYSTEM REGISTER ORGANIZATION

Table 4-2. Peripheral Register Addresses (Sheet 5 of 6)

Expanded

Address

F4CAH Byte WDTSTATUS 00H

F4F8H 03F8H Byte RBR0 /TB R0/D LL0 XX/XX/02H F4F9H 03F9 H Byte IER0/DLH0 0 0 H/00 H F4FAH 03FAH Byte IIR 0 01H F4FBH 03FBH Byte LCR0 00H F4FCH 03FCH B yt e MCR0 00H F4FDH 03FDH B yt e LSR0 60H F4FEH 03FEH Byte MSR0 X0H F4FFH 03FF H Byte SCR0 XX

F800H Byte PWRCON 00H F804H Word CLKPRS 0000H

F820H Byte P1CFG 00H F822H Byte P2CFG 00H F824H Byte P3CFG 00H F826H Byte PINCFG 00H

PC/AT

Address

Access Type

(Byte/Word)

Asynch rono us Seri al I/O Chan nel 0 (COM1)

Clock Generation and Power Management

Device Configuration Registers

F830H Byte DMACFG 00H F832H Byte INTCFG 00H F834H Byte TMRCFG 00H F836H Byte SIOCFG 00H

Parallel I/O Ports

F860H Byte P1PIN XX F862H Byte P1LTC FFH F864H Byte P1DIR FFH F868H Byte P2PIN XX F86AH Byte P2LTC FFH F86CH Byte P2DIR FFH F870H Byte P3PIN XX F872H Byte P3LTC FFH F874H Byte P3DIR FFH

NOTES:

1. Byte pointer in flip-flop in DMA determines which register is accessed.

2. Shaded rows indicate reserved areas.

4-19

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

Table 4-2. Peripheral Register Addresses (Sheet 6 of 6)

Expanded

Address

F8F8H 02F8H Byte RBR1 /TB R1/D LL1 XX/XX/02H F8F9H 02F9 H Byte IER1/DLH1 0 0 H/00 H F8FAH 02FAH Byte IIR 1 01H F8FBH 02FBH Byte LCR1 00H F8FCH 02FCH B yt e MCR1 00H F8FDH 02FDH B yt e LSR1 60H F8FEH 02FEH Byte MSR1 X0H F8FFH 02FF H Byte SCR1 XX

NOTES:

1. Byte pointer in flip-flop in DMA determines which register is accessed.

2. Shaded rows indicate reserved areas.

PC/AT

Address

Access Type

(Byte/Word)

Asynch rono us Seri al I/O Chan nel 1 (COM2)

4-20

DEVICE CONFIGURATION

CHA PT ER 5

DEVICE CO NFIG UR ATION

The Intel386™ EX processor provides many possible signal to pin connections as well as peripheral to periphe ral connections. This chapter des cribes the available configurat ions and how to configure them.

This chapter is organized as follows:

• Introduction (see below)

• Peripheral Configuration (page 5-3)

• Pin Configuratio n (page 5-23)

• Device Configu ration Procedure (page 5-28)

• Configuration Example (page 5-28)

5.1 I NTRO DUCTI ON

Device configuration is the proc ess of setting up the microprocessor’s on-chip peripherals particular system design. Specifically, device configuration co nsists of programming registers to connect peripheral signal s t o the package pins and interconnect the peri p heral s. The peri phe ral s include the following:

†

for a

• DMA Controller (DMA)

• Interrupt Control Unit (ICU )

• Timer/cou nter Unit (TC U)

• Asynchronous Serial I/O Units (SIO0, SIO 1)

• Synchronous Serial I/ O Unit (SSIO)

• Refresh Control Unit (RCU)

• Chip-selec t Unit (CSU )

• Watchdog Timer Unit (WDT)

In addition, the pin con figuration regi st ers c ontrol connections fr om the c oprocessor to t he c ore and pin connections to the bus arbiter.

†

In this chapter, the terms “peripheral” and “on-chip peripheral” are used interchangeably. An “off-chip peripheral” is external to the Intel386 EX processor.

5-1

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

Figure 5-1 shows Peripheral A and its connections to other peripherals and the package pins. The “Internal Connecti on Logic” provides three kinds of connections:

• Connections between peripherals

• Connections to package pins via multiplexers

• Direct connections to package pins without multi ple xers

The internal connection logic is controlled by the Periphera l A co nfig uration register. Each pin multiplexer (“Pin Mux” ) connects one of two internal sig nals to a pin. One is a pe riph-

eral signal. The second signal can be an I /O port signal or a signal fr om/to another peripheral. The pin multiplexers a re contr olled by the pin configurat ion regi st ers. Some input-only pins with out multiplexers (“Shared Pins w/o Muxes”) are routed to two different peripherals. Your design should use only one of the inputs and disable or ignore the input going to the second peripheral.

Toget her, the peripheral configuration registers and the pin configurat ion registers allow you to select the perip herals to be used, to intercon nect them as your design re quires, and to bring se lected signals to the pac kage pins.

Microprocessor

Peripheral A

Peripheral A

Configuration

Internal

Connection

Logic

Control

Peripherals B, C, D, ...

Pin Configuration Registers

Pin

Muxes

Control

Pins

with

Muxes

Shared Pins

w/o Muxes

A2535-01

Figure 5-1. Peripheral and Pin Connections

5-2

DEVICE CONFIGURATI ON

5.2 PERIPHERAL CONFIGURATION

This section describe s the configura tion of each on-chip peripheral . For more detailed information on the peripheral itself, see t he chapt er describing that peripheral.

The symbology used for signals that share a device pin is shown in Figure 5-2. Of the two signal names by a pin, the upper signal is associated with the peripheral in the figure. The lowe r signal in parentheses is the alt ernat e signal , which connec ts to a di fferent perip heral or the co re. When a pin has a multiplexer, it is shown as a switch, and the registe r bit that controls it is noted above the switch.

5.2.1 DMA Controller, Bus Arbiter, and Refresh Unit Configuration

Figure 5-2 shows the DMA controller, bus a rbiter, and refresh unit configuration. Requests for a DMA data t ransfer are shown as inputs to the multipl exer:

• A serial I/O transmitter (TXEDM A 0, TXEDMA1) or receive r (RBF DM A0, RBFDM A1 )

• A synchronous serial I/O transmitter (SSTBE) or receiver (SSRBF)

• A timer (OUT1, OUT2)

• An external source (DRQ0, DRQ1)

The inputs are selected by the DMA configuration register (see Figure 5-3).

5.2.1.1 Using The DMA Unit with External Devices

For each DMA chan nel, three bits in the DMA configurat ion regi ster (Figure 5-3) select the external request input or one of seven request inputs from the peripherals. Another bit enables or disables that channel’s DMA acknowledge signal (DACKn#) at the device pin. Enable the DACKn# signal only when you are using the external request signal (DRQn) and need DACKn#. The acknowledge signals are not routed to the on-chip peripherals, and therefore, these peripherals cannot initiate single-cycl e (fly-by) DMA transfers.

An external bus mast er ca nnot talk directly t o internal perip heral m odules be cause the ext ernal address lines are outputs only. However, an external device could use a DMA channel to transfer data to or from an internal peripheral because the DMA generates the addresses. This transaction would be a two-cycle DMA bus transa ction.

5.2.1.2 DMA Service to an SIO or SSIO Peripheral

A DMA unit is useful for ser vicing an SIO o r SSIO peripheral opera ting at a high baud rate. At high baud rates, the interrupt response time of the core may be too long to allow the serial channels to use an interrupt to service the receive-buffer-full condition. By the time the interrupt service routine (ISR) is ready to transfer the receive-buffer data to memory, new data would have been loaded into the buffer. The issue is the interrupt latency which is the amount of time the processor takes from recognizing the interrupt to executing the first line of code in the ISR. This interrupt latency needs to be calculated to determi ne if an ISR can handle the high baud rate. If the Interrupt Latency i s too high, data transfers to and from the serial channels can occ u r within a few bus cycles of t he t ime that a seria l unit is re ady to move data by using an appropriately

5-3

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

configured DMA channel . SIO and SSIO inputs t o the DMA a re s elected by the DM A configuration register (F igure 5-3).

5.2.1.3 Using The Timer To Initiat e DMA Transfers

A timer output (OUT1, OUT2) can initiate periodic data transfers by the DMA. A DMA channel is programmed for the transfer, then a timer output pulse triggers the transfer. The most useful DMA and timer combinat ions fo r this type of transfer are the periodic timer modes (mode 2 and mode 3) with the DMA block-transfer mode programmed. See Chapter 10, “TIMER/COUNTER UNIT,” and Chapter 12, “DMA CONTROLLER,” for more information on how to program the peripherals.

5.2.1.4 Limitations Due To Pin Signal Multiplexing

Pin signal multiplexing can preclude the simultaneous use of a DMA channel and another peripheral or specific peripheral signal (see Figure 5 -2). For example, using DMA channel 1 with an external requester device precludes using SIO channel 1 due to the multiplexed signal pairs DRQ1/RXD1 and DACK1#/T XD1. P lease refe r to the Intel386™ EX Microprocessor Pin Mul- tiplexin g Map (Order Number 272587) for a complete diagram of multiplexed s ignals.

5-4

DMA

DREQ0

DMACFG.2:0

0 1 2 3 4 5 6 7

RBFDMA0 (SIO0) TXEDMA1 (SIO1) SSTBE (SSIO) OUT1 (TCU) RBFDMA1 (SIO1) TXEDMA0 (SIO0) SSRBF (SSIO)

DEVICE CONFIGURATI ON

DRQ0 (DCD1#)†

To SIO1

DMACFG.3

DMAACK0#

DMACFG.6:4

0 1

DREQ1

2 3 4 5 6 7

DMACFG.7

DMAACK1#

DMAINT

To ICU

End of Process

HOLD

To

Core

HOLD

Bus Arbiter

HLDA

Refresh Unit

From

Core

HLDA

REFRESH#

† Alternate pin signals are in parentheses.

RBFDMA1 (SIO1 ) TXEDMA0 (SIO0) SSRBF (SSIO) OUT2 (TCU) RBFDMA0 (SIO0) TXEDMA1 (SIO1) SSTBE (SSIO)

To/From I/O Port 1

From CSU

From SIO1

From CSU

PINCFG.4

To SIO1

PINCFG.2

PINCFG.3

P1CFG.6

P1CFG.7

PINCFG.6

DACK0# (CS5#)

DRQ1 (RXD1)

DACK1# (TXD1)

EOP# (CTS1#)

HOLD (P1.6)

HLDA (P1.7)

REFRESH# (CS6#)

Figure 5-2. Configuration of DMA, Bus Arbiter, and Refresh Unit

A2516-02

5-5

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

DMA Configuration DMACFG (read/write)

7 0

D1MSK D1REQ2 D 1REQ1 D1 REQ0 D0 MSK D0RE Q2 D0 REQ1 D0RE Q0

Bit

Number

7 D1MSK DMA Acknowledge 1 Mask:

6–4 D1REQ2:0 DMA Channel 1 Request Connecti on:

3 D0MSK DMA Acknowledge 0 Mask:

2–0 D0REQ2:0 DMA Channel 0 Request Connecti on:

Bit

Mnem oni c

0 = DMA channel 1’s acknowledge (DMAACK1#) signal is not masked. 1 = Masks DMA channel 1’s acknowledge (DMAACK1 #) sign al. Useful

when channel 1’s request (DREQ1) input is connected to an internal peripheral.

Connects one of the eight possible hardware sources to channel 1’s request input (DREQ1).

000 = DRQ1 pin (external peripheral) 001 = SIO channel 1’s receive buffer full signal (RBFDMA1) 010 = SIO channel 0’s transmit buffer empty signal (TXEDMA0) 011 = SSIO receive holding buffer full signal (SSRBF) 100 = TCU counter 2’s output signal (OUT2) 101 = SIO channel 0’s receive buffer full signal (RBFDMA0) 110 = SIO channel 1’s transmit buffer empty signal (TXEDMA1) 1 11 = SSIO transmit holding buffer empty signal (SSTBE)

0 = DMA channel 0’s acknowledge (DMAACK0#) signal is not masked. 1 = Masks DMA channel 0’s acknowledge (DMAACK0 #) sign al. Useful

when channel 0’s request (DREQ0) input is connected to an internal peripheral.

Connects one of the eight possible hardware sources to channel 0’s request input (DREQ0).

000 = DRQ0 pin (external peripheral) 001 = SIO channel 0’s receive buffer full signal (RBFDMA0) 010 = SIO channel 1’s transmit buffer empty signal (TXEDMA1) 011 = SSIO transmit holding buffer empty signal (SSTBE) 100 = TCU counter 1’s output signal (OUT1) 101 = SIO channel 1’s receive buffer full signal (RBFDMA1) 110 = SIO channel 0’s transmit buffer empty signal (TXEDMA0) 111 = SSIO receive holding buffer full signal (SSRBF)

Expanded Addr: ISA Addr: Reset Sta te:

Func tion

F830 H — 00H

Figure 5-3. DMA Configuration Register (DMACFG)

5-6

DEVICE CONFIGURATI ON

5.2.2 Interrupt Contr ol Unit Config urati on

The interrupt control unit (ICU) comprises two 82C5 9A interrupt controllers connected in cascade, as shown in Figure 5-4. (See Chapter 9 for more information.) Figure 5-5 describes the interrupt configuration register (INTCFG).

The ICU receives requests from eight internal sourc es:

• Three outputs from the timer/co unter u nit (OUT2:0)

• An output from each of the serial I/O units (SIOINT1:0)

• An output from the synchronous serial I/O unit (SSIOINT)

• An output from the DMA unit (DMAINT)

• An output from the WDT unit (WDTOUT#)

In addition, the ICU controls the interrupt sources on te n external pins:

• INT3:0 (multiplexed with I/ O port signals P3.5:2) are enabled or disabled by the P3CFG

• INT7:4 share their package pins with four TCU inputs: TMRGATE1, TMRCLK1,

TMRGATE 0, and TMRC LK 0. These sig nal pairs are not multipl exed; howeve r, the pin inputs are enabled or disabled by the INTC FG register.

• INT9:8 share their pins with TMROUT1, TMROUT0, P3.1, P3.0

The three cascade outputs (CAS2:0) should be enabled when an external 82C59A module is connected to one of the INT9:8 or INT3:0 signals. The cascade outputs are ORed with address lines A18:16. See “Interrupt Acknowled ge Cycle” on page 6-23 for details.

Use Tables 5-1 and 5-2 to configure the functionality of the master 82C59A’ s IR3, IR4 inputs, and the associated external pins.

5-7

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

Tabl e 5-1. Master’s IR3 Connections

Function INTCFG.6 M CR1.3 P3CFG.1

IR3 connected to SIOINT1 P3.1 selecte d at pin (P3. 1)

IR3 connected to SIOINT1 OUT1 connected to pin (TMROUT1)

IR3 internal ly driven low P3.1 selecte d at pin (P3. 1)

IR3 connecte d to pin (INT8 ) 1 0 1 IR3 connected to SIOINT1

P3.1 selecte d at pin (P3. 1) IR3 connected to SIOINT1

pin (INT8) must not be left floating NOTE: X is a don’t care

0X0

0X1

100

110

111

Tabl e 5-2. Master’s IR4 Connections

Function INTCFG.5 M CR0.3 P3CFG.0

IR4 connected to SIOINT0 P3.0 selecte d at pin (P3.0)

0X0

IR4 connected to SIOINT0 OUT0 connected to pin (TMROUT0)

IR4 internal ly driven low P3.0 selecte d at pin (P3.0)

IR4 connecte d to pin (INT9 ) 1 0 1 IR4 connected to SIOINT0

P3.0 selecte d at pin (P3.0) IR4 connected to SIOINT0

pin (INT9) must not be left floating NOTE: X is a don’t care

5-8

0X1

100

110

111

DEVICE CONFIGURATI ON

INTR

(to

core)

8259A

Master

INT

CAS2:0

INT

8259A

Slave

CAS2:0

IR0 IR1

IR2

IR3

IR4

IR5

IR6

IR7

IR0

P3CFG.2

INTCFG.6

INTCFG.5

P3CFG.3

P3CFG.4

P3CFG.5

INTCFG.0

0 1

OUT0 (TCU)

SIOINT1

SIOINT0

To/From I/O Port 3

MCR1.3

SIOINT1

1 0

OUT1(TCU)

MCR0.3

SIOINT0

1 0

OUT0(TCU)

To/From I/O Port 3

To TCU

P3CFG.2

INTCFG.6

P3.1

INTCFG.5

P3.0

P3CFG.3

P3CFG.1

P3GFG.0

P3CFG.4

P3CFG.5

INT0 (P3.2)†

INT8 TMROUT1 (P3.1)

INT9 TMROUT0 (P3.0)

INT1 (P3.3)

INT2 (P3.4)

INT3 (P3.5)

INT4

(TMRCLK0)

INTCFG.1

SSIOINT

IR1

IR2 IR3

0 1

OUT1(TCU) OUT2(TCU)

To TCU

INT5

(TMRGATE0)

INTCFG.4

A18:16

DMAINT

To TCU

INT6

(TMRCLK1)

INT7

(TMRGATE1)

CAS2:0 (A18:16)

IR4

0 1

IR5

0 1

INTCFG.2

IR6

IR7

WDTOUT#

0 1

INTCFG.3

INTCFG.7

† Alternate pin signals are in parentheses

Heavier lines indicate multiple signals.

Figure 5-4. Interrupt Control Unit Configuration

A2522-03

5-9

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

Interrupt Configuration INTCFG (read/write)

Expanded Addr: ISA Addr: Reset State:

F832H — 00H

7 0

CE IR3 IR4 SWAP IR6 IR5/IR4 IR1 IR0

Bit

Number

Bit

Mnemonic

Function

7 CE Cascade Enable:

0 = Disables the cascade signa ls CAS2:0 from appearing on the A18:16

address lines du ring interrupt acknowledge cycles.

1 = Enables the cascade signals CAS2:0, providing access to external

slave 82C59A devices. The cascade signals are used to address specific slaves. If enabled, slave IDs appear on the A18:16 address lines during interrupt acknowledge cycles, but are high during idle cycles.

6 IR3 Internal Master IR3 Connection:

See Table 5-1 on page 5-8 for all the IR3 configuration options.

5 IR4 Internal Master IR4 Connection:

See Table 5-2 on page 5-8 for all the IR4 configuration options.

4 SWAP INT6/DMAINT Connection:

0 = Connects DMAINT to the slave IR4. Connects INT6 to the slave IR5. 1 = Connects the INT6 pin to the slave IR4. Connects DMAINT to the slave

IR5.

3 IR6 Internal Slave IR6 Connection:

0 = Connects V

to the slave IR6 signal.

1 = Connects the INT7 pin to the slave IR6 signal.

2 IR5/IR4 Internal Slave IR4 or IR5 Connect ion:

These depend on whether INTCFG.4 is set or clear. 0 = Connects V

to the slave IR5 signal.

1 = Connects either the INT6 pin or DMAIN T to the slave IR5 signa l.

1 IR1 Internal Slave IR1 Connection:

0 = Connects the SSIO interrupt signa l (SSIOINT ) to the slave IR1 signal . 1 = Connects the INT5 pin to the slave IR1 signal.

0 IR0 Internal Slave IR0 Connection:

0 = Connects V

to the slave IR0 signal.

1 = Connects the INT4 pin to the slave IR0 signal.

Figure 5-5. Interrupt Co nfiguration R egister (INTCFG)

5-10

DEVICE CONFIGURATI ON

5.2.3 Timer/counter Unit Configuration

The three-channel Timer/counter Unit (TCU) and its configuration register (TMRCFG) are shown in Figure 5-6 and Figure 5-7. The clock inputs can be external signals (TMRCLK2:0) or the on-chip programmable clock (PSCLK). All clock inputs can be held low by programming bits in the TMRCFG regi ster. The gate inputs can be controlled through software using T MR CFG.6 and the appropriate GTnCON bits in the TMRCFG register. Several of the timer signals go to the interrupt control unit (see Figure 5-4).

The Timer/counter0 and Timer/counter1 sig nals are selected individua lly. In contras t, the Timer/counter2 signals (TMRCLK2, TMRGATE2, TMROUT2) are selected as a group. Note that using the Ti mer/counter2 signals precludes us e of the coprocessor si gnals (PEREQ, BUSY#, and ERR OR#).

The CLKINn and GATE n inputs of Timer/counter0 and Timer/counter1 are routed directly to shared input pins, TMRCLK0/INT4, TMRCLK1/INT6, TMRGATE0/INT5 and TMRGATE1/INT7. The OUTn inputs of these two counters can be connected to pins TMROUT0/INT9/ P3.0 and TMROUT1/INT8/P3.1 re spectively, using bi ts in registers P3CFG and INTCFG.

5-11

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

Timer/Counter

Unit

CLKIN0

GATE0

OUT0

CLKIN1

GATE1

OUT1

TMRCFG.6

0 1

TMRCFG.7

TMRCFG.0

0 1

TMRCFG.1

To ICU

To/From I/O Port 3

TMRCFG.2

0 1

TMRCFG.3

To ICU, DMA

To/From I/O Port 3

TMRCFG.4

PSCLK

0 1

To ICU

P3CFG.0

P3CFG.1

TMRCLK0 (INT4)†

TMRGATE0 (INT5)

TMROUT0 (INT9) (P3.0)

TMRCLK1 (INT6)

TMRGATE1 (INT7)

TMROUT1 (INT8) (P3.1)

CLKIN2

TMRCFG.6

GATE2

OUT2

† Alternate pin signals are in parentheses.

Figure 5-6. Timer/Counter Unit Configurat ion

5-12

0 1

TMRCFG.5

To ICU, DMA

PSCLK

0 1

To Core

PINCFG.5

TMRCLK2 (PEREQ)

TMRGATE2 (BUSY#)

TMROUT2 (ERROR#)

A2517-03

DEVICE CONFIGURATI ON

Timer Configuration TMRCFG (read/write)

7 0

TMRDIS SWGTEN GT2CON CK2CON GT1CON CK1CO N GT0CON CK0C ON

Expanded Addr: ISA Addr: Reset Sta te:

F834 H — 00H

Bit

Number

Bit

Mnem oni c

7 TMRDIS Timer Disable:

0 = Enables the CLKIN 1 = Disables the CLKIN

6 SWGTEN Software GATE

Enab le

0 = Connects GATE 1 = Enables GT2CON, GT1CON, and GT0CON to control the

connections to GATE2, GATE1 and GATE0 respectively.

5 GT2CON Gate 2 Connection:

SWGTEN GT2CON

00 01Connects GATE2 to the TMRGATE2 pin. 10Turns GATE2 off. 11Turns GATE2 on.

4 CK2CON Clock 2 Connection:

0 = Connects CLKIN2 to the internal PSCLK signal. 1 = Connects CLKIN2 to the TMRCLK2 pin.

3 GT1CON Gate 1 Connection:

SWGTEN GT1CON

00 01Connects GATE1 to the TMRGATE1 pin. 10Turns GATE1 off. 11Turns GATE1 on.

2 CK1CON Clock 1 Connection:

0 = Connects CLKIN1 to the internal PSCLK signal. 1 = Connects CLKIN1 to the TMRCLK1 pin.

1 GT0CON Gate 0 Connection:

SWGTEN GT0CON

00 01Connects GATE0 to the TMRGATE1 pin. 10Turns GATE0 off. 11Turns GATE0 on.

0 CK0CON Clock 0 Connection:

0 = Connects CLKIN0 to the internal PSCLK signal. 1 = Connects CLKIN0 to the TMRCLK0 pin.

Func tion

signals.

to either the VCC pin or the TMRGATEn pin.

Connects GATE2 to V

Connects GATE1 to V

Connects GATE0 to V

CC.

Figure 5-7. Timer Configurati on Register (TMRCFG )

5-13

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

5.2.4 Asynchrono us S eri al I/O Config ur atio n

Figures 5-8 and 5-9 show the asynchronous serial I/O unit configuration, consisting of channels SIO0 and SIO1. Each channel has one o utput (SIOINT0, SIOINT 1) to the inte rrupt cont rol unit (see Figure 5 -4) and two outputs to the DMA unit . (These signals do not go to package pins.) SIOINTn is active when any one of the SIO status signa ls (receiver line status, receiver bu ffer full, transmit buffer empty, modem status) is set and enabled. All SIO0 pins are multiplexed with I/O port signals.

Using SIO1 precludes using DMA channel 1 for external DMA re quests due to the multiplexing of the transmit and receive signals with DMA signals (RXD1/DRQ1, TXD1/DAC K1#).

NOTE

Using SIO1 modem signals RTS 1#, DSR1#, DTR 1#, and RI1 # precludes use of the SSIO unit.

5-14

DEVICE CONFIGURATI ON

SIO0

BCLKIN

Receive Data

SIOINT0 RBFDMA0 TXEDMA0

Transmit Data

Clear to Send

Request to Send

Data Set Ready

SIOCFG.0

To ICU To DMA To DMA

SIOCFG.6

SERCLK

To/From I/O Port 3

To/From I/O Port 2

To/From I/O Port 1

P3CFG.7

P2CFG.5

P2CFG.6

0 P2CFG.7

P1CFG.1

0 P1CFG.3

COMCLK (P3.7)†

RXD0 (P2.5)

TXD0 (P2.6)

CTS0# (P2.7)

RTS0# (P1.1)

DSR0# (P1.3)

Data Carrier

Detect

Data Terminal

Ready

Ring Indicator

† Alternate pin signals are in parentheses.

Figure 5-8. Serial I/O Unit 0 Configuratio n

P1CFG.0

To/From I/O Port 1

P1CFG.2

DCD0# (P1.0)

DTR0#

To/From I/O Port 1

P1CFG.4

To/From I/O Port 1

(P1.2)

RI0# (P1.4)

A2521-02

5-15

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

SIO1

BCLKIN

Receive Data

SIOINT1

RBFDMA1

TXEDMA1

Transmit Data

Clear to Send

Request to Send

SIOCFG.1

0 1

To ICU To DMA To DMA

SIOCFG.7

0 1

SERCLK

To/From I/O Port 3

To DMA

From DMA

To/From DMA

From SSIO

P3CFG.7

PINCFG.2

PINCFG.3

PINCFG.0

COMCLK (P3.7)†

RXD1 (DRQ1)

TXD1 (DACK1#)

CTS1# (EOP#)

RTS1# (SSIOTX)

Data Set Ready

0 1

Data Carrier

Detect

0 1

Data Terminal

Ready

Ring Indicator

0 1

† Alternate pin signals are in parentheses.

Figure 5-9. Serial I/O Unit 1 Configuratio n

To/From SSIO

To DMA

To/From SSIO

To SSIO

DSR1# (STXCLK)

DCD1# (DRQ0)

PINCFG.1

DTR1# (SRXCLK)

RI1# (SSIORX)

A2519-02

5-16

DEVICE CONFIGURATI ON

SIO and SSIO Configurati on SIOCFG (read/ wri te)

7 0

S1M S 0M — — — SSBSRC S 1BSR C S0BSRC

Bit

Number

7 S1M SIO1 Modem Sign al Conne ctio ns:

6 S0M SIO0 Modem Sign al Conne ctio ns:

5–3 — Reserved. These bits are undefined; for compatibility with future devices,

2 SSBSRC SSIO Baud-rate Generator Clock Source:

1 S1BSRC SIO1 Baud-rate Generator Clock Source:

Bit

Mnem oni c

0 = Connects the SIO1 modem input signals to the package pins. 1 = Connects the SIO1 modem input signals internally.

0 = Connects the SIO0 modem input signals to the package pins. 1 = Connects the SIO0 modem input signals internally.

do not modify these bits.

0 = Connects the internal PSCLK signal to the SSIO baud-rate

generator.

1 = Connects the internal SERCLK signal to the SSIO baud-rate

generator.

0 = Conne cts the COMCL K pin to the SIO1 baud-ra te generat or. 1 = Connects the internal SERCLK signal to the SIO1 baud-rate

generator.

Expanded Addr: ISA Addr: Reset Sta te:

Func tion

F836 H — 00H

0 S0BSRC SIO0 Baud-rate Generator Clock Source:

0 = Conne cts the COMCL K pin to the SIO0 baud-ra te generat or. 1 = Connects the internal SERCLK signal to the SIO0 baud-rate

generator.

Figure 5-10. SIO and SSIO Configuration Register (SIOCFG)

5-17

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

5.2.5 Synchronous Serial I/O Configuration

The synchronous serial I/O uni t (SSIO) is shown in Figure 5-11. Its singl e config uration register bit is in the SIOCFG register (Figure 5-10). The transmit buffer empty and receive buffer full signals (SSTBE and SSR BF) go to the DMA u nit (Figure 5-2), and an interrupt signal (SSIOINT) goes to the ICU (Figure 5-4). Depending on the settings in the SSIOCON1 register (see Chapter

13), SSIOINT is asserted for one of two conditions: the receive buffer is full or the transmit buffer is empty. Note that using t he SSIO signals precludes the use of four of the SIO1 modem signals.

SSIO

BCLKIN

SSTBE SSRBF

SSIOINT

Receive Data

Transmit Data

Transmit Clock

Receive Clock

SIOCFG.2

PSCLK SERCLK

To DMA To DMA To ICU

To SIO1

From SIO1

To SIO1

From SSIO1

PINCFG.0

PINCFG.1

SSIORX (RI1#)*

SSIOTX (RTS1#)

STXCLK (DSR1#)

SRXCLK (DTR1#)

*Alternate pin signals are in parentheses.

5-18

A2518-02

Figure 5-11. SSIO U nit Configuration

DEVICE CONFIGURATI ON

5.2.6 Chip-select Uni t and Cl ock an d Power Managem en t Unit Config urati on

Figure 5-12 shows the multipl exing of signals of the Chip-selec t Unit and the Clock and Power Manageme nt U nit .

The Chip-select signals, CS6# and CS5# a re multiplexed with the REFRES H# signal from the Refresh Control Unit and the DACK0# signal from the DM A U nit, respective ly. Bits 6 and 4 in the PINCFG register (see Figure 5-15) control these multipl exers. CS3#, CS2#, CS1# and CS0 # are multiple xed wit h I/O Port 2 signal s, P2.3, P2.2, P2. 1 and P2.0, respect ively. Bits 4:0 in the P2CFG register (see Figure 5-17) control t hese multiplexers.

The PWRDOWN o utput signal of the Clock and Power M anagement Unit is multiple xed with I/O Port 3 signal, P3.6. Bit 6 in the P3C FG regist er (see Figure 5-18) controls this multiplex er.

5-19

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

CSU

CS0#

CS1#

CS2#

CS3#

CS4#

CS5#

CS6#

To/From I/O Port 2

DACK0# (DMA)

REFRESH# (RCU)

P2CFG.0

P2CFG.1

P2CFG.2

P2CFG.3

P2CFG.4

PINCFG.4

PINCFG.6

CSO# (P2.0)

CS1# (P2.1)

CS2# (P2.2)

CS3# (P2.3)

CS4# (P2.4)

CS5# (DACK0#)

CS6# (REFRESH#)

Clock and

Power

Management

Unit

P3CFG.6

PWRDOWN

To/From I/O Port 3

PWRDOWN (P3.6)

A3380-01

Figure 5-12. Confi guration of Chip-select Unit and Clock and Power Management Unit

5-20

DEVICE CONFIGURATI ON

5.2.7 Core Configuration

Three coprocessor signal s (ERR OR#, PER E Q, and BUSY# in Figure 5-13) can be routed to the core, as determined by bit 5 of the PINCFG register (see Figure 5-15). Due to signal multiplexing at the pins, the coprocessor and Timer/counter 2 cannot be used simultane ousl y.

Core

ERROR#

PEREQ

BUSY#

PINCFG.5

From TCU

To TCU

PINCFG.5

RESET Timing

Generation

ERROR# (TMROUT2)†

PEREQ (TMRCLK2)

BUSY# (TMRGATE2)

PORT92.0

RESET

A20

LOCK#

To/From I/O Port 1

† Alternate pin signals are in parentheses.

Figure 5-13. Core Configuration

From Chip RESET Pin

PORT92.1

To Chip-select Unit and A20 Pin

P1CFG.5

LOCK# (P1.5)

A2520-02

5-21

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

Setting bit 0 in the PORT92 register (see Figure 5-14) resets the core without resetting the peripherals. Unlike the RE SET pin, which is asynch ronous and can be used to synchronize internal clocks to CLK2, this core-only reset is synchronized with the on-chip clocks and does not affect the on-chip cloc k synchronization. After the CPU-R ESET this bit is still set to 1. It must be cleared and then set to cause another core-only reset.

Clearing bit 1 in the PORT92 register forces address line A20 to 0. This bit affects only addresses generated by the core ; addresses genera ted by the DMA a nd the refresh cont rol unit are not affected.

Port 92 Configuration PORT92 (read/write)

7 0

— — — — — — A20G CPURS T

Bit

Number

7–2 — Reserved. These bits are undefined; for compatibility with future devices,

1 A20G A20 Grounded:

0 CPURST CPU Reset:

Bit

Mnem oni c

do not modify these bits.

0 = Cle ari ng this b it for ce s ad dre s s lin e A20 to 0. This bit affect s

addresses generated only by the core. Addresses generated by the DMA and the Refresh Unit are not affected by this bit.

1 = Se tting this bit leaves core-generated addresses unmodified.

0 = Clearing this bit performs no operation. 1 = Setting this bit resets the core without resetting the peripherals.

This bit must be cleared before issuing anothe r reset.

Expanded Addr: ISA Addr: Reset Sta te:

Func tion

F092 H 0092H XXXXXX10B

Figure 5-14. Port 92 Configuration Register (PORT92)

5-22

DEVICE CONFIGURATI ON

5.3 PIN CONFIGURATIO N

Most of the microprocessor’s package pins support two peripheral functions. Some of these pins are routed to two periphera l inputs wit h out the use of a multiple xer. These input-signal pairs are listed in Ta ble 5-3. The pin is connected to both peripheral inputs.

The remaining pins supporting two signals have multiplexers. For each such pin, a bit in a pin configuration register enable s one of the signals. Table 5-9 lists the bits in each of the four pin configuration registers. These abbreviated register tables are discussed in “Configuration Example ” on page 5-28 .

When configuring ports to use INT8 or INT9, first set the appropriate INTCFG bit, then the P3CFG bit. Setting the bits in this order avoids any potential contention on INT8 or INT9.

Table 5-3. Signal Pairs on Pins without a Multiplexer

Names Signal Descriptions

DRQ0/ DCD1#

DRQ1/ RXD1

DSR1#/ STXCLK

RI1#/ SSIORX

TMRCLK0/ INT4

TMRGATE0/ INT5

TMRCLK1/ INT6

DMA Externa l Re qu es t 0 indica tes that an off-chip perip heral requires DMA service. Data Carrier Detect SIO1 indicates that the modem or da ta set has detec ted the

asynchronous serial channel’s data carrier.

DMA Externa l Re qu es t1 in dica tes tha t an off-chip periphera l requi res DMA ser vice. Receive Data SIO1 accepts serial data from the modem or data set to the

asynchronous serial channel SIO1. Data Set Ready SIO1 indicates that the modem or data set is ready to establish a

communication link with asynchronous serial channel SIO1.

SSIO Transmit Cloc k synch ronizes dat a being sent by the synchronous serial port. Ring Indicator SIO1 indicates that the modem or data set has received a telephone

ringing signal. SSIO Receive Serial Data accepts serial data (most-significant bit first) being sent to

the synchro no u s serial port. Timer/Counter0 Clock Input can serve as an externa l cloc k input for timer/co un ter0 .

(The timer/ co unte r s ca n al so be clock ed int ernal ly.)

Interrupt 4 is an undedicat ed extern al interrupt. Timer/Counter0 Gate Input can control timer/counter0’s counting (enable, disable, or

trigger, depending on the programmed mode).

Interrupt 5 is an undedicated external interrupt. Timer/Counter1 Clock Input can serve as an externa l cloc k input for timer/co un ter1 .

(The timer/ co unte r s ca n al so be clock ed int ernal ly.) Interrupt 6 is an undedicated external interrupt.

TMRGATE1/ INT7

Timer/Counter1 Gate Input can control timer/counter1’s counting (enable, disable, or trigger, depending on the programmed mode).

Interrupt 7 is an undedicated external interrupt.

5-23

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

Pin Configuration PINCFG (read/write)

7 0

— PM6 PM 5 P M4 PM 3 PM 2 PM 1 PM 0

Bit

Number

7 — Reserved. This bit is undefined; for compatibility with future devices, do

6 PM6 Pin M od e:

5 PM5 Pin M od e:

4 PM4 Pin M od e:

3 PM3 Pin M od e:

2 PM2 Pin M od e:

1 PM1 Pin M od e:

0 PM0 Pin M od e:

Bit

Mnem oni c

not modify this bit.

0 = Selects CS6# at the package pin. 1 = Selects REFRESH# at the package pin.

0 = Selects the coprocessor signals, PEREQ, BUSY#, and ERROR#, at

the package pins.

1 = Selects the timer control unit signals, TMROUT2, TMRCLK2, and

TMRGATE2, at the package pins.

0 = Selects DACK0# at the package pin. 1 = Selects CS5# at the package pin.

0 = Selects EOP# at the package pin. 1 = Selects CTS1# at the package pin.

0 = Selects DACK1# at the package pin. 1 = Selects TXD1 at the package pin.

0 = Selects SRXCLK at the package pin. 1 = Selects DTR1# at the package pin.

0 = Selects SSIOTX at the package pin. 1 = Selects RTS1# at the package pin.

Expanded Addr: ISA Addr: Reset Sta te:

Func tion

F826 H — 00H

Figure 5-15. Pin Configuration Register (PINCFG)

5-24

DEVICE CONFIGURATI ON

Port 1 Configuration P1CFG (read/write)

7 0

PM7 PM6 PM5 PM4 PM 3 PM2 PM1 PM0

Bit

Number

7 PM7 Pin M od e:

6 PM6 Pin M od e:

5 PM5 Pin M od e:

4 PM4 Pin M od e:

3 PM3 Pin M od e:

2 PM2 Pin M od e:

1 PM1 Pin M od e:

0 PM0 Pin M od e:

Bit

Mnem oni c

0 = Selects P1 .7 at the packag e pin. 1 = Selects HLDA at the package pin.

0 = Selects P1 .6 at the packag e pin. 1 = Selects HOLD at the package pin.

0 = Selects P1 .5 at the packag e pin. 1 = Selects LOCK# at the package pin.

0 = Selects P1 .4 at the packag e pin. 1 = Selects RI0# at the package pin.

0 = Selects P1 .3 at the packag e pin. 1 = Selects DSR0# at the package pin.

0 = Selects P1 .2 at the packag e pin. 1 = Selects DTR0# at the package pin.

0 = Selects P1 .1 at the packag e pin. 1 = Selects RTS0# at the package pin.

0 = Selects P1 .0 at the packag e pin. 1 = Selects DCD0# at the package pin.

Expanded Addr: ISA Addr: Reset Sta te:

Func tion

F820 H — 00H

Figure 5-16. Port 1 Configuration Register (P1CFG)

5-25

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

Port 2 Configuration P2CFG (read/write)

7 0

PM7 PM6 PM5 PM4 PM 3 PM2 PM1 PM0

Bit

Number

7 PM7 Pin M od e:

6 PM6 Pin M od e:

5 PM5 Pin M od e:

4 PM4 Pin M od e:

3 PM3 Pin M od e:

2 PM2 Pin M od e:

1 PM1 Pin M od e:

0 PM0 Pin M od e:

Bit

Mnem oni c

0 = Selects P2 .7 at the packag e pin. 1 = Selects CTS0# at the package pin.

0 = Selects P2 .6 at the packag e pin. 1 = Selects TXD0 at the package pin.

0 = Selects P2 .5 at the packag e pin. 1 = Selects RXD0 at the package pin.

0 = Selects P2 .4 at the packag e pin. 1 = Selects CS4# at the package pin.

0 = Selects P2 .3 at the packag e pin. 1 = Selects CS3# at the package pin.

0 = Selects P2 .2 at the packag e pin. 1 = Selects CS2# at the package pin.

0 = Selects P2 .1 at the packag e pin. 1 = Selects CS1# at the package pin.

0 = Selects P2 .0 at the packag e pin. 1 = Selects CS0# at the package pin.

Expanded Addr: ISA Addr: Reset Sta te:

Func tion

F822 H — 00H

Figure 5-17. Port 2 Configuration Register (P2CFG)

5-26

DEVICE CONFIGURATI ON

Port 3 Configuration P3CFG (read/write)

7 0

PM7 PM6 PM5 PM4 PM 3 PM2 PM1 PM0

Bit

Number

7 PM7 Pin M od e:

6 PM6 Pin M od e:

5 PM5 Pin M od e:

4 PM4 Pin M od e:

Bit

Mnem oni c

0 = Selects P3 .7 at the packag e pin. 1 = Selects COMCLK at the package pin.

0 = Selects P3 .6 at the packag e pin. 1 = Selects PWRDOWN at the package pin.

0 = Selects P3 .5 at the packag e pin. 1 = Connects master IR7 to the package pin (INT3).

0 = Selects P3 .4 at the packag e pin. 1 = Connects master IR6 to the package pin (INT2).

Expanded Addr: ISA Addr: Reset Sta te:

Func tion

F824 H — 00H

3 PM3 Pin M od e:

0 = Selects P3 .3 at the packag e pin. 1 = Connects master IR5 to the package pin (INT1).

2 PM2 Pin M od e:

0 = Selects P3 .2 at the packag e pin. 1 = Connects master IR1 to the package pin (INT0).

1 PM1 Pin M od e:

See Table 5-1 on page 5-8 for all the PM1 configuration options.

0 PM0 Pin M od e:

See Table 5-1 on page 5-8 for all the PM0 configuration options.

Figure 5-18. Port 3 Configuration Register (P3CFG)

5-27

Intel Intel386 EX, Intel386 EXTB, Intel386 EXTC User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual