Intel® I/O Controller Hub 8/9 LAN
NVM Map and Information Guide
April 2012
Revision 2.6
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23 LAN NVM Contents....................................................................................................27
Revision History
RevRev DateDescription
2.6April 2012Updated NVM words 13h (bit 0) and 15h (bits 15:8).
2.5Jan 2012Initial Release (Public).
2.4Jan 2007
2.3Jan 2007Added ICH9 and 82567 NVM information.
2.2Oct 2006Added device IDs for the 82562G and 82562GT 10/100 Mb/s Platform LAN Connects.
2.1July 2006Changed bit 1 of word 13h to 0b.
2.0June 2006
1.75April 2006Updated bit descriptions for words 13h, 14h, and 19h.
1.5Feb 2006
1.0Dec 2005
0.75July 2005Initial release (Intel Secret).
Updated sections 1.2, 1.4.6, 1.4.13, 1.4.14, 1.4.19, and 1.4.20.
Added sections 1.4.25.1 through 1.4.25.4 (PXE words 30h through 33h).
Initial public release.
Added new LAN Word Offset 19h description to Tables 1 and 17.
Added new EEPROM images to Appendix A.
Updated bit defaults and descriptions to Tables 9, 10, 13, 15, and 16.
Initial Intel Confidential release.
Converted this to a stand-alone document. Previously, it was AP-478 Addendum.
Added Section 1.1, ”NVM Programming Procedure Overview,” and Section 1.2,
”EEUPDATE Utility.”
Updated the following sections:
Section 2.12, ”Shared Initialization Control (Word 13h),” bits 10 and 0
Section 2.13, ”Extended Configuration Word 1 (Word 14h),” bits 15, 14, and 11:0
Section 2.14, ”Extended Configuration Word 2 (Word 15h),” bits 15:8
Section 2.15, ”Extended Configuration Word 3 (Word 16h)”
Section 2.16, ”LED 1 Configuration and Power Management (Word 17h),” bit 7
Section 2.17, ”LED 0 and 2 Configuration Defaults (Word 18h),” bit 7
Section 2.18, ”Future Initialization Word 1 (Words 19h)”
Section 2.20, ”Checksum (Word 3Fh)”
Appendix A.1 ”82566DM NVM Image with ICH8”
Appendix A.3 ”82562V NVM Image with ICH8”
Updated Section 2.12, ”Shared Initialization Control (Word 13h),” Table 9 to add the
Ext Pwr Polarity bit.
Added the 82566 NVM image to A.1 ”82566DM NVM Image with ICH8.”
4
ICH8/ICH9—NVM Information Guide
1.0Non-Volatile Memory (NVM)
1.1Introduction
The document is intended for designs using the 10/100/1000 Mb/s LAN controller that
is integrated into the Intel
®
I/O Control Hub 8 or I/O Control Hub 9 (ICH8/ICH9)
device.
The Non-Volatile Memory (NVM) space is used for hardware and software configuration.
It is read by software to determine and configure specific design features.
Unless otherwise specified, all numbers in this document use the following numbering
convention:
• Numbers that do not have a suffix are decimal (base 10).
• Numbers with a suffix of “h” are hexadecimal (base 16).
• Numbers with a suffix of “b” are binary (base 2).
1.2NVM Programming Procedure Overview
The LAN NVM shares space on an SPI Flash device (or devices) along with the BIOS,
Manageability Firmware, and a Flash Descriptor Region. It is programmed through the
ICH8/ICH9. This combined image is shown in Figure 1. The Flash Descriptor Region is
used to define vendor specific information and the location, allocated space, and read
and write permissions for each region. The Manageability (ME) Region contains the
code and configuration data for ME functions such as Intel
Technology, ASF, and Advanced Fan Speed Control. The system BIOS is contained in
the BIOS Region. The ME Region and BIOS Region are beyond the scope of this
document and a more detailed explanation of these areas can be found in the Intel
O Controller Hub 8 (ICH8) Family External Design Specification (ICH8 EDS) and the
This document describes the LAN image contained in the Gigabit Ethernet (GbE) region.
Fast Ethernet (82562V) images are also described.
®
Active Management
®
I/
5
r
GbE
3
BIOS
1
ME
2
Region
Region
Region
Flash Descripto
Region 0
NVM Information Guide—ICH8/ICH9
Figure 1.LAN NVM Regions
To access the NVM, it is essential to correctly setup the following:
1. A valid Flash Descriptor Region must be present. Details for the Flash Descriptor
Region are contained in the ICH8/ICH9 EDS. The
easiest method of configuring this descriptor region. This process is described in
detail in the Intel
FTOOL.exe and the Intel
can be obtained as part of the Intel Active Client Manager kit on ARMS
(https://platformsw.intel.com/) or by contacting your local Intel representative.
2. The GbE region must be part of the original image flashed onto the part.
3. For Intel LAN tools and drivers to work correctly, the BIOS must set the VSCC
register(s) correctly.
For the ICH9, there are two sets of VSCC registers, the upper (UVSCC) and lower
(LVSCC). Note that the LVSCC register is only used if the NVM attributes change.
For example, the use of a second flash component, a change in erase size between
segments, etc. Due to the architecture of the ICH8/ICH9, if these registers are
not set correctly, the LAN tools might not report an error message even though the
NVM contents remain unchanged. Refer to the ICH8/ICH9 EDS for more
information
4. The GbE region of the NVM must be accessible. To keep this region accessible, the
Protected Range register of the GbE LAN Memory Mapped Configuration registers
must be set to their default value of 0000 0000h. (The GbE Protected Range
registers are described in the ICH8/ICH9 EDS).
5. If you are using the 82566/82567, the ICH8/ICH9 soft strap for the GLCI
interface must be set correctly. Bit 19 of STRP0 must be set to 1b (as described in
the ICH8/ICH9 EDS). For the 82562V, this bit can be set to 0b, since it does not
use the GLCI bus.
®
Active Management Technology OEM Bring-Up Guide.
®
Active Management Technology OEM Bring-Up Guide
FTOOL.exe utility provides the
6
ICH8/ICH9—NVM Information Guide
6. The sector size of the NVM must equal 256 bytes, 4 KB, or 64 KB. When a Flash
device that uses a 64 KB sector erase is used, the GbE region size must equal
128 KB. If the Flash part uses a 4 KB or 256-byte sector erase, then the GbE region
size must be set to 8 KB.
The NVM image contains both static and dynamic data. The static data is the basic
platform configuration, and includes OEM specific configuration bits as well as the
unique Printed Circuit Board Assembly (PBA). The dynamic data holds the product’s
Ethernet Individual Address (IA) and Checksum. This file can be created in a simple
text editor and follows the format shown in Appendix A, which provides examples of
GbE Region NVM maps for ICH8/ICH9-based designs. Fast Ethernet (82562V) images
are also provided.
1.3EEUPDATE Utility
Intel has created an EEUPDATE utility that can be used to update the GbE region
images during in-circuit programming. The tool uses two basic data files outlined in the
following section (static data file and IA address file). The EEUPDATE utility is flexible
and can be used to update the entire GbE region image or only the IA address of the
LAN controller. In addition, it also corrects the GbE component checksum field after the
region is modified (FTOOL does not have this ability). For more information on how to
use EEUPDATE, refer to the
utility.
eeupdate.txt file that is included with the EEUPDATE
To obtain a copy of this program, contact your Intel representative.
1.3.1Command Line Parameters
The DOS command format is as follows:
EEUPDATE Parameter_1 Parameter_2
where:
Parameter_1 = /D or /A
/D is used to update the entire GbE region image.
/A is used to update just the Ethernet Individual Address.
Parameter_2 = filename
In Example 1, Parameter_2 is
a specific format used to update the complete GbE region. All comments in the
file must be preceded by a semicolon (;).
Example 1. EEUPDATE /D file1.eep
In Example 1, Parameter 2 is
EEUPDATE utility finds the first unused address from this file and uses it to update the
NVM. An address is marked used if it is followed by a date stamp. When the utility uses
a specific address, a log file called eelog.dat is updated with that address. This updated
file should be used as the
Appendix A provides an example of the raw GbE region contents. Fast Ethernet
(82562V) images are also provided.
file1.eep, which contains the complete NVM image in
file2.dat, which contains a list of IA addresses. The
.dat file for the next update.
.eep
7
1.4LAN NVM Format and Contents
Tab l e 1 lists the NVM maps for the LAN region. Each word listed is described in detail in
the following sections.
Table 1.LAN NVM Address Map
NVM Information Guide—ICH8/ICH9
LAN
Word
Offset
00h00
01h02
02h04
03h06ReservedSW0800h
04h08ReservedSWFFFFh
05h0AImage Version Information 1SW
06h0ChReservedSWFFFFh
07h0EhReservedSWFFFFh
08h10hPBA LowSW
09h12hPBA HighSW
0Ah14hPCI Initialization Control WordHW-PCI
0Bh16hSubsystem IDHW-PCI
0Ch18hSubsystem Vendor IDHW-PCI
0Dh1AhDevice IDHW-PCI
0Eh1ChVendor IDHW-PCI
0Fh1Eh
10h20hLAN Power ConsumptionHW-PCI
11h22hReserved
12h24hReserved
13h26hShared Initialization Control Word
14h28hExtended Configuration Word 1
15h2AhExtended Configuration Word 2
16h2ChExtended Configuration Word 3
17h2EhLEDCTL 1
18h30hLEDCTL 0 2
19h32h
1Ah34hFuture Initialization Word 2 (ICH9)
NVM
Byte
Offset
HIgh Byte (Bits 15:8)Low Byte (Bits 7:0)Used By
Ethernet Individual Address
Ethernet Individual Address
Ethernet Individual Address
Byte 2
Byte 4
Byte 6
Device Rev ID (ICH9)
Reserved (ICH8)
Future Initialization Word (ICH8)
Future Initialization Word 1 (ICH9)
Ethernet Individual Address
Ethernet Individual Address
Ethernet Individual Address
Byte 1
Byte 3
Byte 5
HW-
Shared
HW-
Shared
HW-
Shared
HW-PCI
HW-
Shared
HW-
Shared
HW-
Shared
HW-
Shared
HW-
Shared
HW-
Shared
HW-
Shared
HW-
Shared
Image
Value
IA (2,1)
IA (4,3)
IA (6,5)
0000h
0000h
1
1
8
ICH8/ICH9—NVM Information Guide
LAN
Word
Offset
1Bh36hReserved (ICH9)
1Ch38hReserved (ICH9)294Ch
1Dh3AhReserved (ICH9)294Ch
1Eh3Ch82567MM Device ID (ICH9)10BEh
1Fh3Eh82567MC Device ID (ICH9)10BFh
20h40hReserved (ICH9)294Ch
21h42hReserved (ICH9)294Ch
22h44h82566DC Device ID (ICH9)10BDh
23h46h82566DM Device ID (ICH9)294Ch
20h to
2Fh
24h to
2Fh
30h to
3Eh
3Fh
1. ICH9 only.
Notes:
1.SW = Software: This is access from the network configuration tools and drivers.
2.PXE = PXE Boot Agent: This is access from the PXE Option ROM code in BIOS.
3.HW-Shared = Hardware - Shared: This is read on when the Shared Configuration is reset.
4.HW-PCI = Hardware - PCI: This is read when the PCI Configuration is reset.
5.HW-PCIm = Hardware - PCIm: This is read when the PCIm Configuration is reset.
The Ethernet Individual Address (IA) is a six-byte field that must be unique for each
adapter card or LOM and unique for each copy of the NVM image. The first three bytes
are vendor specific. (For example, these bytes equal 00 AA 00 or 00 A0 C9 for Intel
products.) The last three bytes must be unique for each copy of the NVM. OEM versions
of the product might be required to have non-Intel ID’s in the first three byte positions.
The value from this field is loaded into the Receive Address Register 0 (RAL0/RAH0).
The Intel default is listed in Tab l e 2.
Note:The Ethernet IA is byte swapped, as listed in Tab l e 2 .
The IA bytes read from the NVM are used by the ICH8/ICH9 until an IA Setup
command is issued by software. The IA defined by the IA Setup command overrides the
IA read from the NVM.
Byte 2Byte 1Byte 4Byte 3Byte 6Byte
5
9
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