Intel CORE 2 DUO E4000, CORE 2 DUO E6000, CORE 2 EXTREME X6800 User Manual

Intel® Core™2 Extreme Processor

X6800 and Intel® Core™2 Duo

Desktop Processor E6000 and

E4000 Sequence

Specification Update

— on 65 nm Process in the 775-land LGA Package supporting Intel® 64Φ Architecture, Intel® Virtualization Technology± and Intel® Trusted Execution Technologyŧ

May 2008

Notice: The Intel® CoreTM2 Extreme and Intel® CoreTM2 Duo desktop processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.

Document Number: 313279-026

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

The Intel® Core™2 Duo and Intel® Core™2 Extreme Processors may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Φ Intel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. See http://www.intel.com/technology/intel64/ for more information including details on which processors support Intel 64, or consult with your system vendor for more information.

± Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations. Intel Virtualization Technology-enabled BIOS and VMM applications are currently in development.

ŧ No computer system can provide absolute security under all conditions. Intel Trusted Execution Technology is a security technology under development by Intel and requires for operation a computer system with Intel® Virtualization Technology, an Intel Trusted Execution Technology-enabled Intel processor, chipset, BIOS, Authenticated Code Modules, and an Intel or other Intel Trusted Execution Technology compatible measured virtual machine monitor. In addition, Intel Trusted Execution Technology requires the system to contain a TPMv1.2 as defined by the Trusted Computing Group and specific software for some uses.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details.

Intel, the Intel logo, Celeron, Pentium, Xeon, Intel SpeedStep, Intel Core, and Core Inside are trademarks of Intel Corporation in the U.S. and other countries.

*Other names and brands may be claimed as the property of others. Copyright © 2006 - 2008, Intel Corporation

2 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update

Contents
Contents .............................................................................................................................	3
Revision History ...................................................................................................................	4
Preface ...............................................................................................................................	6
Summary Tables of Changes ..................................................................................................	8
Identification Information ....................................................................................................	17
Component Identification Information....................................................................................	20
Errata ...............................................................................................................................	23
Specification Changes .........................................................................................................	70
Specification Clarifications ...................................................................................................	71
Documentation Changes ......................................................................................................	72
	§

Intel® Core™2 Extreme Processor X6800 and

Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 3 Specification Update

Revision History

	Revision		Description	Date
	-001	•	Initial release of the Intel® Core™2 Extreme Processor X6800 and Intel®	July 2006
			Core™2 Duo Desktop Processor E6000 Sequence Specification Update	Out of Cycle
	-002	•	Updated Erratum AI19, AI29 and AI40	Aug 2006
		•	Added Erratum AI58-AI67
	-003	•	Updated Erratum AI20, AI38	Sept 2006
		•	Added Erratum AI68-AI77
		•	Updated Erratum AI72
	-004	•	Updated Status for Erratum AI55 in Errata table	Oct 2006
		•	Added Erratum AI78-AI82
		•	Added Specification change AI1
		•	Updated Erratum AI46 and AI53
		•	Replaced Erratum AI10 with a new erratum
	-005	•	Added Erratum AI83 – AI85	Nov 2006
		•	Corrected Plan information in Summary Table of Changes for Errata
			AI16, AI69, AI70, AI72 and AI75
		•	Updated Erratum AI75 and AI83
	-006	•	Replaced Erratum AI61 with a new erratum	Dec 2006
		•	Added Erratum AI86 – AI90
		•	Corrected Plan information in Summary Table of Changes for Errata AI8
	-007	•	Added Erratum AI91 - AI94	Jan 2007
	-008	•	Added L step information	Jan 2007
		•	Added processor number E4300 information	Out Of Cycle
		•	Updated Erratum AI70
	-009	•	Added Erratum AI95-AI97	Feb 2007
		•	Updated Component Identification information table
	-010	•	Added Erratum AI98 - AI100	Mar 2007
	-011	•	Added Erratum AI101-AI104	Apr 2007
		•	Updated Erratum AI33 in Summary table of changes
	-012	•	Added processor number E6320, E6420 and E4400 information	Apr 2007
				Out Of Cycle
	-013	•	Added Erratum AI105	Apr 2007
				Out Of Cycle
	4		Intel® Core™2 Extreme Processor X6800 and
			Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
				Specification Update

		•	Added Specification Clarification AI1
-014		•	Updated Erratum AI14, AI25 and AI26	May 2007
-015		•	Included M0 stepping and G0 stepping information (updated summary	July 2007
			tables of change and updated processor identification information)	Out of Cycle
-016		•	Added Errata AI106 to AI111	July 2007
-017		•	Added processor number E4400 on M0 stepping information	Aug 2007
				Out Of Cycle
-018		•	Updated Plan Status for AI33 and AI43	Aug 2007
		•	Added Erratum AI112
-019		•	Added Erratum AI113 and AI114	Sept 2007
		•	Added Erratum AI115 - AI123
-020		•	Updated Plan Status for AI6, AI21 - AI23, AI38 - AI42, AI44, AI50, AI55	Oct 2007
			- AI57, AI61, AI66, AI69, AI72, AI75, AI79, AI91, AI92, AI94, AI101,
			AI109
		•	Added processor number E4600 information
-021		•	Added Erratum AI124	Nov 2007
		•	Updated Plan status for errata AI20, AI24, AI31, AI70, AI102, AI121,
			AI122 and AI123
-022		•	Updated Erratum AI8	Dec 2007
		•	Added Erratum AI125
-023		•	Added Erratum AI126	Jan 16th 2008
		•	Updated Erratum AI51
-024		•	Deleted Erratum AI123 (because it is repeat of AI108) and replaced with	Feb 13th 2008
			a new Erratum
-025		•	Added processor number E4700 information	Mar 3rd 2008
-026		•	Added Erratum AI127, AI128	May 2008

Intel® Core™2 Extreme Processor X6800 and

Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 5 Specification Update

Preface

Preface

This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.

Information types defined in the Nomenclature section of this document are consolidated into this update document and are no longer published in other documents. This document may also contain information that has not been previously published.

Affected Documents

	Document Title	Document Number
	Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo	313278-008
	Desktop Processor E6000 and E4000 Sequence Datasheet

Related Documents

	Document Title	Document Location
	Intel® 64 and IA-32 Architectures Software Developer’s
	Manual Volume 1: Basic Architecture
	Intel® 64 and IA-32 Architectures Software Developer’s
	Manual Volume 2A: Instruction Set Reference Manual A–M	http://www.intel.com/product
	Intel® 64 and IA-32 Architectures Software Developer’s
	Manual Volume 2B: Instruction Set Reference Manual, N–Z	s/processor/manuals/index.h
		tm
	Intel® 64 and IA-32 Architectures Software Developer’s
	Manual Volume 3A: System Programming Guide
	Intel® 64 and IA-32 Architectures Software Developer’s
	Manual Volume 3B: System Programming Guide

6 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update

Preface

Nomenclature

S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number

QDF Number is a several digit code that is used to distinguish between engineering samples. These processors are used for qualification and early design validation. The functionality of these parts can range from mechanical only to fully functional. The NDA specification update has a processor identification information table that lists these QDF numbers and the corresponding product sample details.

Errata are design defects or errors. Errata may cause the processor’s behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

Specification Changes are modifications to the current published specifications. These changes will be incorporated in the next release of the specifications.

Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in the next release of the specifications.

Documentation Changes include typos, errors, or omissions from the current published specifications. These changes will be incorporated in the next release of the specifications.

Note: Errata remain in the specification update throughout the product’s lifecycle, or until a particular stepping is no longer commercially available. Under these circumstances, errata removed from the specification update are archived and available upon request. Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, etc.).

§

Intel® Core™2 Extreme Processor X6800 and

Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 7 Specification Update

Summary Tables of Changes

Summary Tables of Changes

The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted. This table uses the following notations:

Codes Used in Summary Table

Stepping

X:

(No mark) or (Blank Box):

Erratum, Specification Change or Clarification that applies to this stepping.

This erratum is fixed in listed stepping or specification change does not apply to listed stepping.

Status

Doc:	Document change or update that will be implemented.
PlanFix:	This erratum may be fixed in a future stepping of the
	product.
Fixed:	This erratum has been previously fixed.
NoFix:	There are no plans to fix this erratum.

Row

Shaded:	This item is either new or modified from the previous
	version of the document.

8 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update

Summary Tables of Changes

Item Numbering

Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor specification updates:

A =	Dual-Core Intel® Xeon® processor 7000 sequence
C =	Intel® Celeron® processor
D =	Dual-Core Intel® Xeon® processor 2.80 GHz
E =	Intel® Pentium® III processor
	Intel® Pentium® processor Extreme Edition and Intel® Pentium® D
F =	processor
I =	Dual-Core Intel® Xeon® processor 5000 series
J =	64-bit Intel® Xeon® processor MP with 1MB L2 cache
K =	Mobile Intel® Pentium® III processor
L =	Intel® Celeron® D processor
M =	Mobile Intel® Celeron® processor
N =	Intel® Pentium® 4 processor
O =	Intel® Xeon® processor MP
P =	Intel ® Xeon® processor
	Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology
Q =	on 90-nm process technology
R =	Intel® Pentium® 4 processor on 90 nm process
	64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2
S =	cache versions)
T =	Mobile Intel® Pentium® 4 processor-M
U =	64-bit Intel® Xeon® processor MP with up to 8MB L3 cache
	Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA
V =	package
W=	Intel® Celeron® M processor
	Intel® Pentium® M processor on 90nm process with 2-MB L2 cache and
X =	Intel® processor A100 and A110 with 512-KB L2 cache
Y =	Intel® Pentium® M processor
Z =	Mobile Intel® Pentium® 4 processor with 533 MHz system bus
	Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor
AA =	Extreme Edition 955, 965
AB =	Intel® Pentium® 4 processor 6x1 sequence
AC =	Intel(R) Celeron(R) processor in 478 pin package
AD =	Intel(R) Celeron(R) D processor on 65nm process
	Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm
AE =	process
AF =	Dual-Core Intel® Xeon® processor LV
AG =	Dual-Core Intel® Xeon® processor 5100 series

Intel® Core™2 Extreme Processor X6800 and

Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 9 Specification Update

Summary Tables of Changes

Intel® Core™2 Duo/Solo processor for Intel® Centrino® Duo processor AH = technology

Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop AI = processor E6000 and E4000 sequence

AJ = Quad-Core Intel® Xeon® processor 5300 series

Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® AK = Core™2 Quad processor Q6000 sequence

AL = Dual-Core Intel® Xeon® processor 7100 series AM = Intel® Celeron® processor 400 sequence

AN = Intel® Pentium® dual-core processor

AO = Quad-Core Intel® Xeon® processor 3200 series AP = Dual-Core Intel® Xeon® processor 3000 series

AQ = Intel® Pentium® dual-core desktop processor E2000 sequence AR = Intel® Celeron® processor 500 series

AS = Intel® Xeon® processor 7200, 7300 series

AV = Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad processor Q9000 series

AW = Intel® Core™ 2 Duo processor E8000 series

AX = Quad-Core Intel® Xeon® processor 5400 series

		AY=		Dual-Core Intel® Xeon® processor 5200 series
				Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-
		AZ =		nm Process
		AAA = Quad-Core Intel® Xeon® processor 3300 series
		AAB =		Dual-Core Intel® Xeon® E3110 Processor
		AAC =		Intel® Celeron® dual-core processor E1000 series
		AAD = Intel® Core™2 Extreme Processor QX9775
		AAE = Intel® Atom™ processor Z5xx series
			The Specification Updates for the Pentium® processor, Pentium® Pro processor, and
			other Intel products do not use this convention.
NO	B1		B2	L2	M0	G0		Plan	ERRATA
AI1	X		X	X	X	X		No Fix	Writing the Local Vector Table (LVT) when an Interrupt is Pending May
									Cause an Unexpected Interrupt
AI2	X		X	X	X	X		No Fix	LOCK# Asserted During a Special Cycle Shutdown Transaction May
									Unexpectedly De-assert
AI3	X		X	X	X	X		No Fix	Address Reported by Machine-Check Architecture (MCA) on Single-bit
									L2 ECC Errors May be Incorrect
AI4	X		X	X	X	X		No Fix	VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last
									Exception Record (LER) MSR
									DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store Instruction
AI5	X		X	X	X	X		No Fix	May Incorrectly Increment Performance Monitoring Count for Saturating
									SIMD Instructions Retired (Event CFH)
AI6	X		X	X	X			Fixed	SYSRET May Incorrectly Clear RF (Resume Flag) in the RFLAGS Register
AI7	X		X	X	X	X		No Fix	General Protection Fault (#GP) for Instructions Greater than 15 Bytes
									May be Preempted
10									Intel® Core™2 Extreme Processor X6800 and
							Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
									Specification Update

Summary Tables of Changes

	NO	B1	B2	L2	M0	G0	Plan	ERRATA
	AI8	X	X	X	X	X	No Fix	Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
								Before Higher Priority Interrupts
	AI9	X	X	X	X	X	No Fix	The Processor May Report a #TS Instead of a #GP Fault
	AI10	X	X	X	X	X	No Fix	Single Step Interrupts with Floating Point Exception Pending May Be
								Mishandled
	AI11	X	X	X	X	X	No Fix	A Write to an APIC Register Sometimes May Appear to Have Not
								Occurred
	AI12	X	X	X	X	X	No Fix	Programming the Digital Thermal Sensor (DTS) Threshold May Cause
								Unexpected Thermal Interrupts
	AI13	X	X	X	X	X	No Fix	Count Value for Performance-Monitoring Counter PMH_PAGE_WALK May
								be Incorrect
	AI14	X	X	X	X	X	No Fix	LER MSRs May be Incorrectly Updated
	AI15	X	X	X	X	X	No Fix	Performance Monitoring Events for Retired Instructions (C0H) May Not
								Be Accurate
								Performance Monitoring Event For Number Of Reference Cycles When
	AI16	X	X	X	X	X	No Fix	The Processor Is Not Halted (3CH) Does Not Count According To The
								Specification
	AI17	X	X	X	X	X	No Fix	Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect
								Address Translations
	AI18	X	X	X	X	X	No Fix	Writing Shared Unaligned Data that Crosses a Cache Line without
								Proper Semaphores or Barriers May Expose a Memory Ordering Issue
	AI19	X	X	X	X	X	No Fix	Code Segment Limit Violation May Occur on 4 Gigabyte Limit Check
	AI20	X	X	X	X		Fixed	FP Inexact-Result Exception Flag May Not Be Set
								Global Pages in the Data Translation Look-Aside Buffer (DTLB) May Not
	AI21	X	X	X	X		Fixed	Be Flushed by RSM instruction before Restoring the Architectural State
								from SMRAM
	AI22	X	X	X	X		Fixed	Sequential Code Fetch to Non-canonical Address May have Non-
								deterministic Results
	AI23	X	X	X	X		Fixed	VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores
								Reserved Bit settings in VM-exit Control Field
	AI24	X	X	X	X	X	No Fix	The PECI Controller Resets to the Idle State
	AI25	X	X	X	X	X	No Fix	Some Bus Performance Monitoring Events May Not Count Local Events
								under Certain Conditions
	AI26	X	X	X	X	X	No Fix	Premature Execution of a Load Operation Prior to Exception Handler
								Invocation
	AI27	X	X	X	X	X	No Fix	General Protection (#GP) Fault May Not Be Signaled on Data Segment
								Limit Violation above 4-G Limit
	AI28	X	X	X	X	X	No Fix	EIP May be Incorrect after Shutdown in IA-32e Mode
	AI29	X	X	X	X	X	No Fix	#GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34] When
								Execute Disable Bit is Not Supported

Intel® Core™2 Extreme Processor X6800 and

Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 11 Specification Update

Summary Tables of Changes

	NO	B1	B2	L2	M0	G0	Plan	ERRATA
	AI30	X	X				Fixed	(E)CX May Get Incorrectly Updated When Performing Fast String REP
								MOVS or Fast String REP STOS With Large Data Structures
	AI31	X	X	X	X		Fixed	Performance Monitoring Events for Retired Loads (CBH) and Instructions
								Retired (C0H) May Not Be Accurate
	AI32	X	X	X	X	X	No Fix	Upper 32 bits of 'From' Address Reported through BTMs or BTSs May be
								Incorrect
	AI33	X	X	X			Fixed	Unsynchronized Cross-Modifying Code Operations Can Cause
								Unexpected Instruction Execution Results
								MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
	AI34	X	X	X	X	X	No Fix	Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data after
								a Machine Check Exception (MCE)
	AI35	X	X	X	X	X	No Fix	Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image
								Leads to Partial Memory Update
	AI36	X	X	X	X	X	No Fix	Split Locked Stores May not Trigger the Monitoring Hardware
	AI37	X	X				Fixed	REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode when
								RCX >= 0X100000000
								FXSAVE/FXRSTOR Instructions which Store to the End of the Segment
	AI38	X	X	X	X		Fixed	and Cause a Wrap to a Misaligned Base Address (Alignment <= 0x10h)
								May Cause FPU Instruction or Operand Pointer Corruption
								Cache Data Access Request from One Core Hitting a Modified Line in the
	AI39	X	X	X	X		Fixed	L1 Data Cache of the Other Core May Cause Unpredictable System
								Behavior
	AI40	X	X	X	X		Fixed	PREFETCHh Instruction Execution under Some Conditions May Lead to
								Processor Livelock
	AI41	X	X	X	X		Fixed	PREFETCHh Instructions May Not be Executed when Alignment Check
								(AC) is Enabled
	AI42	X	X	X	X		Fixed	Upper 32 Bits of the FPU Data (Operand) Pointer in the FXSAVE Memory
								Image May Be Unexpectedly All 1's after FXSAVE
	AI43	X	X	X			Fixed	Concurrent Multi-processor Writes to Non-dirty Page May Result in
								Unpredictable Behavior
	AI44	X	X	X	X		Fixed	Performance Monitor IDLE_DURING_DIV (18h) Count May Not be
								Accurate
	AI45	X	X	X	X	X	No Fix	Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
	AI46	X	X	X	X	X	No Fix	Shutdown Condition May Disable Non-Bootstrap Processors
	AI47	X	X				Fixed	SYSCALL Immediately after Changing EFLAGS.TF May Not Behave
								According to the New EFLAGS.TF
	AI48	X	X	X	X	X	No Fix	Code Segment Limit/Canonical Faults on RSM May be Serviced before
								Higher Priority Interrupts/Exceptions
	AI49	X	X	X	X	X	No Fix	VM Bit is Cleared on Second Fault Handled by Task Switch from Virtual-
								8086 (VM86)
	AI50	X	X	X	X		Fixed	IA32_FMASK is Reset during an INIT

12 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update

Summary Tables of Changes

	NO	B1	B2	L2	M0	G0	Plan	ERRATA
								An Enabled Debug Breakpoint or Single Step Trap May Be Taken after
	AI51	X	X	X	X	X	No Fix	MOV SS/POP SS Instruction if it is Followed by an Instruction That
								Signals a Floating Point Exception
	AI52	X	X	X	X	X	No Fix	Last Branch Records (LBR) Updates May be Incorrect after a Task
								Switch
	AI53	X	X	X	X	X	No Fix	IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly
	AI54	X	X	X	X	X	No Fix	INIT Does Not Clear Global Entries in the TLB
	AI55	X	X	X	X		Fixed	Using Memory Type Aliasing with Memory Types WB/WT May Lead to
								Unpredictable Behavior
	AI56	X	X	X	X		Fixed	Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P)
								Bits without TLB Shootdown May Cause Unexpected Processor Behavior
	AI57	X	X	X	X		Fixed	BTS Message May Be Lost When the STPCLK# Signal is Active
	AI58	X	X	X	X	X	No Fix	CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal
								to 248 May Terminate Early
								REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
	AI59	X	X	X	X	X	No Fix	Boundaries with Inconsistent Memory Types may use an Incorrect Data
								Size or Lead to Memory-Ordering Violations.
	AI60	X	X	X	X	X	No Fix	MOV To/From Debug Registers Causes Debug Exception
	AI61	X	X	X	X		Fixed	Debug Register May Contain Incorrect Information on a MOVSS or
								POPSS Instruction Followed by SYSRET
	AI62	X	X	X	X	X	No Fix	EFLAGS Discrepancy on a Page Fault After a Multiprocessor TLB
								Shootdown
	AI63	X	X	X	X	X	No Fix	LBR, BTS, BTM May Report a Wrong Address when an
								Exception/Interrupt Occurs in 64-bit Mode
	AI64	X	X	X	X	X	No Fix	Returning to Real Mode from SMM with EFLAGS.VM Set May Result in
								Unpredictable System Behavior
	AI65	X	X	X	X	X	No Fix	A Thermal Interrupt is Not Generated when the Current Temperature is
								Invalid
	AI66	X	X	X	X		Fixed	VMLAUNCH/VMRESUME May Not Fail when VMCS is Programmed to
								Cause VM Exit to Return to a Different Mode
	AI67	X	X	X	X	X	No Fix	IRET under Certain Conditions May Cause an Unexpected Alignment
								Check Exception
	AI68	X	X	X	X	X	No Fix	Performance Monitoring Event FP_ASSIST May Not be Accurate
	AI69	X	X	X	X		Fixed	CPL-Qualified BTS May Report Incorrect Branch-From Instruction
								Address
	AI70	X	X	X	X		Fixed	PEBS Does Not Always Differentiate Between CPL-Qualified Events
	AI71	X	X	X	X	X	No Fix	PMI May Be Delayed to Next PEBS Event
	AI72	X	X	X	X		Fixed	PEBS Buffer Overflow Status Will Not be Indicated Unless
								IA32_DEBUGCTL[12] is Set

Intel® Core™2 Extreme Processor X6800 and

Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 13 Specification Update

										Summary Tables of Changes
NO			B1	B2	L2	M0	G0		Plan	ERRATA
AI73			X	X	X	X	X		No Fix	The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception
AI74			X	X	X	X	X		No Fix	An Asynchronous MCE During a Far Transfer May Corrupt ESP
										In Single-Stepping on Branches Mode, the BS Bit in the Pending-Debug-
AI75			X	X	X	X			Fixed	Exceptions Field of the Guest State Area will be Incorrectly Set by VM-
										Exit on a MOV to CR8 Instruction
AI76			X	X	X	X	X		No Fix	B0-B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint
AI77			X	X	X	X	X		No Fix	BTM/BTS Branch-From Instruction Address May be Incorrect for
										Software Interrupts
AI78			X	X	X	X	X		No Fix	Last Branch Records (LBR) Updates May be Incorrect After a Task
										Switch
AI79			X	X	X	X			Fixed	REP Store Instructions in a Specific Situation may cause the Processor
										to Hang
AI80			X	X	X	X	X		No Fix	Performance Monitoring Events for L1 and L2 Miss May Not be Accurate
AI81			X	X	X	X	X		No Fix	Store to WT Memory Data May be Seen in Wrong Order by Two
										Subsequent Loads
AI82			X	X	X	X	X		No Fix	A MOV Instruction from CR8 Register with 16 Bit Operand Size
										Will Leave Bits 63:16 of the Destination Register Unmodified
AI83			X	X	X	X	X		No Fix	Non-Temporal Data Store May be Observed in Wrong Program Order
AI84			X	X	X	X	X		No Fix	Performance Monitor SSE Retired Instructions May Return Incorrect
										Values
AI85			X	X	X	X	X		No Fix	Fault on ENTER Instruction May Result in Unexpected Values on Stack
										Frame
AI86			X	X					Fixed	CPUID Reports Architectural Performance Monitoring Version 2 is
										Supported, When Only Version 1 Capabilities are Available
AI87			X	X	X	X	X		No Fix	Unaligned Accesses to Paging Structures May Cause the Processor to
										Hang
AI88			X	X	X	X	X		No Fix	Microcode Updates Performed During VMX Non-root Operation Could
										Result in Unexpected Behavior
AI89			X	X	X	X	X		No Fix	INVLPG Operation for Large (2M/4M) Pages May be Incomplete under
										Certain Conditions
AI90			X	X	X	X	X		No Fix	Page Access Bit May be Set Prior to Signaling a Code Segment Limit
										Fault
AI91			X	X	X	X			Fixed	Update of Attribute Bits on Page Directories without Immediate TLB
										Shootdown May Cause Unexpected Processor Behavior
AI92			X	X	X	X			Fixed	Invalid Instructions May Lead to Unexpected Behavior
AI93			X	X	X	X	X		No Fix	EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after
										Shutdown
AI94			X	X	X	X			Fixed	Performance Monitoring Counter MACRO_INSTS.DECODED May Not
										Count Some Decoded Instructions
AI95			X	X	X	X			Fixed	The Stack Size May be Incorrect as a Result of VIP/VIF Check on
										SYSEXIT and SYSRET
14										Intel® Core™2 Extreme Processor X6800 and
								Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
										Specification Update

Summary Tables of Changes

	NO	B1	B2	L2	M0	G0	Plan	ERRATA
	AI96	X	X	X	X	X	No Fix	Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is Counted
								Incorrectly for PMULUDQ Instruction
	AI97	X	X	X	X	X	No Fix	Storage of PEBS Record Delayed Following Execution of MOV SS or STI
	AI98	X	X	X	X	X	No Fix	Store Ordering May be Incorrect between WC and WP Memory Types
	AI99	X	X	X	X	X	No Fix	Updating Code Page Directory Attributes without TLB Invalidation May
								Result in Improper Handling of Code #PF
	AI100	X	X	X	X		Fixed	Performance Monitoring Event CPU_CLK_UNHALTED.REF May Not Count
								Clock Cycles According to the Processors Operating Frequency
	AI101			X	X		Fixed	(E)CX May Get Incorrectly Updated When Performing Fast String REP
								STOS With Large Data Structures
	AI102	X	X	X	X		Fixed	Performance Monitoring Event BR_INST_RETIRED May Count CPUID
								Instructions as Branches
	AI103	X	X	X	X	X	No Fix	Performance Monitoring Event MISALIGN_MEM_REF May Over Count
	AI104	X	X	X	X	X	No Fix	A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent
								Triggering of the Monitoring Hardware
	AI105	X	X	X			Fixed	False Level One Data Cache Parity Machine-Check Exceptions May be
								Signaled
	AI106	X	X	X	X	X	No Fix	A Memory Access May Get a Wrong Memory Type Following a #GP due
								to WRMSR to an MTRR Mask
	AI107	X	X	X	X	X	No Fix	PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR
								Information
	AI108				X		Fixed	VMCALL failure due to corrupt MSEG location may cause VM Exit to load
								the machine state incorrectly
	AI109	X	X	X	X		Fixed	Overlap of an Intel® VT APIC Access Page in a Guest with the DS Save
								Area May Lead to Unpredictable Behavior
	AI110	X	X	X	X	X	No Fix	VTPR Write Access During Event Delivery May Cause an APIC-Access VM
								Exit
	AI111				X	X	No Fix	BIST Failure After Reset
	AI112	X	X	X	X	X	No Fix	Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
								Count Some Transitions
	AI113					X	No Fix	When One Core Executes SEXIT the Other Core's Last Branch Recording
								May be Incorrect
	AI114					X	No Fix	A GETSEC[ENTERACCS] Instruction Executed Immediately after
								GETSEC[WAKEUP] Instruction May Result in a Processor Hang
	AI115	X	X	X	X	X	No Fix	Instruction Fetch May Cause a Livelock During Snoops of the L1 Data
								Cache
	AI116	X	X	X	X	X	No Fix	Use of Memory Aliasing with Inconsistent Memory Type may Cause a
								System Hang or a Machine Check Exception
	AI117	X	X	X	X	X	No Fix	A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to
								Memory-Ordering Violations

Intel® Core™2 Extreme Processor X6800 and

Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 15 Specification Update

Summary Tables of Changes

NO

B1

B2

L2

M0

G0

Plan

ERRATA

VM Exit with Exit Reason “TPR Below Threshold” Can Cause the Blocking

AI118

X

X

X

X

X

No Fix

by MOV/POP SS and Blocking by STI Bits to be Cleared in the Guest

Interruptibility-State Field

AI119

X

X

X

X

X

No Fix

Using Memory Type Aliasing with Cacheable and WC Memory Types May

Lead to Memory Ordering Violations

AI120

X

X

X

X

X

No Fix

VM Exit due to Virtual APIC-Access May Clear RF

Fixed Function Performance Counters MSR_PERF_FIXED_CTR1 (30AH)

AI121

X

Fixed

and MSR_PERF_FIXED_CTR2 (30BH) are Not Cleared When the

Processor is Reset

AI122

X

Fixed

VTPR Access May Lead to System Hang

AI123

X

Fixed

IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check Error

Reporting Enable Correctly

AI124

X

X

X

X

X

No Fix

RSM Instruction Execution under Certain Conditions May Cause

Processor Hang or Unexpected Instruction Execution Results

AI125

X

X

X

Fixed

NMIs May Not Be Blocked by a VM-Entry Failure

AI126

X

X

X

X

X

No Fix

Benign Exception after a Double Fault May Not Cause a Triple Fault

Shutdown

AI127

X

X

X

X

X

No Fix

A VM Exit Due to a Fault While Delivering a Software Interrupt May

Save Incorrect Data into the VMCS

AI128

X

X

X

X

X

No Fix

A VM Exit Occuring in IA-32e Mode May Not Produce a VMX Abort When

Expected

Number

SPECIFICATION CHANGES

-There are no Specification Changes in this Specification Update revision.

Number	SPECIFICATION CLARIFICATIONS
AI1	Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation
Number	DOCUMENTATION CHANGES

-There are no Documentation Changes in this Specification Update revision.

§

16 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update

Identification Information

Identification Information

Figure 1. Intel® Core™2 Duo Desktop Processor 2M SKU Package with 800 MHz FSB

Figure 2. Intel® Core™2 Duo Desktop Processor 2M SKU Package with 1066 MHz FSB

Intel® Core™2 Extreme Processor X6800 and

Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 17 Specification Update

Identification Information

Figure 3. Intel® Core™2 Duo Desktop Processor 4M SKU Package with 1066 MHz FSB

Figure 4. Intel® Core™2 Duo Desktop Processor 4M SKU Package with 1333 MHz FSB

18 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update

Identification Information

Figure 5. Intel® Core™2 Extreme Processor Package

§

Intel® Core™2 Extreme Processor X6800 and

Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 19 Specification Update

Component Identification Information

Component Identification

Information

The Intel® Core™2 Extreme processor and Intel® Core™2 Duo desktop processor can be identified by the following values:

Family1	Model2
0110b	1111b

NOTES:

1.The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.

2.The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register. Refer to the Intel Processor Identification and the CPUID Instruction Application Note (AP-485) and the Conroe and Woodcrest Processor Family BIOS Writer’s Guide (BWG) for further information on the CPUID instruction.

The following notes are applicable to Table 1 through Table 3.

NOTES:

1.These processors support the 775_VR_CONFIG_06 specifications.

2.These processors support the 775_VR_CONFIG_05B specifications

3.These parts support Intel® 64 Architecture

4.These parts support Intel® Virtualization Technology (Intel® VT)

5.These parts support Intel® Trusted Execution Technology (Intel® TXT)

6.These parts support Execute Disable Bit Feature

7.These parts have PROCHOT# enabled

8.These parts have THERMTRIP# enabled

9.These parts support Thermal Monitor 2 (TM2) feature

10.These parts have PECI enabled

11.These parts have Tdiode enabled

12.These parts have Enhanced Intel SpeedStep® Technology (EIST) enabled 13.These parts have Extended HALT State (C1E) enabled

14.These parts have Extended Stop Grant State (C2E) enabled. 15.These parts have Extended HALT (C1E) power of 22W 16.These parts have Extended HALT (C1E) power of 12W 17.These parts have Extended HALT (C1E) power of 8W

20 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update

Component Identification Information

Table 1. Intel® Core™2 Duo Desktop Processor 2M SKU Identification Information

	S-Spec	Core	L2 Cache	Processor	Processor	Speed	Package	Notes
		Stepping	Size	Signature	Number	Core/Bus
			(bytes)
	SL9SA	B2	2M	06F6h	E6300	1.86 GHz /	775-land LGA	1, 3, 4, 6, 7, 8, 9,
						1066 MHz		10, 11, 12, 13, 15
	SL9S9	B2	2M	06F6h	E6400	2.13 GHz /	775-land LGA	1, 3, 4, 6, 7, 8, 9,
						1066 MHz		10, 11, 12, 13, 15
	SL9TB	L2	2M	06F2h	E4300	1.80 GHz /	775-land LGA	1, 3, 6, 7, 8, 9, 10,
						800 MHz		11, 12, 13, 16
	SLA3F	L2	2M	06F2h	E4400	2.00 GHz /	775-land LGA	1, 3, 6, 7, 8, 9, 10,
						800 MHz		11, 12, 13, 16
	SL9TA	L2	2M	06F2h	E6300	1.86 GHz /	775-land LGA	1, 3, 4, 6, 7, 8, 9,
						1066 MHz		10, 11, 12, 13, 16
	SL9T9	L2	2M	06F2h	E6400	2.13 GHz /	775-land LGA	1, 3, 4, 6, 7, 8, 9,
						1066 MHz		10, 11, 12, 13, 16
	SLA98	M0	2M	06FDh	E4400	2.00 GHz /	775-land LGA	1, 3, 6, 7, 8, 9, 10,
						800 MHz		11, 12, 13, 14, 17
	SLA95	M0	2M	06FDh	E4500	2.20 GHz /	775-land LGA	1, 3, 6, 7, 8, 9, 10,
						800 MHz		11, 12, 13, 14, 17
	SLA94	M0	2M	06FDh	E4600	2.40 GHz /	775-land LGA	1, 3, 6, 7, 8, 9, 10,
						800 MHz		11, 12, 13, 14, 17
	SLALT	G0	2M	06FBh	E4700	2.60 GHz /	775-land LGA	1, 3, 6, 7, 8, 9, 10,
						800 MHz		11, 12, 13, 14, 17

Table 2. Intel® Core™2 Duo Desktop Processor 4M SKU Identification Information

S-Spec	Core	L2 Cache	Processor	Processor	Speed	Package	Notes
	Stepping	Size	Signature	Number	Core/Bus
		(bytes)
SLA4U	B2	4M	06F6h	E6320	1.86 GHz /	775-land LGA	1, 3, 4, 6, 7, 8, 9, 10,
					1066 MHz		11, 12, 13, 16
SLA4T	B2	4M	06F6h	E6420	2.13 GHz /	775-land LGA	1, 3, 4, 6, 7, 8, 9, 10,
					1066 MHz		11, 12, 13, 16
SL9S8	B2	4M	06F6h	E6600	2.4 GHz /	775-land LGA	1, 3, 4, 6, 7, 8, 9, 10,
					1066 MHz		11, 12, 13, 15
SL9ZL	B2	4M	06F6h	E6600	2.4 GHz /	775-land LGA	1, 3, 4, 6, 7, 8, 9, 10,
					1066 MHz		11, 12, 13, 16
SL9S7	B2	4M	06F6h	E6700	2.66 GHz /	775-land LGA	1, 3, 4, 6, 7, 8, 9, 10,
					1066 MHz		11, 12, 13, 15

Intel® Core™2 Extreme Processor X6800 and

Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 21 Specification Update

Component Identification Information

Table 2. Intel® Core™2 Duo Desktop Processor 4M SKU Identification Information

S-Spec	Core	L2 Cache	Processor	Processor	Speed	Package	Notes
	Stepping	Size	Signature	Number	Core/Bus
		(bytes)
SL9ZF	B2	4M	06F6h	E6700	2.66 GHz /	775-land LGA	1, 3, 4, 6, 7, 8, 9, 10,
					1066 MHz		11, 12, 13, 16
SLAA5	G0	4M	06FBh	E6540	2.33 GHz /	775-land LGA	1, 3, 4, 6, 7, 8, 9, 10,
					1333 MHz		11, 12, 13, 14, 17
SLA9X	G0	4M	06FBh	E6550	2.33 GHz /	775-land LGA	1, 3, 4, 5, 6, 7, 8, 9,
					1333 MHz		10, 11, 12, 13, 14, 17
SLA9V	G0	4M	06FBh	E6750	2.66 GHz /	775-land LGA	1, 3, 4, 5, 6, 7, 8, 9,
					1333 MHz		10, 11, 12, 13, 14, 17
SLA9U	G0	4M	06FBh	E6850	3.00 GHz /	775-land LGA	1, 3, 4, 5, 6, 7, 8, 9,
					1333 MHz		10, 11, 12, 13, 14, 17

Table 3. Intel® Core™2 Extreme Processor Identification Information

	S-Spec	Core	L2 Cache	Processor	Processor	Speed	Package	Notes
		Stepping	Size	Signature	Number	Core/Bus
			(bytes)
	SL9S5	B2	4M	06F6h	X6800	2.93 GHz /	775-land LGA	2, 3, 4, 6, 7, 8, 9,
						1066 MHz		10, 11, 12, 13, 15

22 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update