Intel CORE 2 DUO E4000, CORE 2 DUO E6000, CORE 2 EXTREME X6800 User Manual

Intel® Core™2 Extreme Processor

X6800 Desktop Processor E6000 E4000

Datasheet

and Intel® Core™2 Duo

and

Series

—on 65 nm Process in the 775-land LGA Package and supporting Intel® 64

Architecture and supporting Intel

March 2008

Virtualization Technology

Document Number: 313278-008

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE , E XPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "un defined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future ro admaps. See www.intel.com/products/ processor_number for details.

64 requires a computer system with a processor , chipset, BIOS, oper ating system, device drivers, and applications enabled for Intel 64. Processor

Intel will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or consult with your system vendor for more information.

No computer system can provide absolute security under all conditions. Intel development by Intel and req u ir es f or operation a computer system with In te l Intel processor, chipset, BIOS, Authenticated Code Modules, and an Intel or other Intel Trusted Execution Technology compatible measured virtual machine monitor . In addition, Intel Trusted Execution Technology requires the system to contain a TPMv1.2 as defined by the Trusted Computing Group and specific software for some uses.

±Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or ot he r be ne fit s wi ll vary depending on hardwa re and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

The Intel known as errata which may cause the product to deviate from published specifications.

Core™2 Duo desktop processor E6000 and E4000 series and Intel® Core™2 Extreme processor X6800 may contain design defects or errors

Trusted Execution Technology (Intel® TXT) is a security technology under

Virtualization Technology, a Intel Trusted Execution Technology-enabled

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, Intel Core, Core Inside, Intel Inside, Intel Leap ahead, Intel SpeedStep, and the Intel logo are trademarks of Intel Corporation in the U.S.

2 Datasheet

1Introduction............................................................................................................11

1.1 Terminology .....................................................................................................12

1.1.1 Processor Terminology............................................................................12

1.2 References.......................................................................................................14

2 Electrical Specifications...........................................................................................15

2.1 Power and Ground Lands....................................................................................15

2.2 Decoupling Guidelines ........................................................................................15

2.2.1 VCC Decoupling .....................................................................................15

2.2.2 Vtt Decoupling.......................................................................................15

2.2.3 FSB Decoupling......................................................................................16

2.3 Voltage Identification.........................................................................................16

2.4 Market Segment Identification (MSID) .................................. .. .. ...........................18

2.5 Reserved, Unused, and TESTHI Signals ................................................................18

2.6 Voltage and Current Specification........................................................................19

2.6.1 Absolute Maximum and Minimum Ratings ..................................................19

2.6.2 DC Voltage and Current Specification.................................................. .. .. ..20

2.6.3 V

2.6.4 Die Voltage Validation............................................................ ... .. ............24

2.7 Signaling Specifications............................................ .. ............................ .. ..........25

2.7.1 FSB Signal Groups..................................................................................25

2.7.2 CMOS and Open Drain Signals .................................................................27

2.7.3 Processor DC Specifications .....................................................................27

2.7.4 Clock Specifications................................................................................29

2.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking............................29

2.7.6 FSB Frequency Select Signals (BSEL[2:0]).................................................29

2.7.7 Phase Lock Loop (PLL) and Filter..............................................................30

2.7.8 BCLK[1:0] Specifications (CK505 based Platforms) ............. .. ...................... 30

2.7.9 BCLK[1:0] Specifications (CK410 based Platforms) ............. .. ...................... 32

2.8 PECI DC Specifications.......................................................................................33

3 Package Mechanical Specifications ..........................................................................35

3.1 Package Mechanical Drawing...................... .........................................................35

3.1.1 Processor Component Keep-Out Zones......................................................39

3.1.2 Package Loading Specifications .......................... .. ... .. .. .............................39

3.1.3 Package Handling Guidelines.............................. .. ... .. ...............................39

3.1.4 Package Insertion Specifications.......................................... .. .. ... ..............40

3.1.5 Processor Mass Specification....................................................................40

3.1.6 Processor Materials.................................................................................40

3.1.7 Processor Markings.................................................................................40

3.1.8 Processor Land Coordinates.....................................................................43

4 Land Listing and Signal Descriptions .......................................................................45

4.1 Processor Land Assignments...............................................................................45

4.2 Alphabetical Signals Reference............................................................................68

5 Thermal Specifications and Design Considerations ..................................................77

5.1 Processor Thermal Specifications.........................................................................77

5.1.1 Thermal Specifications............................................................................77

5.1.2 Thermal Metrology .................................................................................84

5.2 Processor Thermal Features................................................................................84

5.2.1 Thermal Monitor.....................................................................................84

5.2.2 Thermal Monitor 2..................................................................................85

5.2.3 On-Demand Mode ..................................................................................86

Overshoot ............................................... ........................................24

2.7.3.1 GTL+ Front Side Bus Specifications .............................................28

Datasheet 3

5.2.4 PROCHOT# Signal ..................................................................................87

5.2.5 THERMTRIP# Signal............................................................. ...................87

5.3 Thermal Diode...................................................................................................88

5.4 Platform Environment Control Interface (PECI)......................................................90

5.4.1 Introduction...........................................................................................90

5.4.1.1 Key Difference with Legacy Diode-Based Thermal

Management ............................................................................90

5.4.2 PECI Specifications .................................................................................92

5.4.2.1 PECI Device Address................................... .. .. ...........................92

5.4.2.2 PECI Command Support.............................. .. .............................92

5.4.2.3 PECI Fault Handling Requirements...............................................92

5.4.2.4 PECI GetTemp0() Error Code Support ..........................................92

6Features..................................................................................................................93

6.1 Power-On Configuration Options..........................................................................93

6.2 Clock Control and Low Power States......................... .. ........................... ... ............93

6.2.1 Normal State .........................................................................................94

6.2.2 HALT and Extended HALT Powerdown States..............................................94

6.2.2.1 HALT Powerdown State.......................... .. ... ...............................94

6.2.2.2 Extended HALT Powerdown State ................................................95

6.2.3 Stop Grant and Extended Stop Grant States...............................................95

6.2.3.1 Stop Grant State..................................................................... ..95

6.2.3.2 Extended Stop Grant State.........................................................96

6.2.4 Extended HALT State, HALT Snoop State, Extended Stop Grant Snoop

State, and Stop Grant Snoop State ...........................................................96

6.2.4.1 HALT Snoop State, Stop Grant Snoop State ..................................96

6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop

State.......................................................................................96

6.3 Enhanced Intel

SpeedStep® Technology .............................................................96

7 Boxed Processor Specifications................................................................................99

7.1 Mechanical Specifications..................................................................................100

7.1.1 Boxed Processor Cooling Solution Dimensions...........................................100

7.1.2 Boxed Processor Fan Heatsink Weight .....................................................101

7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip

Assembly.............................................................................................101

7.2 Electrical Requirements ............................................ .. .. .. ............................ .. ....101

7.2.1 Fan Heatsink Power Supply.............................. ............................ .. .. ......101

7.3 Thermal Specifications........................... .. .. ............................ .. .. .......................103

7.3.1 Boxed Processor Cooling Requirements....................................................103

7.3.2 Fan Speed Control Operation (Intel

Core2 Extreme Processor

X6800 Only) ........................................................................................105

7.3.3 Fan Speed Control Operation (Intel® Core2 Duo Desktop Processor

E6000 and E4000 Series Only) .......................... .....................................105

8 Balanced Technology Extended (BTX) Boxed Processor Specifications...................107

8.1 Mechanical Specifications..................................................................................108

8.1.1 Balanced Technology Extended (BTX) Type I and Type II Boxed Processor

Cooling Solution Dimensions ..................................................................108

8.1.2 Boxed Processor Thermal Module Assembly Weight ...................................110

8.1.3 Boxed Processor Support and Retention Module (SRM) ..............................111

8.2 Electrical Requirements ............................................ .. .. .. ............................ .. ....112

8.2.1 Thermal Module Assembly Power Supply..................................................112

8.3 Thermal Specifications........................... .. .. ............................ .. .. .......................114

8.3.1 Boxed Processor Cooling Requirements....................................................114

8.3.2 Variable Speed Fan........................................................................... ....114

9 Debug Tools Specifications ....................................................................................117

9.1 Logic Analyzer Interface (LAI) ...........................................................................117

9.1.1 Mechanical Considerations .....................................................................117

9.1.2 Electrical Considerations........................................................................117

4 Datasheet

Figures

1VCC Static and Transient Tolerance.............................................................................23

3 Differential Clock Waveform ......................... .. .. ............................ .. .. .........................31

4 Differential Clock Crosspoint Specification ...................................................................31

5 Differential Measurements....................................... .. .. .. ........................... ... .. ............31

6 Differential Clock Crosspoint Specification ...................................................................32

7 Processor Package Assembly Sketch...........................................................................35

8 Processor Package Drawing Sheet 1 of 3................................. ....................................36

9 Processor Package Drawing Sheet 2 of 3................................. ....................................37

10 Processor Package Drawing Sheet 3 of 3......................................................... .. .. .. ......38

11 Processor Top-Side Markings Example for the Intel 12 Processor Top-Side Markings Example for the Intel 13 Processor Top-Side Markings Example for the Intel 14 Processor Top-Side Markings Example for the Intel 15 Processor Top-Side Markings for the Intel

16 Processor Land Coordinates and Quadrants (Top View) .................................................43

17 land-out Diagram (Top View – Left Side).....................................................................46

18 land-out Diagram (Top View – Right Side)...................................................................47

19 Thermal Profile 1 .....................................................................................................79

20 Thermal Profile 2 .....................................................................................................80

21 Thermal Profile 3 .....................................................................................................81

22 Thermal Profile 4 .....................................................................................................82

23 Thermal Profile 5 .....................................................................................................83

24 Case Temperature (TC) Measurement Location ...... ......................................................84

25 Thermal Monitor 2 Frequency and Voltage Ordering......................................................86

26 Processor PECI Topology................................ .. .. ............................ ...........................90

27 Conceptual Fan Control on PECI-Based Platforms .........................................................91

28 Conceptual Fan Control on Thermal Diode-Based Platforms............................................91

29 Processor Low Power State Machine ...........................................................................94

30 Mechanical Representation of the Boxed Processor ................. ......................................99

31 Space Requirements for the Boxed Processor (Side View)............................................ 100

32 Space Requirements for the Boxed Processor (Top View)............................................. 100

33 Space Requirements for the Boxed Processor (Overall View)......................... ............... 101

34 Boxed Processor Fan Heatsink Power Cable Connector Description................................ 102

35 Baseboard Power Header Placement Relative to Processor Socket................................. 103

36 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) .... .. .. .. .. .. .. . 104

37 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)................. 104

38 Boxed Processor Fan Heatsink Set Points................................................................... 106

39 Mechanical Representation of the Boxed Processor with a Type I TMA ........................... 109

40 Mechanical Representation of the Boxed Processor with a Type II TMA .......................... 110

41 Requirements for the Balanced Technology Extended (BTX) Type I Keep-out 42 Requirements for the Balanced Technology Extended (BTX) Type II Keep-out

43 Assembly Stack Including the Support and Retention Module ....................................... 113

44 Boxed Processor TMA Power Cable Connector Description............................................ 114

45 Balanced Technology Extended (BTX) Mainboard Power Header Placement

46 Boxed Processor TMA Set Points............................................................................... 117

Overshoot Example Waveform.............................................................................24

Core™2 Duo Desktop

Processor E6000 Series with 4 MB L2 Cache with 1333 MHz FSB..................................... 40

Processors E6000 Series with 4 MB L2 Cache with 1066 MHz FSB........................ ........... 41

Processors E6000 Series with 2 MB L2 Cache...............................................................41

Processors E4000 Series with 2 MB L2 Cache...............................................................42

Core™2 Extreme Processor X6800.................42

Core™2 Duo Desktop

Volumes ............................................................................................................... 111

Volume................................................................................................................. 112

(hatched area) .................................................................... .................................. 115

Datasheet 5

Tables

1 Reference Documents ...................................... .. ................................................... .. ..14

2 Voltage Identification Definition..................................................................................17

3 Market Segment Selection Truth Table for MSID[1:0] ...................................................18

4 Absolute Maximum and Minimum Ratings ....................................................................20

5 Voltage and Current Specifications..............................................................................20

6V 7V

8 FSB Signal Groups....................................................................................................25

9 Signal Characteristics.............................................. .. ........................... .. .. .................26

10 Signal Reference Voltages ................................ .. .. ............................ .........................26

11 GTL+ Signal Group DC Specifications..........................................................................27

12 Open Drain and TAP Output Signal Group DC Specifications ...........................................27

13 CMOS Signal Group DC Specifications..........................................................................28

14 GTL+ Bus Voltage Definitions.....................................................................................28

15 Core Frequency to FSB Multiplier Configuration.............................................................29

16 BSEL[2:0] Frequency Table for BCLK[1:0] ...................................................................30

17 Front Side Bus Differential BCLK Specifications.............................................................30

18 Front Side Bus Differential BCLK Specifications.............................................................32

19 PECI DC Electrical Limits ...........................................................................................33

20 Processor Loading Specifications.................................................................................39

21 Package Handling Guidelines.......................................... .. .. .. ............................ ..........39

22 Processor Materials...................................................................................................40

23 Alphabetical Land Assignments...................................................................................48

24 Numerical Land Assignment.......................................................................................58

25 Signal Description (Sheet 1 of 9)................................................................................68

26 Processor Thermal Specifications................................................................................78

27 Thermal Profile 1......................................................................................................79

28 Thermal Profile 2......................................................................................................80

29 Thermal Profile 3......................................................................................................81

30 Thermal Profile 4......................................................................................................82

31 Thermal Profile 5......................................................................................................83

32 Thermal “Diode” Parameters using Diode Model............................................................88

33 Thermal “Diode” Parameters using Transistor Model......................................................89

34 Thermal Diode Interface............................................................................................89

35 GetTemp0() Error Codes ...........................................................................................92

36 Power-On Configuration Option Signals .......................................................................93

37 Fan Heatsink Power and Signal Specifications.............................................................102

38 Fan Heatsink Power and Signal Specifications.............................................................106

39 TMA Power and Signal Specifications.........................................................................113

40 TMA Set Points for 3-wire operation of BTX Type I and Type II Boxed

Static and Transient Tolerance .............................................................................22

Overshoot Specifications................... .. .. .. ........................... ... .. ........................... ..24

Processors.............................................................................................................115

6 Datasheet

Revision History

Revision

Number

Description Date

-001 • Initial release July 2006

-002 • Corrected L1 Cache information September 2006

•Added Intel

Core™2 Duo Desktop Processor E4300 information

• Updated Table 5, DC Voltage and Current Specification

• Added Section 2.3, PECI DC Specifications

-003

• Updated Section 5.3, Platform Environment Control Interface (PECI)

• Updated Section 7.1.2, Boxed Processor Fan Heatsink Weight

• Updated Table 37, Fan Heatsink Power and Signal Specifications

• Added Section 7.3.2, Fan Speed Control Operation Intel X6800 Only) and Section 7.3.3, Fan Speed Control Operation (Intel

Core2 Extreme Processor

Core2 Duo Desktop

January 2007

Processor E6000 and E4000 series Only)

-004 • Added Intel

•Added Intel

Core™2 Duo Desktop Processor E6420, E6320, and E4400 information April 2007

Core™2 Duo Desktop Processor E6850, E6750, E6550, E6540, and E4500

information.

-005

• Added specifications for 1333 MHz FSB.

July 2007

• Added support for Extended Stop Grant State, Extended Stop Grant Snoop States.

• Added new thermal profile table and figure.

-006 • Added Intel

-007 • Added Intel

-008 • Added Intel

Core™2 Duo Desktop Processor E4400 with CPUID = 065Dh. August 2007

Core™2 Duo Desktop Processor E4600 October 2007

Core™2 Duo Desktop Processor E4700 March 2008

Datasheet 7

8 Datasheet

Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Series Features

• Available at 2.93 GHz (Intel Core™2 Extreme processor X6800 only)

• Available at 3.00 GHz, 2.66 GHz, 2.40 GHz,

2.33 GHz, 2.13 GHz, and 1.86 GHz (Intel Core™2 Duo desktop processor E6850, E6750, E6700, E6600, E6540, E6540, E6420, E6400, E6320, and E6300 only)

• Available at 2.40 GHz, 2.20 GHz, 2.00 GHz, and

1.80 GHz and (Intel Core™2 Duo desktop processor E4700, E4600, E4500, E4400, and E4300 only)

• Enhanced Intel SpeedStep

• Supports Intel

• Supports Intel Core™2 Extreme processor X6800 and Intel Core™2 Duo desktop processor E6000 series only)

• Supports Execute Disable Bit capability

• Supports Intel (Intel® TXT) (Intel Core2 Duo desktop processors E6850, E6750, and E6550 only)

• FSB frequency at 1333 MHz (Intel Core2 Duo desktop processors E6850, E6750, E6550, and E6540 only)

• FSB frequency at 1066 MHz (Intel Core™2 Extreme processor X6800 and Intel Core™2 Duo desktop processor E6700, E6600, E6420, E6400, E6320, and E6300 only)

• FSB frequency at 800 MHz (Intel Core™2 Duo desktop processor E4000 series only)

64 architecture

Virtualization Technology (Intel

Trusted Execution Technology

Technology

• Binary compatible with applications running on previous members of the Intel microprocessor line

• Advance Dynamic Execution

• Very deep out-of-order execution

• Enhanced branch prediction

• Optimized for 32-bit applications running on advanced 32-bit operating systems

• Two 32-KB Level 1 data caches

•4MB Intel Extreme processor X6800 and Intel Core™2 Duo desktop processor E6850, E6750, E6700, E6540, E6540, E6600, E6420, and E6320, only)

•2MB Intel Duo desktop processor E6400, E6300, E4700, E4600, E4500, E4400, and E4300 only)

•Intel

• Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance

• Power Management capabilities

• System Management mode

• Multiple low-power states

• 8-way cache associativity provides improved cache hit rate on load/store operations

• 775-land Package

Advanced Smart Cache (Intel Core™2

Advanced Digital Media Boost

The Intel Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000, E4000 series deliver Intel's advanced, powerful processors for desktop PCs. The processor is designed to deliver performance across applications and usages where end-users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and multitasking user environments.

Intel

64 architecture enables the processor to execute operating systems and applications written to

take advantage of the Intel 64 architecture. The processor supporting Enhanced Intel SpeedStep

technology allows tradeoffs to be made between performance and power consumption. The Intel Core™2 Extreme processor X6800 and Intel

Core™2 Duo desktop processor E6000, E4000 series also include the Execute Disable Bit capability. This feature, combined with a supported operating system, allows memory to be marked as executable or non-executable.

The Intel Core™2 Extreme processor X6800 and Intel support Intel

Virtualization T echnology. Virtualization Technology provides silicon-based functionality

Core™2 Duo desktop processor E6000 series

that works together with compatible Virtual Machine Monitor (VMM) software to improve on softwareonly solutions.

The Intel Core™2 Duo desktop processors E6850, E6750, and E6550 support Intel Execution Technology (Intel

TXT). Intel® Trusted Execution Technology (Intel® TXT) is a security

Trusted

technology.

§ §

Datasheet 9

10 Datasheet

Introduction

1 Introduction

The Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000 and E4000 series combine the performance of the previous generation of desktop products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems. These processors are 64-bit processors that maintain compatibility with IA-32 software.

The Intel processor E6000 and E4000 series use Flip-Chip Land Grid Array (FC-LGA6) package technology, and plugs into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the LGA775 socket.

Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop

Note: In this document, unless otherwise specified, the Intel

processor E6000 series refers to Intel E6550, E6540, E6700, E6600, E6420, E6400, E6320, and E6300. The Intel Duo desktop processor E4000 series refers to Intel

Core™2 Duo desktop processors E6850, E6750,

Core™2 Duo desktop processor

E4700, E4600, E4500, E4400, and E4300.

Note: In this document, unless otherwise specified, the Intel

X6800 and Intel

Core™2 Duo desktop processor E6000 and E4000 series are referred

to as “processor.” The processors support several Advanced Technologies including the Execute Disable

Bit, Intel

64 architecture, and Enhanced Intel SpeedStep® Technology. The Intel Core™2 Duo desktop processor E6000 series and Intel Core™2 Extreme processor X6800 support Intel® Virtualization Technology (Intel VT). In addition, the Intel Core™2 Duo desktop processors E6850, E6750, and E6550 support Intel Execution Technology (Intel

The processor's front side bus (FSB) uses a split-transaction, deferred reply protocol like the Intel

Pentium® 4 processor. The FSB uses Source-Synchronous T ransfer (S ST)

TXT).

of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "doubleclocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 10.7 GB/s.

Intel has enabled support components for the processor including heatsink, heatsink retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling.

Core™2 Duo desktop

Core™2

Core™2 Extreme processor

Trusted

The processor includes an address bus power-down capability which removes power from the address and data signals when the FSB is not in use. This feature is always enabled on the processor.

Datasheet 11

1.1 Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

The phrase “Front Side Bus” refers to the interface between the processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O.

1.1.1 Processor Terminology

Commonly used terms are explained here for clarification:

• Intel LGA6 package with a 4 MB L2 cache.

• Intel E6700, E6600, E6420, and E6320, — Dual core processor in the FC-LGA6 package with a 4 MB L2 cache.

• Intel E4500, E4400, and E4300— Dual core processor in the FC-LGA6 package with a 2MB L2 cache.

• Processor — For this document, the term processor is the generic form of the Intel® Core™2 Duo desktop processor E6000 and E4000 series and the Intel® Core™2 Extreme processor X6800. The processor is a single package that contains one or more execution units.

• Keep-out zone — The area on or near the processor that system design can not use.

• Processor core — Processor core die with integrated L2 cache.

• LGA775 socket — The processors mate with the system board through a surface mount, 775-land, LGA socket.

• Integrated heat spreader (IHS) —A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface.

• Retention mechanism (RM) — Since the LGA775 socket does not include any mechanical features for heatsink attach, a retention mechanism is required. Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket.

• FSB (Front Side Bus) — The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB.

• Storage conditions — Refers to a non-operational state. The processor may be installed in a platform, in a tray , or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks. Upon exposure to “free air”(i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.

Core™2 Extreme processor X6800 — Dual core processor in the FC-

Core™2 Duo desktop processor E6850, E6750, E6550, E6540,

Core™2 Duo desktop processor E6400, E6300, E4700, E4600,

Introduction

12 Datasheet

Introduction

• Functional operation — Refers to normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical and thermal are satisfied.

• Execute Disable Bit — Allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the over all security of the system. See the Intel

Architecture Software Developer's Manual for more detailed

information.

• Intel® 64 Architecture — An enhancement to Intel's IA-32 architecture, allowing the processor to execute operating systems and applications written to take advantage of Intel 64 architecture. Further details on Intel 64 architecture and programming model can be found in the Intel

Extended Memory 64 Technology

Software Developer Guide at http://www.intel.com/technology/intel64/index.htm.

• Enhanced Intel SpeedStep

Technology — Enhanced Intel Speedstep®

technology allows trade-offs to be made between performance and power consumptions, based on processor utilization. This may lower average power consumption (in conjunction with OS support).

• Intel® Virtualization Technology (Intel VT) — Intel Virtualization Technology provides silicon-based functionality that works together with compatible Virtual Machine Monitor (VMM) software to improve upon software-only solutions. Because this virtualization hardware provides a new architecture upon which the operating system can run directly, it removes the need for binary translation. Thus, it helps eliminate associated performance overhead and vastly simplifies the design of the VMM, in turn allowing VMMs to be written to common standards and to be more robust. See the Intel

Virtualization Technology Specification for the IA-32 Intel®

Architecture for more details.

• Intel® Trusted Execution Technology (Intel® TXT)— Intel® T rusted Ex ecution Technology (Intel requires for operation a computer system with Intel

TXT) is a security technology under development by Intel and

Virtualization Technology, a Intel Trusted Execution Technology-enabled Intel processor, chipset, BIOS, Authenticated Code Modules, and an Intel or other Intel Trusted Execution T echnology compatible measured virtual machine monitor. In addition, Intel T rusted Execution Technology requires the system to contain a TPMv1.2 as defined by the Trusted Computing Group and specific software for some uses.

Datasheet 13

1.2 References

Material and concepts available in the following documents may be beneficial when reading this document.

Table 1. Reference Documents

Core™2 Extreme Processor X6800 and Intel® Core™2 Duo

Intel Desktop Processor E6000 and E4000 Series Specification Update

Intel

Core™2 Duo Processor and Intel® Pentium® Dual Core

Processor Thermal and Mechanical Design Guidelines

Intel

Pentium® D Processor, Intel® Pentium® Processor Extreme Edition, Intel Processor X6800 Thermal and Mechanical Design Guidelines

Balanced Technology Extended (BTX) System Design Guide www.formfactors.org Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design

Guidelines For Desktop LGA775 Socket

LGA775 Socket Mechanical Design Guide

Intel Architecture

Intel the IA-32 Intel® Architecture

Intel

Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide

Pentium® 4 Processor, Intel® Core™2 Duo Extreme

Virtualization Technology Specification for the IA-32 Intel®

Trusted Exectuion Technology (Intel® TXT) Specification for

64 and IA-32 Intel Architecture Software Developer's Manuals

Introduction

Document Location

www.intel.com/design/ processor/specupdt/

313279.htm http://www.intel.com/

design/processor/ designex/317804.htm

http://www.intel.com/ design/pentiumXE/ designex/306830.htm

http://www.intel.com/ design/processor/ applnots/313214.htm

http://intel.com/design/ Pentium4/guides/

302666.htm http://www.intel.com/

technology/computing/ vptech/index.htm

http://www.intel.com/ technology/security/

http://www.intel.com/ products/processor/ manuals/

§ §

14 Datasheet

Electrical Specifications

2 Electrical Specifications

This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided.

2.1 Power and Ground Lands

The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to V connected to a system ground plane. The processor V voltage determined by the Voltage IDentification (VID) lands.

The signals denoted as VTT provide termination for the front side bus and power to the I/O buffers. A separate supply must be implemented for these lands, that meets the VTT specifications outlined in Table 5.

2.2 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings. This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate. Larger bulk storage (C current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 5. Failure to do so can result in timing violations or reduced lifetime of the component.

), such as electrolytic or aluminum-polymer capacitors, supply

BULK

, while all VSS lands must be

lands must be supplied the

2.2.1 VCC Decoupling

VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications. This includes bulk capacitance with low effective series resistance (ESR) to keep the voltage rail within specifications during large swings in load current. In addition, ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity. Consult the

Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket.

2.2.2 VTT Decoupling

Decoupling must be provided on the motherboard. Decoupling solutions must be sized to meet the expected load. T o insure complian ce with the specifications, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors.

Datasheet 15

2.2.3 FSB Decoupling

The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation.

2.3 Voltage Identification

The Voltage Identification (VID) specification for the processor is defined by the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage

to be delivered to the processor V specifications). Refer to Table 13 for the DC specifications for these signals. Voltages for each processor frequency is provided in Table 5.

Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings. This is reflected by the VID Range values provided in Table 5. Refer to the Intel

Desktop Processor E6000 and E4000 Series and Intel X6800 Specification Update for further details on specific valid core frequency and VID

values of the processor. Note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Extended HALT State).

pins (see Chapter 2.6.3 for VCC overshoot

Electrical Specifications

Core™2 Extreme Processor

Core™2 Duo

The processor uses six voltage identification signals, VID[6:1], to support automatic selection of power supply voltages. Table 2 specifies the voltage level corresponding to the state of VID[6:1]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is empty (VID[6:1] = 111111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. The Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket defines VID [7:0], VID7 and VID0 are not used on the processor; VID0 and VID7 are strapped to V and VID7 must be connected to the VR controller for compatibility with future

on the processor package. VID0

processors. The processor provides the ability to operate while transitioning to an adjacent VID and

its associated processor core voltage (V line. It should be noted that a low-to-high or high-to-low voltage state change may

). This will represent a DC shift in the load

result in as many VID transitions as necessary to reach the target core voltage. Transitions above the specified VID are not permitted. Table 5 includes VID step sizes and DC shift ranges. Minimum and maximum v oltages must be maintained as shown in

Table 6 and Figure 1 as measured across the VCC_SENSE and VSS_SENSE lands.

The VRM or VRD used must be capable of regulating its output to the value defined by the new VID. DC specifications for dynamic VID transitions are included in Table 5 and

Table 6. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery

Design Guidelines For Desktop LGA775 Socket for further details.

16 Datasheet

Electrical Specifications

Table 2. Voltage Identification Definition

VID6 VID5 VID4 VID3 VID2 VID1 VID (V) VID6 VID5 VID4 VID3 VID2 VID1 VID (V)

1111010.8500 0111101.2375

1111000.8625 0111011.2500

1110110.8750 0111001.2625

1110100.8875 0110111.2750

1110010.9000 0110101.2875

1110000.9125 0110011.3000

1101110.9250 0110001.3125

1101100.9375 0101111.3250

1101010.9500 0101101.3375

1101000.9625 0101011.3500

1100110.9750 0101001.3625

1100100.9875 0100111.3750

1100011.0000 0100101.3875

1100001.0125

1011111.0250 0100001.4125

1011101.0375 0011111.4250

1011011.0500 0011101.4375

1011001.0625 0011011.4500

1010111.0750 0011001.4625

1010101.0875 0010111.4750

1010011.1000 0010101.4875

1010001.1125 0010011.5000

1001111.1250 0010001.5125

1001101.1375 0001111.5250

1001011.1500 0001101.5375

1001001.1625 0001011.5500

1000111.1750 0001001.5625

1000101.1875 0000111.5750

1000011.2000 0000101.5875

1000001.2125 0000011.6000

0111111.2250 000000 OFF

0 1 0 0 0 11.4000

Datasheet 17

2.4 Market Segment Identification (MSID)

The MSID[1:0] signals may be used as outputs to determine the Market Segment of the processor. Table 3 provides details regarding the state of MSID[1:0]. A circuit can be used to prevent 130 W TDP processors from booting on boards optimized for 65 W TDP.

Electrical Specifications

Table 3. Market Segment Selection Truth Table for MSID[1:0]

MSID1 MSID0 Description

Intel

01Reserved 10Reserved 11Reserved

NOTES:

The MSID[1:0] signals are provided to indicate the Market Segment for the processor

Core™2 Duo desktop processor E6000 and E4000 series and the

Intel

Core™2 Extreme processor X6800

1, 2, 3, 4

and may be used for future processor compatibility or for keying. Circuitry on the motherboard may use these signals to identify the processor installed.

2. These signals are not connected to the processor die.

3. A logic 0 is achieved by pulling the signal to ground on the package.

4. A logic 1 is achieved by leaving the signal as a no connect on the package.

2.5 Reserved, Unused, and TESTHI Signals

All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, V

, or to any other signal (including each other) can result in component malfunction

or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands.

In a system level design, on-die termination has been included by the processor to allow signals to be terminated within the processor silicon. Most unused GTL+ inputs should be left as no connects as GTL+ termination is provided on the processor silicon. However, see Table 8 for details on GTL+ signals that do not include on-die termination.

Unused active high inputs, should be connected through a resistor to ground (V Unused outputs can be left unconnected, however this may interfere with some TAP

functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ± 20% of the impedance of the motherboard trace for front side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the same value as the on-die termination resistors (R

). For details, see Table 14.

TAP and CMOS signals do not include on-die termination. Inputs and used outputs must be terminated on the motherboard. Unused outputs may be terminated on the motherboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing.

All TESTHI[13:0] lands should be individually connected to V that matches the nominal trace impedance.

18 Datasheet

via a pull-up resistor

Electrical Specifications

The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group:

• TESTHI[1:0]

• TESTHI[7:2]

• TESTHI8/FC42 – cannot be grouped with other TESTHI signals

• TESTHI9/FC43 – cannot be grouped with other TESTHI signals

• TESTHI10 – cannot be grouped with other TESTHI signals

• TESTHI11 – cannot be grouped with other TESTHI signals

• TESTHI12/FC44 – cannot be grouped with other TESTHI signals

• TESTHI13 – cannot be grouped with other TESTHI signals

However, utilization of boundary scan test will not be functional if these lands are connected together. For optimum noise margin, all pull-up resistor values used for TESTHI[13:0] lands should have a resistance value within ± 20% of the impedance of the board transmission line traces. For example, if the nominal trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω should be used.

2.6 Voltage and Current Specification

2.6.1 Absolute Maximum and Minimum Ratings

Table 4 specifies absolute maximum and minimum ratings only and lie outside the

functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected.

At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded.

Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields.

Datasheet 19

Table 4. Absolute Maximum and Minimum Ratings

Symbol Parameter Min Max Unit Notes

STORAGE

NOTES:

1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied.

2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.

3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-term reliability of the device. For functional operation, refer to the processor case temperature specifications .

4. This rating applies to the processor and does not include any tray or packaging.

5. Failure to adhere to this specification can affect the long term reliability of the processor.

Core voltage with respect to V

FSB termination voltage with respect to V

Processor case temperature

Processor storage temperature –40 85 °C

Electrical Specifications

–0.3 1.55 V -

See

Chapter 5

See

Chapter 5

°C -

1, 2

3, 4, 5

2.6.2 DC Voltage and Current Specification

Table 5. Voltage and Current Specifications

Symbol Parameter Min Typ Max Unit Notes

VID Range VID 0.8500 — 1.5 V

CC_BOOT

Processor Number (4 MB L2 Cache)

E6850 E6750 E6700 E6600 E6550 E6540 E6420 E6320

Processor Number (4 MB L2 Cache)

X6800

Processor Number (2 MB L2 Cache)

E6400 E6300 E4700

E4600,

E4500 E4400 E4300

Default VCC voltage for initial power up — 1.10 — V

for

775_VR_CONFIG_06

3.00 GHz

2.66 GHz

2.40 GHz

2.33 GHz

2.13 GHz

1.86 GHz

VCC for 775_VR_CONFIG_05B

2.93 GHz

for

775_VR_CONFIG_06

2.13 GHz

1.86 GHz

2.60 GHz

2.40 GHz

2.20 GHz

2.00 GHz

1.80 GHz

Refer to Table 6 and

Figure 1

1, 2

4, 5, 6

20 Datasheet

Electrical Specifications

Table 5. Voltage and Current Specifications

Symbol Parameter Min Typ Max Unit Notes

CCPLL

VTT_OUT_LEFT and VTT_OUT_RIGHT I

CC_VCCPLL

CC_GTLREF

PLL V

Processor Number

775_VR_CONFIG_06

E6850 E6750 E6700 E6600 E6550

E6540 E6400/E6420 E6300/E6320

E4700

E4600

E4500

E4400

E4300

Processor Number

ICC for 775_VR_CONFIG_05B

X6800

FSB termination voltage (DC + AC specifications)

for

3.00 GHz

2.66 GHz

2.40 GHz

2.33 GHz

2.13 GHz

1.86 GHz

2.60 GHz

2.40 GHz

2.20 GHz

2.00 GHz

1.80 GHz

2.93 GHz

- 5% 1.50 + 5%

75 75 75 75 75

——

75 75 75 75 75 75 75 75

——

1.14 1.20 1.26 V

DC Current that may be drawn from VTT_OUT_LEFT and VTT_OUT_RIGHT per

pin ICC for VTT supply before VCC stable

for VTT supply after VCC stable

— — 580 mA

——

4.5

4.6 ICC for PLL land — — 130 mA ICC for GTLREF — — 200 μA

NOTES:

1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date.

2. Adh erence to the voltage specifications for the processor are required to ensure reliable processor operation.

3. Eac h processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep

Technology, or Extended HALT State).

4. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.3 and Table 2 for more information.

5. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.

6. Refer to Table 6 and Figure 1 for the minimum, typical, and maximum V processor should not be subjected to any V current.

7. I

8. V at the land.

specification is based on the V

CC_MAX

must be provided via a separate voltage source and not be connected to VCC. This specification is meas ured

and ICC combination wherein VCC exceeds V

loadline. Refer to Figure 1 for details.

CC_MAX

allowed for a given current. The

CC_MAX

for a given

9. Baseboard bandwidth is limited to 20 MHz.

10.This is maximum total current drawn from V the current coming from RTT (through the signal line). Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA77 5 Socket to determine the total I system. This parameter is based on design characterization and is not tested.

plane by only the processor. This specificat ion does not include

drawn by the

1, 2

Datasheet 21

Table 6. VCC Static and Transient Tolerance

Voltage Deviation from VID Setting (V)

ICC (A)

0 0.000 -0.019 -0.038

5 -0.007 -0.026 -0.046 10 -0.013 -0.033 -0.054 15 -0.020 -0.040 -0.061 20 -0.026 -0.048 -0.069 25 -0.033 -0.055 -0.077 30 -0.039 -0.062 -0.085 35 -0.046 -0.069 -0.092 40 -0.052 -0.076 -0.100 45 -0.059 -0.083 -0.108 50 -0.065 -0.090 -0.116 55 -0.072 -0.097 -0.123 60 -0.078 -0.105 -0.131 65 -0.085 -0.112 -0.139 70 -0.091 -0.119 -0.147 75 -0.098 -0.126 -0.154

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.6.3.

2. This table is intended to aid in reading discrete points on Figure 1.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details.

4. Adherence to this loadline specificatio n is required to ensure reliable processor operation.

Maximum Voltage

1.30 mΩ

Typical Voltage

1.425 mΩ

Electrical Specifications

1, 2, 3, 4

Minimum Voltage

1.55 mΩ

22 Datasheet

Electrical Specifications

Figure 1. VCC Static and Transient Tolerance

Icc [A]

Vcc Maximum

VID - 0.000

VID - 0.013

VID - 0.025

VID - 0.038

VID - 0.050

VID - 0.063

VID - 0.075

Vcc [V]

VID - 0.088

VID - 0.100

VID - 0.113

VID - 0.125

VID - 0.138

VID - 0.150

VID - 0.163

0 10203040506070

Vcc Typical

Vcc Minimum

NOTES:

1. The loadline spec ification includes both static and transient limits except for overshoot allowed as shown in Section 2.6.3.

2. This loadline s p ecification shows the deviation from the VID set point.

Datasheet 23

2.6.3 VCC Overshoot

The processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + V The time duration of the overshoot event must not exceed T maximum allowable time duration above VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.

OS_MAX

Electrical Specifications

is the maximum allowable overshoot voltage).

OS_MAX

is the

Table 7. V

Overshoot Specifications

Symbol Parameter Min Max Unit Figure N otes

OS_MAX

NOTES:

1. Adherence to these specifications is required to ensure reliable processor operation.

Magnitude of VCC overshoot above VID — 50 mV 2 Time duration of VCC overshoot above VID — 25 μs 2

Figure 2. VCC Overshoot Example Waveform

Example Overshoot Waveform

VID + 0.050

Voltage [V]

VID - 0.000

0 5 10 15 20 25

Time [us]

TOS: Overshoot time above VID V

: Overshoot above VID

NOTES:

1. V

2. T

is measured overshoot voltage.

is measured time duration above VID.

2.6.4 Die Voltage Validation

Overshoot events on processor must meet the specifications in Table 7 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit.

24 Datasheet

Electrical Specifications

2.7 Signaling Specifications

Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Platforms implement a termination voltage level for GTL+ signals defined as V separate power planes for each processor (and chipset), separate V are necessary. This configuration allows for improved noise tolerance as processor frequency increases. Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families.

The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the motherboard (see Table 14 for GTLREF specifications). Termination resistors (R GTL+ signals are provided on the processor silicon and are terminated to V chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+ signals.

2.7.1 FSB Signal Groups

The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers, which use GTLREF[1:0] as a reference level. In this document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as well as the GTL+ I/O group when driving.

With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 8 identifies which signals are common clock, source synchronous, and asynchronous.

Table 8. FSB Signal Groups (Sheet 1 of 2)

Signal Group Type Signals

GTL+ Common Clock Input

GTL+ Common Clock I/O

Synchronous to BCLK[1:0]

BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY# ADS#, BNR#, BPM[5:0]#, BR0#, DBSY#, DRDY#,

HIT#, HITM#, LOCK#

. Because platforms implement

and V

supplies

. Intel

) for

Signals Associated Strobe

REQ[4:0]#, A[16:3]#

GTL+ Source Synchronous I/O

GTL+ Strobes

Datasheet 25

Synchronous to assoc. strobe

Synchronous to BCLK[1:0]

A[35:17]# D[15:0]#, DBI0# DSTBP0#, DSTBN0# D[31:16]#, DBI1# DSTBP1#, DSTBN1# D[47:32]#, DBI2# DSTBP2#, DSTBN2# D[63:48]#, DBI3# DSTBP3#, DSTBN3#

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

ADSTB0# ADSTB1#

Table 8. FSB Signal Groups (Sheet 2 of 2)

Signal Group Type Signals

CMOS

Open Drain Output FERR#/PBE#, IERR#, THERMTRIP#, TDO Open Drain Input/

Output FSB Clock Clock BCLK[1:0], ITP_CLK[1:0]

Power/Other

NOTES:

1. Refer to Section 4.2 for signal descriptions.

2. In processor systems where no debug port is implemented on the syst em board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.

3. The value of these signals durin g the active-to-inactive edge of RESET# defines the processor configuration options. See Section 6.1 for details.

4. PROCHOT# signal type is open drain output and CMOS input.

Table 9. Signal Characteristics

Electrical Specifications

A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, STPCLK#, PWRGOOD, TCK, TDI, TMS, TRST#, BSEL[2:0], VID[6:1]

PROCHOT#

VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA, GTLREF[1:0], COMP[8,3:0], RESERVED, TESTHI[13:0], VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE, VSS_MB_REGULATION, DBR#

, VTT_OUT_LEFT,

VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0]

Signals with R

A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, LOCK#, PROCHOT#, REQ[4:0]#, RS[2:0]#, TRDY#

Open Drain Signals

THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#, BR0#, TDO, FCx

NOTES:

1. Signals that do not have R

Table 10. Signal Reference Voltages

GTLREF VTT/2

BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#, TRDY#

NOTES:

1. Th ese signals also have hysteresis added to the reference voltage. See Table 12 for more

information.

Signals with No R

A20M#, BCLK[1:0], BSEL[2:0], COMP[8,3:0], IGNNE#, INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#, SMI#, STPCLK#, TESTHI[13:0], VID[6:1], GTLREF[1:0], TCK, TDI, TMS, TRST#, VTT_SEL, MSID[1:0]

, nor are actively driven to their high-voltage level.

A20M#, LINT0/INTR, LINT1/NMI, IGNNE#, INIT#, PROCHOT#, PWRGOOD TDI

, SMI#, STPCLK#, TCK1,

, TMS1, TRST#

26 Datasheet

Electrical Specifications

2.7.2 CMOS and Open Drain Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of the CMOS and Open Drain signals are required to be asserted/deasserted for at least four BCLKs in order for the processor to recognize the proper signal state. See Section 2.7.3 for the DC. See Section 6.2 for additional timing requirements for entering and leaving the low power states.

2.7.3 Processor DC Specifications

The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated.

Table 11. GTL+ Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

V V

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

3. The V

4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

5. V

6. Leakage to VSS with land held at VTT.

7. Leakage to VTT with land held at 300 mV.

Table 12. Open Drain and TAP Output Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

I I

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. VOH is determined by the value of the external pull-up resister to VTT.

3. Measured at VTT * 0.2.

4. For Vin between 0 and VOH.

Input Low Voltage -0.10 GTLREF – 0.10 V

Input High Voltage GTLREF + 0.10 V

Output High Voltage V

Output Low Current N/A

Input Leakage Current N/A ± 100 µA

Output Leakage

Current Buffer On Resistance 10 13 Ω

referred to in these specifications is the instantaneous VTT.

and VOH may experience excursions above VTT.

Output Low Voltage 0 0.20 V -

Output High Voltage VTT – 0.05 VTT + 0.05 V

Output Low Current 16 50 mA

Output Leakage Current N/A ± 200 µA

– 0.10 V

[(R

TT_MIN

N/A ± 100 µA

+ 0.10 V

TT_MAX

)+(2*R

ON_MIN

A-

)]

2, 3

4, 5, 3

5, 3

2 3 4

Datasheet 27

Table 13. CMOS Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

V V V

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

3. The V

4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

5. V

6. All outputs are open drain.

7. I

8. Leakage to VSS with land held at VTT.

9. Leakage to VTT with land held at 300 mV.

Input Low Voltage -0.10 VTT * 0.30 V

Input High Voltage VTT * 0.70 V

Output Low Voltage -0.10 VTT * 0.10 V

Output High Voltage 0.90 * V

Output Low Current 1.70 4.70 mA

Output High Current 1.70 4.70 mA

Input Leakage Current N/A ± 100 µA

Output Leakage Current N/A ± 100 µA

referred to in these specifications refers to instantaneous VTT.

and VOH may experience excursions above VTT.

is measured at 0.10 * V

is measured at 0.90 * V

TT. IOH

TTVTT

TT .

Electrical Specifications

+ 0.10 V

2, 3

3, 4, 5

3, 6, 5

3, 7 3, 7

8 9

2.7.3.1 GTL+ Front Side Bus Specifications

In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 9 for details on which GTL+ signals do not include on-die termination.

Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF. Table 14 lists the GTLREF specifications. The GTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits.

Table 14. GTL+ Bus Voltage Definitions

Symbol Parameter Min Typ Max Units Notes

GTLREF_PU GTLREF pull up resistor 124 * 0.99 124 124 * 1.01 Ω GTLREF_PD GTLREF pull down resistor 210 * 0.99 210 210 * 1.01 Ω R

COMP[3:0] COMP Resistance 49.40 49.90 50.40 Ω COMP8 COMP Resistance 24.65 24.90 25.15 Ω

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. GTLREF is to be generated from VTT by a voltage divider of 1% resistors (one divider for each GTLEREF land).

3. RTT is the on-die termination resistance measured at VTT/3 of the GTL+ output driver.

4. COMP resistance must be provided on the system board with 1% resistors. See the applicable platform design guide for implementation details. COMP[3:0] and COMP8 resistors are tied to V

Termination Resistance 45 50 55 Ω

3 4

28 Datasheet

Electrical Specifications

2.7.4 Clock Specifications

2.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor’s core frequency is a multiple of the BCLK[1:0] frequency. The processor bus r atio multiplier will be set at its default ratio during manufacturing. Refer to Table 15 for the processor supported ratios.

The processor uses a differential clocking implementation. For more information on the processor clocking, contact your Intel Field representative. Platforms using a CK505 Clock Synthesizer/Driver should comply with the specifications in Section 2.7.8. Platforms using a CK410 Clock Synthesizer/Driver should comply with the specifications in Section 2.7.9.

Table 15. Core Frequency to FSB Multiplier Configuration

Multiplication of

System Core

Frequency to FSB

Frequency

1/6 1.20 GHz 1.60 GHz 2.00 GHz 1/7 1.40 GHz 1.87 GHz 2.33 GHz 1/8 1.60 GHz 2.13 GHz 2.66 GHz -

1/9 1.80 GHz 2.40 GHz 3.00 GHz 1/10 2 GHz 2.66 GHz 3.33 GHz 1/11 2.2 GHz 2.93 GHz 3.66 GHz 1/12 2.4 GHz 3.20 GHz 4.00 GHz

NOTES:

1. Individual processors operate only at or below the rated frequency.

2. Lis ted frequencies are not necessarily committed production frequencies.

Core Frequency

(200 MHz BCLK/

800 MHz FSB)

Core Frequency

(266 MHz BCLK/

1066 MHz FSB)

Core Frequency

(333 MHz BCLK/

1333 MHz FSB)

2.7.6 FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 16 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency.

The Intel Core2 Duo desktop processors E6850, E6750, E6550, and E6540 operate at 1333 MHz (selected by the 333 MHz BCLK[2:0] frequency). The Intel Core2 Duo desktop processors E6700, E6600, E6420, E6400, E6320, and E6300 operate at 1066 MHz (selected by the 266 MHz BCLK[2:0] frequency). The Intel Core2 Extreme processor X6800 operates at a 1066 MHz FSB frequency (selected by a 266 MHz BCLK[1:0] frequency). The Intel Core2 Duo desktop processors E4700, E4600, E4500, E4400 and E4300 operate at a 800 MHz FSB frequency (selected by a 200 MHz BCLK[1:0] frequency).

Notes

1, 2

Datasheet 29

Electrical Specifications

Table 16. BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2 BSEL1 BSEL0 FSB Frequency

L L L 266 MHz LL HRESERVED LH HRESERVED

L H L 200 MHz HH LRESERVED HH HRESERVED HL HRESERVED H L L 333 MHz

2.7.7 Phase Lock Loop (PLL) and Filter

An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is used for the PLL. Refer to Table 5 for DC specifications.

2.7.8 BCLK[1:0] Specifications (CK505 based Platforms)

Table 17. Front Side Bus Differential BCLK Specifications

Symbol Parameter Min Typ Max Unit Figure Notes

V V

CROSS(abs)

ΔV

CROSS

SWING

Cpad Pad Capacitance .95 1.2 1.45 pF

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. "Steady state" voltage, not including overshoot or undershoot.

3. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1.

4. V

Havg

5. Th e crossing point must meet the absolute and relative crossing point specifications simultaneously.

6. Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as the absolute value of the minimum voltage.

7. Measurement taken from differential waveform.

8. Cpad includes die capacitance only. No package parasitics are included.

Input Low Voltage -0.30 N/A N/A V 3

Input High Voltage N/A N/A 1.15 V 3 Absolute Crossing Point 0.300 N/A 0.550 V 3, 4 Range of Crossing Points N/A N/A 0.140 V 3, 4 Overshoot N/A N/A 1.4 V 3 Undershoot -0.300 N/A N/A V 3 Differential Output Swing 0.300 N/A N/A V 5 Input Leakage Current -5 N/A 5 μA

is the statistical average of the VH measured by the oscilloscope.

3, 4, 5

30 Datasheet

+ 88 hidden pages

Intel CORE 2 DUO E4000, CORE 2 DUO E6000, CORE 2 EXTREME X6800 User Manual

Contents

Figures

Tables

Revision History

Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Series Features

1 Introduction

1.1 Terminology

1.1.1 Processor Terminology

1.2 References

Table 1. Reference Documents

2 Electrical Specifications

2.1 Power and Ground Lands

2.2 Decoupling Guidelines

2.2.1 VCC Decoupling

2.2.2 VTT Decoupling

2.2.3 FSB Decoupling

2.3 Voltage Identification

Table 2. Voltage Identification Definition

2.4 Market Segment Identification (MSID)

2.5 Reserved, Unused, and TESTHI Signals

2.6 Voltage and Current Specification

2.6.1 Absolute Maximum and Minimum Ratings

Table 4. Absolute Maximum and Minimum Ratings

2.6.2 DC Voltage and Current Specification

Table 5. Voltage and Current Specifications

Table 6. VCC Static and Transient Tolerance

Figure 1. VCC Static and Transient Tolerance

2.6.3 VCC Overshoot

Figure 2. VCC Overshoot Example Waveform

2.6.4 Die Voltage Validation

2.7 Signaling Specifications

2.7.1 FSB Signal Groups

Table 8. FSB Signal Groups (Sheet 1 of 2)

Table 9. Signal Characteristics

Table 10. Signal Reference Voltages

2.7.2 CMOS and Open Drain Signals

2.7.3 Processor DC Specifications

Table 11. GTL+ Signal Group DC Specifications

Table 12. Open Drain and TAP Output Signal Group DC Specifications

Table 13. CMOS Signal Group DC Specifications

2.7.3.1 GTL+ Front Side Bus Specifications

Table 14. GTL+ Bus Voltage Definitions

2.7.4 Clock Specifications

2.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

Table 15. Core Frequency to FSB Multiplier Configuration

2.7.6 FSB Frequency Select Signals (BSEL[2:0])

Table 16. BSEL[2:0] Frequency Table for BCLK[1:0]

2.7.7 Phase Lock Loop (PLL) and Filter

2.7.8 BCLK[1:0] Specifications (CK505 based Platforms)

Table 17. Front Side Bus Differential BCLK Specifications