Intel CORE 2 DUO E4000, CORE 2 DUO E6000, CORE 2 EXTREME X6800 User Manual

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Intel® Core™2 Extreme Processor

X6800 Desktop Processor E6000 E4000

Datasheet

and Intel® Core™2 Duo

and

Series

—on 65 nm Process in the 775-land LGA Package and supporting Intel® 64

Architecture and supporting Intel

March 2008

Virtualization Technology

Document Number: 313278-008

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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "un defined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future ro admaps. See www.intel.com/products/ processor_number for details.

64 requires a computer system with a processor , chipset, BIOS, oper ating system, device drivers, and applications enabled for Intel 64. Processor

Intel will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or consult with your system vendor for more information.

No computer system can provide absolute security under all conditions. Intel development by Intel and req u ir es f or operation a computer system with In te l Intel processor, chipset, BIOS, Authenticated Code Modules, and an Intel or other Intel Trusted Execution Technology compatible measured virtual machine monitor . In addition, Intel Trusted Execution Technology requires the system to contain a TPMv1.2 as defined by the Trusted Computing Group and specific software for some uses.

±Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or ot he r be ne fit s wi ll vary depending on hardwa re and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

The Intel known as errata which may cause the product to deviate from published specifications.

Core™2 Duo desktop processor E6000 and E4000 series and Intel® Core™2 Extreme processor X6800 may contain design defects or errors

Trusted Execution Technology (Intel® TXT) is a security technology under

Virtualization Technology, a Intel Trusted Execution Technology-enabled

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, Intel Core, Core Inside, Intel Inside, Intel Leap ahead, Intel SpeedStep, and the Intel logo are trademarks of Intel Corporation in the U.S.

2 Datasheet

1Introduction............................................................................................................11

1.1 Terminology .....................................................................................................12

1.1.1 Processor Terminology............................................................................12

1.2 References.......................................................................................................14

2 Electrical Specifications...........................................................................................15

2.1 Power and Ground Lands....................................................................................15

2.2 Decoupling Guidelines ........................................................................................15

2.2.1 VCC Decoupling .....................................................................................15

2.2.2 Vtt Decoupling.......................................................................................15

2.2.3 FSB Decoupling......................................................................................16

2.3 Voltage Identification.........................................................................................16

2.4 Market Segment Identification (MSID) .................................. .. .. ...........................18

2.5 Reserved, Unused, and TESTHI Signals ................................................................18

2.6 Voltage and Current Specification........................................................................19

2.6.1 Absolute Maximum and Minimum Ratings ..................................................19

2.6.2 DC Voltage and Current Specification.................................................. .. .. ..20

2.6.3 V

2.6.4 Die Voltage Validation............................................................ ... .. ............24

2.7 Signaling Specifications............................................ .. ............................ .. ..........25

2.7.1 FSB Signal Groups..................................................................................25

2.7.2 CMOS and Open Drain Signals .................................................................27

2.7.3 Processor DC Specifications .....................................................................27

2.7.4 Clock Specifications................................................................................29

2.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking............................29

2.7.6 FSB Frequency Select Signals (BSEL[2:0]).................................................29

2.7.7 Phase Lock Loop (PLL) and Filter..............................................................30

2.7.8 BCLK[1:0] Specifications (CK505 based Platforms) ............. .. ...................... 30

2.7.9 BCLK[1:0] Specifications (CK410 based Platforms) ............. .. ...................... 32

2.8 PECI DC Specifications.......................................................................................33

3 Package Mechanical Specifications ..........................................................................35

3.1 Package Mechanical Drawing...................... .........................................................35

3.1.1 Processor Component Keep-Out Zones......................................................39

3.1.2 Package Loading Specifications .......................... .. ... .. .. .............................39

3.1.3 Package Handling Guidelines.............................. .. ... .. ...............................39

3.1.4 Package Insertion Specifications.......................................... .. .. ... ..............40

3.1.5 Processor Mass Specification....................................................................40

3.1.6 Processor Materials.................................................................................40

3.1.7 Processor Markings.................................................................................40

3.1.8 Processor Land Coordinates.....................................................................43

4 Land Listing and Signal Descriptions .......................................................................45

4.1 Processor Land Assignments...............................................................................45

4.2 Alphabetical Signals Reference............................................................................68

5 Thermal Specifications and Design Considerations ..................................................77

5.1 Processor Thermal Specifications.........................................................................77

5.1.1 Thermal Specifications............................................................................77

5.1.2 Thermal Metrology .................................................................................84

5.2 Processor Thermal Features................................................................................84

5.2.1 Thermal Monitor.....................................................................................84

5.2.2 Thermal Monitor 2..................................................................................85

5.2.3 On-Demand Mode ..................................................................................86

Overshoot ............................................... ........................................24

2.7.3.1 GTL+ Front Side Bus Specifications .............................................28

Datasheet 3

5.2.4 PROCHOT# Signal ..................................................................................87

5.2.5 THERMTRIP# Signal............................................................. ...................87

5.3 Thermal Diode...................................................................................................88

5.4 Platform Environment Control Interface (PECI)......................................................90

5.4.1 Introduction...........................................................................................90

5.4.1.1 Key Difference with Legacy Diode-Based Thermal

Management ............................................................................90

5.4.2 PECI Specifications .................................................................................92

5.4.2.1 PECI Device Address................................... .. .. ...........................92

5.4.2.2 PECI Command Support.............................. .. .............................92

5.4.2.3 PECI Fault Handling Requirements...............................................92

5.4.2.4 PECI GetTemp0() Error Code Support ..........................................92

6Features..................................................................................................................93

6.1 Power-On Configuration Options..........................................................................93

6.2 Clock Control and Low Power States......................... .. ........................... ... ............93

6.2.1 Normal State .........................................................................................94

6.2.2 HALT and Extended HALT Powerdown States..............................................94

6.2.2.1 HALT Powerdown State.......................... .. ... ...............................94

6.2.2.2 Extended HALT Powerdown State ................................................95

6.2.3 Stop Grant and Extended Stop Grant States...............................................95

6.2.3.1 Stop Grant State..................................................................... ..95

6.2.3.2 Extended Stop Grant State.........................................................96

6.2.4 Extended HALT State, HALT Snoop State, Extended Stop Grant Snoop

State, and Stop Grant Snoop State ...........................................................96

6.2.4.1 HALT Snoop State, Stop Grant Snoop State ..................................96

6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop

State.......................................................................................96

6.3 Enhanced Intel

SpeedStep® Technology .............................................................96

7 Boxed Processor Specifications................................................................................99

7.1 Mechanical Specifications..................................................................................100

7.1.1 Boxed Processor Cooling Solution Dimensions...........................................100

7.1.2 Boxed Processor Fan Heatsink Weight .....................................................101

7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip

Assembly.............................................................................................101

7.2 Electrical Requirements ............................................ .. .. .. ............................ .. ....101

7.2.1 Fan Heatsink Power Supply.............................. ............................ .. .. ......101

7.3 Thermal Specifications........................... .. .. ............................ .. .. .......................103

7.3.1 Boxed Processor Cooling Requirements....................................................103

7.3.2 Fan Speed Control Operation (Intel

Core2 Extreme Processor

X6800 Only) ........................................................................................105

7.3.3 Fan Speed Control Operation (Intel® Core2 Duo Desktop Processor

E6000 and E4000 Series Only) .......................... .....................................105

8 Balanced Technology Extended (BTX) Boxed Processor Specifications...................107

8.1 Mechanical Specifications..................................................................................108

8.1.1 Balanced Technology Extended (BTX) Type I and Type II Boxed Processor

Cooling Solution Dimensions ..................................................................108

8.1.2 Boxed Processor Thermal Module Assembly Weight ...................................110

8.1.3 Boxed Processor Support and Retention Module (SRM) ..............................111

8.2 Electrical Requirements ............................................ .. .. .. ............................ .. ....112

8.2.1 Thermal Module Assembly Power Supply..................................................112

8.3 Thermal Specifications........................... .. .. ............................ .. .. .......................114

8.3.1 Boxed Processor Cooling Requirements....................................................114

8.3.2 Variable Speed Fan........................................................................... ....114

9 Debug Tools Specifications ....................................................................................117

9.1 Logic Analyzer Interface (LAI) ...........................................................................117

9.1.1 Mechanical Considerations .....................................................................117

9.1.2 Electrical Considerations........................................................................117

4 Datasheet

Figures

1VCC Static and Transient Tolerance.............................................................................23

3 Differential Clock Waveform ......................... .. .. ............................ .. .. .........................31

4 Differential Clock Crosspoint Specification ...................................................................31

5 Differential Measurements....................................... .. .. .. ........................... ... .. ............31

6 Differential Clock Crosspoint Specification ...................................................................32

7 Processor Package Assembly Sketch...........................................................................35

8 Processor Package Drawing Sheet 1 of 3................................. ....................................36

9 Processor Package Drawing Sheet 2 of 3................................. ....................................37

10 Processor Package Drawing Sheet 3 of 3......................................................... .. .. .. ......38

11 Processor Top-Side Markings Example for the Intel 12 Processor Top-Side Markings Example for the Intel 13 Processor Top-Side Markings Example for the Intel 14 Processor Top-Side Markings Example for the Intel 15 Processor Top-Side Markings for the Intel

16 Processor Land Coordinates and Quadrants (Top View) .................................................43

17 land-out Diagram (Top View – Left Side).....................................................................46

18 land-out Diagram (Top View – Right Side)...................................................................47

19 Thermal Profile 1 .....................................................................................................79

20 Thermal Profile 2 .....................................................................................................80

21 Thermal Profile 3 .....................................................................................................81

22 Thermal Profile 4 .....................................................................................................82

23 Thermal Profile 5 .....................................................................................................83

24 Case Temperature (TC) Measurement Location ...... ......................................................84

25 Thermal Monitor 2 Frequency and Voltage Ordering......................................................86

26 Processor PECI Topology................................ .. .. ............................ ...........................90

27 Conceptual Fan Control on PECI-Based Platforms .........................................................91

28 Conceptual Fan Control on Thermal Diode-Based Platforms............................................91

29 Processor Low Power State Machine ...........................................................................94

30 Mechanical Representation of the Boxed Processor ................. ......................................99

31 Space Requirements for the Boxed Processor (Side View)............................................ 100

32 Space Requirements for the Boxed Processor (Top View)............................................. 100

33 Space Requirements for the Boxed Processor (Overall View)......................... ............... 101

34 Boxed Processor Fan Heatsink Power Cable Connector Description................................ 102

35 Baseboard Power Header Placement Relative to Processor Socket................................. 103

36 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) .... .. .. .. .. .. .. . 104

37 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)................. 104

38 Boxed Processor Fan Heatsink Set Points................................................................... 106

39 Mechanical Representation of the Boxed Processor with a Type I TMA ........................... 109

40 Mechanical Representation of the Boxed Processor with a Type II TMA .......................... 110

41 Requirements for the Balanced Technology Extended (BTX) Type I Keep-out 42 Requirements for the Balanced Technology Extended (BTX) Type II Keep-out

43 Assembly Stack Including the Support and Retention Module ....................................... 113

44 Boxed Processor TMA Power Cable Connector Description............................................ 114

45 Balanced Technology Extended (BTX) Mainboard Power Header Placement

46 Boxed Processor TMA Set Points............................................................................... 117

Overshoot Example Waveform.............................................................................24

Core™2 Duo Desktop

Processor E6000 Series with 4 MB L2 Cache with 1333 MHz FSB..................................... 40

Processors E6000 Series with 4 MB L2 Cache with 1066 MHz FSB........................ ........... 41

Processors E6000 Series with 2 MB L2 Cache...............................................................41

Processors E4000 Series with 2 MB L2 Cache...............................................................42

Core™2 Extreme Processor X6800.................42

Core™2 Duo Desktop

Volumes ............................................................................................................... 111

Volume................................................................................................................. 112

(hatched area) .................................................................... .................................. 115

Datasheet 5

Tables

1 Reference Documents ...................................... .. ................................................... .. ..14

2 Voltage Identification Definition..................................................................................17

3 Market Segment Selection Truth Table for MSID[1:0] ...................................................18

4 Absolute Maximum and Minimum Ratings ....................................................................20

5 Voltage and Current Specifications..............................................................................20

6V 7V

8 FSB Signal Groups....................................................................................................25

9 Signal Characteristics.............................................. .. ........................... .. .. .................26

10 Signal Reference Voltages ................................ .. .. ............................ .........................26

11 GTL+ Signal Group DC Specifications..........................................................................27

12 Open Drain and TAP Output Signal Group DC Specifications ...........................................27

13 CMOS Signal Group DC Specifications..........................................................................28

14 GTL+ Bus Voltage Definitions.....................................................................................28

15 Core Frequency to FSB Multiplier Configuration.............................................................29

16 BSEL[2:0] Frequency Table for BCLK[1:0] ...................................................................30

17 Front Side Bus Differential BCLK Specifications.............................................................30

18 Front Side Bus Differential BCLK Specifications.............................................................32

19 PECI DC Electrical Limits ...........................................................................................33

20 Processor Loading Specifications.................................................................................39

21 Package Handling Guidelines.......................................... .. .. .. ............................ ..........39

22 Processor Materials...................................................................................................40

23 Alphabetical Land Assignments...................................................................................48

24 Numerical Land Assignment.......................................................................................58

25 Signal Description (Sheet 1 of 9)................................................................................68

26 Processor Thermal Specifications................................................................................78

27 Thermal Profile 1......................................................................................................79

28 Thermal Profile 2......................................................................................................80

29 Thermal Profile 3......................................................................................................81

30 Thermal Profile 4......................................................................................................82

31 Thermal Profile 5......................................................................................................83

32 Thermal “Diode” Parameters using Diode Model............................................................88

33 Thermal “Diode” Parameters using Transistor Model......................................................89

34 Thermal Diode Interface............................................................................................89

35 GetTemp0() Error Codes ...........................................................................................92

36 Power-On Configuration Option Signals .......................................................................93

37 Fan Heatsink Power and Signal Specifications.............................................................102

38 Fan Heatsink Power and Signal Specifications.............................................................106

39 TMA Power and Signal Specifications.........................................................................113

40 TMA Set Points for 3-wire operation of BTX Type I and Type II Boxed

Static and Transient Tolerance .............................................................................22

Overshoot Specifications................... .. .. .. ........................... ... .. ........................... ..24

Processors.............................................................................................................115

6 Datasheet

Revision History

Revision

Number

Description Date

-001 • Initial release July 2006

-002 • Corrected L1 Cache information September 2006

•Added Intel

Core™2 Duo Desktop Processor E4300 information

• Updated Table 5, DC Voltage and Current Specification

• Added Section 2.3, PECI DC Specifications

-003

• Updated Section 5.3, Platform Environment Control Interface (PECI)

• Updated Section 7.1.2, Boxed Processor Fan Heatsink Weight

• Updated Table 37, Fan Heatsink Power and Signal Specifications

• Added Section 7.3.2, Fan Speed Control Operation Intel X6800 Only) and Section 7.3.3, Fan Speed Control Operation (Intel

Core2 Extreme Processor

Core2 Duo Desktop

January 2007

Processor E6000 and E4000 series Only)

-004 • Added Intel

•Added Intel

Core™2 Duo Desktop Processor E6420, E6320, and E4400 information April 2007

Core™2 Duo Desktop Processor E6850, E6750, E6550, E6540, and E4500

information.

-005

• Added specifications for 1333 MHz FSB.

July 2007

• Added support for Extended Stop Grant State, Extended Stop Grant Snoop States.

• Added new thermal profile table and figure.

-006 • Added Intel

-007 • Added Intel

-008 • Added Intel

Core™2 Duo Desktop Processor E4400 with CPUID = 065Dh. August 2007

Core™2 Duo Desktop Processor E4600 October 2007

Core™2 Duo Desktop Processor E4700 March 2008

Datasheet 7

8 Datasheet

Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Series Features

• Available at 2.93 GHz (Intel Core™2 Extreme processor X6800 only)

• Available at 3.00 GHz, 2.66 GHz, 2.40 GHz,

2.33 GHz, 2.13 GHz, and 1.86 GHz (Intel Core™2 Duo desktop processor E6850, E6750, E6700, E6600, E6540, E6540, E6420, E6400, E6320, and E6300 only)

• Available at 2.40 GHz, 2.20 GHz, 2.00 GHz, and

1.80 GHz and (Intel Core™2 Duo desktop processor E4700, E4600, E4500, E4400, and E4300 only)

• Enhanced Intel SpeedStep

• Supports Intel

• Supports Intel Core™2 Extreme processor X6800 and Intel Core™2 Duo desktop processor E6000 series only)

• Supports Execute Disable Bit capability

• Supports Intel (Intel® TXT) (Intel Core2 Duo desktop processors E6850, E6750, and E6550 only)

• FSB frequency at 1333 MHz (Intel Core2 Duo desktop processors E6850, E6750, E6550, and E6540 only)

• FSB frequency at 1066 MHz (Intel Core™2 Extreme processor X6800 and Intel Core™2 Duo desktop processor E6700, E6600, E6420, E6400, E6320, and E6300 only)

• FSB frequency at 800 MHz (Intel Core™2 Duo desktop processor E4000 series only)

64 architecture

Virtualization Technology (Intel

Trusted Execution Technology

Technology

• Binary compatible with applications running on previous members of the Intel microprocessor line

• Advance Dynamic Execution

• Very deep out-of-order execution

• Enhanced branch prediction

• Optimized for 32-bit applications running on advanced 32-bit operating systems

• Two 32-KB Level 1 data caches

•4MB Intel Extreme processor X6800 and Intel Core™2 Duo desktop processor E6850, E6750, E6700, E6540, E6540, E6600, E6420, and E6320, only)

•2MB Intel Duo desktop processor E6400, E6300, E4700, E4600, E4500, E4400, and E4300 only)

•Intel

• Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance

• Power Management capabilities

• System Management mode

• Multiple low-power states

• 8-way cache associativity provides improved cache hit rate on load/store operations

• 775-land Package

Advanced Smart Cache (Intel Core™2

Advanced Digital Media Boost

The Intel Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000, E4000 series deliver Intel's advanced, powerful processors for desktop PCs. The processor is designed to deliver performance across applications and usages where end-users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and multitasking user environments.

Intel

64 architecture enables the processor to execute operating systems and applications written to

take advantage of the Intel 64 architecture. The processor supporting Enhanced Intel SpeedStep

technology allows tradeoffs to be made between performance and power consumption. The Intel Core™2 Extreme processor X6800 and Intel

Core™2 Duo desktop processor E6000, E4000 series also include the Execute Disable Bit capability. This feature, combined with a supported operating system, allows memory to be marked as executable or non-executable.

The Intel Core™2 Extreme processor X6800 and Intel support Intel

Virtualization T echnology. Virtualization Technology provides silicon-based functionality

Core™2 Duo desktop processor E6000 series

that works together with compatible Virtual Machine Monitor (VMM) software to improve on softwareonly solutions.

The Intel Core™2 Duo desktop processors E6850, E6750, and E6550 support Intel Execution Technology (Intel

TXT). Intel® Trusted Execution Technology (Intel® TXT) is a security

Trusted

technology.

§ §

Datasheet 9

10 Datasheet

Introduction

1 Introduction

The Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000 and E4000 series combine the performance of the previous generation of desktop products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems. These processors are 64-bit processors that maintain compatibility with IA-32 software.

The Intel processor E6000 and E4000 series use Flip-Chip Land Grid Array (FC-LGA6) package technology, and plugs into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the LGA775 socket.

Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop

Note: In this document, unless otherwise specified, the Intel

processor E6000 series refers to Intel E6550, E6540, E6700, E6600, E6420, E6400, E6320, and E6300. The Intel Duo desktop processor E4000 series refers to Intel

Core™2 Duo desktop processors E6850, E6750,

Core™2 Duo desktop processor

E4700, E4600, E4500, E4400, and E4300.

Note: In this document, unless otherwise specified, the Intel

X6800 and Intel

Core™2 Duo desktop processor E6000 and E4000 series are referred

to as “processor.” The processors support several Advanced Technologies including the Execute Disable

Bit, Intel

64 architecture, and Enhanced Intel SpeedStep® Technology. The Intel Core™2 Duo desktop processor E6000 series and Intel Core™2 Extreme processor X6800 support Intel® Virtualization Technology (Intel VT). In addition, the Intel Core™2 Duo desktop processors E6850, E6750, and E6550 support Intel Execution Technology (Intel

The processor's front side bus (FSB) uses a split-transaction, deferred reply protocol like the Intel

Pentium® 4 processor. The FSB uses Source-Synchronous T ransfer (S ST)

TXT).

of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "doubleclocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 10.7 GB/s.

Intel has enabled support components for the processor including heatsink, heatsink retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling.

Core™2 Duo desktop

Core™2

Core™2 Extreme processor

Trusted

The processor includes an address bus power-down capability which removes power from the address and data signals when the FSB is not in use. This feature is always enabled on the processor.

Datasheet 11

1.1 Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

The phrase “Front Side Bus” refers to the interface between the processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O.

1.1.1 Processor Terminology

Commonly used terms are explained here for clarification:

• Intel LGA6 package with a 4 MB L2 cache.

• Intel E6700, E6600, E6420, and E6320, — Dual core processor in the FC-LGA6 package with a 4 MB L2 cache.

• Intel E4500, E4400, and E4300— Dual core processor in the FC-LGA6 package with a 2MB L2 cache.

• Processor — For this document, the term processor is the generic form of the Intel® Core™2 Duo desktop processor E6000 and E4000 series and the Intel® Core™2 Extreme processor X6800. The processor is a single package that contains one or more execution units.

• Keep-out zone — The area on or near the processor that system design can not use.

• Processor core — Processor core die with integrated L2 cache.

• LGA775 socket — The processors mate with the system board through a surface mount, 775-land, LGA socket.

• Integrated heat spreader (IHS) —A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface.

• Retention mechanism (RM) — Since the LGA775 socket does not include any mechanical features for heatsink attach, a retention mechanism is required. Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket.

• FSB (Front Side Bus) — The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB.

• Storage conditions — Refers to a non-operational state. The processor may be installed in a platform, in a tray , or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks. Upon exposure to “free air”(i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.

Core™2 Extreme processor X6800 — Dual core processor in the FC-

Core™2 Duo desktop processor E6850, E6750, E6550, E6540,

Core™2 Duo desktop processor E6400, E6300, E4700, E4600,

Introduction

12 Datasheet

Introduction

• Functional operation — Refers to normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical and thermal are satisfied.

• Execute Disable Bit — Allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the over all security of the system. See the Intel

Architecture Software Developer's Manual for more detailed

information.

• Intel® 64 Architecture — An enhancement to Intel's IA-32 architecture, allowing the processor to execute operating systems and applications written to take advantage of Intel 64 architecture. Further details on Intel 64 architecture and programming model can be found in the Intel

Extended Memory 64 Technology

Software Developer Guide at http://www.intel.com/technology/intel64/index.htm.

• Enhanced Intel SpeedStep

Technology — Enhanced Intel Speedstep®

technology allows trade-offs to be made between performance and power consumptions, based on processor utilization. This may lower average power consumption (in conjunction with OS support).

• Intel® Virtualization Technology (Intel VT) — Intel Virtualization Technology provides silicon-based functionality that works together with compatible Virtual Machine Monitor (VMM) software to improve upon software-only solutions. Because this virtualization hardware provides a new architecture upon which the operating system can run directly, it removes the need for binary translation. Thus, it helps eliminate associated performance overhead and vastly simplifies the design of the VMM, in turn allowing VMMs to be written to common standards and to be more robust. See the Intel

Virtualization Technology Specification for the IA-32 Intel®

Architecture for more details.

• Intel® Trusted Execution Technology (Intel® TXT)— Intel® T rusted Ex ecution Technology (Intel requires for operation a computer system with Intel

TXT) is a security technology under development by Intel and

Virtualization Technology, a Intel Trusted Execution Technology-enabled Intel processor, chipset, BIOS, Authenticated Code Modules, and an Intel or other Intel Trusted Execution T echnology compatible measured virtual machine monitor. In addition, Intel T rusted Execution Technology requires the system to contain a TPMv1.2 as defined by the Trusted Computing Group and specific software for some uses.

Datasheet 13

1.2 References

Material and concepts available in the following documents may be beneficial when reading this document.

Table 1. Reference Documents

Core™2 Extreme Processor X6800 and Intel® Core™2 Duo

Intel Desktop Processor E6000 and E4000 Series Specification Update

Intel

Core™2 Duo Processor and Intel® Pentium® Dual Core

Processor Thermal and Mechanical Design Guidelines

Intel

Pentium® D Processor, Intel® Pentium® Processor Extreme Edition, Intel Processor X6800 Thermal and Mechanical Design Guidelines

Balanced Technology Extended (BTX) System Design Guide www.formfactors.org Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design

Guidelines For Desktop LGA775 Socket

LGA775 Socket Mechanical Design Guide

Intel Architecture

Intel the IA-32 Intel® Architecture

Intel

Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide

Pentium® 4 Processor, Intel® Core™2 Duo Extreme

Virtualization Technology Specification for the IA-32 Intel®

Trusted Exectuion Technology (Intel® TXT) Specification for

64 and IA-32 Intel Architecture Software Developer's Manuals

Introduction

Document Location

www.intel.com/design/ processor/specupdt/

313279.htm http://www.intel.com/

design/processor/ designex/317804.htm

http://www.intel.com/ design/pentiumXE/ designex/306830.htm

http://www.intel.com/ design/processor/ applnots/313214.htm

http://intel.com/design/ Pentium4/guides/

302666.htm http://www.intel.com/

technology/computing/ vptech/index.htm

http://www.intel.com/ technology/security/

http://www.intel.com/ products/processor/ manuals/

§ §

14 Datasheet

Electrical Specifications

2 Electrical Specifications

This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided.

2.1 Power and Ground Lands

The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to V connected to a system ground plane. The processor V voltage determined by the Voltage IDentification (VID) lands.

The signals denoted as VTT provide termination for the front side bus and power to the I/O buffers. A separate supply must be implemented for these lands, that meets the VTT specifications outlined in Table 5.

2.2 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings. This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate. Larger bulk storage (C current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 5. Failure to do so can result in timing violations or reduced lifetime of the component.

), such as electrolytic or aluminum-polymer capacitors, supply

BULK

, while all VSS lands must be

lands must be supplied the

2.2.1 VCC Decoupling

VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications. This includes bulk capacitance with low effective series resistance (ESR) to keep the voltage rail within specifications during large swings in load current. In addition, ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity. Consult the

Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket.

2.2.2 VTT Decoupling

Decoupling must be provided on the motherboard. Decoupling solutions must be sized to meet the expected load. T o insure complian ce with the specifications, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors.

Datasheet 15

2.2.3 FSB Decoupling

The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation.

2.3 Voltage Identification

The Voltage Identification (VID) specification for the processor is defined by the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage

to be delivered to the processor V specifications). Refer to Table 13 for the DC specifications for these signals. Voltages for each processor frequency is provided in Table 5.

Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings. This is reflected by the VID Range values provided in Table 5. Refer to the Intel

Desktop Processor E6000 and E4000 Series and Intel X6800 Specification Update for further details on specific valid core frequency and VID

values of the processor. Note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Extended HALT State).

pins (see Chapter 2.6.3 for VCC overshoot

Electrical Specifications

Core™2 Extreme Processor

Core™2 Duo

The processor uses six voltage identification signals, VID[6:1], to support automatic selection of power supply voltages. Table 2 specifies the voltage level corresponding to the state of VID[6:1]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is empty (VID[6:1] = 111111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. The Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket defines VID [7:0], VID7 and VID0 are not used on the processor; VID0 and VID7 are strapped to V and VID7 must be connected to the VR controller for compatibility with future

on the processor package. VID0

processors. The processor provides the ability to operate while transitioning to an adjacent VID and

its associated processor core voltage (V line. It should be noted that a low-to-high or high-to-low voltage state change may

). This will represent a DC shift in the load

result in as many VID transitions as necessary to reach the target core voltage. Transitions above the specified VID are not permitted. Table 5 includes VID step sizes and DC shift ranges. Minimum and maximum v oltages must be maintained as shown in

Table 6 and Figure 1 as measured across the VCC_SENSE and VSS_SENSE lands.

The VRM or VRD used must be capable of regulating its output to the value defined by the new VID. DC specifications for dynamic VID transitions are included in Table 5 and

Table 6. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery

Design Guidelines For Desktop LGA775 Socket for further details.

16 Datasheet

Electrical Specifications

Table 2. Voltage Identification Definition

VID6 VID5 VID4 VID3 VID2 VID1 VID (V) VID6 VID5 VID4 VID3 VID2 VID1 VID (V)

1111010.8500 0111101.2375

1111000.8625 0111011.2500

1110110.8750 0111001.2625

1110100.8875 0110111.2750

1110010.9000 0110101.2875

1110000.9125 0110011.3000

1101110.9250 0110001.3125

1101100.9375 0101111.3250

1101010.9500 0101101.3375

1101000.9625 0101011.3500

1100110.9750 0101001.3625

1100100.9875 0100111.3750

1100011.0000 0100101.3875

1100001.0125

1011111.0250 0100001.4125

1011101.0375 0011111.4250

1011011.0500 0011101.4375

1011001.0625 0011011.4500

1010111.0750 0011001.4625

1010101.0875 0010111.4750

1010011.1000 0010101.4875

1010001.1125 0010011.5000

1001111.1250 0010001.5125

1001101.1375 0001111.5250

1001011.1500 0001101.5375

1001001.1625 0001011.5500

1000111.1750 0001001.5625

1000101.1875 0000111.5750

1000011.2000 0000101.5875

1000001.2125 0000011.6000

0111111.2250 000000 OFF

0 1 0 0 0 11.4000

Datasheet 17

2.4 Market Segment Identification (MSID)

The MSID[1:0] signals may be used as outputs to determine the Market Segment of the processor. Table 3 provides details regarding the state of MSID[1:0]. A circuit can be used to prevent 130 W TDP processors from booting on boards optimized for 65 W TDP.

Electrical Specifications

Table 3. Market Segment Selection Truth Table for MSID[1:0]

MSID1 MSID0 Description

Intel

01Reserved 10Reserved 11Reserved

NOTES:

The MSID[1:0] signals are provided to indicate the Market Segment for the processor

Core™2 Duo desktop processor E6000 and E4000 series and the

Intel

Core™2 Extreme processor X6800

1, 2, 3, 4

and may be used for future processor compatibility or for keying. Circuitry on the motherboard may use these signals to identify the processor installed.

2. These signals are not connected to the processor die.

3. A logic 0 is achieved by pulling the signal to ground on the package.

4. A logic 1 is achieved by leaving the signal as a no connect on the package.

2.5 Reserved, Unused, and TESTHI Signals

All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, V

, or to any other signal (including each other) can result in component malfunction

or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands.

In a system level design, on-die termination has been included by the processor to allow signals to be terminated within the processor silicon. Most unused GTL+ inputs should be left as no connects as GTL+ termination is provided on the processor silicon. However, see Table 8 for details on GTL+ signals that do not include on-die termination.

Unused active high inputs, should be connected through a resistor to ground (V Unused outputs can be left unconnected, however this may interfere with some TAP

functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ± 20% of the impedance of the motherboard trace for front side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the same value as the on-die termination resistors (R

). For details, see Table 14.

TAP and CMOS signals do not include on-die termination. Inputs and used outputs must be terminated on the motherboard. Unused outputs may be terminated on the motherboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing.

All TESTHI[13:0] lands should be individually connected to V that matches the nominal trace impedance.

18 Datasheet

via a pull-up resistor

Electrical Specifications

The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group:

• TESTHI[1:0]

• TESTHI[7:2]

• TESTHI8/FC42 – cannot be grouped with other TESTHI signals

• TESTHI9/FC43 – cannot be grouped with other TESTHI signals

• TESTHI10 – cannot be grouped with other TESTHI signals

• TESTHI11 – cannot be grouped with other TESTHI signals

• TESTHI12/FC44 – cannot be grouped with other TESTHI signals

• TESTHI13 – cannot be grouped with other TESTHI signals

However, utilization of boundary scan test will not be functional if these lands are connected together. For optimum noise margin, all pull-up resistor values used for TESTHI[13:0] lands should have a resistance value within ± 20% of the impedance of the board transmission line traces. For example, if the nominal trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω should be used.

2.6 Voltage and Current Specification

2.6.1 Absolute Maximum and Minimum Ratings

Table 4 specifies absolute maximum and minimum ratings only and lie outside the

functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected.

At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded.

Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields.

Datasheet 19

Table 4. Absolute Maximum and Minimum Ratings

Symbol Parameter Min Max Unit Notes

STORAGE

NOTES:

1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied.

2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.

3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-term reliability of the device. For functional operation, refer to the processor case temperature specifications .

4. This rating applies to the processor and does not include any tray or packaging.

5. Failure to adhere to this specification can affect the long term reliability of the processor.

Core voltage with respect to V

FSB termination voltage with respect to V

Processor case temperature

Processor storage temperature –40 85 °C

Electrical Specifications

–0.3 1.55 V -

See

Chapter 5

See

Chapter 5

°C -

1, 2

3, 4, 5

2.6.2 DC Voltage and Current Specification

Table 5. Voltage and Current Specifications

Symbol Parameter Min Typ Max Unit Notes

VID Range VID 0.8500 — 1.5 V

CC_BOOT

Processor Number (4 MB L2 Cache)

E6850 E6750 E6700 E6600 E6550 E6540 E6420 E6320

Processor Number (4 MB L2 Cache)

X6800

Processor Number (2 MB L2 Cache)

E6400 E6300 E4700

E4600,

E4500 E4400 E4300

Default VCC voltage for initial power up — 1.10 — V

for

775_VR_CONFIG_06

3.00 GHz

2.66 GHz

2.40 GHz

2.33 GHz

2.13 GHz

1.86 GHz

VCC for 775_VR_CONFIG_05B

2.93 GHz

for

775_VR_CONFIG_06

2.13 GHz

1.86 GHz

2.60 GHz

2.40 GHz

2.20 GHz

2.00 GHz

1.80 GHz

Refer to Table 6 and

Figure 1

1, 2

4, 5, 6

20 Datasheet

Electrical Specifications

Table 5. Voltage and Current Specifications

Symbol Parameter Min Typ Max Unit Notes

CCPLL

VTT_OUT_LEFT and VTT_OUT_RIGHT I

CC_VCCPLL

CC_GTLREF

PLL V

Processor Number

775_VR_CONFIG_06

E6850 E6750 E6700 E6600 E6550

E6540 E6400/E6420 E6300/E6320

E4700

E4600

E4500

E4400

E4300

Processor Number

ICC for 775_VR_CONFIG_05B

X6800

FSB termination voltage (DC + AC specifications)

for

3.00 GHz

2.66 GHz

2.40 GHz

2.33 GHz

2.13 GHz

1.86 GHz

2.60 GHz

2.40 GHz

2.20 GHz

2.00 GHz

1.80 GHz

2.93 GHz

- 5% 1.50 + 5%

75 75 75 75 75

——

75 75 75 75 75 75 75 75

——

1.14 1.20 1.26 V

DC Current that may be drawn from VTT_OUT_LEFT and VTT_OUT_RIGHT per

pin ICC for VTT supply before VCC stable

for VTT supply after VCC stable

— — 580 mA

——

4.5

4.6 ICC for PLL land — — 130 mA ICC for GTLREF — — 200 μA

NOTES:

1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date.

2. Adh erence to the voltage specifications for the processor are required to ensure reliable processor operation.

3. Eac h processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep

Technology, or Extended HALT State).

4. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.3 and Table 2 for more information.

5. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.

6. Refer to Table 6 and Figure 1 for the minimum, typical, and maximum V processor should not be subjected to any V current.

7. I

8. V at the land.

specification is based on the V

CC_MAX

must be provided via a separate voltage source and not be connected to VCC. This specification is meas ured

and ICC combination wherein VCC exceeds V

loadline. Refer to Figure 1 for details.

CC_MAX

allowed for a given current. The

CC_MAX

for a given

9. Baseboard bandwidth is limited to 20 MHz.

10.This is maximum total current drawn from V the current coming from RTT (through the signal line). Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA77 5 Socket to determine the total I system. This parameter is based on design characterization and is not tested.

plane by only the processor. This specificat ion does not include

drawn by the

1, 2

Datasheet 21

Table 6. VCC Static and Transient Tolerance

Voltage Deviation from VID Setting (V)

ICC (A)

0 0.000 -0.019 -0.038

5 -0.007 -0.026 -0.046 10 -0.013 -0.033 -0.054 15 -0.020 -0.040 -0.061 20 -0.026 -0.048 -0.069 25 -0.033 -0.055 -0.077 30 -0.039 -0.062 -0.085 35 -0.046 -0.069 -0.092 40 -0.052 -0.076 -0.100 45 -0.059 -0.083 -0.108 50 -0.065 -0.090 -0.116 55 -0.072 -0.097 -0.123 60 -0.078 -0.105 -0.131 65 -0.085 -0.112 -0.139 70 -0.091 -0.119 -0.147 75 -0.098 -0.126 -0.154

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.6.3.

2. This table is intended to aid in reading discrete points on Figure 1.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details.

4. Adherence to this loadline specificatio n is required to ensure reliable processor operation.

Maximum Voltage

1.30 mΩ

Typical Voltage

1.425 mΩ

Electrical Specifications

1, 2, 3, 4

Minimum Voltage

1.55 mΩ

22 Datasheet

Electrical Specifications

Figure 1. VCC Static and Transient Tolerance

Icc [A]

Vcc Maximum

VID - 0.000

VID - 0.013

VID - 0.025

VID - 0.038

VID - 0.050

VID - 0.063

VID - 0.075

Vcc [V]

VID - 0.088

VID - 0.100

VID - 0.113

VID - 0.125

VID - 0.138

VID - 0.150

VID - 0.163

0 10203040506070

Vcc Typical

Vcc Minimum

NOTES:

1. The loadline spec ification includes both static and transient limits except for overshoot allowed as shown in Section 2.6.3.

2. This loadline s p ecification shows the deviation from the VID set point.

Datasheet 23

2.6.3 VCC Overshoot

The processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + V The time duration of the overshoot event must not exceed T maximum allowable time duration above VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.

OS_MAX

Electrical Specifications

is the maximum allowable overshoot voltage).

OS_MAX

is the

Table 7. V

Overshoot Specifications

Symbol Parameter Min Max Unit Figure N otes

OS_MAX

NOTES:

1. Adherence to these specifications is required to ensure reliable processor operation.

Magnitude of VCC overshoot above VID — 50 mV 2 Time duration of VCC overshoot above VID — 25 μs 2

Figure 2. VCC Overshoot Example Waveform

Example Overshoot Waveform

VID + 0.050

Voltage [V]

VID - 0.000

0 5 10 15 20 25

Time [us]

TOS: Overshoot time above VID V

: Overshoot above VID

NOTES:

1. V

2. T

is measured overshoot voltage.

is measured time duration above VID.

2.6.4 Die Voltage Validation

Overshoot events on processor must meet the specifications in Table 7 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit.

24 Datasheet

Electrical Specifications

2.7 Signaling Specifications

Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Platforms implement a termination voltage level for GTL+ signals defined as V separate power planes for each processor (and chipset), separate V are necessary. This configuration allows for improved noise tolerance as processor frequency increases. Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families.

The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the motherboard (see Table 14 for GTLREF specifications). Termination resistors (R GTL+ signals are provided on the processor silicon and are terminated to V chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+ signals.

2.7.1 FSB Signal Groups

The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers, which use GTLREF[1:0] as a reference level. In this document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as well as the GTL+ I/O group when driving.

With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 8 identifies which signals are common clock, source synchronous, and asynchronous.

Table 8. FSB Signal Groups (Sheet 1 of 2)

Signal Group Type Signals

GTL+ Common Clock Input

GTL+ Common Clock I/O

Synchronous to BCLK[1:0]

BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY# ADS#, BNR#, BPM[5:0]#, BR0#, DBSY#, DRDY#,

HIT#, HITM#, LOCK#

. Because platforms implement

and V

supplies

. Intel

) for

Signals Associated Strobe

REQ[4:0]#, A[16:3]#

GTL+ Source Synchronous I/O

GTL+ Strobes

Datasheet 25

Synchronous to assoc. strobe

Synchronous to BCLK[1:0]

A[35:17]# D[15:0]#, DBI0# DSTBP0#, DSTBN0# D[31:16]#, DBI1# DSTBP1#, DSTBN1# D[47:32]#, DBI2# DSTBP2#, DSTBN2# D[63:48]#, DBI3# DSTBP3#, DSTBN3#

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

ADSTB0# ADSTB1#

Table 8. FSB Signal Groups (Sheet 2 of 2)

Signal Group Type Signals

CMOS

Open Drain Output FERR#/PBE#, IERR#, THERMTRIP#, TDO Open Drain Input/

Output FSB Clock Clock BCLK[1:0], ITP_CLK[1:0]

Power/Other

NOTES:

1. Refer to Section 4.2 for signal descriptions.

2. In processor systems where no debug port is implemented on the syst em board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.

3. The value of these signals durin g the active-to-inactive edge of RESET# defines the processor configuration options. See Section 6.1 for details.

4. PROCHOT# signal type is open drain output and CMOS input.

Table 9. Signal Characteristics

Electrical Specifications

A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, STPCLK#, PWRGOOD, TCK, TDI, TMS, TRST#, BSEL[2:0], VID[6:1]

PROCHOT#

VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA, GTLREF[1:0], COMP[8,3:0], RESERVED, TESTHI[13:0], VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE, VSS_MB_REGULATION, DBR#

, VTT_OUT_LEFT,

VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0]

Signals with R

A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, LOCK#, PROCHOT#, REQ[4:0]#, RS[2:0]#, TRDY#

Open Drain Signals

THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#, BR0#, TDO, FCx

NOTES:

1. Signals that do not have R

Table 10. Signal Reference Voltages

GTLREF VTT/2

BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#, TRDY#

NOTES:

1. Th ese signals also have hysteresis added to the reference voltage. See Table 12 for more

information.

Signals with No R

A20M#, BCLK[1:0], BSEL[2:0], COMP[8,3:0], IGNNE#, INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#, SMI#, STPCLK#, TESTHI[13:0], VID[6:1], GTLREF[1:0], TCK, TDI, TMS, TRST#, VTT_SEL, MSID[1:0]

, nor are actively driven to their high-voltage level.

A20M#, LINT0/INTR, LINT1/NMI, IGNNE#, INIT#, PROCHOT#, PWRGOOD TDI

, SMI#, STPCLK#, TCK1,

, TMS1, TRST#

26 Datasheet

Electrical Specifications

2.7.2 CMOS and Open Drain Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of the CMOS and Open Drain signals are required to be asserted/deasserted for at least four BCLKs in order for the processor to recognize the proper signal state. See Section 2.7.3 for the DC. See Section 6.2 for additional timing requirements for entering and leaving the low power states.

2.7.3 Processor DC Specifications

The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated.

Table 11. GTL+ Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

V V

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

3. The V

4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

5. V

6. Leakage to VSS with land held at VTT.

7. Leakage to VTT with land held at 300 mV.

Table 12. Open Drain and TAP Output Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

I I

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. VOH is determined by the value of the external pull-up resister to VTT.

3. Measured at VTT * 0.2.

4. For Vin between 0 and VOH.

Input Low Voltage -0.10 GTLREF – 0.10 V

Input High Voltage GTLREF + 0.10 V

Output High Voltage V

Output Low Current N/A

Input Leakage Current N/A ± 100 µA

Output Leakage

Current Buffer On Resistance 10 13 Ω

referred to in these specifications is the instantaneous VTT.

and VOH may experience excursions above VTT.

Output Low Voltage 0 0.20 V -

Output High Voltage VTT – 0.05 VTT + 0.05 V

Output Low Current 16 50 mA

Output Leakage Current N/A ± 200 µA

– 0.10 V

[(R

TT_MIN

N/A ± 100 µA

+ 0.10 V

TT_MAX

)+(2*R

ON_MIN

A-

)]

2, 3

4, 5, 3

5, 3

2 3 4

Datasheet 27

Table 13. CMOS Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

V V V

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

3. The V

4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

5. V

6. All outputs are open drain.

7. I

8. Leakage to VSS with land held at VTT.

9. Leakage to VTT with land held at 300 mV.

Input Low Voltage -0.10 VTT * 0.30 V

Input High Voltage VTT * 0.70 V

Output Low Voltage -0.10 VTT * 0.10 V

Output High Voltage 0.90 * V

Output Low Current 1.70 4.70 mA

Output High Current 1.70 4.70 mA

Input Leakage Current N/A ± 100 µA

Output Leakage Current N/A ± 100 µA

referred to in these specifications refers to instantaneous VTT.

and VOH may experience excursions above VTT.

is measured at 0.10 * V

is measured at 0.90 * V

TT. IOH

TTVTT

TT .

Electrical Specifications

+ 0.10 V

2, 3

3, 4, 5

3, 6, 5

3, 7 3, 7

8 9

2.7.3.1 GTL+ Front Side Bus Specifications

In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 9 for details on which GTL+ signals do not include on-die termination.

Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF. Table 14 lists the GTLREF specifications. The GTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits.

Table 14. GTL+ Bus Voltage Definitions

Symbol Parameter Min Typ Max Units Notes

GTLREF_PU GTLREF pull up resistor 124 * 0.99 124 124 * 1.01 Ω GTLREF_PD GTLREF pull down resistor 210 * 0.99 210 210 * 1.01 Ω R

COMP[3:0] COMP Resistance 49.40 49.90 50.40 Ω COMP8 COMP Resistance 24.65 24.90 25.15 Ω

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. GTLREF is to be generated from VTT by a voltage divider of 1% resistors (one divider for each GTLEREF land).

3. RTT is the on-die termination resistance measured at VTT/3 of the GTL+ output driver.

4. COMP resistance must be provided on the system board with 1% resistors. See the applicable platform design guide for implementation details. COMP[3:0] and COMP8 resistors are tied to V

Termination Resistance 45 50 55 Ω

3 4

28 Datasheet

Electrical Specifications

2.7.4 Clock Specifications

2.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor’s core frequency is a multiple of the BCLK[1:0] frequency. The processor bus r atio multiplier will be set at its default ratio during manufacturing. Refer to Table 15 for the processor supported ratios.

The processor uses a differential clocking implementation. For more information on the processor clocking, contact your Intel Field representative. Platforms using a CK505 Clock Synthesizer/Driver should comply with the specifications in Section 2.7.8. Platforms using a CK410 Clock Synthesizer/Driver should comply with the specifications in Section 2.7.9.

Table 15. Core Frequency to FSB Multiplier Configuration

Multiplication of

System Core

Frequency to FSB

Frequency

1/6 1.20 GHz 1.60 GHz 2.00 GHz 1/7 1.40 GHz 1.87 GHz 2.33 GHz 1/8 1.60 GHz 2.13 GHz 2.66 GHz -

1/9 1.80 GHz 2.40 GHz 3.00 GHz 1/10 2 GHz 2.66 GHz 3.33 GHz 1/11 2.2 GHz 2.93 GHz 3.66 GHz 1/12 2.4 GHz 3.20 GHz 4.00 GHz

NOTES:

1. Individual processors operate only at or below the rated frequency.

2. Lis ted frequencies are not necessarily committed production frequencies.

Core Frequency

(200 MHz BCLK/

800 MHz FSB)

Core Frequency

(266 MHz BCLK/

1066 MHz FSB)

Core Frequency

(333 MHz BCLK/

1333 MHz FSB)

2.7.6 FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 16 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency.

The Intel Core2 Duo desktop processors E6850, E6750, E6550, and E6540 operate at 1333 MHz (selected by the 333 MHz BCLK[2:0] frequency). The Intel Core2 Duo desktop processors E6700, E6600, E6420, E6400, E6320, and E6300 operate at 1066 MHz (selected by the 266 MHz BCLK[2:0] frequency). The Intel Core2 Extreme processor X6800 operates at a 1066 MHz FSB frequency (selected by a 266 MHz BCLK[1:0] frequency). The Intel Core2 Duo desktop processors E4700, E4600, E4500, E4400 and E4300 operate at a 800 MHz FSB frequency (selected by a 200 MHz BCLK[1:0] frequency).

Notes

1, 2

Datasheet 29

Electrical Specifications

Table 16. BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2 BSEL1 BSEL0 FSB Frequency

L L L 266 MHz LL HRESERVED LH HRESERVED

L H L 200 MHz HH LRESERVED HH HRESERVED HL HRESERVED H L L 333 MHz

2.7.7 Phase Lock Loop (PLL) and Filter

An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is used for the PLL. Refer to Table 5 for DC specifications.

2.7.8 BCLK[1:0] Specifications (CK505 based Platforms)

Table 17. Front Side Bus Differential BCLK Specifications

Symbol Parameter Min Typ Max Unit Figure Notes

V V

CROSS(abs)

ΔV

CROSS

SWING

Cpad Pad Capacitance .95 1.2 1.45 pF

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. "Steady state" voltage, not including overshoot or undershoot.

3. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1.

4. V

Havg

5. Th e crossing point must meet the absolute and relative crossing point specifications simultaneously.

6. Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as the absolute value of the minimum voltage.

7. Measurement taken from differential waveform.

8. Cpad includes die capacitance only. No package parasitics are included.

Input Low Voltage -0.30 N/A N/A V 3

Input High Voltage N/A N/A 1.15 V 3 Absolute Crossing Point 0.300 N/A 0.550 V 3, 4 Range of Crossing Points N/A N/A 0.140 V 3, 4 Overshoot N/A N/A 1.4 V 3 Undershoot -0.300 N/A N/A V 3 Differential Output Swing 0.300 N/A N/A V 5 Input Leakage Current -5 N/A 5 μA

is the statistical average of the VH measured by the oscilloscope.

3, 4, 5

30 Datasheet

Electrical Specifications

Figure 3. Differential Clock Waveform

CLK 0

CROSS

Median + 75 mV

CROSS

median

CROSS

Median - 75 mV

CLK 1

Figure 4. Differential Clock Crosspoint Specification

650

600 550 500 450 400 350

Crossing Point (mV)

300 250 200

550 + 0.5 (VHavg - 700)

300 + 0.5 (VHavg - 700)

300 mV

660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850

VHavg (mV)

High Time

550 mV

Period

CROSS

550 mV

CROSS

300 mV

Low Time

Max

Min

CROSS

median

Figure 5. Differential Measurements

+150 mV

0.0 V 0.0V

-150 mV

Slew_rise

Slew _fall

+150mV

V_swing

-150mV

Diff

Datasheet 31

Electrical Specifications

2.7.9 BCLK[1:0] Specifications (CK410 based Platforms)

Table 18. Front Side Bus Differential BCLK Specifications

Symbol Parameter Min Typ Max Unit Figure Notes

CROSS(abs)

CROSS(rel)

ΔV

CROSS

RBM

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1.

3. The crossing point must meet the absolute and relative crossing point specifications simultaneously.

4. V

Havg

5. V

Havg

6. Overshoot is defined as the absolute value of the maximum voltage.

7. Undershoot is defined as the absolute value of the minimum voltage.

8. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback.

9. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis.

Input Low Voltage -0.150 0.000 N/A V 3 - Input High Voltage 0.660 0.700 0.850 V 3 - Absolute Crossing

Point Relative Crossing

Point Range of Crossing

Points

0.250 N/A 0.550 V 3, 4

0.5(V

0.250 + – 0.700)

Havg

N/A

0.5(V

0.550 + – 0.700)

Havg

N/A N/A 0.140 V 3, 4 -

V 3, 4

Overshoot N/A N/A VH + 0.3 V 3 Undershoot -0.300 N/A N/A V 3 Ringback Margin 0.200 N/A N/A V 3 Threshold Region V

– 0.100 N/A V

CROSS

+ 0.100 V 3

CROSS

is the statistical average of the VH measured by the oscilloscope. can be measured directly using “Vtop” on Agilent* oscilloscopes and “High” on T ektronix* oscilloscopes.

2, 3

4, 3, 5

6 7 8 9

Figure 6. Differential Clock Crosspoint Specification

650

600 550 500 450 400 350

Crossing Point (mV)

300 250 200

550 + 0.5 (VHavg - 700)

250 + 0.5 (VHavg - 700)

250 mV

660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850

VHavg (mV)

32 Datasheet

550 mV

Electrical Specifications

2.8 PECI DC Specifications

PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors (may also include chipset components in the future) and external thermal monitoring devices. The processor contains Digital Thermal Sensors (DTS) distributed throughout die. These sensors are implemented as analog-to-digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature. PECI provides an interface to relay the highest DTS temperature within a die to external management devices for thermal/ fan speed control. More detailed information is available in the Platform Environment Control Interface (PECI) Specification.

Table 19. PECI DC Electrical Limits

Symbol Definition and Conditions Min Max Units Notes

hysteresis

V V

source

sink

leak+

leak-

bus

noise

Input Voltage Range -0.15 V

Hysteresis 0.1 * V Negative-edge threshold voltage 0.275 * V

Positive-edge threshold voltage 0.550 * V

High level output source

= 0.75 * V

TT)

Low level output sink

= 0.25 * VTT)

0.500 * V

0.725 * V

-6.0 N/A mA

0.5 1.0 mA

High impedance state leakage to VTT N/A 50 µA High impedance leakage to GND N/A 10 µA Bus capacitance per node N/A 10 pF Signal noise immunity above 300 MHz 0.1 * V

—V

p-p

NOTES:

1. V

supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. Refer

to Table 4 for VTT specifications.

2. The input buffers use a Schmitt-triggered input design for improved noise immunity.

3. The leakage specification applies to powered devices on the PECI bus.

4. On e node is counte d for each client and one node for the syst em host. Exten ded trace lengths might appear as additional nodes.

§ §

Datasheet 33

Electrical Specifications

34 Datasheet

Package Mechanical Specifications

3 Package Mechanical

Specifications

The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink. Figure 7 shows a sketch of the processor package components and how they are assembled together. Refer to the LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket.

The package components shown in Figure 7 include the following:

• Integrated Heat Spreader (IHS)

• Thermal Interface Material (TIM)

• Processor core (die)

• Package substrate

• Capacitors

Figure 7. Processor Package Assembly Sketch

Core (die)

IHS

Substrate

System Board

NOTE:

1. Socket and System Board are included for reference and are not part of processor

package.

3.1 Package Mechanical Drawing

The package mechanical drawings are shown in Figure 8 and Figure 9. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include:

• Package reference with tolerances (total height, length, width, etc.)

• IHS parallelism and tilt

• Land dimensions

• Top-side and back-side component keep-out dimensions

• Reference datums

• All drawing dimensions are in mm [in].

• Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and Mechanical Design Guidelines.

TIM

Capacitors

LGA775 Socket

Datasheet 35

Figure 8. Processor Package Drawing Sheet 1 of 3

Package Mechanical Specifications

36 Datasheet

Package Mechanical Specifications

Figure 9. Processor Package Drawing Sheet 2 of 3

Datasheet 37

Figure 10. Processor Package Drawing Sheet 3 of 3

Package Mechanical Specifications

38 Datasheet

Package Mechanical Specifications

3.1.1 Processor Component Keep-Out Zones

The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 8 and Figure 9 for keep-out zones. The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep-in.

3.1.2 Package Loading Specifications

Table 20 provides dynamic and static load specifications for the processor package.

These mechanical maximum load limits should not be exceeded during heatsink assembly , shipping conditions, or standard use condition. Also, any mechanical system or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solution. The minimum loading specification must be

Table 20. Processor Loading Specifications

maintained by any thermal and mechanical solutions.

Parameter Minimum Maximum Notes

Static 80 N [17 lbf] 311 N [70 lbf]

Dynamic — 756 N [170 lbf]

NOTES:

1. These specifications apply to uniform compressive loading in a direction normal to the

processor IHS.

2. This is the maximum force that can be applied by a heatsink ret ention clip. The clip must also

provide the minimum specified load on the processor package.

3. These specifications are based on limited testing for design characterization. Loading limits are

for the package only and do not include the limits of the processor socket.

4. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load

requirement.

1, 2, 3

1, 3, 4

3.1.3 Package Handling Guidelines

Table 21 includes a list of guidelines on package handling in terms of recommended

maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal.

Table 21. Package Handling Guidelines

Parameter Maximum Recommended Notes

Shear 311 N [70 lbf] Tensile 111 N [25 lbf] Torque 3.95 N-m [35 lbf-in]

NOTES:

1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.

2. These guidelines are based on limited testing for design characterization.

3. A tensile load is defined as a pu lling load applied to the IHS in a direction normal to the IHS

surface.

4. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the

IHS top surface.

Datasheet 39

1, 2

2, 3 2, 4

3.1.4 Package Insertion Specifications

The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide.

3.1.5 Processor Mass Specification

The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package.

3.1.6 Processor Materials

Package Mechanical Specifications

Table 22. Processor Materi als

Table 22 lists some of the package components and associated materials.

Component Material

Integrated Heat Spreader (IHS) Nickel Plated Copper

Substrate Fiber Reinforced Resin

Substrate Lands Gold Plated Copper

3.1.7 Processor Markings

Figure 11 through Figure 15show the topside markings on the processor . The diagrams

are to aid in the identification of the processor.

Figure 11. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop

Processor E6000 Series with 4 MB L2 Cache with 1333 MHz FSB

INTEL ©'05 E6850

INTEL® CORE™2 DUO SLxxx [COO]

3.00GHZ/4M/1333/06 [FPO]

ATPO

S/N

40 Datasheet

Package Mechanical Specifications

Figure 12. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop

Processors E6000 Series with 4 MB L2 Cache with 1066 MHz FSB

INTEL ©'05

INTEL® CORE™2 DUO 6700 SLxxx [COO]

2.66GHZ/4M/1066/06 [FPO]

Figure 13. Processor Top-Side Markings Example for the Intel

Processors E6000 Series with 2 MB L2 Cache

INTEL ©'05

ATPO

S/N

INTEL® CORE™2 DUO 6400 SLxxx [COO]

2.13GHZ/2M/1066/06 [FPO]

Core™2 Duo Desktop

ATPO

S/N

Datasheet 41

Package Mechanical Specifications

Figure 14. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop

Processors E4000 Series with 2 MB L2 Cache

INTEL ©'05 E4500

INTEL® CORE™2 DUO SLxxx [COO]

2.20GHZ/2M/800/06 [FPO]

E E

Figure 15. Processor Top-Side Markings for the Intel® Core™2 Extreme Processor X6800

ATPO

S/N

INTEL ©'05

INTEL® CORE™2 EXTREME 6800 SLxxx [COO]

2.93GHZ/4M/1066/05B [FPO]

42 Datasheet

ATPO

S/N

Package Mechanical Specifications

3.1.8 Processor Land Coordinates

Figure 16 shows the top view of the processor land coordinates. The coordinates are

Figure 16. Processor Land Coordinates and Quadrants (Top View)

referred to throughout the document to identify processor lands.

/ V

101112131415161718192021222324252627282930

123456789

AN AM

AJ AH AG AF AE AD AC AB AA

AN AM AL AK AJ AH AG AF AE AD AC AB

P N M

J H G

E D C

Pre liminary

Socket 775

Quadrants

Top View

Y W

Address/

Comm on Clock/

U T R P N M L K J H G F E D C

B A

Async

123456789101112131415161718192021222324252627282930

VTT / Cloc k s Da ta

§ §

Datasheet 43

Package Mechanical Specifications

44 Datasheet

Land Listing and Signal Descriptions

4 Land Listing and Signal

Descriptions

This chapter provides the processor land assignment and signal descriptions.

4.1 Processor Land Assignments

This section contains the land listings for the processor. The land-out footprint is shown in Figure 17 and Figure 18. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view). Table 23 provides a listing of all processor lands ordered alphabetically by land (signal) name. Table 24 provides a listing of all processor lands ordered by land number.

Datasheet 45

Figure 17. land-out Diagram (Top View – Left Side)

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15

VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VSS VCC VCC VSS VSS VCC

VCC VCC VCC VCC VCC VCC VCC VCC

VSS VSS VSS VSS VSS VSS VSS VSS

VCC VCC VCC VCC VCC VCC VCC VCC

VSS VSS VSS VSS VSS VSS VSS VSS

VCC VCC VCC VCC VCC VCC VCC VCC

VSS VSS VSS VSS VSS VSS VSS VSS

VCC VCC VCC VCC VCC VCC VCC VCC

VSS VSS VSS VSS VSS VSS VSS VSS

VCC VCC VCC VCC VCC VCC VCC VCC

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC FC34 FC31 VCC

Land Listing and Signal Descriptions

BSEL1 FC15 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS FC33 FC32

BSEL2 BSEL0 BCLK1 TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET# D47# D44# DSTBN2# DSTBP2# D35# D36# D32# D31#

F E

B A

RSVD BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 RSVD VSS D43# D41# VSS D38# D37# VSS D30#

FC26 VSS VSS VSS VSS FC10 RSVD D45# D42# VSS D40# D39# VSS D34# D33#

VTT VTT VTT VTT VTT VTT VSS VCCPLL D46# VSS D48# DBI2# VSS D49# RSVD VSS

VTT VTT VTT VTT VTT VTT VSS

VTT VTT VTT VTT VTT VTT VSS VSSA D63# D59# VSS D60# D57# VSS D55# D53#

VTT VTT VTT VTT VTT VTT FC23 VCCA D62# VSS RSVD D61# VSS D56# DSTBN3# VSS

VCCIO

VSS D58# DBI3# VSS D54# DSTBP3# VSS D51#

PLL

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15

46 Datasheet

Land Listing and Signal Descriptions

Figure 18. land-out Diagram (Top View – Right Side)

14 13 12 11 10 9 8 7 6 5 4 3 2 1

VCC VSS VCC VCC VSS VCC VCC

VCC VSS VCC VCC VSS VCC VCC VID7 FC40 VID6 VSS VID2 VID0 VSS

VCC VSS VCC VCC VSS VCC VCC VSS VID3 VID1 VID5 VRDSEL PROCHOT# THERMDA

VCC VSS VCC VCC VSS VCC VCC VSS FC8 VSS VID4 ITP_CLK0 VSS THERMDC

VCC VSS VCC VCC VSS VCC VCC VSS A35# A34# VSS IT P_CLK1 BPM0# BPM1#

VCC VSS VCC VCC VSS VCC VCC VSS VSS A33# A32# VSS RSVD VSS

VCC VSS VCC VCC VSS VCC VCC VSS A29# A31# A30# BPM5# BPM3# TRST#

VCC VSS VCC VCC VSS VCC VCC VSS VSS A27# A28# VSS BPM4# TDO

VCC VSS VCC VCC VSS VCC SKTOCC# VSS RSVD VSS RSVD FC18 VSS TCK

VCC VCC VCC VCC VCC VCC VCC VSS REQ4# REQ1# VSS FC22 FC3

VSS VSS VSS VSS VSS VSS VSS VSS VSS TESTHI10 FC35 VSS GTLREF1 GTLREF0

D29# D27# DSTBN1# DBI1# FC38 D16# BPRI# DEFER# RSVD PECI

D28# VSS D24# D23# VSS D18# D17# VSS FC21 RS1# VSS BR0# FC5

VSS D26# DSTBP1# VSS D21# D19# VSS RSVD RSVD FC20 HITM# TRDY# VSS

RSVD D25# VSS D15# D22# VSS D12# D20# VSS VSS HIT# VSS ADS# RSVD

D52# VSS D14# D11# VSS FC38 DSTBN0# VSS D3# D1# VSS LOCK# BNR# DRDY#

VID_SELECTVSS_MB_

VCC VSS A22# ADSTB1# VSS FC36 BPM2# TDI

VCC VSS VSS A25# RSVD VSS DBR# TMS

VCC VSS A17# A24# A26# FC37 IERR# VSS

VCC VSS VSS A23# A21# VSS FC39

VCC VSS A19# VSS A20# FC17 VSS FC0

VCC VSS A18# A16# VSS TESTHI1

VCC VSS VSS A14# A15# VSS RSVD MSID1

VCC VSS A10# A12# A13# FC30 FC29 FC28

VCC VSS VSS A9# A11# VSS FC4 COMP1

VCC VSS ADSTB0# VSS A8#

VCC VSS A4# RSVD VSS INIT# SMI# TESTHI11

VCC VSS VSS RSVD RSVD VSS IGNNE# PWRGOOD

VCC VSS REQ2# A5# A7# STPCLK# THERMTRIP# VSS

VCC VSS VSS A3# A6# VSS TESTHI13 LINT1

VCC VSS REQ3# VSS REQ0# A20M# VSS LINT0

REGULATION

VCC_MB_

REGULATION

VSS_

SENSE

TESTHI9/

FC43

VCC_

SENSE

FERR#/

PBE#

TESTHI8/

FC42

VSS VSS

VTT_OUT_

TESTHI12/

FC44

VSS COMP3

VTT_OUT_

COMP2 FC27

RIGHT

MSID0

LEFT

AL AK

AJ AH AG

AE AD

V U T

P N

L K

F E D C

VSS COMP8 D13# VSS D10# DSTBP0# VSS D6# D5# VSS D0# RS0# DBSY# VSS

D50# COMP0 VSS D9# D8# VSS DBI0# D7# VSS D4# D2# RS2# VSS

14 13 12 11 10 9 8 7 6 5 4 3 2 1

Datasheet 47

B A

Land Listing and Signal Descriptions

Table 23. Alphabetical Land

Assignments

Land Name

A3# L5 Source Synch Input/Output A4# P6 Source Synch Input/Output A5# M5 Source Synch Input/Output A6# L4 Source Synch Input/Output A7# M4 Source Synch Input/Output A8# R4 Source Synch Input/Output

A9# T5 Source Synch Input/Output A10# U6 Source Synch Input/Output A11# T4 Source Synch Input/Output A12# U5 Source Synch Input/Output A13# U4 Source Synch Input/Output A14# V5 Source Synch Input/Output A15# V4 Source Synch Input/Output A16# W5 Source Synch Input/Output A17# AB6 Source Synch Input/Output A18# W6 Source Synch Input/Output A19# Y6 Source Synch Input/Output A20# Y4 Source Synch Input/Output

A20M# K3 Asynch CMOS Input

A21# AA4 Source Synch Input/Output A22# AD6 Source Synch Input/Output A23# AA5 Source Synch Input/Output A24# AB5 Source Synch Input/Output A25# AC5 Source Synch Input/Output A26# AB4 Source Synch Input/Output A27# AF5 Source Synch Input/Output A28# AF4 Source Synch Input/Output A29# AG6 Source Synch Input/Output A30# AG4 Source Synch Input/Output A31# AG5 Source Synch Input/Output A32# AH4 Source Synch Input/Output A33# AH5 Source Synch Input/Output A34# AJ5 Source Synch Input/Output A35# AJ6 Source Synch Input/Output ADS# D2 Common Clock Input/Output

ADSTB0# R6 Source Synch Input/Output ADSTB1# AD5 Source Synch Input/Output

BCLK0 F28 Clock Input BCLK1 G28 Clock Input

Land #Signal Buffer

Type

Direction

Table 23. Alphabetical Land

Assignments

Land Name

BNR# C2 Common Clock Input/Output BPM0# AJ2 Common Clock Input/Output BPM1# AJ1 Common Clock Input/Output BPM2# AD2 Common Clock Input/Output BPM3# AG2 Common Clock Input/Output BPM4# AF2 Common Clock Input/Output BPM5# AG3 Common Clock Input/Output

BPRI# G8 Common Clock Input

BR0# F3 Common Clock Input/Output

BSEL0 G29 Power/Other Output BSEL1 H30 Power/Other Output

BSEL2 G30 Power/Other Output COMP0 A13 Power/Other Input COMP1 T 1 Power/Other Input COMP2 G2 Power/Other Input COMP3 R1 Power/Other Input COMP8 B13 Power/Other Input

D0# B4 Source Synch Input/Output D1# C5 Source Synch Input/Output D2# A4 Source Synch Input/Output D3# C6 Source Synch Input/Output D4# A5 Source Synch Input/Output D5# B6 Source Synch Input/Output D6# B7 Source Synch Input/Output D7# A7 Source Synch Input/Output D8# A10 Source Synch Input/Output

D9# A11 Source Synch Input/Output D10# B10 Source Synch Input/Output D11# C11 Source Synch Inpu t/Output D12# D8 Source Synch Input/Output D13# B12 Source Synch Input/Output D14# C12 Source Synch Inpu t/Output D15# D11 Source Synch Input/Output D16# G9 Source Synch Input/Output D17# F8 Source Synch Input/Output D18# F9 Source Synch Input/Output D19# E9 Source Synch Input/Output D20# D7 Source Synch Input/Output D21# E10 Source Synch Input/Output

Land #Signal Buffer

Type

Direction

48 Datasheet

Land Listing and Signal Descriptions

Table 23. Alphabetical Land

Assignments

Land Name

D22# D10 Source Synch Input/Output D23# F11 Source Synch Input/Output D24# F12 Source Synch Input/Output D25# D13 Source Synch Input/Output D26# E13 Source Synch Input/Output D27# G13 Source Synch Input/Output D28# F14 Source Synch Input/Output D29# G14 Source Synch Input/Output D30# F15 Source Synch Input/Output D31# G15 Source Synch Input/Output D32# G16 Source Synch Input/Output D33# E15 Source Synch Input/Output D34# E16 Source Synch Input/Output D35# G18 Source Synch Input/Output D36# G17 Source Synch Input/Output D37# F17 Source Synch Input/Output D38# F18 Source Synch Input/Output D39# E18 Source Synch Input/Output D40# E19 Source Synch Input/Output D41# F20 Source Synch Input/Output D42# E21 Source Synch Input/Output D43# F21 Source Synch Input/Output D44# G21 Source Synch Input/Output D45# E22 Source Synch Input/Output D46# D22 Source Synch Input/Output D47# G22 Source Synch Input/Output D48# D20 Source Synch Input/Output D49# D17 Source Synch Input/Output D50# A14 Source Synch Input/Output D51# C15 Source Synch Input/Output D52# C14 Source Synch Input/Output D53# B15 Source Synch Input/Output D54# C18 Source Synch Input/Output D55# B16 Source Synch Input/Output D56# A17 Source Synch Input/Output D57# B18 Source Synch Input/Output D58# C21 Source Synch Input/Output D59# B21 Source Synch Input/Output D60# B19 Source Synch Input/Output

Land #Signal Buffer

Type

Direction

Table 23. Alphabetical Land

Assignments

Land Name

D61# A19 Source Synch Input/Output D62# A22 Source Synch Input/Output

D63# B22 Source Synch Input/Output DBI0# A8 Source Synch Input/Output DBI1# G11 Source Synch Input/Output DBI2# D19 Source Synch Input/Output DBI3# C20 Source Synch Input/Output

DBR# AC2 Power/Other Output

DBSY# B2 Common Clock Input/Output

DEFER# G7 Common Clock Input

DRDY# C1 Common Clock Input/Output DSTBN0# C8 Source Synch Input/Output DSTBN1# G12 Source Synch Input/Output DSTBN2# G20 Source Synch Input/Output DSTBN3# A16 Source Synch Input/Output DSTBP0# B9 Source Synch Input/Output DSTBP1# E12 Source Synch Input/Output DSTBP2# G19 Source Synch Input/Output DSTBP3# C17 Source Synch Input/Output

FC0 Y1 Power/Other FC3 J2 Power/Other FC4 T2 Power/Other FC5 F2 Power/Other

FC8 AK6 Power/Other FC10 E24 Power/Other FC15 H29 Power/Other FC17 Y3 Power/Other FC18 AE3 Power/Other FC20 E5 Power/Other FC21 F6 Power/Other FC22 J3 Power/Other FC23 A24 Power/Other FC26 E29 Power/Other FC27 G1 Power/Other FC28 U1 Power/Other FC29 U2 Power/Other FC30 U3 Power/Other FC31 J16 Power/Other FC32 H15 Power/Other

Land #Signal Buffer

Type

Direction

Datasheet 49

Land Listing and Signal Descriptions

Table 23. Alphabetical Land

Assignments

Land Name

FC33 H16 Power/Other FC34 J17 Power/Other FC35 H4 Power/Other FC36 AD3 Power/Other FC37 AB3 Power/Other FC38 G10 Power/Other FC38 C9 Power/Other FC39 AA2 Power/Other FC40 AM6 Power/Other

FERR#/PBE# R3 Asynch CMOS Output

GTLREF0 H1 Power/Other Input GTLREF1 H2 Power/Other Input

HIT# D4 Common Clock Input/Output

HITM# E4 Common Clock Input/Output

IERR# AB2 Asynch CMOS Output

IGNNE# N2 Asynch CMOS Input

INIT# P3 Asynch CMOS Input ITP_CLK0 AK3 TAP Input ITP_CLK1 AJ3 TAP Input

LINT0 K1 Asynch CMOS Input

LINT1 L1 Asynch CMOS Input LOCK# C3 Common Clock Input/Output MSID0 W1 Power/Other Output MSID1 V1 Power/Other Output

PECI G5 Power/Other Input/Output

PROCHOT# AL2 Asynch CMOS Input/Output

PWRGOOD N1 Power/Other Input

REQ0# K4 Source Synch Input/Output REQ1# J5 Source Synch Input/Output REQ2# M6 Source Synch Input/Output REQ3# K6 Source Synch Input/Output REQ4# J6 Source Synch Input/Output

RESERVED A20 RESERVED AC4 RESERVED AE4 RESERVED AE6 RESERVED AH2 RESERVED D1 RESERVED D14

Land #Signal Buffer

Type

Direction

Table 23. Alphabetical Land

Assignments

Land Name

RESERVED D16 RESERVED E23 RESERVED E6 RESERVED E7 RESERVED F23 RESERVED F29 RESERVED G6 RESERVED N4 RESERVED N5 RESERVED P5 RESERVED V2

RESET# G23 Common Clock Input

RS0# B3 Common Clock Input RS1# F5 Common Clock Input RS2# A3 Common Clock Input

SKTOCC# AE8 Power/Other Output

SMI# P2 Asynch CMOS Input

STPCLK# M3 Asynch CMOS Input

TCK AE1 TAP Input

TDI AD1 TAP Input

TDO AF1 TAP Output TESTHI0 F26 Power/Other Input TESTHI1 W3 Power/Other Input

TESTHI10 H5 Power/Other Input TESTHI11 P1 Power/Other Input

TESTHI12/

FC44

TESTHI13 L2 Power/Other Input

TESTHI2 F25 Power/Other Input TESTHI3 G25 Power/Other Input TESTHI4 G27 Power/Other Input TESTHI5 G26 Power/Other Input TESTHI6 G24 Power/Other Input TESTHI7 F24 Power/Other Input

TESTHI8/FC42 G3 Power/Other Input TESTHI9/FC43 G4 Power/Other Input

THERMDA AL1 Power/Other THERMDC AK1 Power/Other

THERMTRIP# M2 Asynch CMOS Output

TMS AC1 TAP Input

Land #Signal Buffer

W2 Power/Other Input

Type

Direction

50 Datasheet

Land Listing and Signal Descriptions

Table 23. Alphabetical Land

Assignments

Land Name

TRDY# E3 Common Clock Input TRST# AG1 TAP I nput

VCC AA8 Power/Other VCC AB8 Power/Other VCC AC23 Power/Other VCC AC24 Power/Other VCC AC25 Power/Other VCC AC26 Power/Other VCC AC27 Power/Other VCC AC28 Power/Other VCC AC29 Power/Other VCC AC30 Power/Other VCC AC8 Power/Other VCC AD23 Power/Other VCC AD24 Power/Other VCC AD25 Power/Other VCC AD26 Power/Other VCC AD27 Power/Other VCC AD28 Power/Other VCC AD29 Power/Other VCC AD30 Power/Other VCC AD8 Power/Other VCC AE11 Power/Other VCC AE12 Power/Other VCC AE14 Power/Other VCC AE15 Power/Other VCC AE18 Power/Other VCC AE19 Power/Other VCC AE21 Power/Other VCC AE22 Power/Other VCC AE23 Power/Other VCC AE9 Power/Other VCC AF11 Power/Other VCC AF12 Power/Other VCC AF14 Power/Other VCC AF15 Power/Other VCC AF18 Power/Other VCC AF19 Power/Other VCC AF21 Power/Other

Land #Signal Buffer

Type

Direction

Table 23. Alphabetical Land

Assignments

Land Name

VCC AF22 Power/Other VCC AF8 Power/Other VCC AF9 Power/Other VCC AG11 Power/Other VCC AG12 Power/Other VCC AG14 Power/Other VCC AG15 Power/Other VCC AG18 Power/Other VCC AG19 Power/Other VCC AG21 Power/Other VCC AG22 Power/Other VCC AG25 Power/Other VCC AG26 Power/Other VCC AG27 Power/Other VCC AG28 Power/Other VCC AG29 Power/Other VCC AG30 Power/Other VCC AG8 Power/Other VCC AG9 Power/Other VCC AH11 Power/Other VCC AH12 Power/Other VCC AH14 Power/Other VCC AH15 Power/Other VCC AH18 Power/Other VCC AH19 Power/Other VCC AH21 Power/Other VCC AH22 Power/Other VCC AH25 Power/Other VCC AH26 Power/Other VCC AH27 Power/Other VCC AH28 Power/Other VCC AH29 Power/Other VCC AH30 Power/Other VCC AH8 Power/Other VCC AH9 Power/Other VCC AJ11 Power/Other VCC AJ12 Power/Other VCC AJ14 Power/Other VCC AJ15 Power/Other

Land #Signal Buffer

Type

Direction

Datasheet 51

Land Listing and Signal Descriptions

Table 23. Alphabetical Land

Assignments

Land Name

VCC AJ18 Power/Other VCC AJ19 Power/Other VCC AJ21 Power/Other VCC AJ22 Power/Other VCC AJ25 Power/Other VCC AJ26 Power/Other VCC AJ8 Power/Other VCC AJ9 Power/Other VCC AK11 Power/Other VCC AK12 Power/Other VCC AK14 Power/Other VCC AK15 Power/Other VCC AK18 Power/Other VCC AK19 Power/Other VCC AK21 Power/Other VCC AK22 Power/Other VCC AK25 Power/Other VCC AK26 Power/Other VCC AK8 Power/Other VCC AK9 Power/Other VCC AL11 Power/Other VCC AL12 Power/Other VCC AL14 Power/Other VCC AL15 Power/Other VCC AL18 Power/Other VCC AL19 Power/Other VCC AL21 Power/Other VCC AL22 Power/Other VCC AL25 Power/Other VCC AL26 Power/Other VCC AL29 Power/Other VCC AL30 Power/Other VCC AL8 Power/Other VCC AL9 Power/Other VCC AM11 Power/Other VCC AM12 Power/Other VCC AM14 Power/Other VCC AM15 Power/Other VCC AM18 Power/Other

Land #Signal Buffer

Type

Direction

Table 23. Alphabetical Land

Assignments

Land Name

VCC AM19 Power/Other

VCC AM21 Power/Other

VCC AM22 Power/Other

VCC AM25 Power/Other

VCC AM26 Power/Other

VCC AM29 Power/Other

VCC AM30 Power/Other

VCC AM8 Power/Other

VCC AM9 Power/Other

VCC AN11 Power/Other

VCC AN12 Power/Other

VCC AN14 Power/Other

VCC AN15 Power/Other

VCC AN18 Power/Other

VCC AN19 Power/Other

VCC AN21 Power/Other

VCC AN22 Power/Other

VCC AN25 Power/Other

VCC AN26 Power/Other

VCC AN29 Power/Other

VCC AN30 Power/Other

VCC AN8 Power/Other

VCC AN9 Power/Other

VCC J10 Power/Other

VCC J11 Power/Other

VCC J12 Power/Other

VCC J13 Power/Other

VCC J14 Power/Other

VCC J15 Power/Other

VCC J18 Power/Other

VCC J19 Power/Other

VCC J20 Power/Other

VCC J21 Power/Other

VCC J22 Power/Other

VCC J23 Power/Other

VCC J24 Power/Other

VCC J25 Power/Other

VCC J26 Power/Other

VCC J27 Power/Other

Land #Signal Buffer

Type

Direction

52 Datasheet

Land Listing and Signal Descriptions

Table 23. Alphabetical Land

Assignments

Land Name

VCC J28 Power/Other VCC J29 Power/Other VCC J30 Power/Other VCC J8 Power/Other VCC J9 Power/Other VCC K23 Power/Other VCC K24 Power/Other VCC K25 Power/Other VCC K26 Power/Other VCC K27 Power/Other VCC K28 Power/Other VCC K29 Power/Other VCC K30 Power/Other VCC K8 Power/Other VCC L8 Power/Other VCC M23 Power/Other VCC M24 Power/Other VCC M25 Power/Other VCC M26 Power/Other VCC M27 Power/Other VCC M28 Power/Other VCC M29 Power/Other VCC M30 Power/Other VCC M8 Power/Other VCC N23 Power/Other VCC N24 Power/Other VCC N25 Power/Other VCC N26 Power/Other VCC N27 Power/Other VCC N28 Power/Other VCC N29 Power/Other VCC N30 Power/Other VCC N8 Power/Other VCC P8 Power/Other VCC R8 Power/Other VCC T23 Power/Other VCC T24 Power/Other VCC T25 Power/Other VCC T26 Power/Other

Land #Signal Buffer

Type

Direction

Table 23. Alphabetical Land

Assignments

Land Name

VCC T27 Power/Other VCC T28 Power/Other VCC T29 Power/Other VCC T30 Power/Other VCC T8 Power/Other VCC U23 Power/Other VCC U24 Power/Other VCC U25 Power/Other VCC U26 Power/Other VCC U27 Power/Other VCC U28 Power/Other VCC U29 Power/Other VCC U30 Power/Other VCC U8 Power/Other VCC V8 Power/Other VCC W23 Power/Other VCC W24 Power/Other VCC W25 Power/Other VCC W26 Power/Other VCC W27 Power/Other VCC W28 Power/Other VCC W29 Power/Other VCC W30 Power/Other VCC W8 Power/Other VCC Y23 Power/Other VCC Y24 Power/Other VCC Y25 Power/Other VCC Y26 Power/Other VCC Y27 Power/Other VCC Y28 Power/Other VCC Y29 Power/Other VCC Y30 Power/Other VCC Y8 Power/Other

VCC_MB_

REGULATION

VCC_SENSE AN3 Power/Other Output

VCCA A23 Power/Other

VCCIOPLL C23 Power/Other

VCCPLL D23 Power/Other

VID_SELECT AN7 Power/Other O utput

Land #Signal Buffer

Type

AN5 Power/Other Output

Direction

Datasheet 53

Land Listing and Signal Descriptions

Table 23. Alphabetical Land

Assignments

Land Name

VID0 AM2 Power/Other Output VID1 AL5 Power/Other Output VID2 AM3 Power/Other Output VID3 AL6 Power/Other Output VID4 AK4 Power/Other Output VID5 AL4 Power/Other Output VID6 AM5 Power/Other Output VID7 AM7 Power/Other Output

VRDSEL AL3 Power/Other

VSS A12 Power/Other VSS A15 Power/Other VSS A18 Power/Other VSS A2 Power/Other VSS A21 Power/Other VSS A6 Power/Other VSS A9 Power/Other VSS AA23 Power/Other VSS AA24 Power/Other VSS AA25 Power/Other VSS AA26 Power/Other VSS AA27 Power/Other VSS AA28 Power/Other VSS AA29 Power/Other VSS AA3 Power/Other VSS AA30 Power/Other VSS AA6 Power/Other VSS AA7 Power/Other VSS AB1 Power/Other VSS AB23 Power/Other VSS AB24 Power/Other VSS AB25 Power/Other VSS AB26 Power/Other VSS AB27 Power/Other VSS AB28 Power/Other VSS AB29 Power/Other VSS AB30 Power/Other VSS AB7 Power/Other VSS AC3 Power/Other VSS AC6 Power/Other

Land #Signal Buffer

Type

Direction

Table 23. Alphabetical Land

Assignments

Land Name

VSS AC7 Power/Other

VSS AD4 Power/Other

VSS AD7 Power/Other

VSS AE10 Power/Other

VSS AE13 Power/Other

VSS AE16 Power/Other

VSS AE17 Power/Other

VSS AE2 Power/Other

VSS AE20 Power/Other

VSS AE24 Power/Other

VSS AE25 Power/Other

VSS AE26 Power/Other

VSS AE27 Power/Other

VSS AE28 Power/Other

VSS AE29 Power/Other

VSS AE30 Power/Other

VSS AE5 Power/Other

VSS AE7 Power/Other

VSS AF10 Power/Other

VSS AF13 Power/Other

VSS AF16 Power/Other

VSS AF17 Power/Other

VSS AF20 Power/Other

VSS AF23 Power/Other

VSS AF24 Power/Other

VSS AF25 Power/Other

VSS AF26 Power/Other

VSS AF27 Power/Other

VSS AF28 Power/Other

VSS AF29 Power/Other

VSS AF3 Power/Other

VSS AF30 Power/Other

VSS AF6 Power/Other

VSS AF7 Power/Other

VSS AG10 Power/Other

VSS AG13 Power/Other

VSS AG16 Power/Other

VSS AG17 Power/Other

VSS AG20 Power/Other

Land #Signal Buffer

Type

Direction

54 Datasheet

Land Listing and Signal Descriptions

Table 23. Alphabetical Land

Assignments

Land Name

VSS AG23 Power/Other VSS AG24 Power/Other VSS AG7 Power/Other VSS AH1 Power/Other VSS AH10 Power/Other VSS AH13 Power/Other VSS AH16 Power/Other VSS AH17 Power/Other VSS AH20 Power/Other VSS AH23 Power/Other VSS AH24 Power/Other VSS AH3 Power/Other VSS AH6 Power/Other VSS AH7 Power/Other VSS AJ10 Power/Other VSS AJ13 Power/Other VSS AJ16 Power/Other VSS AJ17 Power/Other VSS AJ20 Power/Other VSS AJ23 Power/Other VSS AJ24 Power/Other VSS AJ27 Power/Other VSS AJ28 Power/Other VSS AJ29 Power/Other VSS AJ30 Power/Other VSS AJ4 Power/Other VSS AJ7 Power/Other VSS AK10 Power/Other VSS AK13 Power/Other VSS AK16 Power/Other VSS AK17 Power/Other VSS AK2 Power/Other VSS AK20 Power/Other VSS AK23 Power/Other VSS AK24 Power/Other VSS AK27 Power/Other VSS AK28 Power/Other VSS AK29 Power/Other VSS AK30 Power/Other

Land #Signal Buffer

Type

Direction

Table 23. Alphabetical Land

Assignments

Land Name

VSS AK5 Power/Other VSS AK7 Power/Other VSS AL10 Power/Other VSS AL13 Power/Other VSS AL16 Power/Other VSS AL17 Power/Other VSS AL20 Power/Other VSS AL23 Power/Other VSS AL24 Power/Other VSS AL27 Power/Other VSS AL28 Power/Other VSS AL7 Power/Other VSS AM1 Power/Other VSS AM10 Power/Other VSS AM13 Power/Other VSS AM16 Power/Other VSS AM17 Power/Other VSS AM20 Power/Other VSS AM23 Power/Other VSS AM24 Power/Other VSS AM27 Power/Other VSS AM28 Power/Other VSS AM4 Power/Other VSS AN1 Power/Other VSS AN10 Power/Other VSS AN13 Power/Other VSS AN16 Power/Other VSS AN17 Power/Other VSS AN2 Power/Other VSS AN20 Power/Other VSS AN23 Power/Other VSS AN24 Power/Other VSS AN27 Power/Other VSS AN28 Power/Other VSS B1 Power/Other VSS B11 Power/Other VSS B14 Power/Other VSS B17 Power/Other VSS B20 Power/Other

Land #Signal Buffer

Type

Direction

Datasheet 55

Land Listing and Signal Descriptions

Table 23. Alphabetical Land

Assignments

Land Name

VSS B24 Power/Other VSS B5 Power/Other VSS B8 Power/Other VSS C10 Power/Other VSS C13 Power/Other VSS C16 Power/Other VSS C19 Power/Other VSS C22 Power/Other VSS C24 Power/Other VSS C4 Power/Other VSS C7 Power/Other VSS D12 Power/Other VSS D15 Power/Other VSS D18 Power/Other VSS D21 Power/Other VSS D24 Power/Other VSS D3 Power/Other VSS D5 Power/Other VSS D6 Power/Other VSS D9 Power/Other VSS E11 Power/Other VSS E14 Power/Other VSS E17 Power/Other VSS E2 Power/Other VSS E20 Power/Other VSS E25 Power/Other VSS E26 Power/Other VSS E27 Power/Other VSS E28 Power/Other VSS E8 Power/Other VSS F10 Power/Other VSS F13 Power/Other VSS F16 Power/Other VSS F19 Power/Other VSS F22 Power/Other VSS F4 Power/Other VSS F7 Power/Other VSS H10 Power/Other VSS H11 Power/Other

Land #Signal Buffer

Type

Direction

Table 23. Alphabetical Land

Assignments

Land Name

VSS H12 Power/Other

VSS H13 Power/Other

VSS H14 Power/Other

VSS H17 Power/Other

VSS H18 Power/Other

VSS H19 Power/Other

VSS H20 Power/Other

VSS H21 Power/Other

VSS H22 Power/Other

VSS H23 Power/Other

VSS H24 Power/Other

VSS H25 Power/Other

VSS H26 Power/Other

VSS H27 Power/Other

VSS H28 Power/Other

VSS H3 Power/Other

VSS H6 Power/Other

VSS H7 Power/Other

VSS H8 Power/Other

VSS H9 Power/Other

VSS J4 Power/Other

VSS J7 Power/Other

VSS K2 Power/Other

VSS K5 Power/Other

VSS K7 Power/Other

VSS L23 Power/Other

VSS L24 Power/Other

VSS L25 Power/Other

VSS L26 Power/Other

VSS L27 Power/Other

VSS L28 Power/Other

VSS L29 Power/Other

VSS L3 Power/Other

VSS L30 Power/Other

VSS L6 Power/Other

VSS L7 Power/Other

VSS M1 Power/Other

VSS M7 Power/Other

VSS N3 Power/Other

Land #Signal Buffer

Type

Direction

56 Datasheet

Land Listing and Signal Descriptions

Table 23. Alphabetical Land

Assignments

Land Name

VSS N6 Power/Other VSS N7 Power/Other VSS P23 Power/Other VSS P24 Power/Other VSS P25 Power/Other VSS P26 Power/Other VSS P27 Power/Other VSS P28 Power/Other VSS P29 Power/Other VSS P30 Power/Other VSS P4 Power/Other VSS P7 Power/Other VSS R2 Power/Other VSS R23 Power/Other VSS R24 Power/Other VSS R25 Power/Other VSS R26 Power/Other VSS R27 Power/Other VSS R28 Power/Other VSS R29 Power/Other VSS R30 Power/Other VSS R5 Power/Other VSS R7 Power/Other VSS T3 Power/Other VSS T6 Power/Other VSS T7 Power/Other VSS U7 Power/Other VSS V23 Power/Other VSS V24 Power/Other VSS V25 Power/Other VSS V26 Power/Other VSS V27 Power/Other VSS V28 Power/Other VSS V29 Power/Other VSS V3 Power/Other VSS V30 Power/Other VSS V6 Power/Other VSS V7 Power/Other VSS W4 Power/Other

Land #Signal Buffer

Type

Direction

Table 23. Alphabetical Land

Assignments

Land Name

VSS W7 Power/Other VSS Y2 Power/Other VSS Y5 Power/Other VSS Y7 Power/Other

VSS_MB_

REGULATION

VSS_SENSE AN4 Power/Other Output

VSSA B23 Power/Other

VTT A25 Power/Other VTT A26 Power/Other VTT A27 Power/Other VTT A28 Power/Other VTT A29 Power/Other VTT A30 Power/Other VTT B25 Power/Other VTT B26 Power/Other VTT B27 Power/Other VTT B28 Power/Other VTT B29 Power/Other VTT B30 Power/Other VTT C25 Power/Other VTT C26 Power/Other VTT C27 Power/Other VTT C28 Power/Other VTT C29 Power/Other VTT C30 Power/Other VTT D25 Power/Other VTT D26 Power/Other VTT D27 Power/Other VTT D28 Power/Other VTT D29 Power/Other VTT D30 Power/Other

VTT_OUT_LEFT J1 Power/Other Output

VTT_OUT_RIG

VTT_SEL F27 Power/Other Output

Land #Signal Buffer

Type

AN6 Power/Other Output

AA1 Power/Other Output

Direction

Datasheet 57

Land Listing and Signal Descriptions

Table 24. Numerical Land

Assignment

Land

Land Name

A2 VSS Power/Other A3 RS2# Common Clock Input A4 D02# Source Synch Input/Output A5 D04# Source Synch Input/Output A6 VSS Power/Other A7 D07# Source Synch Input/Output A8 DBI0# Source Synch Input/Output

A9 VSS Power/Other A10 D08# Source Synch Input/Output A11 D09# Source Synch Input/Output A12 VSS Power/Other A13 COMP0 Power/Other Input A14 D50# Source Synch Input/Output A15 VSS Power/Other A16 DSTBN3# Source Synch Input/Output A17 D56# Source Synch Input/Output A18 VSS Power/Other A19 D61# Source Synch Input/Output A20 RESERVED A21 VSS Power/Other A22 D62# Source Synch Input/Output A23 VCCA Power/Other A24 FC23 Power/Other A25 VTT Power/Other A26 VTT Power/Other A27 VTT Power/Other A28 VTT Power/Other A29 VTT Power/Other A30 VTT Power/Other

B1 VSS Power/Other

B2 DBSY# Common Clock Input/Output

B3 RS0# Common Clock Input

B4 D00# Source Synch Input/Output

B5 VSS Power/Other

B6 D05# Source Synch Input/Output

B7 D06# Source Synch Input/Output

B8 VSS Power/Other

B9 DSTBP0# Source Synch Input/Output B10 D10# Source Synch Input/Output

Signal Buffer

Type

Direction

Table 24. Numerical Land

Assignment

Land

Land Name

B11 VSS Power/Other B12 D13# Source Synch Input/Output B13 COMP8 Power/Other Input B14 VSS Power/Other B15 D53# Source Synch Input/Output B16 D55# Source Synch Input/Output B17 VSS Power/Other B18 D57# Source Synch Input/Output B19 D60# Source Synch Input/Output B20 VSS Power/Other B21 D59# Source Synch Input/Output B22 D63# Source Synch Input/Output B23 VSSA Power/Other B24 VSS Power/Other B25 VTT Power/Other B26 VTT Power/Other B27 VTT Power/Other B28 VTT Power/Other B29 VTT Power/Other B30 VTT Power/Other

C1 DRDY# Common Clock Input/Output C2 BNR# Common Clock Input/Output C3 LOCK# Common Clock Input/Output C4 VSS Power/Other C5 D01# Source Synch Input/Output C6 D03# Source Synch Input/Output C7 VSS Power/Other C8 DSTBN0# Source Synch Input/Output

C9 FC38 Power/Other C10 VSS Power/Other C11 D11# Source Synch Input/Output C12 D14# Source Synch Input/Output C13 VSS Power/Other C14 D52# Source Synch Input/Output C15 D51# Source Synch Input/Output C16 VSS Power/Other C17 DSTBP3# Source Synch Input/Output C18 D54# Source Synch Input/Output C19 VSS Power/Other

Signal Buffer

Type

Direction

58 Datasheet

Land Listing and Signal Descriptions

Table 24. Numerical Land

Assignment

Land

Land Name

C20 DBI3# Source Synch Input/Output C21 D58# Source Synch Input/Output C22 VSS Power/Other C23 VCCIOPLL Power/Other C24 VSS Power/Other C25 VTT Power/Other C26 VTT Power/Other C27 VTT Power/Other C28 VTT Power/Other C29 VTT Power/Other C30 VTT Power/Other

D1 RESERVED D2 ADS# Common Clock Input/Output D3 VSS Power/Other D4 HIT# Common Clock Input/Output D5 VSS Power/Other D6 VSS Power/Other D7 D20# Source Synch Input/Output D8 D12# Source Synch Input/Output

D9 VSS Power/Other D10 D22# Source Synch Input/Output D11 D15# Source Synch Input/Output D12 VSS Power/Other D13 D25# Source Synch Input/Output D14 RESERVED D15 VSS Power/Other D16 RESERVED D17 D49# Source Synch Input/Output D18 VSS Power/Other D19 DBI2# Source Synch Input/Output D20 D48# Source Synch Input/Output D21 VSS Power/Other D22 D46# Source Synch Input/Output D23 VCCPLL Power/Other D24 VSS Power/Other D25 VTT Power/Other D26 VTT Power/Other D27 VTT Power/Other D28 VTT Power/Other

Signal Buffer

Type

Direction

Table 24. Numerical Land

Assignment

Land

Land Name

D29 VTT Power/Other D30 VTT Power/Other

E2 VSS Power/Other E3 TRDY# Common Clock Input E4 HITM# Common Clock Input/Output E5 FC20 Power/Other E6 RESERVED E7 RESERVED E8 VSS Power/Other

E9 D19# Source Synch Input/Output E10 D21# Source Synch Input/Output E11 VSS Power/Other E12 DSTBP1# Source Synch Input/Output E13 D26# Source Synch Input/Output E14 VSS Power/Other E15 D33# Source Synch Input/Output E16 D34# Source Synch Input/Output E17 VSS Power/Other E18 D39# Source Synch Input/Output E19 D40# Source Synch Input/Output E20 VSS Power/Other E21 D42# Source Synch Input/Output E22 D45# Source Synch Input/Output E23 RESERVED E24 FC10 Power/Other E25 VSS Power/Other E26 VSS Power/Other E27 VSS Power/Other E28 VSS Power/Other E29 FC26 Power/Other

F2 FC5 Power/Other

F3 BR0# Common Clock Input/Output

F4 VSS Power/Other

F5 RS1# Common Clock Input

F6 FC21 Power/Other

F7 VSS Power/Other

F8 D17# Source Synch Input/Output

F9 D18# Source Synch Input/Output F10 VSS Power/Other

Signal Buffer

Type

Direction

Datasheet 59

Land Listing and Signal Descriptions

Table 24. Numerical Land

Assignment

Land

Land Name

F11 D23# Source Synch Input/Output F12 D24# Source Synch Input/Output F13 VSS Power/Other F14 D28# Source Synch Input/Output F15 D30# Source Synch Input/Output F16 VSS Power/Other F17 D37# Source Synch Input/Output F18 D38# Source Synch Input/Output F19 VSS Power/Other F20 D41# Source Synch Input/Output F21 D43# Source Synch Input/Output F22 VSS Power/Other F23 RESERVED F24 TESTHI7 Power/Other Input F25 TESTHI2 Power/Other Input F26 TESTHI0 Power/Other Input F27 VTT_SEL Power/Other Output F28 BCLK0 Clock Input F29 RESERVED

G1 FC27 Power/Other G2 COMP2 Power/Other Input G3 TESTHI8/FC42 Power/Other Input G4 TESTHI9/FC43 Power/Other Input G5 PECI Power/Other Input/Output G6 RESERVED G7 DEFER# Common Clock Input G8 BPRI# Common Clock Input

G9 D16# Source Synch Input/Output G10 FC38 Power/Other G11 DBI1# Source Synch Input/Output G12 DSTBN1# Source Synch Input/Output G13 D27# Source Synch Input/Output G14 D29# Source Synch Input/Output G15 D31# Source Synch Input/Output G16 D32# Source Synch Input/Output G17 D36# Source Synch Input/Output G18 D35# Source Synch Input/Output G19 DSTBP2# Source Synch Input/Output G20 DSTBN2# Source Synch Input/Output

Signal Buffer

Type

Direction

Table 24. Numerical Land

Assignment

Land

G21 D44# Source Synch Input/Output G22 D47# Source Synch Input/Output G23 RESET# Common Clock Input G24 TESTHI6 Power/Other Input G25 TESTHI3 Power/Other Input G26 TESTHI5 Power/Other Input G27 TESTHI4 Power/Other Input G28 BCLK1 Clock Input G29 BSEL0 Power/Other Output G30 BSEL2 Power/Other Output

Land Name

H1 GTLREF0 Power/Other Input H2 GTLREF1 Power/Other Input H3 VSS Power/Other H4 FC35 Power/Other H5 TESTHI10 Power/Other Input H6 VSS Power/Other H7 VSS Power/Other H8 VSS Power/Other

H9 VSS Power/Other H10 VSS Power/Other H11 VSS Power/Other H12 VSS Power/Other H13 VSS Power/Other H14 VSS Power/Other H15 FC32 Power/Other H16 FC33 Power/Other H17 VSS Power/Other H18 VSS Power/Other H19 VSS Power/Other H20 VSS Power/Other H21 VSS Power/Other H22 VSS Power/Other H23 VSS Power/Other H24 VSS Power/Other H25 VSS Power/Other H26 VSS Power/Other H27 VSS Power/Other H28 VSS Power/Other H29 FC15 Power/Other

Signal Buffer

Type

Direction

60 Datasheet

Land Listing and Signal Descriptions

Table 24. Numerical Land

Assignment

Land

Land Name

H30 BSEL1 Power/Other Output

J1 VTT_OUT_LEFT Power/Other Output J2 FC3 Power/Other J3 FC22 Power/Other J4 VSS Power/Other J5 REQ1# Source Synch Input/Output J6 REQ4# Source Synch Input/Output J7 VSS Power/Other J8 VCC Power/Other

J9 VCC Power/Other J10 VCC Power/Other J11 VCC Power/Other J12 VCC Power/Other J13 VCC Power/Other J14 VCC Power/Other J15 VCC Power/Other J16 FC31 Power/Other J17 FC34 Power/Other J18 VCC Power/Other J19 VCC Power/Other J20 VCC Power/Other J21 VCC Power/Other J22 VCC Power/Other J23 VCC Power/Other J24 VCC Power/Other J25 VCC Power/Other J26 VCC Power/Other J27 VCC Power/Other J28 VCC Power/Other J29 VCC Power/Other J30 VCC Power/Other

K1 LINT0 Asynch CMOS Input K2 VSS Power/Other K3 A20M# Asynch CMOS Input K4 REQ0# Source Synch Input/Output K5 VSS Power/Other K6 REQ3# Source Synch Input/Output K7 VSS Power/Other K8 VCC Power/Other

Signal Buffer

Type

Direction

Table 24. Numerical Land

Assignment

Land

Land Name

K23 VCC Power/Other K24 VCC Power/Other K25 VCC Power/Other K26 VCC Power/Other K27 VCC Power/Other K28 VCC Power/Other K29 VCC Power/Other K30 VCC Power/Other

L1 LINT1 Asynch CMOS Input L2 TESTHI13 Power/Other Input L3 VSS Power/Other L4 A06# Source Synch Input/Output L5 A03# Source Synch Input/Output L6 VSS Power/Other L7 VSS Power/Other

L8 VCC Power/Other L23 VSS Power/Other L24 VSS Power/Other L25 VSS Power/Other L26 VSS Power/Other L27 VSS Power/Other L28 VSS Power/Other L29 VSS Power/Other L30 VSS Power/Other

M1 VSS Power/Other M2 THERMTRIP# Asynch CMOS Output M3 STPCLK# Asynch CMOS Input M4 A0 7# Source Synch Input/Output M5 A0 5# Source Synch Input/Output M6 REQ2# Source Synch Input/Output M7 VSS Power/Other

M8 VCC Power/Other M23 VCC Power/Other M24 VCC Power/Other M25 VCC Power/Other M26 VCC Power/Other M27 VCC Power/Other M28 VCC Power/Other M29 VCC Power/Other

Signal Buffer

Type

Direction

Datasheet 61

Land Listing and Signal Descriptions

Table 24. Numerical Land

Assignment

Land

Land Name

M30 VCC Power/Other

N1 PWRGOOD Power/Other Input N2 IGNNE# Asynch CMOS Input N3 VSS Power/Other N4 RESERVED N5 RESERVED N6 VSS Power/Other N7 VSS Power/Other

N8 VCC Power/Other N23 VCC Power/Other N24 VCC Power/Other N25 VCC Power/Other N26 VCC Power/Other N27 VCC Power/Other N28 VCC Power/Other N29 VCC Power/Other N30 VCC Power/Other

P1 TESTHI11 Power/Other Input

P2 SMI# Asynch CMOS Input

P3 INIT# Asynch CMOS Input

P4 VSS Power/Other

P5 RESERVED

P6 A04# Source Synch Input/Output

P7 VSS Power/Other

P8 VCC Power/Other P23 VSS Power/Other P24 VSS Power/Other P25 VSS Power/Other P26 VSS Power/Other P27 VSS Power/Other P28 VSS Power/Other P29 VSS Power/Other P30 VSS Power/Other

R1 COMP3 Power/Other Input

R2 VSS Power/Other

R3 FERR#/PBE# Asynch CMOS Output

R4 A08# Source Synch Input/Output

R5 VSS Power/Other

R6 ADSTB0# Source Synch Input/Output

Signal Buffer

Type

Direction

Table 24. Numerical Land

Assignment

Land

Land Name

R7 VSS Power/Other

R8 VCC Power/Other R23 VSS Power/Other R24 VSS Power/Other R25 VSS Power/Other R26 VSS Power/Other R27 VSS Power/Other R28 VSS Power/Other R29 VSS Power/Other R30 VSS Power/Other

T1 COMP1 Power/Other Input

T2 FC4 Power/Other

T3 VSS Power/Other

T4 A11# Source Synch Input/Output

T5 A09# Source Synch Input/Output

T6 VSS Power/Other

T7 VSS Power/Other

T8 VCC Power/Other T23 VCC Power/Other T24 VCC Power/Other T25 VCC Power/Other T26 VCC Power/Other T27 VCC Power/Other T28 VCC Power/Other T29 VCC Power/Other T30 VCC Power/Other

U1 FC28 Power/Other

U2 FC29 Power/Other

U3 FC30 Power/Other

U4 A13# Source Synch Input/Output

U5 A12# Source Synch Input/Output

U6 A10# Source Synch Input/Output

U7 VSS Power/Other

U8 VCC Power/Other U23 VCC Power/Other U24 VCC Power/Other U25 VCC Power/Other U26 VCC Power/Other U27 VCC Power/Other

Signal Buffer

Type

Direction

62 Datasheet

Land Listing and Signal Descriptions

Table 24. Numerical Land

Assignment

Land

Land Name

U28 VCC Power/Other U29 VCC Power/Other U30 VCC Power/Other

V1 MSID1 Power/Other Output V2 RESERVED V3 VSS Power/Other V4 A15# Source Synch Input/Output V5 A14# Source Synch Input/Output V6 VSS Power/Other V7 VSS Power/Other

V8 VCC Power/Other V23 VSS Power/Other V24 VSS Power/Other V25 VSS Power/Other V26 VSS Power/Other V27 VSS Power/Other V28 VSS Power/Other V29 VSS Power/Other V30 VSS Power/Other

W1 MSID0 Power/Other Output W2 TESTHI12/FC44 Power/Other Input W3 TESTHI1 Power/Other Input W4 VSS Power/Other W5 A16# Source Synch Input/Output W6 A18# Source Synch Input/Output W7 VSS Power/Other

W8 VCC Power/Other W23 VCC Power/Other W24 VCC Power/Other W25 VCC Power/Other W26 VCC Power/Other W27 VCC Power/Other W28 VCC Power/Other W29 VCC Power/Other W30 VCC Power/Other

Y1 FC0 Power/Other Y2 VSS Power/Other Y3 FC17 Power/Other Y4 A20# Source Synch Input/Output

Signal Buffer

Type

Direction

Table 24. Numerical Land

Assignment

Land

AA23 VSS Power/Other AA24 VSS Power/Other AA25 VSS Power/Other AA26 VSS Power/Other AA27 VSS Power/Other AA28 VSS Power/Other AA29 VSS Power/Other AA30 VSS Power/Other

AB23 VSS Power/Other AB24 VSS Power/Other AB25 VSS Power/Other

Land Name

Y5 VSS Power/Other Y6 A19# Source Synch Input/Output Y7 VSS Power/Other

Y8 VCC Power/Other Y23 VCC Power/Other Y24 VCC Power/Other Y25 VCC Power/Other Y26 VCC Power/Other Y27 VCC Power/Other Y28 VCC Power/Other Y29 VCC Power/Other Y30 VCC Power/Other AA1 VTT_OUT_RIGHT Power/Other Output AA2 FC39 Power/Other AA3 VSS Power/Other AA4 A21# Source Synch Input/Output AA5 A23# Source Synch Input/Output AA6 VSS Power/Other AA7 VSS Power/Other AA8 VCC Power/Other

AB1 VSS Power/Other AB2 IERR# Asynch CMOS Output AB3 FC37 Power/Other AB4 A26# Source Synch Input/Output AB5 A24# Source Synch Input/Output AB6 A17# Source Synch Input/Output AB7 VSS Power/Other AB8 VCC Power/Other

Signal Buffer

Type

Direction

Datasheet 63

Land Listing and Signal Descriptions

Table 24. Numerical Land

Assignment

Land

AB26 VSS Power/Other AB27 VSS Power/Other AB28 VSS Power/Other AB29 VSS Power/Other AB30 VSS Power/Other

AC23 VCC Power/Other AC24 VCC Power/Other AC25 VCC Power/Other AC26 VCC Power/Other AC27 VCC Power/Other AC28 VCC Power/Other AC29 VCC Power/Other AC30 VCC Power/Other

AD23 VCC Power/Other AD24 VCC Power/Other AD25 VCC Power/Other AD26 VCC Power/Other AD27 VCC Power/Other AD28 VCC Power/Other AD29 VCC Power/Other AD30 VCC Power/Other

Land Name

AC1 TMS TAP Input AC2 DBR# Power/Other Output AC3 VSS Power/Other AC4 RESERVED AC5 A25# Source Synch Input/Output AC6 VSS Power/Other AC7 VSS Power/Other AC8 VCC Power/Other

AD1 TDI TAP Input AD2 BPM2# Common Clock Input/Output AD3 FC36 Power/Other AD4 VSS Power/Other AD5 ADSTB1# Source Synch Input/Output AD6 A22# Source Synch Input/Output AD7 VSS Power/Other AD8 VCC Power/Other

AE1 TCK TAP Input AE2 VSS Power/Other

Signal Buffer

Type

Direction

Table 24. Numerical Land

Assignment

Land

AE10 VSS Power/Other AE11 VCC Power/Other AE12 VCC Power/Other AE13 VSS Power/Other AE14 VCC Power/Other AE15 VCC Power/Other AE16 VSS Power/Other AE17 VSS Power/Other AE18 VCC Power/Other AE19 VCC Power/Other AE20 VSS Power/Other AE21 VCC Power/Other AE22 VCC Power/Other AE23 VCC Power/Other AE24 VSS Power/Other AE25 VSS Power/Other AE26 VSS Power/Other AE27 VSS Power/Other AE28 VSS Power/Other AE29 VSS Power/Other AE30 VSS Power/Other

AF10 VSS Power/Other AF11 VCC Power/Other

Land Name

AE3 FC18 Power/Other AE4 RESERVED AE5 VSS Power/Other AE6 RESERVED AE7 VSS Power/Other AE8 SKTOCC# Power/Other Output AE9 VCC Power/Other

AF1 TDO TAP Output AF2 BPM4# Common Clock Input/Output AF3 VSS Power/Other AF4 A28# Source Synch Input/Output AF5 A27# Source Synch Input/Output AF6 VSS Power/Other AF7 VSS Power/Other AF8 VCC Power/Other AF9 VCC Power/Other

Signal Buffer

Type

Direction

64 Datasheet

Land Listing and Signal Descriptions

Table 24. Numerical Land

Assignment

Land

AF12 VCC Power/Other AF13 VSS Power/Other AF14 VCC Power/Other AF15 VCC Power/Other AF16 VSS Power/Other AF17 VSS Power/Other AF18 VCC Power/Other AF19 VCC Power/Other AF20 VSS Power/Other AF21 VCC Power/Other AF22 VCC Power/Other AF23 VSS Power/Other AF24 VSS Power/Other AF25 VSS Power/Other AF26 VSS Power/Other AF27 VSS Power/Other AF28 VSS Power/Other AF29 VSS Power/Other AF30 VSS Power/Other

AG10 VSS Power/Other AG11 VCC Power/Other AG12 VCC Power/Other AG13 VSS Power/Other AG14 VCC Power/Other AG15 VCC Power/Other AG16 VSS Power/Other AG17 VSS Power/Other AG18 VCC Power/Other AG19 VCC Power/Other AG20 VSS Power/Other

Land Name

AG1 TRST# TAP Input AG2 BPM3# Common Clock Input/Output AG3 BPM5# Common Clock Input/Output AG4 A30# Source Synch Input/Output AG5 A31# Source Synch Input/Output AG6 A29# Source Synch Input/Output AG7 VSS Power/Other AG8 VCC Power/Other AG9 VCC Power/Other

Signal Buffer

Type

Direction

Table 24. Numerical Land

Assignment

Land

AG21 VCC Power/Other AG22 VCC Power/Other AG23 VSS Power/Other AG24 VSS Power/Other AG25 VCC Power/Other AG26 VCC Power/Other AG27 VCC Power/Other AG28 VCC Power/Other AG29 VCC Power/Other AG30 VCC Power/Other

AH10 VSS Power/Other AH11 VCC Power/Other AH12 VCC Power/Other AH13 VSS Power/Other AH14 VCC Power/Other AH15 VCC Power/Other AH16 VSS Power/Other AH17 VSS Power/Other AH18 VCC Power/Other AH19 VCC Power/Other AH20 VSS Power/Other AH21 VCC Power/Other AH22 VCC Power/Other AH23 VSS Power/Other AH24 VSS Power/Other AH25 VCC Power/Other AH26 VCC Power/Other AH27 VCC Power/Other AH28 VCC Power/Other AH29 VCC Power/Other

Land Name

AH1 VSS Power/Other AH2 RESERVED AH3 VSS Power/Other AH4 A32# Source Synch Input/Output AH5 A33# Source Synch Input/Output AH6 VSS Power/Other AH7 VSS Power/Other AH8 VCC Power/Other AH9 VCC Power/Other

Signal Buffer

Type

Direction

Datasheet 65

Land Listing and Signal Descriptions

Table 24. Numerical Land

Assignment

Land

AH30 VCC Power/Other

AJ10 VSS Power/Other AJ11 VCC Power/Other AJ12 VCC Power/Other AJ13 VSS Power/Other AJ14 VCC Power/Other AJ15 VCC Power/Other AJ16 VSS Power/Other AJ17 VSS Power/Other AJ18 VCC Power/Other AJ19 VCC Power/Other AJ20 VSS Power/Other AJ21 VCC Power/Other AJ22 VCC Power/Other AJ23 VSS Power/Other AJ24 VSS Power/Other AJ25 VCC Power/Other AJ26 VCC Power/Other AJ27 VSS Power/Other AJ28 VSS Power/Other AJ29 VSS Power/Other AJ30 VSS Power/Other

Land Name

AJ1 BPM1# Common Clock Input/Output AJ2 BPM0# Common Clock Input/Output AJ3 ITP_CLK1 TAP Input AJ4 VSS Power/Other AJ5 A34# Source Synch Input/Output AJ6 A35# Source Synch Input/Output AJ7 VSS Power/Other AJ8 VCC Power/Other AJ9 VCC Power/Other

AK1 THERMDC Power/Other AK2 VSS Power/Other AK3 ITP_CLK0 TAP Input AK4 VID4 Power/Other Output AK5 VSS Power/Other AK6 FC8 Power/Other AK7 VSS Power/Other AK8 VCC Power/Other

Signal Buffer

Type

Direction

Table 24. Numerical Land

Assignment

Land

AK10 VSS Power/Other AK11 VCC Power/Other AK12 VCC Power/Other AK13 VSS Power/Other AK14 VCC Power/Other AK15 VCC Power/Other AK16 VSS Power/Other AK17 VSS Power/Other AK18 VCC Power/Other AK19 VCC Power/Other AK20 VSS Power/Other AK21 VCC Power/Other AK22 VCC Power/Other AK23 VSS Power/Other AK24 VSS Power/Other AK25 VCC Power/Other AK26 VCC Power/Other AK27 VSS Power/Other AK28 VSS Power/Other AK29 VSS Power/Other AK30 VSS Power/Other

AL10 VSS Power/Other AL11 VCC Power/Other AL12 VCC Power/Other AL13 VSS Power/Other AL14 VCC Power/Other AL15 VCC Power/Other AL16 VSS Power/Other AL17 VSS Power/Other

Land Name

AK9 VCC Power/Other

AL1 THERMDA Power/Other AL2 PROCHOT# Asynch CMOS Input/Output AL3 VRDSEL Power/Other AL4VID5Power/OtherOutput AL5VID1Power/OtherOutput AL6VID3Power/OtherOutput AL7 VSS Power/Other AL8 VCC Power/Other AL9 VCC Power/Other

Signal Buffer

Type

Direction

66 Datasheet

Land Listing and Signal Descriptions

Table 24. Numerical Land

Assignment

Land

AL18 VCC Power/Other AL19 VCC Power/Other AL20 VSS Power/Other AL21 VCC Power/Other AL22 VCC Power/Other AL23 VSS Power/Other AL24 VSS Power/Other AL25 VCC Power/Other AL26 VCC Power/Other AL27 VSS Power/Other AL28 VSS Power/Other AL29 VCC Power/Other AL30 VCC Power/Other

AM10 VSS Power/Other AM11 VCC Power/Other AM12 VCC Power/Other AM13 VSS Power/Other AM14 VCC Power/Other AM15 VCC Power/Other AM16 VSS Power/Other AM17 VSS Power/Other AM18 VCC Power/Other AM19 VCC Power/Other AM20 VSS Power/Other AM21 VCC Power/Other AM22 VCC Power/Other AM23 VSS Power/Other AM24 VSS Power/Other AM25 VCC Power/Other AM26 VCC Power/Other

Land Name

AM1 VSS Power/Other AM2 VID0 Power/Other Output AM3 VID2 Power/Other Output AM4 VSS Power/Other AM5 VID6 Power/Other Output AM6 FC40 Power/Other AM7 VID7 Power/Other Output AM8 VCC Power/Other AM9 VCC Power/Other

Signal Buffer

Type

Direction

Table 24. Numerical Land

Assignment

Land

AM27 VSS Power/Other AM28 VSS Power/Other AM29 VCC Power/Other AM30 VCC Power/Other

AN10 VSS Power/Other AN11 VCC Power/Other AN12 VCC Power/Other AN13 VSS Power/Other AN14 VCC Power/Other AN15 VCC Power/Other AN16 VSS Power/Other AN17 VSS Power/Other AN18 VCC Power/Other AN19 VCC Power/Other AN20 VSS Power/Other AN21 VCC Power/Other AN22 VCC Power/Other AN23 VSS Power/Other AN24 VSS Power/Other AN25 VCC Power/Other AN26 VCC Power/Other AN27 VSS Power/Other AN28 VSS Power/Other AN29 VCC Power/Other AN30 VCC Power/Other

Land Name

AN1 VSS Power/Other AN2 VSS Power/Other AN3 VCC_SENSE Power/Other Output AN4 VSS_SENSE Power/Other Output

AN5

AN6

AN7 VID_SELECT Power/Other Output AN8 VCC Power/Other AN9 VCC Power/Other

VCC_MB_

REGULATION

VSS_MB_

REGULATION

Signal Buffer

Type

Power/Other Output

Direction

Datasheet 67

4.2 Alphabetical Signals Reference

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description

A[35:3]# (Address) define a 2 space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the

A[35:3]#

A20M# Input

ADS#

Input/

Output

Input/

Output

appropriate pins/lands of all agents on the processor FSB. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#.

On the active-to-inactive transition of RESET#, the processor samples a subset of the A[35:3]# signals to determine power-on configuration. See Section 6.1 for more details.

If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wraparound at the 1-MB boundary. Assertion of A20M# is only supported in real mode.

A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/ Output Write bus transaction.

ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# signals. All bus agents observe the ADS# activation to begin protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction.

Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below.

Land Listing and Signal Descriptions

-byte physical memory address

ADSTB[1:0]#

BCLK[1:0] Input

BNR#

68 Datasheet

Input/

Output

Input/

Output

Signals Associated Strobe

REQ[4:0]#, A[16:3]# ADSTB0# A[35:17]# ADSTB1#

The differential pair BCLK (Bus Clock) determines the FSB frequency. All processor FSB agents must receive these signals to drive their outputs and latch their inputs.

All external timing parameters are specified with respect to the rising edge of BCLK0 crossing V

BNR# (Block Next Request) is used to assert a bus stall by any bus agent unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions.

CROSS

Land Listing and Signal Descriptions

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are output s from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins/lands of all processor FSB agents.

BPM[5:0]#

Input/

Output

BPRI# Input

BR0#

Input/

Output

BSEL[2:0] Output

COMP8 COMP[3:0]

Analog

BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness.

BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processor.

These signals do not have on-die termination. BPRI# (Bus Priority Request) is used to arbitrate for ownership of

the processor FSB. It must connect the appropriate pins/lands of all processor FSB agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by de-asserting BPRI#.

BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this signal is sampled to determine the agent ID = 0.

This signal does not have on-die termination and must be terminated.

The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor input clock frequency. Table 16 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. For more information about these signals, including termination recommendations refer to

Section 2.7.6.

COMP[3:0] and COMP8 must be terminated to V board using precision resistors.

on the system

Datasheet 69

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description

D[63:0]# (Data) are the data signals. These signals provide a 64bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer.

D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DBI#.

Quad-Pumped Signal Groups

D[63:0]#

Input/

Output

Data Group

D[15:0]# 0 0 D[31:16]# 1 1 D[47:32]# 2 2 D[63:48]# 3 3

Land Listing and Signal Descriptions

DSTBN#/

DSTBP#

DBI#

DBI[3:0]#

Input/

Output

DBR# Output

DBSY#

Input/

Output

Furthermore, the DBI# signals determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the correspon ding data group is inverted and therefore sampled active high.

DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals.The DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than half the data bits, within a 16-bit group, would have been asserted electrically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group.

DBI[3:0] Assignment To Data Bus

Bus Signal

Data Bus

Signals

DBI3# D[63:48]# DBI2# D[47:32]# DBI1# D[31:16]# DBI0# D[15:0]#

DBR# (Debug Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal.

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use. The data bus is released after DBSY# is de-asserted. This signal must connect the appropriate pins/lands on all processor FSB agents.

70 Datasheet

Land Listing and Signal Descriptions

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description

DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is

DEFER# Input

DRDY#

Input/

Output

normally the responsibility of the addressed memory or input/ output agent. This signal must connect the appropriate pins/lands of all processor FSB agents.

DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be de-asserted to insert idle clocks. This signal must connect the appropriate pins/lands of all processor FSB agents.

DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.

Signals Associated Strobe

DSTBN[3:0]#

DSTBP[3:0]#

Input/

Output

Input/

Output

FCx Other

FERR#/PBE# Output

GTLREF[1:0] Input

D[15:0]#, DBI0# DSTBN0# D[31:16]#, DBI1# DSTBN1# D[47:32]#, DBI2# DSTBN2# D[63:48]#, DBI3# DSTBN3#

DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.

Signals Associated Strobe

D[15:0]#, DBI0# DSTBP0# D[31:16]#, DBI1# DSTBP1# D[47:32]#, DBI2# DSTBP2# D[63:48]#, DBI3# DSTBP3#

FC signals are signals that are available for compatibility with other processors.

FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/ PBE# indicates that the processor sh ould be returned t o the Normal state. For additional information on the pending break event functionality, including the identification of support of the feature and enable/disable information, refer to volume 3 of the Intel

Architecture Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note.

GTLREF[1:0] determine the signal reference level for GTL+ input signals. GTLREF is used by the GTL+ receivers to determine if a signal is a logical 0 or logical 1.

Datasheet 71

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description

Input/

HIT#

HITM#

Output

Input/

Output

IERR# Output

IGNNE# Input

INIT# Input

ITP_CLK[1:0] Input

LINT[1:0] Input

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop s tal l, which can be continued by reasserting HIT# and HITM# together.

IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor FSB . This transactio n may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#.

This signal does not have on-die termination. R efer to Section 2.6.2 for termination requirements.

IGNNE# (Ignore Numeric Error) is asserted to the processor to ignore a numeric error and continue to execute noncontrol floatingpoint instructions. If IGNNE# is de-asserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.

IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/ Output Write bus transaction.

INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins/lands of all processor FSB agents.

ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the sy stem. These are not processor signals.

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins/lands of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous .

Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/ INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these signals as LINT[1:0] is the default configuration.

Land Listing and Signal Descriptions

72 Datasheet

Land Listing and Signal Descriptions

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description

LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins/lands of all processor FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the

LOCK#

Input/

Output

MSID[1:0] Output

PECI

PROCHOT#

Input/

Output

Input/

Output

PWRGOOD Input

REQ[4:0]#

Input/

Output

RESET# Input

end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of

the processor FSB, it will wait until it observes LOCK# de-asserted. This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and en sure the atomicity of lock.

These signals indicate the Market Segment for the processor. Refer to Table 3 for additional information.

PECI is a proprietary one-wire bus interface. See Section 5.4 for details.

As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (T CC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled. The TCC will remain active until the system de-asserts PROCHOT#. See Section 5.2.4 for more details.

PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (c apable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD.

The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation.

REQ[4:0]# (Request Command) must connect the appropriate pins/ lands of all processor FSB agents. They are assert ed by t h e c u rrent bus owner to define the currently active transaction ty pe. These signals are source synchronous to ADSTB0#.

Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after V specifications. On observing active RESET#, all F S B agents will deassert their outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while PWRGOOD is asserted.

A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These configuration options are described in the Section 6.1.

This signal does not have on-die termination and must be terminated on the system board.

and BCLK have reached their proper

Datasheet 73

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description

All RESERVED lands must rema in unconn ected. Conn ection of th ese

RESERVED

RS[2:0]# Input

SKTOCC# Output

SMI# Input

STPCLK# Input

TCK Input

TDI Input

TDO Output

TESTHI[13:0] Input

THERMDA Other Thermal Diode Anode. See Section 5.3. THERMDC Other Thermal Diode Cathode. See Section 5.3.

lands to V can result in component malfunction or incompatibility with f u ture processors.

RS[2:0]# (Response Status) are driven by the res ponse agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins/lands of all processor FSB agents.

SKTOCC# (Socket Occupied) will be pulled to ground by the processor . S ystem board designers may use this signal to determine if the processor is present.

SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.

If SMI# is asserted during the de-assertion of RESET#, the processor will tri-state its outputs.

STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a StopGrant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. Wh en STPCLK# is de-asserted, the processor restarts its internal clock to all unit s and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.

TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port).

TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support.

TDO (Test Data Out) transfers serial test data out of th e processor. TDO provides the serial output needed for JTAG specification support.

TESTHI[13:0] must be connected to the processor’s appropriate power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal description) through a resistor for proper processor operation. See

Section 2.5 for more details.

Land Listing and Signal Descriptions

, VSS, VTT, or to any other signal (including each other)

74 Datasheet

Land Listing and Signal Descriptions

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description

In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum T Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has rea ch ed a level beyond where permanent silicon damage may occur. Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus, halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor, its core voltage (V

THERMTRIP# Output

TMS Input

TRDY# Input

TRST# Input

VCC Input VCCPLL Input VCCPLL provides isolated power for internal processor FSB PLLs.

VCC_SENSE Output

VCC_MB_ REGULATION

Output

VID[7:0] Output

VID_SELECT Output

be removed following the assertion of THERMTRIP#. Driving of the THERMTRIP# signal is enabled within 10 μs of the assertion of PWRGOOD (provided V assertion of PWRGOOD (if V may also be disabled). Once activated, THERMTRIP# remains latched until PWRGOOD, V assertion of the PWRGOOD, V if the processor’s junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 μs of the assertion of PWRGOOD (provided V

TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins/lands of all FSB agents.

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset.

VCC are the power pins for the processor. The voltage supplied to these pins is determined by the VID[7:0] pins.

VCC_SENSE is an isolated low impedance connection to processor core power (V the silicon with little noise.

This land is provided as a voltage regulator feedback sense point for V

. It is connected internally in the processor package to the sense

point land U27 as described in the Voltage Regulator-Down (VRD)

11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket.

VID[7:0] (Voltage ID) signals are used to support automatic selection of power supply voltages (V

Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for more information. The

voltage supply for these signals must be valid before the VR can supply V disabled until the voltage supply for the VID signals becomes valid.

The VID signals are needed to support the processor voltage specification variations. See Table 2 for definitions of these signals. The VR must supply the voltage that is requested by the signals, or disable itself.

This land is tied high on the processor package and is used by the VR to choose the proper VID table. Refer to the Voltage Regulator-

Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for more information.

) must

and VCC are valid) and is disabled on de-

or VCC are not valid, THERMTRIP#

, or VCC is de-asserted. While the de-

, or VCC will de-assert THERMTRIP#,

and VCC are valid).

). It can be used to sense or measure voltage near

). Refer to the Voltage

to the processor. Conversel y, the VR output must be

Datasheet 75

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description

VRDSEL Input

VSS Input VSSA Input VSSA is the isolated ground for internal PLLs.

VSS_SENSE Output

VSS_MB_ REGULATION

Output

VTT Input Miscellaneous voltage supply. VTT_OUT_LEFT

Output

VTT_OUT_RIGHT

VTT_SEL Output

This input should be left as a no connect in order for the processor to boot. The processor will not boot on legacy platforms where this land is connected to V

VSS are the ground pins for the processor and should be connected to the system ground plane.

VSS_SENSE is an isolated low impedance connection to processor core V silicon with little noise.

. It can be used to sense or measure ground near the

This land is provided as a voltage regulator feedback sense point for V

. It is connected internally in the processor pack age to the sense

point land V27 as described in the Voltage Regulator-Down (VRD)

11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket.

The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a voltage supply for some signals that require termination to V

on the motherboard.

The VTT_SEL signal is used to select the correct VTT voltage level for the processor. Thi s land is connected internally in the package to V

Land Listing and Signal Descriptions

§ §

76 Datasheet

Thermal Specifications and Design Considerations

5 Thermal Specifications and

Design Considerations

5.1 Processor Thermal Specifications

The processor requires a thermal solution to maintain temperatures within the operating limits as described in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation.

A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of system fans combined with ducting and venting.

For more information on designing a component level thermal solution, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2).

Note: The boxed processor will ship with a component thermal solution. Refer to Chapter 7

for details on the boxed processor.

5.1.1 Thermal Specifications

To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (T specifications when operating at or below the Thermal Design Power (TDP) value listed per frequency in Table 26. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. For more details on thermal solution design, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2).

The processor uses a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control. Selection of the appropriate fan speed is based on the relative temperature data reported by the processor’s Platform Environment Control Interface (PECI) bus as described in

Section 5.4.1.1. The temperature reported over PECI is always a negative value and

represents a delta below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT# (see Section 5.2). Systems that implement fan speed control must be designed to take these conditions in to account. Systems that do not alter the fan speed only need to specifications.

T o determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions. Refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) and the Processor Power Characterization Methodology for the details of this methodology.

ensure the case temperature meets the thermal profile

)

The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that

Datasheet 77

complete thermal solution designs target the Thermal Design Power (TDP) indicated in

Table 26 instead of the maximum processor power consumption. The Thermal Monitor

feature is designed to protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained periods of time. For more details on the usage of this feature, refer to Section 5.2. In all cases the Thermal Monitor and

Thermal Monitor 2 feature must be enabled for the processor to remain within specification.

Table 26. Processor Thermal Specifications

Thermal Specifications and Design Considerations

Processor

Number

Core

Frequency

(GHz)

E6850 3.00 65.0 8.0 E6750 2.66 65.0 8.0 5 E6550 2.33 65.0 8.0 5 E6540 2.33 65.0 8.0 5 E6700 2.66 65.0 22.0/12.0 E6600 2.40 65.0 22.0/12.0 5 E6420 2.13 65.0 12.0 5 E6320 1.86 65.0 12.0 5 E4700 2.40 65.0 8.0 E4600 2.40 65.0 8.0 5 E4500 2.20 65.0 8.0 5 E4400 2.00 65.0 8.0 5 E6400 2.13 65.0 12.0 E6400 2.13 65.0 22.0 5 E6300 1.86 65.0 12.0 E6300 1.86 65.0 22.0 5 E4400 2.00 65.0 12.0 5 E4300 1.80 65.0 12.0 5

Thermal

Design

Power (W)

1,2

Extended

HALT

Power (W)

775_VR_

CONFIG_05B/

06 Guidance

775_VR_CONFIG

_06

775_VR_CONFIG

_06

775_VR_CONFIG

_06

775_VR_CONFIG

_06

Minimum

(°C)

Maximum T

(°C)

Thermal Profile 1

(See Table 27,

Figure 19)

Thermal Profile 2

(See Table 28,

Figure 20)

Thermal Profile 3

(See Table 29,

Figure 21)

Thermal Profile 4

(See Table 30,

Figure 22)

Notes

5,6

5,6 5,6 5,6

7,8

7,8 7,8 7,8 5,6 5,9 5,9 5,9

7, 10

7,8

7, 10

7,8

7, 10

7,10

Thermal

X6800 2.93 75.0 22.0

775_VR_CONFIG

_05B

Profile 5

(See Table 31

7,8

Figure 23)

NOTES:

1. Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not the maximum power that the processor can dissipate.

This table shows the maximum TDP for a given frequency range. Individual processors may have a lower TDP.

Therefore, the maximum T figure and associated table for the allowed combinations of power and TC.

3. Refe r to the “Component Identifica tion Information” section of th e Intel® Core™2 Extreme and Intel® Core™2 Duo D esktop Processor Specification Update for processor specific Idle power.

4. 775_VR_CONFIG_06/775_VR_CONFIG_05B guidelines provide a design target for meeting future thermal requirements.

5. Specification is at 35 °C TC and typical voltage loadline.

6. These processors have CPUID = 06FBh.

7. Specification is at 50 °C TC and typical voltage loadline.

8. These processors have CPUID = 06F6h.

9. These processors have CPUID = 06FDh.

10.These processors have CPUID = 06F2h.

will vary depending on the TDP of the individual processor. Refer to thermal profile

78 Datasheet

Thermal Specifications and Design Considerations

Table 27. Thermal Profile 1

Power

(W)

Maximum

Tc (°C)

0 44.7 24 54.8 48 64.9 2 45.5 26 55.6 50 65.7 4 46.4 28 56.5 52 66.5 6 47.2 30 57.3 54 67.4

8 48.1 32 58.1 56 68.2 10 48.9 34 59.0 58 69.1 12 49.7 36 59.8 60 69.9 14 50.6 38 60.7 62 70.7 16 51.4 40 61.5 64 71.6 18 52.3 42 62.3 65 72.0 20 53.1 44 63.2 22 53.9 46 64.0

NOTE: For the Intel® Core™2 Duo Desktop processor E6x50 series with 4 MB L2 Cache and

CPUID = 06FBh, and Intel and CPUID = 06FBh.

Figure 19. Thermal Profile 1

Power

(W)

Core™2 Duo Desktop processor E6540 with 4 MB L2 Cache

Maximum

Tc (°C)

Power

(W)

Maximum

Tc (°C)

NOTE: For the Intel

CPUID = 06FBh, and Intel

Core™2 Duo Desktop processor E6x50 series with 4 MB L2 Cache and

Core™2 Duo Desktop processorr E6540 with 4 MB L2 Cache

and CPUID = 06FBh.

Datasheet 79

Table 28. Thermal Profile 2

Thermal Specifications and Design Considerations

Power

(W)

Maximum

Tc (°C)

0 43.2 24 49.4 48 55.7 2 43.7 26 50.0 50 56.2 4 44.2 28 50.5 52 56.7 6 44.8 30 51.0 54 57.2

8 45.3 32 51.5 56 57.8 10 45.8 34 52.0 58 58.3 12 46.3 36 52.6 60 58.8 14 46.8 38 53.1 62 59.3 16 47.4 40 53.6 64 59.8 18 47.9 42 54.1 65 60.1 20 48.4 44 54.6 22 48.9 46 55.2

NOTE: For the Intel® Core™2 Duo Desktop processor E6000 series with 4 MB L2 Cache and

CPUID = 06F6h.

Figure 20. Thermal Profile 2

65.0

Power

(W)

Maximum

Tc (°C)

Power

(W)

Maximum

Tc (°C)

60.0

55.0

y = 0.26x + 43.2

Tcase (C)

50.0

45.0

40.0 0 102030405060

NOTE: For the Intel

Core™2 Duo Desktop processor E6000 series with 4 MB L2 Cache and

Power (W)

CPUID = 06F6h.

80 Datasheet

Thermal Specifications and Design Considerations

Table 29. Thermal Profile 3

Power

(W)

Maximum

Tc (°C)

0 45.3 24 55.6 48 65.9

2 46.2 26 56.5 50 66.8 4 47.0 28 57.3 52 67.7 6 47.9 30 58.2 54 68.5

8 48.7 32 59.1 56 69.4 10 49.6 34 59.9 58 70.2 12 50.5 36 60.8 60 71.1 14 51.3 38 61.6 62 72.0 16 52.2 40 62.5 64 72.8 18 53.0 42 63.4 65 73.3 20 53.9 44 64.2 22 54.8 46 65.1

NOTE: For the Intel® Core™2 Duo Desktop processor E4000 series with 2 MB L2 Cache and

CPUID = 06FDh, and for the Intel Cache and CPUID = 06FBh.

Figure 21. Thermal Profile 3

Power

(W)

Maximum

Tc (°C)

Core™2 Duo Desktop processor E4700 with 2 MB L2

Power

(W)

Maximum

Tc (°C)

NOTE: For the Intel

CPUID = 06FDh, and for the Intel

Core™2 Duo Desktop processor E4000 series with 2 MB L2 Cache and

Core™2 Duo Desktop processor E4700 with 2 MB L2

Cache and CPUID = 06FBh.

Datasheet 81

Table 30. Thermal Profile 4

Thermal Specifications and Design Considerations

Power

(W)

Maximum

Tc (°C)

0 43.2 24 49.9 48 56.6 2 43.8 26 50.5 50 57.2 4 44.3 28 51.0 52 57.8 6 44.9 30 51.6 54 58.3

8 45.4 32 52.2 56 58.9 10 46.0 34 52.7 58 59.4 12 46.6 36 53.3 60 60.0 14 47.1 38 53.8 62 60.6 16 47.7 40 54.4 64 61.1 18 48.2 42 55.0 65 61.4 20 48.8 44 55.5 22 49.4 46 56.1

NOTE: For the Intel® Core™2 Duo Desktop processor E6000 and E4000 series with 2 MB L2

Cache and CPUID = 06F2h, and for the Intel series with 2 MB L2 Cache and CPUID = 06F6h.

Figure 22. Thermal Profile 4

65.0

Power

(W)

Maximum

Tc (°C)

Core™2 Duo Desktop processor E6000

Power

(W)

Maximum

Tc (°C)

60.0

55.0

Tcase (C)

50.0

45.0

40.0 0 102030405060

NOTE: For the Intel

Cache and CPUID = 06F2h, and for the Intel series with 2 MB L2 Cache and CPUID = 06F6h.

y = 0.28x + 43.2

Power (W)

Core™2 Duo Desktop processor E6000 and E4000 series with 2 MB L2

Core™2 Duo Desktop processor E6000

82 Datasheet

Thermal Specifications and Design Considerations

Table 31. Thermal Profile 5

Power

(W)

Maximum

Tc (°C)

0 43.2 26 49.2 52 55.2 2 43.7 28 49.6 54 55.6 4 44.1 30 50.1 56 56.1 6 44.6 32 50.6 58 56.5

8 45.0 34 51.0 60 57.0 10 45.5 36 51.5 62 57.5 12 46.0 38 51.9 64 57.9 14 46.4 40 52.4 66 58.2 16 46.9 42 52.9 68 58.8 18 47.3 44 53.3 70 59.3 20 47.8 46 53.8 72 59.8 22 48.3 48 54.2 74 60.2 24 48.7 50 54.7 75 60.4

NOTE: For the Intel® Core™2 Extreme processor X6800.

Figure 23. Thermal Profile 5

65.0

Power

(W)

Maximum

Tc (°C)

Power

(W)

Maximum

Tc (°C)

60.0

55.0

Tcase (C)

50.0

45.0

40.0 0 10203040506070

NOTE: For the Intel

Datasheet 83

Core™2 Extreme processor X6800.

Power (W)

y = 0.23x + 43.2

5.1.2 Thermal Metrology

The maximum and minimum case temperatures (TC) for the processor is specified in

Table 26. This temperature specification is meant to help ensure proper operation of

the processor. Figure 24 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2).

Thermal Specifications and Design Considerations

Figure 24. Case Temperature (T

37.5 mm

) Measurement Location

37.5 mm

5.2 Processor Thermal Features

5.2.1 Thermal Monitor

The Thermal Monitor feature helps control the processor temper ature by activ ating the thermal control circuit (TCC) when the processor silicon reaches its maximum operating temperature. The TCC reduces processor power consumption by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to be operating within specifications. The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active.

Measure TCat this point

(geo metric center of the package)

When the Thermal Monitor feature is enabled, and a high temperature situation exists (i.e., TC C is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30–50%). Clocks often will not be off for more than 3.0 microseconds when the TCC is active. Cycle times are processor speed dependent and will decrease as processor core frequencies increase. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases.

With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss,

84 Datasheet

Thermal Specifications and Design Considerations

and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) for information on designing a thermal solution.

The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and cannot be modified. The Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines.

5.2.2 Thermal Monitor 2

The processor also supports an additional power reduction capability known as Thermal Monitor 2. This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor.

When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the Thermal Control Circuit (TCC) will be activated. The TCC causes the processor to adjust its operating frequency (via the bus multiplier) and input voltage (via the VID signals). This combination of reduced frequency and VID results in a reduction to the processor power consumption.

A processor enabled for Thermal Monitor 2 includes two operating points, each consisting of a specific operating frequency and voltage. The first operating point represents the normal operating condition for the processor. Under this condition, the core-frequency-to-FSB multiple used by the processor is that contained in the appropriate MSR and the VID is that specified in Table 5. These parameters represent normal system operation.

The second operating point consists of both a lower operating frequency and voltage. When the TCC is activated, the processor automatically transitions to the new frequency. This transition occurs very rapidly (on the order of 5 μs). During the frequency transition, the processor is unable to service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency.

Once the new operating frequency is engaged, the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator. The voltage regulator must support dynamic VID steps to support Thermal Monitor 2. During the voltage change, it will be necessary to transition through multiple VID codes to reach the target operating voltage. Each step will likely be one VID table entry (see Table 5). The processor continues to execute instructions during the voltage transition. Operation at the lower voltage reduces the power consumption of the processor.

A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the operating frequency and voltage transition back to the normal system operating point. Transition of the VID code will occur first, to insure proper operation once the processor reaches its normal operating frequency. Refer to Figure 25 for an illustration of this ordering.

Datasheet 85

Thermal Specifications and Design Considerations

Figure 25. Thermal Monitor 2 Frequency and Voltage Ordering

MAX

TM2

Temperature

Frequency

VID

TM2

VID

PROCHOT#

The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled.

It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode. The Thermal Monitor TCC, however, can be activated through the use of the on demand mode.

5.2.3 On-Demand Mode

The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. This mechanism is referred to as “OnDemand” mode and is distinct from the Thermal Monitor and Thermal Monitor 2 features. On-Demand mode is intended as a means to reduce system level power consumption. Systems must not rely on software usage of this mechanism to limit the processor temperature. If bit 4 of the IA32_CLOCK_MODULATION MSR is set to a 1, the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, independent of the processor temperature. When using On-Demand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of the same IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off to 87.5% on/ 12.5% off in 12.5% increments. On-Demand mode may be used in conjunction with the Thermal Monitor; however, if the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode.

86 Datasheet

Thermal Specifications and Design Considerations

5.2.4 PROCHOT# Signal

An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.

As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that one or both cores has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled, for both cores. The T CC will remain active until the system de-asserts PROCHOT#.

PROCHOT# allows for some protection of various components from over-temperature situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor (either core) has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components.

PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power. With a properly designed and characterized thermal solution, it is anticipated that PROCHOT# would only be asserted for very short periods of time when running the most power intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for details on implementing the bi-directional PROCHOT# feature.

5.2.5 THERMTRIP# Signal

Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in

Table 25). At this point, the FSB signal THERMTRIP# will go active and stay active as

described in Table 25. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles.

Datasheet 87

5.3 Thermal Diode

The processor incorporates an on-die PNP transistor where the base emitter junction is used as a thermal "diode", with its collector shorted to ground. A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management and fan speed control. Table 32,Table 33, and Table 34 provide the "diode" parameter and interface specifications. Two different sets of "diode" parameters are listed in Table 32 and Table 33. The Diode Model parameters (Table 32) apply to traditional thermal sensors that use the Diode Equation to determine the processor temperature. Transistor Model parameters (Table 33) have been added to support thermal sensors that use the transistor equation method. The Transistor Model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits. This thermal "diode" is separate from the Thermal Monitor's thermal sensor and cannot be used to predict the behavior of the Thermal Monitor.

Thermal Specifications and Design Considerations

CONTROL

thermal diode. The value for T configured for each processor. When T below T temperature can be maintained at T diode.

is a temperature specification based on a temperature reading from the

CONTROL

as defined by the thermal profile in Table 28; otherwise, the processor

C_MAX

will be calibrated in manufacturing and

is above T

DIODE

CONTROL

(or lower) as measured by the thermal

Table 32. Thermal “Diode” Parameters using Diode Model

Symbol Parameter Min Typ Max Unit Notes

n Diode Ideality Factor 1.000 1.009 1.050 - 2, 3, 4 R

NOTES:

1. Intel does not support or recommend operation of the thermal diode under reverse bias.

2. Characterized across a temperature range of 50 – 80 °C.

3. Not 100% tested. Specified by design characterization.

4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by

5. The series resistance, R

Forward Bias Current 5 — 200 µA 1

Series Resistance 2.79 4.52 6.24 Ω 2, 3, 5

the diode equation:

= IS * (e

where I k = Boltzmann Constant, and T = absolute temperature (Kelvin).

junction temperature. R include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. R with automatic series resistance cance llation to calibrate out this error term. Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation:

where T Constant, q = electronic charge.

= saturation current, q = electronic charge, VD = voltage across the diode,

, is provided to allow for a more accurate measurement of the

, as defined, includes the lands of the processor but does not

= [RT * (N–1) * I

= sensor temperature error, N = sensor current ratio, k = Boltzmann

error

qVD/nkT

–1)

can be used by remote diode thermal sensors

CONTROL

] / [nk/q * ln N]

FWmin

, then TC must be at or

88 Datasheet

Thermal Specifications and Design Considerations

Table 33. Thermal “Diode” Parameters using Transistor Model

Symbol Parameter Min Typ Max Unit Notes

Beta 0.391 — 0.760 3, 4 R

NOTES:

1. Intel does not support or recommend operation of the thermal diode under reverse bias.

2. Same as I

3. Characterized across a temperature range of 50–80 °C.

4. Not 100% tested. Specified by design characterization.

5. The ideality factor, nQ, represents the deviation from ideal transistor model behavior as

6. The series resistance, R

Forward Bias Current 5 — 200 µA 1, 2 Emitter Current 5 — 200 µ A Transistor Ideality 0.997 1.001 1.005 - 3, 4, 5

Series Resistance 2.79 4.52 6.24 Ω 3, 6

in Table 32.

exemplified by the equation for the collector current:

= IS * (e

Where I base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute

= saturation current, q = electr onic charge, VBE = voltage across the transist or

qVBE/nQkT

–1)

temperature (Kelvin).

provided in the Diode Model Table (Table 32) can be used for

Table 34. Thermal Diode Interface

Signal Name Land Number

THERMDA AL1 diode anode THERMDC AK1 diode cathode

Signal

Description

Datasheet 89

Thermal Specifications and Design Considerations

5.4 Platform Environment Control Interface (PECI)

5.4.1 Introduction

PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues. Figure 26 shows an example of the PECI topology in a system. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices. Also, data transfer speeds across the PECI interface are negotiable within a wide range (2 Kbps to 2 Mbps). The PECI interface on the processor is disabled by de fault and must be enabled through BIOS.

Figure 26. Processor PECI Topology

PECI Host Controller

Land G5

Domain 0

30h

5.4.1.1 Key Difference with Legacy Diode-Based Thermal Management

Fan speed control solutions based on PECI uses a T processor IA32_TEMPERATURE_TARGET MSR. The T temperature format as PECI though it contains no sign bit. Thermal management devices should infer the T should use the relative temperature value delivered over PECI in conjunction with the T

CONTROL

fan control diagram using PECI temperatures. The relative temperature value reported over PECI represents the delta below the onset

of thermal control circuit (TCC) activation as indicated by PROCHOT# assertions. As the temperature approaches TCC activation, the PECI value approaches zero. T CC activates at a PECI count of zero.

MSR value to control or optimize fan speeds. Figure 27 shows a conceptual

CONTROL

value as negative. Thermal management algorithms

CONTROL

value stored in the

MSR uses the same offset

90 Datasheet

Thermal Specifications and Design Considerations

Figure 27. Conceptual Fan Control on PECI-Based Platforms

CONTROL

Setting

TCC Ac tiva tion

Temperature

Max

Fan Speed

PECI = -10

(RPM )

Min

PECI = -20

Temperature

Note: No t inte n d ed to d e pict a c tua l im ple m e n tation

Figure 28. Conceptual Fan Control on Thermal Diode-Based Platforms

CONTROL

Setting

TCC Activation

Temperature

Max

Fan Speed

DIODE

= 80 °C

(RPM)

PECI = 0

DIODE

= 90 °C

Min

= 70 °C

DIODE

Temperature

Datasheet 91

5.4.2 PECI Specifications

5.4.2.1 PECI Device Address

The PECI device address for the socket is 30h. For more information on PECI domains, refer to the Platform Environment Control Interface Specification.

5.4.2.2 PECI Command Support

PECI command support is covered in detail in the Platform Environment Control Interface Specification. Refer to this document for details on supported PECI command

function and codes.

5.4.2.3 PECI Fault Handling Requirements

PECI is largely a fault tolerant interface, including noise immunity and error checking improvements over other comparable industry standard interfaces. The PECI client is as reliable as the device that it is embedded in, and thus given operating conditions that fall under the specification, the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures. There are, however, certain scenarios where the PECI is know to be unresponsive.

Prior to a power on RESET# and during RESET# assertion, PECI is not ensured to provide reliable thermal data. System designs should implement a default power-on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI.

Thermal Specifications and Design Considerations

To protect platforms from potential operational or safety issues due to an abnormal condition on PECI, the Host controller should take action to protect the system from possible damaging states. It is recommended that the PECI host controller take appropriate action to protect the client processor device if valid temperature readings have not been obtained in response to three consecutive gettemp()s or for a one second time interval. The host controller may also implement an alert to software in the event of a critical or continuous fault condition.

5.4.2.4 PECI GetTemp0() Error Code Support

The error codes supported for the processor GetTemp() command are listed in

Table 35.

Table 35. GetT em p0 () Err or Co des

Error Code Description

8000h General sensor error

8002h

Sensor is operational, but has detected a temperature below its operational range (underflow).

§ §

92 Datasheet

Features

6 Features

6.1 Power-On Configuration Options

Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. F or specifications on these options, refer to Table 36.

The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor; for reset purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset.

Table 36. Power-On Configuration Option Signals

Configuration Option Signal

Output tristate SMI# Execute BIST A3# Disable dynamic bus parking A25# Symmetric agent arbitration ID BR0# RESERVED A[8:5]#, A[24:11]#, A[35:26]#

NOTES:

1. Asserting this signal during RESET# will select the corresponding option.

Address signals not identified in this table as configuration options should not

be asserted during RESET#.

3. Disabling of any of the cores within the processor must be handled by

configuring the EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a single core.

1,2,3

6.2 Clock Control and Low Power States

The processor allows the use of AutoHALT and Stop Grant states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 29 for a visual representation of the processor low power states.

Datasheet 93

Figure 29. Processor Low Power State Machine

HALT or MWAIT Instruction and HALT Bus Cycle Generated

Normal State

- Norm al Execution

INIT#, INTR, NMI, SMI#, R ES ET# , FSB interrupts

Features

Extended HALT or HALT State

-BCLK running

- Snoops and interrupts

allowed

STPCLK#

Asserted

Extended Stop Grant State or Stop Grant State

- BCLK running

- Snoops and interrupts

allowed

STPCLK#

De-asserted

STPCLK#

Asserted

Snoop Event Occurs

Snoop Event Serviced

STPCLK#

De-asserted

Extended HALT Snoop or HALT Snoop State

-BCLK running

- Service Snoops to caches

Extended Stop Grant Snoop or Stop Grant Snoop State

-BCLK running

- Service Snoops to caches

6.2.1 Normal State

This is the normal operating state for the processor.

6.2.2 HALT and Extended HALT Powerdown States

The processor supports the HALT or Extended HALT powerdown state. The Extended HALT Powerdown must be enabled via the BIOS for the processor to remain within its specification.

The Extended HALT state is a lower power state as compared to the Stop Grant State.

Snoop

Event

Occurs

Snoop

Event

Serviced

If Extended HALT is not enabled, the default Powerdown state entered will be HALT. Refer to the following sections for details about the HALT and Extended HALT states.

6.2.2.1 HALT Powerdown State

HAL T is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions. When one of the processor cores executes the HALT instruction, that processor core is halted; however, the other processor continues normal operation. The processor transitions to the Normal state upon the occurrence of SMI#, INIT#, or LINT[1:0] (NMI, INTR). RESET# causes the processor to immediately initialize itself.

The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information.

94 Datasheet

Features

The system can generate a STPCLK# while the processor is in the HALT powerdown state. When the system de-asserts the STPCLK# interrupt, the processor will return execution to the HALT state.

While in HALT Power powerdown, the processor processes bus snoops.

6.2.2.2 Extended HALT Powerdown State

Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS. When one of the processor cores executes the HALT instruction, that logical processor is halted; however, the other processor continues normal operation. The Extended HAL T Powerdown state must be enabled via the BIOS for the processor to remain within its specification.

The processor automatically transitions to a lower frequency and voltage operating point before entering the Extended HALT state. Note that the processor FSB frequency is not altered; only the internal core frequency is changed. When entering the low power state, the processor first switches to the lower bus ratio and then transitions to the lower VID.

While in Extended HALT state, the processor processes bus snoops. The processor exits the Extended HALT state when a break event occurs. When the

processor exits the Extended HALT state, it will resume operation at the lower frequency , transitions the VID to the original value and then changes the bus ratio back to the original value.

6.2.3 Stop Grant and Extended Stop Grant States

The processor supports the Stop Grant and Extended Stop Grant states. The Extended Stop Grant state is a feature that must be configured and enabled via the BIOS. Refer to the following sections for details about the Stop Grant and Extended Stop Grant states.

6.2.3.1 Stop Grant State

When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle.

Since the GTL+ signals receive power from the FSB, these signals should not be driven (allowing the level to return to V resistors in this state. In addition, all other input signals on the FSB should be driven to the inactive state.

RESET# causes the processor to immediately initialize itself, but the processor will stay in Stop Grant state. A transition back to the Normal state occurs with the de-assertion of the STPCLK# signal.

A transition to the Grant Snoop state occurs when the processor detects a snoop on the FSB (see Section 6.2.4).

While in the Stop Grant State, SMI#, INIT#, and LINT[1:0] is latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state.

While in Stop Grant state, the processor processes a FSB snoop.

) for minimum power drawn by the termination

Datasheet 95

Features

6.2.3.2 Extended Stop Grant State

Extended Stop Grant is a low power state entered when the STPCLK# signal is asserted and Extended Stop Grant has been enabled via the BIOS.

The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended Stop Grant state. When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower VID.

The processor exits the Extended Stop Grant state when a break event occurs. When the processor exits the Extended Stop Grant state, it will resume operation at the lower frequency, transition the VID to the original value, and then change the bus ratio back to the original value.

6.2.4 Extended HALT State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State

The Extended HALT Snoop State is used in conjunction with the new Extended HALT state. If Extended HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State. Refer to the following sections for details on HALT Snoop State, Stop Grant Snoop State and Extended HALT Snoop State, and Extended Stop Grant Snoop State.

6.2.4.1 HALT Snoop State, Stop Grant Snoop State

The processor will respond to snoop transactions on the FSB while in Stop Grant state or in HALT Power Down state. During a snoop transaction, the processor enters the HAL T Snoop State:Stop Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB). After the snoop is serviced, the processor returns to the Stop Grant state or HAL T Power Down state, as appropriate.

6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State

The processor will remain in the lower bus ratio and VID operating point of the Extended HAL T state or Extended Stop Grant state. While in the Extended HALT Snoop State or Extended Stop Grant Snoop State, snoops are handled the same way as in the HALT Snoop State or Stop Grant Snoop State. After the snoop is serviced, the processor will return to the Extended HALT state or Extended Stop Grant state.

6.3 Enhanced Intel® SpeedStep® Technology

The processor supports Enhanced Intel SpeedStep® Technology. This technology enables the processor to switch between multiple frequency and voltage points, which results in platform power savings. Enhanced Intel SpeedStep support for dynamic VID transitions in the platform. Switching between voltage/ frequency states is software controlled.

Note: Not all processors are capable of supporting Enhanced Intel SpeedStep

More details on which processor frequencies support this feature is provided in the

Core™2 Duo Desktop Processor E6000 and E4000 Series and Intel® Core™2

Intel Extreme Processor X6800 Specification Update.

Enhanced Intel SpeedStep states) or voltage/frequency operating points. P-states are lower power capability states within the Normal state as shown in Figure 29. Enhanced I ntel SpeedStep Technology enables real-time dynamic switching between frequency and voltage

Technology creates processor performance states (P-

Technology requires

Technology.

96 Datasheet

Features

points. It alters the performance of the processor by changing the bus to core frequency ratio and voltage. This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system. The processor has hardware logic that coordinates the requested voltage (VID) between the processor cores. The highest voltage that is requested for either of the processor cores is selected for that processor package. Note that the front side bus is not altered; only the internal core frequency is changed. To run at reduced power consumption, the voltage is altered in step with the bus ratio.

The following are key features of Enhanced Intel SpeedStep

Technology:

• Multiple voltage/frequency operating points provide optimal performance at reduced power consumption.

• Voltage/frequency selection is software controlled by writing to processor MSRs (Model Specific Registers), thus eliminating chipset dependency.

— If the target frequency is higher than the current frequency, V

in steps (+12.5 mV) by placing a new value on the VID signals and the

is incremented

processor shifts to the new frequency. Note that the top frequency for the processor can not be exceeded.

— If the target frequency is lower than the current frequency , the processor shifts

to the new frequency and V changing the target VID through the VID signals.

is then decremented in steps (-12.5 mV) by

§ §

Datasheet 97

Features

98 Datasheet

Boxed Processor Specifications

7 Boxed Processor Specifications

The processor is also offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor. This chapter is particularly important for OEMs that manufacture baseboards for system integrators. Figure 30 shows a mechanical representation of a boxed processor.

Note: Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and

inches [in brackets].

Note: Drawings in this section reflect only the specifications on the Intel boxed processor

Figure 30. Mechanical Representation of the Boxed Processor

product. These dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system designers’ responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platforms and chassis. Refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) for further guidance.

NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.

Datasheet 99

Boxed Processor Specifications

7.1 Mechanical Specifications

7.1.1 Boxed Processor Cooling Solution Dimensions

This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 30 shows a mechanical representation of the boxed processor.

Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 31 (Side View), and Figure 32 (Top View). The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs. Airspace requirements are shown in Figure 36 and Figure 37. Note that some figures have centerlines shown (marked with alphabetic designations) to clarify relative dimensioning.

Figure 31. Space Requirements for the Boxed Processor (Side View)

95.0

[3.74]

81.3 [3.2]

10.0

[0.39]

Figure 32. Space Requirements for the Boxed Processor (Top View)

25.0

[0.98]

NOTES:

1. Diagram does not show the attached hardware fo r the clip design and is provided only as a mechanical representation.

100 Datasheet

Intel CORE 2 DUO E4000, CORE 2 DUO E6000, CORE 2 EXTREME X6800 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Figures

Tables

Revision History

Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Series Features

1 Introduction

1.1 Terminology

1.1.1 Processor Terminology

1.2 References

Table 1. Reference Documents

2 Electrical Specifications

2.1 Power and Ground Lands

2.2 Decoupling Guidelines

2.2.1 VCC Decoupling

2.2.2 VTT Decoupling

2.2.3 FSB Decoupling

2.3 Voltage Identification

Table 2. Voltage Identification Definition

2.4 Market Segment Identification (MSID)

2.5 Reserved, Unused, and TESTHI Signals

2.6 Voltage and Current Specification

2.6.1 Absolute Maximum and Minimum Ratings

Table 4. Absolute Maximum and Minimum Ratings

2.6.2 DC Voltage and Current Specification

Table 5. Voltage and Current Specifications

Table 6. VCC Static and Transient Tolerance

Figure 1. VCC Static and Transient Tolerance

2.6.3 VCC Overshoot

Figure 2. VCC Overshoot Example Waveform

2.6.4 Die Voltage Validation

2.7 Signaling Specifications

2.7.1 FSB Signal Groups

Table 8. FSB Signal Groups (Sheet 1 of 2)

Table 9. Signal Characteristics

Table 10. Signal Reference Voltages

2.7.2 CMOS and Open Drain Signals

2.7.3 Processor DC Specifications

Table 11. GTL+ Signal Group DC Specifications

Table 12. Open Drain and TAP Output Signal Group DC Specifications

Table 13. CMOS Signal Group DC Specifications

2.7.3.1 GTL+ Front Side Bus Specifications

Table 14. GTL+ Bus Voltage Definitions

2.7.4 Clock Specifications

2.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

Table 15. Core Frequency to FSB Multiplier Configuration

2.7.6 FSB Frequency Select Signals (BSEL[2:0])

Table 16. BSEL[2:0] Frequency Table for BCLK[1:0]

2.7.7 Phase Lock Loop (PLL) and Filter

2.7.8 BCLK[1:0] Specifications (CK505 based Platforms)

Table 17. Front Side Bus Differential BCLK Specifications

Figure 3. Differential Clock Waveform

Figure 4. Differential Clock Crosspoint Specification

Figure 5. Differential Measurements

2.7.9 BCLK[1:0] Specifications (CK410 based Platforms)

Table 18. Front Side Bus Differential BCLK Specifications

Figure 6. Differential Clock Crosspoint Specification

2.8 PECI DC Specifications

Table 19. PECI DC Electrical Limits

Package Mechanical Specifications

Figure 7. Processor Package Assembly Sketch

3.1 Package Mechanical Drawing

Figure 8. Processor Package Drawing Sheet 1 of 3

Figure 9. Processor Package Drawing Sheet 2 of 3

Figure 10. Processor Package Drawing Sheet 3 of 3

3.1.1 Processor Component Keep-Out Zones

3.1.2 Package Loading Specifications

Table 20. Processor Loading Specifications

3.1.3 Package Handling Guidelines

Table 21. Package Handling Guidelines

3.1.4 Package Insertion Specifications

3.1.5 Processor Mass Specification

3.1.6 Processor Materials

Table 22. Processor Materi als

3.1.7 Processor Markings

Figure 15. Processor Top-Side Markings for the Intel® Core™2 Extreme Processor X6800

3.1.8 Processor Land Coordinates