Supporting 7th Generation Intel® Core™ Processor Families
based on Y/U/H/S-Processor Line, Y/U With iHDCP2.2Processor Line and Intel® Pentium® Processors and Intel®
Celeron® Processor
February 2017
Revision 004
Document Number: 334663-004
Revision History
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damages resulting from such losses.
The products described may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
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*Other names and brands may be claimed as the property of others.
This document is an update to the specifications contained in the documents listed in
the following Affected Documents/Related Documents table. It is a compilation of
device and document errata and specification clarifications and changes, and is
intended for hardware system manufacturers and for software developers of
applications, operating system, and tools.
Information types defined in the Nomenclature section of this document are
consolidated into this update document and are no longer published in other
documents. This document may also contain information that has not been previously
published.
Affected Documents
7th Generation Intel® Processor Families for U/Y Platforms Datasheet,
Volume 1 of 2
7th Generation Intel® Processor Families for U/Y Platforms Datasheet,
Volume 2 of 2
Related Documents
AP-485, Intel® Processor Identification and the CPUID Instructionhttp://www.intel.com
Intel® 64 and IA-32 Architectures Software Dev eloper’s Manual,
Volume 1: Basic Architecture
®
64 and IA-32 Architectures Software Developer’s Manual,
Intel
Volume 2A: Instruction Set Reference Manual A-M
®
64 and IA-32 Architectures Software Dev eloper’s Manual,
Intel
Volume 2B: Instruction Set Reference Manual N-Z
®
64 and IA-32 Architectures Software Dev eloper’s Manual,
Intel
Volume 3A: System Progra mming Guide
®
64 and IA-32 Architectures Software Dev eloper’s Manual,
Intel
Volume 3B: System Programming Guide
®
64 and IA-32 Intel Architecture Optimization Reference Manual
Intel
Intel® 64 and IA-32 Architectures Software Dev eloper’s Manual
Documentation Changes
ACPI Specifications www.acpi.info
Document Title Document
Document Title Document
Number/Location
334661
334662
Number/Location
/design/processor/ap
plnots/241618.htm
http://www.intel.com
/products/processor/
manuals/index.htm
http://www.intel.com
/content/www/us/en/
processors/architectur
es-software-
developer-
manuals.html
Specification Update 5
Nomenclature
Errata are design defects or errors. Errata may cause the processor’s behavior to
deviate from published specifications. Hardware and software designed to be used
with any given stepping must assume that all errata documented for that stepping are
present on all devices.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in the next release of the specifications.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications will
be incorporated in the next release of the specifications.
Documentation Changes include typos, errors, or omissions from the current
published specifications. These changes will be incorporated in the next release of the
specifications.
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon request.
Specification changes, specification clarifications, and documentation changes are
removed from the specification update when the appropriate changes are made to the
appropriate product specification or user documentation (datasheets, manuals, etc.).
Preface
§
6Specification Update
Identification Information
Identification Information
Component Identification via Programming Interface
The processor stepping can be identified by the following register contents:
1. The Extended Family, Bits [27:20] are used in conjunction with the Family
Code, specified in Bits[11:8], to indicate whether the processor belongs to the
Intel386™, Intel486™, Pentium®, Pentium 4, or Intel® Core™ processor
family.
2. The Extended Model, Bits [19:16] in conjunction with the Model Number,
specified in Bits [7:4], are used to identify the model of the processor within
the processor’s family.
3. The Family Code corresponds to Bits [11:8] of the EDX register after RESET,
Bits [11:8] of the EAX register after the CPUID instruction is executed with a 1
in the EAX register, and the generation field of the Device ID register
accessible through Boundary Scan.
4. The Model Number corresponds to Bits [7:4] of the EDX register after RESET,
Bits [7:4] of the EAX register after the CPUID instruction is executed with a 1
in the EAX register, and the model field of the Device ID register accessible
through Boundary Scan.
5. The Stepping ID in Bits [3:0] indicates the revision number of that model. See
Table 1 for the processor stepping ID number in the CPUID information.
6. Please refer to Kaby Lake Processor BIOS Writers Guide for additional
information. When EAX is initialized to a value of ‘1’, the CPUID instruction
returns the Extended Family, Extended Model, Processor Type, Family Code,
Model Number and Stepping ID value in the EAX register. Note that the EDX
processor signature value after reset is equivalent to the processor signature
output value in the EAX register.
Type
Type
Family
Code
Family
Code
Model
Number
Model
Number
Stepping
ID
Stepping
ID
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after
the CPUID instruction is executed with a 2 in the EAX register.
Specification Update 7
Component Marking Information
Figure 1. Y-Processor Line BGA Top-Side Markings
Identification Information
Pin Count: 1515 Package Size: 20 mm x 16.5 mm
Production (SSPEC):
GRP1LINE1: FPOxxxxxSSPEC
GRP2LINE1 (G2L1): Intel logo
GRP3LINE1 (G3L1): {eX}
The following table indicates the Specification Changes, Errata, Specification
Clarifications or Documentation Changes, which apply to the listed processor stepping.
Intel intends to fix some of the errata in a future stepping of the component, and to
account for the other outstanding issues through documentation or Specification
Changes as noted. This table uses the following notations:
Codes Used in Summary Table
Stepping
X: Erratum, Specification Change or Clarification that applies
to this stepping.
(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification
change does not apply to listed stepping.
Status
Doc: Document change or update that will be implemented.
Plan Fix: This erratum may be fixed in a future stepping of the
product.
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.
Specification Update 15
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