Intel BX80646I54430, CM8064601465902, BX80646I54570, BX80646I54440, CM8064601466203 User Manual

...

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

Specification Update

December 2013

Revision 007

Reference Number: 328899-007

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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined”. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800548-4725, or go to: http://www.intel.com/design/literature.htm.

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Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM). Functionality,

Intel performance or other benefits will vary depending on hardware and software configurations. Software applications may not be compatible with all operating systems. Consult your PC manufacturer. For more information, visit: http://www.intel.com/go/virtualization.

Intel

Turbo Boost Technology requires a system with Intel® Turbo Boost Technology. Intel Turbo Boost Technology and Intel Turbo Boost Technology

2.0 are only available on select Intel configuration. For more information, visit: http://www.intel.com/go/turbo.

Intel

Hyper-Threading Technology requires an Intel® HT Technology enabled system, check with your PC manufacturer. Performance will vary depending on the specific hardware and software used. Not available on Intel processors support HT Technology, visit http://www.intel.com/info/hyperthreading.

64 architecture requires a system with a 64-bit enabled processor, chipset, BIOS and software. Performance will vary depending on the specific

Intel hardware and software you use. Consult your PC manufacturer for more information. For more information, visit: http://www.intel.com/info/em64t.

processors. Consult your PC manufacturer. Performance varies depending on hardware, software, and system

Core™ i5-750. For more information including details on which

Intel, Intel Core, Intel386, Intel486, Pentium, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

*Other names and brands may be claimed as the property of others.

2 Specification Update



Contents

Revision History............................................................................................................... 5

Preface ..............................................................................................................................6

Summary Tables of Changes.......................................................................................... 8

Identification Information ..............................................................................................14

Errata...............................................................................................................................17

Specification Changes...................................................................................................47

Specification Clarifications ...........................................................................................48

Documentation Changes ...............................................................................................49

§ §

Specification Update 3

Contents

4 Specification Update



Revision History

Revision Description Date

001 • Initial Release. June 2013

002

003

004

005

006

007

• No Updates. Revision number added to Revision History to maintain consistency with NDA Specification Update numbering.

•Errata

— Added HSD59-99

• Updated Identification Information

• No Updates. Revision number added to Revision History to maintain consistency with NDA Specification Update numbering.

•Errata

— Moved previous HSD99 to HSD108 — Added HSD99-107 and HSD109-115

• Updated Identification Information

• Identification Information

— Updated Desktop Processor Identification table

•Errata

— Added HSD116-118

N/A

August 2013

N/A

November 2013

December 2013

Specification Update 5

Preface

This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools.

Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.

This document may also contain information that was not previously published.

Affected Documents

Desktop 4th Generation Intel and Desktop Intel

Celeron® Processor Family Datasheet – Volume 1 of 2

Celeron® Processor Family Datasheet – Volume 2 of 2

Nomenclature

Errata are design defects or errors. These may cause the processor behavior to

deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics such as, core speed, L2 cache size, package type, etc. as described in the processor identification information table. Read all notes associated with each S-Spec number.

Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification.

Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in any new release of the specification.

Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification.

Note: Errata remain in the specification update throughout the product’s lifecycle, or until a

particular stepping is no longer commercially available. Under these circumstances, errata removed from the specification update are archived and available upon request. Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, and so on).

Specification Update 7

Summary Tables of Changes

The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations.

Codes Used in Summary Tables

Stepping

Page

Status

Row

X: Errata exists in the stepping indicated. Specification Change or

Clarification that applies to this stepping.

(No mark)

or (Blank box): This erratum is fixed in listed stepping or specification change

does not apply to listed stepping.

(Page): Page location of item in this document.

Doc: Document change or update will be implemented.

Plan Fix: This erratum may be fixed in a future stepping of the product.

Fixed: This erratum has been previously fixed.

No Fix: There are no plans to fix this erratum.

Change bar to left of a table row indicates this erratum is either new or modified from the previous version of the document.

8 Specification Update



Errata (Sheet 1 of 5)

Number

HSD1

HSD2

HSD3

HSD4

HSD5

HSD6

HSD7

HSD8

HSD9

HSD10

HSD11

HSD12

HSD13

HSD14

HSD15

HSD16

HSD17

HSD18

HSD19

HSD20

HSD21

HSD22

HSD23

HSD24

HSD25

Steppings

C-0

XNo Fix

Status ERRATA

LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode

EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change

MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error

XNo FixLER MSRs May Be Unreliable

XNo Fix

MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang

An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a System Hang

#GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code

FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM

XNo FixAPIC Error “Received Illegal Vector” May be Lost

XNo Fix

Changing the Memory Type for an In-Use Page Translation May Lead to Memory-Ordering Violations

Performance Monitor Precise Instruction Retired Event May Present Wrong Indications

XNo FixCR0.CD Is Ignored in VMX Operation

XNo Fix

Instruction Fetch May Cause Machine Check if Page Size and Memory Type Was Changed Without Invalidation

Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for VEX.vvvv May Produce a #NM Exception

XNo FixProcessor May Fail to Acknowledge a TLP Request

XNo Fix

Interrupt From Local APIC Timer May Not Be Detectable While Being Delivered

PCIe* Root-port Initiated Compliance State Transmitter Equalization Settings May be Incorrect

XNo FixPCIe* Controller May Incorrectly Log Errors on Transition to RxL0s

XNo FixUnused PCIe* Lanes May Report Correctable Errors

XNo Fix

Accessing Physical Memory Space 0-640K through the Graphics Aperture May Cause Unpredictable System Behavior

XNo FixPCIe Root Port May Not Initiate Link Speed Change

XNo Fix

Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than Expected

DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP SS is Followed by a Store or an MMX Instruction

XNo FixVEX.L is Not Ignored with VCVT*2SI Instructions

XNo Fix

Certain Local Memory Read / Load Retired PerfMon Events May Undercount

Specification Update 9

Errata (Sheet 2 of 5)

Number

HSD26

HSD27

HSD28

HSD29

HSD30

HSD31

HSD32

HSD33

HSD34

HSD35

HSD36

HSD37

HSD38

HSD39

HSD40

HSD41

HSD42

HSD43

HSD44

HSD45

HSD46

HSD47

HSD48

HSD49

HSD50

HSD51

HSD52

HSD53

HSD54

Steppings

C-0

XNo Fix

Status ERRATA

Specific Graphics Blitter Instructions May Result in Unpredictable Graphics Controller Behavior

Processor May Enter Shutdown Unexpectedly on a Second Uncorrectable Error

Modified Compliance Patterns for 2.5 GT/s and 5 GT/s Transfer Rates Do Not Follow PCIe* Specification

XNo FixPerformance Monitor Counters May Produce Incorrect Results

XNo FixPerformance Monitor UOPS_EXECUTED Event May Undercount

XNo FixMSR_PERF_STATUS May Report an Incorrect Core Voltage

XNo Fix

PCIe* Atomic Transactions From Two or More PCIe Controllers May Cause Starvation

The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated After a UC Error is Logged

An AVX Gather Instruction That Causes an EPT Violation May Not Update Previous Elements

XNo FixPLATFORM_POWER_LIMIT MSR Not Visible

XNo FixLPDDR Memory May Report Incorrect Temperature

XNo FixPCIe* Host Bridge DID May Be Incorrect

XNo FixTSC May be Incorrect After a Deep C-State Exit

XNo Fix

PCIe* Controller May Initiate Speed Change While in DL_Init State Causing Certain PCIe Devices to Fail to Train

XNo FixSpurious VT-d Interrupts May Occur When the PFO Bit is Set

XNo FixN/A. Erratum has been removed.

XNo Fix

AVX Gather Instruction That Causes a Fault or VM Exit May Incorrectly Modify Its Destination Register

Inconsistent NaN Propagation May Occur When Executing (V)DPPS Instruction

XNo FixDisplay May Flicker When Package C-States Are Enabled

XNo Fix

Certain Combinations of AVX Instructions May Cause Unpredictable System Behavior

XNo FixProcessor May Incorrectly Estimate Peak Power Delivery Requirements

XNo FixIA32_PERF_CTL MSR is Incorrectly Reset

XNo FixProcessor May Hang During a Function Level Reset of the Display

XNo Fix

AVX Gather Instruction That Should Result in #DF May Cause Unexpected System Behavior

Throttling and Refresh Rate Maybe be Incorrect After Exiting Package CState

XNo FixProcessor May Livelock During On Demand Clock Modulation

XNo Fix

IA32_DEBUGCTL.FREEZE_PERFMON_ON_PMI is Incorrectly Cleared by SMI

XNo FixThe From-IP for Branch Tracing May be Incorrect

XNo FixTM1 Throttling May Continue indefinitely

10 Specification Update



Errata (Sheet 3 of 5)

Number

HSD55

HSD56

HSD57

HSD58

HSD59

HSD60

HSD61

HSD62

HSD63

HSD64

HSD65

HSD66

HSD67

HSD68

HSD69

HSD70

HSD71

HSD72

HSD73

HSD74

HSD75

HSD76

HSD77

HSD78

HSD79

HSD80

HSD81

Steppings

C-0

XNo Fix

Status ERRATA

Internal Parity Errors May Incorrectly Report Overflow in The IA32_MCi_STATUS MSR

Performance Monitor Events OTHER_ASSISTS.AVX_TO_SSE And OTHER_ASSISTS.SSE_TO_AVX May Over Count

XNo FixProcessor May Run at Incorrect P-State

XNo Fix

Performance Monitor Event DSB2MITE_SWITCHES.COUNT May Over Count

Performance Monitor Register UNC_PERF_GLOBAL_STATUS Not Restored on Package C7 Exit

Processor May Not Enter Package C6 or Deeper C-states When PCIe* Links Are Disabled

Performance Monitor Event For Outstanding Offcore Requests And Snoop Requests May Over Count

Some Performance Monitor Event Counts May be Inaccurate During SMT Mode

XNo FixTimed MWAIT May Use Deadline of a Previous Execution

XNo FixThe Upper 32 Bits of CR3 May be Incorrectly Used With 32-Bit Paging

XNo Fix

Performance Monitor Events HLE_RETIRED.ABORTED_MISC4 And RTM_RETIRED.ABORTED_MISC4 May Over Count

XNo FixA PCIe* LTR Update Message May Cause The Processor to Hang

XNo FixGETSEC Does Not Report Support For S-CRTM

XNo FixEPT Violations May Report Bits 11:0 of Guest Linear Address Incorrectly

XNo FixAPIC Timer Might Not Signal an Interrupt While in TSC-Deadline Mode

XNo Fix

IA32_VMX_VMCS_ENUM MSR (48AH) Does Not Properly Report The Highest Index Value Used For VMCS Encoding

Incorrect FROM_IP Value For an RTM Abort in BTM or BTS May be Observed

VT-d Hardware May Perform STRP And SIRTP Operations on a Package C7 Exit

XNo FixGeneral-Purpose Performance Counters Can Unexpectedly Increment

XNo Fix

Performance Monitoring Events May Report Incorrect Number of Load Hits or Misses to LLC

Performance Monitoring Event INSTR_RETIRED.ALL May Generate Redundant PEBS Records For an Overflow

XNo FixLocked Load Performance Monitoring Events May Under Count

XNo Fix

Graphics Processor Ratio And C-State Transitions May Cause a System Hang

Certain Performance Monitoring Events May Over Count Software Demand Loads

Accessing Nonexistent Uncore Performance Monitoring MSRs May Not Signal a #GP

XNo FixCall Stack Profiling May Produce Extra Call Records

XNo FixWarm Reset May Fail or Lead to Incorrect Power Regulation

Specification Update 11

Errata (Sheet 4 of 5)

Number

HSD82

HSD83

HSD84

HSD85

HSD86

HSD87

HSD88

HSD89

HSD90

HSD91

HSD92

HSD93

HSD94

HSD95

HSD96

HSD97

HSD98

HSD99

HSD100

HSD101

HSD102

HSD103

HSD104

HSD105

HSD106

HSD107

HSD108

HSD109

Steppings

C-0

Status ERRATA

XNo FixPCIe* Host Bridge DID May Be Incorrect

XNo FixTransactional Abort May Produce an Incorrect Branch Record

XNo Fix

SMRAM State-Save Area Above the 4GB Boundary May Cause Unpredictable System Behavior

DMA Remapping Faults for the Graphics VT-d Unit May Not Properly Report Type of Faulted Request

AVX Gather Instructions Page Faults May Report an Incorrect Faulting Address

XNo FixIntel® TSX Instructions May Cause Unpredictable System behavior

XNo FixEvent Injection by VM Entry May Use an Incorrect B Flag for SS

XNo FixA Fault in SMM May Result in Unpredictable System Behavior

XNo Fix

Processor Frequency is Unexpectedly Limited Below Nominal P1 When cTDP Down is Enabled

PMI May be Signaled More Than Once For Performance Monitor Counter Overflow

Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a #NM Exception

RDRAND Execution in a Transactional Region May Cause a System Hang

XNo FixUncore Clock Frequency Changes May Cause Audio/Video Glitches

XNo Fix

Processor May Experience a Spurious LLC-Related Machine Check During Periods of High Activity

XNo FixThe Processor May Not Enter Package C7 When Using a PSR Display

XNo FixVideo/Audio Distortion May Occur

XNo FixSystem May Hang When Audio is Enabled During Package C3

XNo FixINVPCID May Not Cause #UD in VMX Non-Root Operation

XNo Fix

Non-Compliant PFAT Module Base Address May Cause Unpredictable System Behavior

Incorrect LBR Source Address May be Reported For a Transactional Abort

Address Translation Faults for Intel® VT-d May Not be Reported for Display Engine Memory Accesses

L3 Cache Corrected Error Count May be Inaccurate After Package C7 Exit

XNo FixPCIe* Device’s SVID is Not Preserved Across The Package C7 C-State

XNo FixWarm Reset Does Not Stop GT Power Draw

XNo FixUnused PCIe* Lanes May Remain Powered After Package C7

XNo FixBMI1 And BMI2 Instruction Groups Are Not Available

XNo Fix

Virtual-APIC Page Accesses With 32-Bit PAE Paging May Cause a System Crash

XNo FixProcessor Energy Policy Selection May Not Work as Expected

12 Specification Update



Errata (Sheet 5 of 5)

Number

HSD110

HSD111

HSD112

HSD113

HSD114

HSD115

HSD116

HSD117

HSD118

Steppings

Status ERRATA

C-0

XNo Fix

XNo FixMSR_PP1_ENERGY_STATUS Reports Incorrect Energy Data

XNo Fix

XNo FixProcessor May Hang During Package C7 Exit

XNo FixIntel® TSX Instructions May Cause Unpredictable System behavior

XNo FixSpurious LLC Machine Check May Occur

XNo FixPage Fault May Report Incorrect Fault Information

XNo FixCATERR# Pin Assertion is Not Cleared on a Warm Reset

XNo Fix

Specification Changes

Number SPECIFICATION CHANGES

None for this revision of this specification update.

Specification Clarifications

A PEBS Record May Contain Processor State for an Unexpected Instruction

x87 FPU DP May be Incorrect After Instructions That Save FP State to Memory

Uncorrectable Machine Check Error During Core C6 Entry May Not be Signaled

Number SPECIFICATION CLARIFICATIONS

None for this revision of this specification update.

Documentation Changes

Number DOCUMENTATION CHANGES

HSD1

”On-Demand Clock Modulation Feature Clarification”

Specification Update 13

Identification Information

Component Identification using Programming Interface

The processor stepping can be identified by the following register contents.

Table 1. Desktop 4th Generation Intel® Core™ Processor Family Component

Identification

Reserved

Extended

Family

Extended

Model

Reserved

Processor

Type

Family

Code

Model

Number

Stepping

31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0

00000000b 0011b 00b 0110b 1100b xxxxb

Notes:

1. The Extended Family, Bits [27:20] are used in conjunction with the Family Code, specified in Bits[11:8], to indicate whether the processor belongs to the Intel386™, Intel486™, Pentium Core™ processor family.

2. The Extended Model, Bits [19:16] in conjunction with the Model Number, specified in Bits [7:4], are used to identify the model of the processor within the processor’s family.

3. The Family Code corresponds to Bits [11:8] of the EDX register after RESET, Bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.

4. The Model Number corresponds to Bits [7:4] of the EDX register after RESET, Bits [7:4] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan.

5. The Stepping ID in Bits [3:0] indicates the revision number of that model. See the processor Identification table for the processor stepping ID number in the CPUID information.

, Pentium 4, or Intel®

When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended Family, Extended Model, Processor Type, Family Code, Model Number and Stepping ID value in the EAX register. Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register.

The processor can be identified by the following register contents.

Host Device

Stepping Vendor ID

C-0 8086h 0C04h GT2 = 0416h 06h 06h

Notes:

1. The Vendor ID corresponds to bits 15:0 of the Vendor ID Register located at offset 00h–01h in the PCI

2. The Host Device ID corresponds to bits 15:0 of the Device ID Register located at Device 0 offset 02h–

3. The Processor Graphics Device ID (DID2) corresponds to bits 15:0 of the Device ID Register located at

4. The Revision Number corresponds to bits 7:0 of the Revision ID Re gister loc ated at offse t 08h in the PC I

14 Specification Update

function 0 configuration space.

03h in the PCI function 0 configuration space.

Device 2 offset 02h–03h in the PCI function 0 configuration space.

function 0 configuration space.

Processor Graphics

Device ID

Revision ID

CRID



Component Marking Information

The processor stepping can be identified by the following component markings.

Figure 1. Desktop 4th Generation Intel® Core™ Processor Family Top-Side Markings

Table 2. Desktop Processor Identification (Sheet 1 of 2)

S-Spec

Number

SR147 I7-4770K C-0 8 4 2 3.9 1600 3.5 95

SR149 I7-4770 C-0 8 4 2 3.9 1600 3.4 95

SR14A I5-4670K C-0 6 4 2 3.8 1600 3.4 95

SR14D I5-4670 C-0 6 4 2 3.8 1600 3.4 95

SR14E I5-4570 C-0 6 4 2 3.6 1600 3.2 95

SR14F I5-4440 C-0 6 4 2 3.3 1600 3.1 95

SR14G I5-4430 C-0 6 4 2 3.2 1600 3 95

SR14H I7-4770S C-0 8 4 2 3.9 1600 3.1 65

SR14J I5-4570S C-0 6 4 2 3.6 1600 2.9 65

SR14K I5-4670S C-0 6 4 2 3.8 1600 3.1 65

SR14L I5-4440S C-0 6 4 2 3.3 1600 2.8 65

SR14M I5-4430S C-0 6 4 2 3.2 1600 2.7 65

SR14N I7-4770T C-0 8 4 2 3.7 1600 2.5 45

SR14P I5-4670T C-0 6 4 2 3.3 1600 2.3 45

SR14Q I7-4765T C-0 8 4 2 3 1600 2 35

Processor

Number

Stepping

Cache

Size

(MB)

Functional

Core

Integrated

Graphics

Cores

Max

Turbo

Freq.

Rate

(GHz)

Memory

(MHz)

Core

Freq.

(GHz)

Thermal

Design

Power

(W)

Specification Update 15

+ 35 hidden pages

Intel BX80646I54430, CM8064601465902, BX80646I54570, BX80646I54440, CM8064601466203 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

Revision History

Preface

Affected Documents

Related Documents

Nomenclature

Summary Tables of Changes

Codes Used in Summary Tables

Specification Clarifications

Documentation Changes

Identification Information

Component Identification using Programming Interface

Component Marking Information